LPDDR Tec104 Slides

LPDDR4 Its not just for mobile
anymore
Lou Ternullo Product Marketing Director - Cadence Design Systems
October 15, 2014
DRAM Consumption by Application

Application
Protocol
Transition
DDR3 ->DDR4
1. Density
2. Performance
3. Power
DDR3 -> DDR4
1. Density
2. Performance
3. Power
DDR3 -> DDR4
1. Cost
2. Performance
3. Power
DDR3 -> DDR4
1. Reliability
2. Power
3. Cost
LPDDR3 -> LPDDR4
1. Power
2. Performance
3. Cost
Storage
RAID
SSD
Networking
Network Storage
Network Processors
Consumer
HDTV
Camera
Display
Industrial, Medical,
Instrumentation, FPGAs
Tester equipment
FPGAs
Mobile
Tablets/ cell phones
Wearables
2014 Cadence Design Systems, Inc. All rights reserved.
Requirements
Typical Consumer Product DRAM Requirements

Typical Consumer products
HDTV
Set top Box
Blue ray players
Printers..
Typical off chip memory (DRAM) requirements
Cost cost competitive markets

Performance continuous increasing performance requirements
Density - ~ 1GB DRAM density
Interface/bandwidth: typical interfaces are 32 bits wide
DRAM Cost Requirements for

Consumer Products
DRAM Industry Trends

Supply and demand impacts cost
Graphics
SDR
DDR
Mobile DRAM
DDR2
DDR3
DDR4
Mobile DRAM growth
Source:IHS
Increase in mobile DRAM bit consumption

IHS: Mobile devices to surpass PCs in DRAM consumption by 2015
Introduction of Uni-DIMM at IDF- LP DRAM on a DIMM
Potential Path to Lower Cost LP-DRAM
DRAM Density Requirements for

Consumer Products
DDR4 Consumer Product System Scenarios

Typical 32 bit DRAM interface
PCB
SoC
SoC
DDR
Controller
DDR
Controller
DDR PHY
DDR PHY
DDR4
x16
Protocol
DDR4
x16
PCB
DDR
4 x8
DDR
4 x8
DDR
4 x8
Density/ DRAM
# DRAMs
Total DRAM
Density
DDR4 X8
4Gb 8 Gb
2 GB 4GB
DDR4x16
4Gb 8Gb
1 GB 2 GB
Density requirements drive selection of x16 DRAM

Typical system density requirements ~ 1GB
7
DDR
4 x8
Alternate Consumer Product System Scenarios
PCB
SoC
SoC
DDR
Controller
DDR
Controller
DDR PHY
DDR PHY
DDR4
x16
Protocol
DDR4
x16
PCB
Density/ DRAM
# DRAMs
LPDDR4
LPDDR4
x32
x32
1 or 2 ranks
Total DRAM
Density
DDR4x16
4Gb 8Gb
1 GB 2 GB
LPDDR4x32
6Gb 8Gb
0.75 GB 1 GB
12Gb 16Gb
2 (stacked)
1.5 GB 2 GB
LPDDR4x32 2 rank
LPDDR4 x32 DRAM is an option to meet density requirements

LPDDR4 DRAM satisfy typical system density requirements ~ 1GB
8
DRAM Performance Requirements for

Consumer Products
2.6 Gbps
2.4 Gbps
LPDDR4 DRAM performance out pacing DDR4

10
DDR4 DRAM Timing Comparison

Number of Clock Cycles
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2667(1)
x8
x16
x8
x16
tCCD_S (min)
tCCD_L (min)
Symbol
nRRDS
nRRDL
tRRD_S: ACTIVATE to ACTIVATE Command delay to a different bank

group
tRRD_L: ACTIVATE to ACTIVATE Command delay to same bank
group
tCCD_S: CAS_n to CAS_n command delay for different bank group
tCCD_L: CAS_n to CAS_n command delay for the same bank group
Optimal DDR4 tCCD is 4 clock cycles to align with BL 8
(1) Projected timings for DDR4-2667
11
Introduction to DDR4 Bank Groups

DDR4 X8 DRAM Devices
BG0
tCCD_S
BG1
B0
B1
B0
B1
B2
B3
B2
B3
BG2
B2
B1
tCCD_L
B0
BG3
B3
B0
B2
tCCD_S
12
B1
B3
DDR4 DRAMs are architected

with Banks and Bank Groups
X8 DRAM devices have 2 Bank
address bits and 2 Bank group
bits
Timing differences exist across
banks accesses
Longer timing within the same bank
group. IE B0 to B1 tCCD_L
Shorter time across bank groups. IE
BG0 to BG1 tCCD_S
DDR controller address

mechanism must take Bank
Group restrictions into account
DDR4 Bank Groups

DDR4 X16 DRAM Devices
BG0
tCCD_S
BG1
B1
B0
B1
B2
B3
B2
B3
B4
B5
B4
B5
B6
B7
B6
B7
tCCD_L
B0
tCCD_S
13
X16 DRAM devices have 3 bank

address bits and 1 bank group
bit
X16 devices increase the
probability of back to back
commands in the same bank
group
DDR4 tCCD_S vs tCCD_L Comparison
tCCD_S (min): 4 CK cycles
tCCD_L(min): 6 CK cycles
2 dead cycles
tCCD_S: 4 DRAM clock cycles aligns well with DDR4 BL8

tCCD_L: 6 DRAM clock cycles is two more clock cycles than BL8
leaving 2 dead cycles
Random traffic to DDR4 x8 devices with 4 bank groups will have some
efficiency challenges
Random traffic to DDR4 x16 devices with only 2 bank groups will have
much more efficiency challenges
14
LPDDR4 DRAM Timing Comparison

Number of Clock Cycles
Example LDDR4 timing diagram
Symbol
LPDDR41600 - 3200
tRRD
tCCD
No dead cycles
tRRD: ACTIVATE bank A to ACTIVATE bank B command delay

tCCD: CAS to CAS command delay
Optimal LPDDR4 tCCD is less than or equal to 8 clock cycle to align with
BL 16
15
Estimated Data Throughput Efficiency

Example DRAM System Scenarios
100
100
75
75
1600 Mb/s
50
1600 Mb/s
50
2667 Mb/s
25
25
0
DDR4 X8
DDR4 x16
LPDDR4
Random addressing with BG

disabled
DDR4 X16 has worse timings
than X8
DDR4 timing worse at higher
data rates
16
2667 Mb/s
DDR4 X8
DDR4 x16
LPDDR4
Random addressing with DDR4

BG enabled
No change in LPDDR4
throughput
LPDDR4/DDR4 Device Comparison Summary

Symbol
LPDDR4 x32
DDR4 x8
DDR4 x16
tRRD
4-6
5-8
tCCD
4-6
4-6
16 or 32
6Gb 8Gb
4Gb 8Gb
4Gb 8Gb
Up to 3200Mb/s
Roadmap to 4267
Up to 3200Mb/s
Up to 3200Mb/s
Discrete & POP
Discrete
Discrete
12
22
22
BL
density
Data rate
# devices - 32 bit
Package type
Command/Address
Pin count
LPDDR4 Devices May Be Ideal for Low Density High

Performance Consumer Applications
17
Summary
Consumer products must be competitive on cost and
performance
Consumer products use lower cost PC DRAM today
Trends in the DRAM device market are driving the demand
to consider LPDDR4 DRAMs in consumer products
LPDDR4 DRAM devices have potential to replace DDR4
devices in consumer products
LPDDR4 is higher performance than DDR4
Potential for lower cost BOM with LPDDR4
DRAM performance trend is driving consumer product

developers to investigate LPDDR4/DDR4 combination IP
18

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LPDDR4 Its not just for mobile

DRAM Consumption by Application

DDR3 -> DDR4

DDR3 -> DDR4

DDR3 -> DDR4

LPDDR3 -> LPDDR4

2014 Cadence Design Systems, Inc. All rights reserved.

Typical Consumer Product DRAM Requirements

Typical off chip memory (DRAM) requirements

Cost cost competitive markets

2014 Cadence Design Systems, Inc. All rights reserved.

DRAM Cost Requirements for

2014 Cadence Design Systems, Inc. All rights reserved.

DRAM Industry Trends

Mobile DRAM growth

Increase in mobile DRAM bit consumption

DRAM Density Requirements for

2014 Cadence Design Systems, Inc. All rights reserved.

DDR4 Consumer Product System Scenarios

Density requirements drive selection of x16 DRAM

2014 Cadence Design Systems, Inc. All rights reserved.

Alternate Consumer Product System Scenarios

LPDDR4 x32 DRAM is an option to meet density requirements

2014 Cadence Design Systems, Inc. All rights reserved.

DRAM Performance Requirements for

2014 Cadence Design Systems, Inc. All rights reserved.

LPDDR4 DRAM performance out pacing DDR4

2014 Cadence Design Systems, Inc. All rights reserved.

DDR4 DRAM Timing Comparison

tRRD_S: ACTIVATE to ACTIVATE Command delay to a different bank

2014 Cadence Design Systems, Inc. All rights reserved.

Introduction to DDR4 Bank Groups

2014 Cadence Design Systems, Inc. All rights reserved.

DDR4 DRAMs are architected

DDR controller address

DDR4 Bank Groups

2014 Cadence Design Systems, Inc. All rights reserved.

X16 DRAM devices have 3 bank

DDR4 tCCD_S vs tCCD_L Comparison

tCCD_S (min): 4 CK cycles

tCCD_S: 4 DRAM clock cycles aligns well with DDR4 BL8

2014 Cadence Design Systems, Inc. All rights reserved.

LPDDR4 DRAM Timing Comparison

tRRD: ACTIVATE bank A to ACTIVATE bank B command delay

2014 Cadence Design Systems, Inc. All rights reserved.

Estimated Data Throughput Efficiency

Random addressing with BG

2014 Cadence Design Systems, Inc. All rights reserved.

Random addressing with DDR4

LPDDR4/DDR4 Device Comparison Summary

Discrete & POP

LPDDR4 Devices May Be Ideal for Low Density High

2014 Cadence Design Systems, Inc. All rights reserved.

DRAM performance trend is driving consumer product

2014 Cadence Design Systems, Inc. All rights reserved.

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