Dftbist

DFTMAX LogicBIST
User Guide
Version K-2015.06-SP4, December 2015
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DFTMAX LogicBIST User Guide, Version K-2015.06-SP4 ii

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DFTMAX LogicBIST User Guide, Version K-2015.06-SP4 iii

DFTMAX LogicBIST User Guide, Version K-2015.06-SP4 iv
Contents
About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1. Introduction to LogicBIST
Introduction to LogicBIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
LogicBIST Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
The LogicBIST Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2. The LogicBIST Architecture

LogicBIST Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
The LogicBIST Decompressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
The LogicBIST Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
The LogicBIST BIST Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
The LogicBIST Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
The LogicBIST Control and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
The LogicBIST Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
The LBIST_EN and START Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
The STATUS_0 and STATUS_1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
The Scan-In and Scan-Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
LogicBIST Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Overview of Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
OCC-Controlled Clocks With Default Capture Behavior . . . . . . . . . . . . . . . . . . 2-11
OCC-Controlled Clocks With Weighted Clock Capture Groups. . . . . . . . . . . . . 2-12
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External and Internal Clocks in the Same Design . . . . . . . . . . . . . . . . . . . . . . . 2-14

Isolating the Design During LogicBIST Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Isolating the Self-Test Design Using Core Wrapping . . . . . . . . . . . . . . . . . . . . . 2-15
Isolating the Self-Test Design Using User-Defined Test Points . . . . . . . . . . . . . 2-16
Providing Testability for LogicBIST Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Enabling DFT Logic During Autonomous Self-Test . . . . . . . . . . . . . . . . . . . . . . 2-17
Blocking Internal X Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Ensuring Testability for Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Ensuring Testability for Clock-Gating Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
3. Using LogicBIST Compression

Configuring LogicBIST Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Defining the LogicBIST Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Defining the LogicBIST Compression Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Configuring the PRPG and MISR Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Configuring the Pattern Counter and Shift Counter Lengths . . . . . . . . . . . . . . . 3-4
Configuring Clock and Reset Weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Configuring Self-Test Isolation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Configuring Wrapper Chain Isolation Logic . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Configuring User-Defined Test Point Isolation Logic . . . . . . . . . . . . . . . . . 3-6
Inserting LogicBIST in Designs With Trailing-Edge Flip-Flops . . . . . . . . . . . . . 3-8
Previewing and Inserting the LogicBIST Implementation . . . . . . . . . . . . . . . . . . . . . 3-8
Writing Out the LogicBIST Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Computing the Seed and Signature Values in TetraMAX . . . . . . . . . . . . . . . . . . . . . 3-10
Setting the Seed and Signature Values in Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Simulating Autonomous BIST Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Connecting LogicBIST Self-Test to Functional Design Logic . . . . . . . . . . . . . . . . . . 3-13
Example LogicBIST Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Example Core Insertion Script Using Core Wrapping . . . . . . . . . . . . . . . . . . . . 3-15
Example Core Insertion Script Using User-Defined Test Points . . . . . . . . . . . . 3-16
Example Script to Automatically Set Seed and Signature Values . . . . . . . . . . . 3-17
4. Advanced LogicBIST Configuration

Using Programmable LogicBIST Configuration Values . . . . . . . . . . . . . . . . . . . . . . 4-1
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DFTMAX LogicBIST User Guide Version K-2015.06-SP4
Simplifying the MISR XOR Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Simplifying the Weighted Capture Groups Comparator . . . . . . . . . . . . . . . . . . . . . . 4-3
Configuring the Clock-Gating Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Implementing Burn-In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Post-DFT Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Post-DFT Optimization and BIST Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Preserving the BIST Constants in a compile Flow . . . . . . . . . . . . . . . . . . . . . . 4-7
Preserving the BIST Constants in a compile_ultra Flow . . . . . . . . . . . . . . . . . . 4-7
Regenerating Seed and Signature Values after Design Changes . . . . . . . . . . . 4-8
Ungrouping LogicBIST Blocks for Additional Area Reduction . . . . . . . . . . . . . . 4-9
5. LogicBIST Limitations and Known Issues

LogicBIST Limitations and Known Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Glossary
Chapter 1: Contents
Contents vii
1-vii
K-2015.06-SP4
Contents viii
Preface
This preface includes the following sections:
About This User Guide
Customer Support
ix
K-2015.06-SP4
About This User Guide

The DFTMAX LogicBIST User Guide describes the process for inserting built-in self-test
(BIST) logic into a design using the DFTMAX LogicBIST tool. You can then generate seed

and expected signature values for these designs with the Synopsys TetraMAX tool. The
BIST logic uses the same scan chain logic resources as manufacturing test.
Audience
This manual is intended for ASIC design engineers who have some experience with
testability concepts, are familiar with the DFT Compiler and DFTMAX tools, and want to
implement built-in self-test (BIST) logic in their design.
Related Publications
For additional information about the DFTMAX LogicBIST tool, see the documentation on the
Synopsys SolvNet online support site at the following address:
https://solvnet.synopsys.com/DocsOnWeb
You might also want to see the documentation for the following related Synopsys products:
DFT Compiler and DFTMAX
Design Compiler
TetraMAX
VCS
Preface
About This User Guide x
Conventions
The following conventions are used in Synopsys documentation.
Convention Description
Courier Indicates syntax, such as write_file.
Courier italic Indicates a user-defined value in syntax, such as

write_file design_list.
Courier bold Indicates user inputtext you type verbatimin

examples, such as
prompt> write_file top
[] Denotes optional arguments in syntax, such as

write_file [-format fmt]
... Indicates that arguments can be repeated as many

times as needed, such as
pin1 pin2 ... pinN
| Indicates a choice among alternatives, such as

low | medium | high
Ctrl+C Indicates a keyboard combination, such as holding

down the Ctrl key and pressing C.
\ Indicates a continuation of a command line.
/ Indicates levels of directory structure.
Edit > Copy Indicates a path to a menu command, such as

opening the Edit menu and choosing Copy.
Customer Support
Customer support is available through SolvNet online customer support and through
contacting the Synopsys Technical Support Center.
Preface 1: Preface
Chapter
Customer Support 1-xi
xi
K-2015.06-SP4
Accessing SolvNet
The SolvNet site includes a knowledge base of technical articles and answers to frequently
asked questions about Synopsys tools. The SolvNet site also gives you access to a wide
range of Synopsys online services including software downloads, documentation, and
technical support.
To access the SolvNet site, go to the following address:
https://solvnet.synopsys.com
If prompted, enter your user name and password. If you do not have a Synopsys user name
and password, follow the instructions to sign up for an account.
If you need help using the SolvNet site, click HELP in the top-right menu bar.
Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact the Synopsys Technical
Support Center in the following ways:
Open a support case to your local support center online by signing in to the SolvNet site
at https://solvnet.synopsys.com, clicking Support, and then clicking Open A Support
Case.
Send an e-mail message to your local support center.
E-mail [email protected] from within North America.
Find other local support center e-mail addresses at
http://www.synopsys.com/Support/GlobalSupportCenters/Pages
Telephone your local support center.
Call (800) 245-8005 from within North America.
Find other local support center telephone numbers at
http://www.synopsys.com/Support/GlobalSupportCenters/Pages
Preface
Customer Support xii
1
Introduction to LogicBIST 1
This chapter provides an introduction to the LogicBIST tool, which is a synthesis-based
solution for in-system self-test of digital integrated circuits used in automotive, medical, and
aerospace applications. LogicBIST addresses functional safety requirements set forth by
standards such as ISO 26262 for the automotive semiconductor industry.
The following topics introduce LogicBIST compression:
Introduction to LogicBIST
LogicBIST Requirements
The LogicBIST Flow
1-1
K-2015.06-SP4
Introduction to LogicBIST
Built-in self-test (BIST) capability enables a design to test itself autonomously, without test
data supplied from an external source. The LogicBIST tool provides a low-overhead logic
BIST (LBIST) solution for digital logic designs, such as automotive applications. The
characteristics of this solution are:
Low BIST controller area overhead
Reuses the scan chain and test-mode control logic already implemented for
manufacturing test
Limited LogicBIST-mode pin requirementsthree functional pins, plus two scan-ins and
a scan-out that can be shared with non-LogicBIST scan modes
Seed and expected signature values can be hardcoded or programmable
Targets stuck-at and transition-delay faults
Simple one-pass DFT insertion flow
LogicBIST Requirements
The LogicBIST flow requires the following:
You must have the Design Compiler, DFTMAX, and LogicBIST tools installed and
licensed at your site.
You must have an HDL-Compiler license for compressed scan insertion.
Blocks must be X-clean.
The design must have three functional signals (START, STATUS_0, STATUS_1), plus
two scan-ins and a scan-out that can be shared with non-LogicBIST scan modes
The LogicBIST Flow

From a high level, the LogicBIST flow can be summarized as follows:
1. Insert the LogicBIST DFT logic in the design. The bused seed and signature values are
tied to logic 0 in the initial netlist.
2. Read the design into TetraMAX ATPG and run LogicBIST ATPG. TetraMAX ATPG
chooses a seed value for the design, and it computes the expected signature value for
that seed value.
Chapter 1: Introduction to LogicBIST

Introduction to LogicBIST 1-2
3. Modify the bused seed, signature, and pattern count values in the netlist to use the
values computed by TetraMAX ATPG.
4. Simulate the resulting netlist in a Verilog simulator, such as VCS, to verify the
correctness of autonomous BIST operation.
Figure 1-1 shows the flow diagram for LogicBIST insertion, pattern generation, and
verification.
Figure 1-1 The LogicBIST Flow
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The LogicBIST Flow 1-3
K-2015.06-SP4

The LogicBIST Flow 1-4
2
The LogicBIST Architecture 2
LogicBIST compression enables a design to test itself using the same scan chains already
implemented for manufacturing test. It uses a pseudo-random pattern generator (PRPG) to
create scan data, and a multiple-input signature register (MISR) to capture the design
response. At the end of the test, if the actual signature matches the expected signature, the
self-test asserts a PASS signal.
The following topics describe the LogicBIST architecture:
LogicBIST Architecture Overview
LogicBIST Clock Control
Isolating the Design During LogicBIST Self-Test
Providing Testability for LogicBIST Self-Test
LogicBIST Architecture Overview

The LogicBIST architecture consists of four components - LogicBIST controller,
decompressor, compressor, and LogicBIST clock controller - as shown in Figure 2-1.
2-1
K-2015.06-SP4
Figure 2-1 The LogicBIST Architecture

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These components are described in the following sections:

The LogicBIST Decompressor
The LogicBIST Compressor
The LogicBIST BIST Controller
The LogicBIST Clock Controller
The LogicBIST Control and Data Signals
The LogicBIST Decompressor

The LogicBIST decompressor feeds data into the compressed scan chains in the core logic.
It is responsible for generation of target fault care bits.
A PRPG, or pseudo-random pattern generator, is comprised of the following two
components:
A LFSR that generates the next data bit of the next data word as a linear XOR function
of its current data word
An XOR phase shifter that removes the correlations that result from the shift-register
nature of the LFSR output taps
Figure 2-2 shows a simple example PRPG register.
Chapter 2: The LogicBIST Architecture

LogicBIST Architecture Overview 2-2
Figure 2-2 An Example PRPG Register
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In the LogicBIST architecture, the PRPG operates as follows:

When the design is operating in mission mode, the PRPG is idle and is not clocked.
When the design is in a non-LogicBIST scan mode, the PRPG operates as scannable
design logic so that the decompressor logic can be scan-tested.
During LogicBIST operation,
At the beginning of the test program, the user-specified seed value is parallel-loaded
into the PRPG in a single clock cycle.
During the test program, the PRPG generates a new pseudorandom data word in
each clock cycle, which is used to generate scan data for the compressed scan
chains.
Note:
For simplicity, the control logic that implements these modes of operation is not shown in
the figure.
After the PRPG is loaded with a seed value and clocked, it generates a stream of data
values that have the appearance of random values, but are actually a function of that seed
value. Each seed value produces a stream of data values unique to that seed value.
The LogicBIST Compressor

The LogicBIST compressor receives and compresses data from the internal chains during
the unload process. It consists of an XOR-tree compactor and a multiple-input signature
register (MISR). The XOR compressor has no X-tolerance masking.
The MISR is a multiple-input signature register where each register input captures an XOR
of the previous register's input and a data input signal from the XOR compactor to the MISR.
Figure 2-3 shows a simple example MISR.

K-2015.06-SP4
Figure 2-3 An Example MISR Register

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In the LogicBIST architecture, the MISR operates as follows:

When the design is operating in mission mode, the MISR is idle and is not clocked.
When the design is in a non-LogicBIST scan mode, the MISR operates as scannable
design logic so that the compressor logic can be scan-tested.
During LogicBIST operation,
The MISR is reset when the design enters the LogicBIST operation mode. The MISR
now has an initial known signature value (all zeros).
For the first pattern, the MISR remains unclocked because the unloaded scan data is
unknown.
For the second and subsequent patterns, the MISR is clocked. The MISR captures
values from the XOR compressor in each shift clock cycle and incorporates it into the
current signature value of the MISR.
During the test program, the sequence of MISR values is dependent on the scan data that it
captures. At the end of the test program, the signature value of the MISR is compared
against the user-specified expected signature value, and the STATUS_* signals are set to
indicate test completion and pass/fail status.
The LogicBIST BIST Controller

The LogicBIST BIST controller contains the following:
A small finite state machine (FSM) that controls BIST operation.
A pattern counter that applies the user-specified number of test patterns.
A shift counter that applies the correct number of shift clock cycles for each test pattern.
For each completed sequence of the shift counter, the pattern counter decrements by
one.

In the LogicBIST architecture, the LogicBIST controller operates as follows:

When the design is in mission mode, the LogicBIST controller is idle and is not clocked.
When the design is in a non-LogicBIST scan mode, the pattern counter and shift counter
operate as scannable design logic so that their logic can be scan-tested. The FSM
flip-flops are excluded from scan testing so any OCC, ICG, reset, or scan-enable control
logic does not interfere with scan testing.
When LogicBIST self-test is active,
At the beginning of the test program, the FSM initializes the decompressor PRPG and
compressor MISR to their initial states, and it loads the pattern and shift counters to
their user-specified initial values.
During the test program, the LogicBIST controller runs the pattern and shift counters
through their sequences. As the shift counter counts through its sequence, the scan
chains perform load/unload using the PRPG/MISR, respectively. When the shift
counter reaches zero, the FSM performs a single capture cycle, decrements the
pattern counter, and begins a new shift counter sequence.
When the pattern counter reaches zero, the current MISR signature value is
compared with the user-specified expected signature value. If they match, the test
passes; if not, the test fails.
The LogicBIST controller controls the scan-enable signals in the design.
The LogicBIST Clock Controller

The LogicBIST clock controller operates as follows:
When the design is in mission mode, the clocks operate normally.
When the design is in a non-LogicBIST scan mode, the clocks operate normally.
When LogicBIST self-test is active,
The clock controller gates the clock signal to the functional design logic as directed
by the LogicBIST controller.
A free-running BIST clock must be available, running at the desired scan frequency,
for the duration of the LogicBIST test operation.
LogicBIST compression supports multiple clock configurations, each of which uses its own
clock controller logic structure. For more information, see LogicBIST Clock Control on
page 2-9.

K-2015.06-SP4
The LogicBIST Control and Data Signals

The LogicBIST-specific control and data signals in a LogicBIST implementation are
described in the following topics:
The LogicBIST Operational Modes
The LBIST_EN and START Signals
The STATUS_0 and STATUS_1 Signals
The Scan-In and Scan-Out Signals
The LogicBIST Operational Modes

LogicBIST self-test can operate in the following modes:
TetraMAX modeThis mode is used only for core-level seed and signature computation
in TetraMAX ATPG. TetraMAX accesses state elements (via a scan chain) through
core-level scan ports during this process; the LogicBIST FSM is unused.
This mode is activated when the LogicBIST test-mode encoding is applied. The
LBIST_EN and START signals are not used.
Autonomous modeThis mode can be used after the seed and signature values have
been applied to the design. All BIST operations perform autonomously, as controlled by
the LogicBIST FSM. This is the mode that is simulated and ultimately used in silicon
operation.
This mode is activated when the LBIST_EN and START signals are asserted while the
mission-mode test-mode encoding is applied.
The LBIST_EN and START Signals

The LBIST_EN and START signals work together as follows:
The LBIST_EN signal is used only when the mission-mode test-mode encoding is
applied. When this signal is asserted in mission mode, the design enters autonomous
LogicBIST operation mode. Any DFT logic associated with the LogicBIST compression
mode (wrapper chains, test points, and so on) is enabled.
When the START signal is deasserted (regardless of the state of the LBIST_EN signal),
the LogicBIST FSM is unclocked and asynchronously held in reset to the idle state.
When the LBIST_EN signal is asserted while the START signal is deasserted, the
pattern counter and MISR are reset to all-zeros.

LogicBIST self-test begins when the START signal is asserted while the LBIST_EN
signal is already asserted. The test runs to completion as long as the START signal
remains asserted. If the START signal is deasserted during the test, the test halts and the
LogicBIST logic returns to its idle state.
When the LBIST_EN signal is deasserted, any DFT logic associated with the LogicBIST
compression mode (wrapper chains, test points, and so on) is disabled.
The START signal is synchronized the to the BIST clock, as shown in Figure 2-4, to avoid
metastability issues. Due to the synchronizer delay, the pattern counter and MISR are reset
even if the LBIST_EN and START signals are asserted at the same time. The metastability
registers are included in scan testing.
Figure 2-4 Synchronization of the START Signal to the BIST Clock
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These signals are used in autonomous mode.
See Also
Enabling DFT Logic During Autonomous Self-Test on page 2-17 for more information
on how test-mode signals are used in a LogicBIST design
The STATUS_0 and STATUS_1 Signals

The STATUS_0 and STATUS_1 signals indicate the status of the LogicBIST test logic. The
two-bit bus {STATUS_1, STATUS_0} has the following possible status values:
00: LogicBIST logic idle
01: LogicBIST test running
10: LogicBIST test complete and passed
11: LogicBIST test complete and failed
These signals are used in autonomous mode.

Figure 2-5 shows the status signal behavior when self-test completes and passes. The
passing status is held until START is deasserted.

K-2015.06-SP4
Figure 2-5 Status Signal Behavior When Self-Test Completes and Passes
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Figure 2-6 shows the status signal behavior when self-test completes and fails. The failing
status is held until START is deasserted
Figure 2-6 Status Signal Behavior When Self-Test Completes and Fails
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The Scan-In and Scan-Out Signals

A LogicBIST implementation requires two user-defined scan-in signals. However, in a
LogicBIST design, they function differently than typical scan-in signals:
One scan-in signal acts as a scan-enable signal that turns key LogicBIST logic (pattern
counter, shift counter, START synchronizer, PRPG, and MISR) into a scannable chain
accessed by TetraMAX DRC during LogicBIST seed and signature computation. This
signal is called the LogicBIST DRC enable signal.
The other scan-in signal, along with a scan-out signal (user-defined or DFT-created),
provides scan load/unload access to this scannable LogicBIST chain when asserted.
These scan-in signals are used as described only in TetraMAX mode. For other test modes,
these scan-in ports are free to be used as regular scan-in ports.
Figure 2-7 shows how TetraMAX accesses the scannable LogicBIST access chain in
TetraMAX mode.

Figure 2-7 Scan Chain Access to the LogicBIST Logic
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LogicBIST Clock Control

LogicBIST clock control is described in the following topics:
Overview of Clock Configurations
External Clocks
OCC-Controlled Clocks With Default Capture Behavior
OCC-Controlled Clocks With Weighted Clock Capture Groups
External and Internal Clocks in the Same Design
Overview of Clock Configurations

LogicBIST compression supports the following three clock configurations:
External (port-driven) clocks
Use this configuration when all clocks are driven by input ports and there are no on-chip
clocking (OCC) sources, such as phase-locked loops (PLLs).
OCC-controlled clocks with default capture behavior
Use this configuration when there is a single OCC-controlled clock or multiple
OCC-controlled clocks that do not interact during capture.
OCC-controlled clocks with weighted clock captures
Use this configuration when there are multiple OCC-controlled clocks that interact or if
there is an asynchronous set or reset signal in your design.

LogicBIST Clock Control 2-9
K-2015.06-SP4
If the communication between asynchronous clock domains is small, you can use test
points to block the capture path between clock domains.
All clocks in the design must use the same configuration. If you have a mix of external and
OCC-controlled clocks, you must use an OCC controller for the external clocks. If you have
an asynchronous set or reset in your design, you must disable it or use weighted clock
captures-even for a single clock.
External Clocks
If the design has no on-chip clocking (OCC) sources, then all clocks are external (driven by
input ports).Figure 2-8 shows how the clock controller passes all clocks transparently when
LogicBIST self-test is inactive.
Figure 2-8 External Clocks When LogicBIST Self-Test Is Inactive
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When LogicBIST self-test is active, if the design contains multiple scan clock domains, the
clock controller drives all scan clock domains with a single BIST clock. The non-BIST clock
input ports do not clock any scan chains.
Figure 2-9 shows how the clock controller drives all scan clock domains with the LogicBIST
clock when LogicBIST self-test is active (gated under the control of the LogicBIST
controller).

Figure 2-9 External Clocks When LogicBIST Self-Test Is Active

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Important:
When the design contains multiple external clocks, you must ensure that cross-domain
paths meet timing in LogicBIST mode because the clock trees are driven by a single port
but might have different latencies.
The LogicBIST clock controller logic structure is shown in Figure 2-10. (The figure is
intended to show the logic function; actual implementation might vary.)
Figure 2-10 External Clock Controller Structure
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OCC-Controlled Clocks With Default Capture Behavior

When you have a DFT-inserted OCC controller in your design, the tool uses an OCC
controller design with additional LogicBIST clock control logic. The ATE clock is used as the
BIST clock.
In autonomous mode, the OCC controller operates normally, except that the clock pulses
are determined by a pulse pattern signal (lbist_clk_enable[]) instead of the clock chain. The
width of this bus is the same as the clock chain length. By default, the first clock pulse bit for
each clock is tied to logic 1 and any remaining bits are tied to logic 0. You can optionally drive
this bus from design logic to make the pulse behavior programmable.

K-2015.06-SP4
In TetraMAX mode, the OCC controller is placed in the pll_bypass mode.

The OCC controller logic is shown in Figure 2-11.
Figure 2-11 LogicBIST OCC Controller
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If you have multiple OCC-controlled clocks in your design, all clocks capture in each pattern.
If capture paths exist between the clock domains, you must use weighted-clock captures as
described in the next section, or you must block the capture paths using RTL logic or test
points.
Some limitations apply to designs with OCC controllers. See Chapter 5, LogicBIST
Limitations and Known Issues.
OCC-Controlled Clocks With Weighted Clock Capture Groups

By default, all OCC clocks capture in each LogicBIST pattern. If capture paths exist between
clock domains, additional logic is required to selectively enable non-interacting capture
clocks in each pattern. This avoids capturing an X value from an asynchronous clock
domain that is also clocked in that pattern.
To do this, you separate clocks into groups and assign a weight to each group. In each
pattern, a single clock group is selected for capture, proportionally to the weight values.
In the following example, clock domains A2 and B1 do not interact with each other and can
be grouped together. Clock domains A1 and B2 have less logic than A2+B1 and can have a
lower weight than A2+B1 to capture less often.

Figure 2-12 LogicBIST OCC Controller With Weighted Capture Groups

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Because LogicBIST does not use the clock chain registers, they are repurposed for clock
group selection during LogicBIST self-test. In each pattern, the clock chains load a
pseudorandom value from the PRPG. This value feeds a weighted clock group selector that
enables the pulse pattern for one of the capture groups, as shown in Figure 2-13.
Figure 2-13 Weighted Capture Groups Logic Structure
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The comparator value is seven bits. Thus, you must have at least seven clock chain bits in
the design; additional bits are not used for clock selection. In addition, all OCC controller
clocks must have the same clock chain length.
The clock pulses are determined by a pulse pattern signal instead of the clock chain. The
width of this bus is the value specified for the -cycles_per_clock option. By default, the
first clock pulse bit is tied to logic 1 and any remaining bits are tied to logic 0. You can
optionally drive this bus from design logic to make the pulse behavior programmable.

K-2015.06-SP4
Table 2-1 shows the minimum clock chain length as a function of clock count.
Table 2-1 Minimum Total Clock Chain Length in a LogicBIST Design
Number of OCC clocks Minimum clock chain length
2 4
3 3
4 to 6 2
7 or more 1
Additional limitations apply to designs with OCC controllers. See Chapter 5, LogicBIST
Limitations and Known Issues.
See Also
Configuring Clock and Reset Weights on page 3-4 for details on configuring clock
weights
Simplifying the Weighted Capture Groups Comparator on page 4-3 for details on
simplifying the comparator logic
External and Internal Clocks in the Same Design

If you have a mix of external (port-driven) and internal (OCC-controlled) clocks in the same
design, you must control the external clocks with a DFT-inserted OCC controller. If the clock
domains have capture interactions, you must also use weighted clock capture groups.
Figure 2-14 shows a design with one external clock and one internal clock using weighted
clock capture groups.
Figure 2-14 Using OCC Control for External Clocks
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For more information, see Specifying OCC Controllers for External Clock Sources in the
On-Chip Clocking Support chapter of the DFT Compiler, DFTMAX, and DFTMAX Ultra
User Guide.
Isolating the Design During LogicBIST Self-Test

When LogicBIST self-test is active, it generates and applies the test data autonomously
(on-chip). ATE data is not available to control the design input ports, and the ATE does not
observe the design output ports.
As a result, the design must be isolated on-chip during LogicBIST self-test. Its inputs must
be controlled to avoid X capture; its outputs should be observed to ensure coverage.
The following topics describe two design isolation methods:
Isolating the Self-Test Design Using Core Wrapping
Isolating the Self-Test Design Using User-Defined Test Points
Isolating the Self-Test Design Using Core Wrapping

You can use the core wrapping feature to insert a wrapper chain that isolates the design
during self-test. Wrapper chains inherently provide this needed isolation.
With this approach, the LogicBIST test mode becomes an inward-facing mode that drives
LogicBIST-generated data into the input wrapper chain and incorporates the captured
output wrapper chain data into the MISR, as shown in Figure 2-15.
Figure 2-15 Isolating the Self-Test Design Using Core Wrapping
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If your design already implements wrapper chains, you use this approach by default.

Isolating the Design During LogicBIST Self-Test 2-15
K-2015.06-SP4
If the I/O ports in your design are mostly registered, you can reuse the existing I/O registers
to build the wrapper chain, which minimizes area. This is called the maximized-reuse flow.
If the self-test design drives top-level logic that cannot tolerate pseudorandom output data
during self-test, you can specify safe values to be driven at the outputs during self-test.
See Also
Configuring Wrapper Chain Isolation Logic on page 3-5 for details on using wrapper
chains for self-test isolation
Isolating the Self-Test Design Using User-Defined Test Points

To reduce area, you can use user-defined test points instead of core wrapping to provide
boundary testability. For example, you can use force_01 test points at the inputs and
observe test points at the outputs, as shown in Figure 2-16.
Figure 2-16 Isolating the Self-Test Design Using User-Defined Test Points
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Multiple test points can share a single test-point register, which reduces the area.
Use this isolation method only if your design is not already core-wrapped.
Note:
If the I/O ports in your design are mostly registered, a maximized-reuse wrapper chain
might require less area than adding test points.
See Also
Configuring User-Defined Test Point Isolation Logic on page 3-6 for details on using
test points for self-test isolation

Isolating the Design During LogicBIST Self-Test 2-16
Providing Testability for LogicBIST Self-Test

During LogicBIST self-test, no X values can be captured during testing. If an X value
reaches the MISR, it recirculates and spreads within the MISR, corrupting its value. The
following topics describe ways to keep the design clean of X values:
Enabling DFT Logic During Autonomous Self-Test
Blocking Internal X Sources
Ensuring Testability for Reset Signals
Ensuring Testability for Clock-Gating Cells
Enabling DFT Logic During Autonomous Self-Test

When a LogicBIST core performs autonomous self-test, its LBIST_EN signal is asserted
while its test-mode signals are set to the mission-mode encoding. To ensure that testability
logic inside the core is enabled during autonomous self-test, the LogicBIST test-mode
output of the test control module (TCM) is asserted during self-test, as shown in Figure 2-17.
Figure 2-17 Test Control Module (TCM) in a LogicBIST Design
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This enables all testability logic controlled by the DFT-inserted TCM, such as reconfiguration
MUXs, wrapper chains, and so on.
If you have testability logic in your RTL that is enabled directly from test-mode input ports,
you must also enable it during autonomous self-test when the LBIST_EN signal is asserted,
as shown in Figure 2-18. (In TetraMAX mode, the RTL testability logic is activated by the
DFT_TM signal instead of the LBIST_EN signal.)

Providing Testability for LogicBIST Self-Test 2-17
K-2015.06-SP4
Figure 2-18 RTL Testability Logic in a LogicBIST Design
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assign nRST = (DFT_TM || LBIST_EN) ? RSTN : nRSTgen;
Blocking Internal X Sources

If you have X sources inside your design, you must block them during LogicBIST operation
to ensure they do not corrupt the MISR.
If you have nonscan cells that capture values from scan cells, you might be able to use the
loadable nonscan cell feature in TetraMAX ATPG to prevent the nonscan cells from driving
X values. For more information, see Using Loadable Nonscan Cells in TetraMAX Help.
If you have black-box macro cells or memories without test models, you must insert
X-blocking logic in your RTL.
Ensuring Testability for Reset Signals

Asynchronous reset (and set) signals are defined using the set_dft_signal command:
set_dft_signal -view existing_dft -type Reset \
-port RSTN -active_state 0
These signals are similar to clocks in that they cause sequential cells to capture a value. As
a result, you must ensure that there is no capture interaction between clock and reset
signals during LogicBIST operation.
If you have OCC-controlled clocks, you must use weighted clock capture groups to allocate
capture cycles between clocks and reset signals.

If all clocks are external (port-driven), you can choose either of the following:
Use the external clock controller and disable the reset signal during LogicBIST
operation.
Because all clocks capture on every cycle, this method improves clock capture efficiency
but does not provide coverage on the reset network.
Insert OCC controllers for the external clocks and use weighted clock capture groups to
allocate capture cycles between clocks and reset signals.
Because clocks and resets are separated into groups that avoid capture interactions, this
method provides coverage of the reset network but might increase pattern count.
Figure 2-19 shows the weighted clock/reset logic structure.

Figure 2-19 Using Weighted Capture Groups for Reset (or Set) Signals
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When LogicBIST operation is active,

The reset signal is deasserted during scan shift.
The reset signal is controlled by the clock/reset weight decoder during scan capture.
For a design with multiple reset signals, you typically include all reset signals in a single
reset group.
If your design uses external clocks, see Specifying OCC Controllers for External Clock
Sources in the On-Chip Clocking Support chapter of the DFT Compiler, DFTMAX, and
DFTMAX Ultra User Guide.
See Also
OCC-Controlled Clocks With Weighted Clock Capture Groups on page 2-12 for details
on how weighted capture groups work

K-2015.06-SP4
Ensuring Testability for Clock-Gating Cells

The tool automatically inserts testability logic for clock-gating cells when you define a
clock-gating scan-enable signal using the -usage clock_gating option of the
set_dft_signal command:
set_dft_signal -view spec -type ScanEnable \
-port SE_CG -usage clock_gating
Figure 2-20 shows the clock-gating cell testability logic structure.

Figure 2-20 LogicBIST Testability Logic for Clock-Gating Cells
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When LogicBIST operation is active,

The clock-gating scan-enable signal is asserted during scan shift.
The clock-gating scan-enable signal is controlled by a dedicated testability scan cell
during scan capture.
If you declare multiple clock-gating scan-enable signals, the tool inserts a separate control
register for each signal declaration.

3
Using LogicBIST Compression 3
To use LogicBIST compression, you specify the desired number of compressed chains and
scan patterns to run. The tool synthesizes the scan and BIST circuitry and writes the
architectural information to the SPF file. The TetraMAX tool then computes seed and
signature values, which are used for both testbench simulation and autonomous device
self-test operation.
This chapter includes the following topics:
Configuring LogicBIST Compression
Previewing and Inserting the LogicBIST Implementation
Computing the Seed and Signature Values in TetraMAX
Setting the Seed and Signature Values in Synthesis
Simulating Autonomous BIST Operation
Connecting LogicBIST Self-Test to Functional Design Logic
Example LogicBIST Scripts
3-1
K-2015.06-SP4
Configuring LogicBIST Compression

LogicBIST configuration is described in the following topics:
Defining the LogicBIST Control Signals
Defining the LogicBIST Compression Mode
Configuring the PRPG and MISR Lengths
Configuring the Pattern Counter and Shift Counter Lengths
Configuring Clock and Reset Weights
Configuring Self-Test Isolation Logic
Inserting LogicBIST in Designs With Trailing-Edge Flip-Flops
Defining the LogicBIST Control Signals

You can define the LogicBIST-specific signals (LBIST_EN, START, STATUS_0, STATUS_1)
on existing ports using the following signal types:
set_dft_signal -view spec -port my_enable -type lbistEnable
set_dft_signal -view spec -port my_start -type lbistStart
set_dft_signal -view spec -port my_status0 -type lbistStatus_0
set_dft_signal -view spec -port my_status1 -type lbistStatus_1
You can also define these signals on internal pins using the -hookup_pin option.
If you do not define these signals, the tool automatically creates them using the following
signal port names: LBIST_EN, START, STATUS_0, STATUS_1.
Defining the LogicBIST Compression Mode

Commands and command options related to LogicBIST compression use the word
logicbist. To enable LogicBIST compression insertion, simply enable LogicBIST
compression as follows:
dc_shell> set_dft_configuration -logicbist enable
Chapter 3: Using LogicBIST Compression

Configuring LogicBIST Compression 3-2
To define the LogicBIST compression mode, define a LogicBIST compression mode by

specifying a usage of logicbist, then configure it and specify the LogicBIST clock using
the set_logicbist_configuration command.
The following example script is for a design that uses core wrapping for boundary testability:
# enable scan compression
set_dft_configuration -logicbist enable
# define the uncompressed inward-facing mode and its

# corresponding inward-facing scan compression mode
define_test_mode -usage wrp_if WRP_IF
define_test_mode -usage logicbist LBIST
# configure uncompressed scan mode

set_scan_configuration -test_mode WRP_IF -chain_count 2
# configure LogicBIST compression mode

set_logicbist_configuration \
-base_mode WRP_IF -test_mode LBIST \
-clock CLK1 \
-chain_count 32
You must explicitly configure the LogicBIST codec using the -chain_count or
-max_length option of the set_logicbist_configuration command; there is no default
for these options.
To ensure that the LogicBIST mode can use the two required user-defined scan-in signals,
the chain count of the underlying base mode must be set to a minimum of two.
If your design has multiple scan clocks, you can use the -clock option to specify which
clock to use for LogicBIST operation. The specified clock must be previously defined as a
scan clock using the set_dft_signal command. The default is the first-defined scan clock.
Configuring the PRPG and MISR Lengths

By default, the tool chooses the PRPG and MISR register widths. To specify a particular
width for the PRPG or MISR register, use the following options:
-prpg_width width_value \
-misr_width width_value
In some cases, the PRPG might be one bit wider than the specified value due to PRPG
architecture requirements.

K-2015.06-SP4
Configuring the Pattern Counter and Shift Counter Lengths

By default, the tool creates a pattern counter register with a width of 8, which allows up to
256 patterns. To specify a particular width for the pattern counter register, use the following
option:
-pattern_counter_width width_value
By default, the tool sizes the shift counter register according to the longest shift chain in the
design. To change the shift counter width, use the following option:
-shift_counter_width width_value
You normally do not need to specify this value.
Configuring Clock and Reset Weights

If your design requires weighted clock capture groups to be used, use the
-occ_clock_weights option to define them:
set_logicbist_configuration ... \
-occ_clock_weights {{weight1 clock1 [clock2 ...]} \
{weight2 clock3 [clock4 ...]} \
...}
The -occ_clock_weights option takes a list of group definitions, where each group is itself
a list containing a weight value followed by the OCC-controlled clock signals in that group.
If you also have asynchronous reset (or set) signals, specify their weights with the
-reset_weights option using the same group syntax. Typically there is a single reset
group.
For example,
-occ_clock_weights {{80 UPLL/CLKO CLK33} {44 CLK266}} \
-reset_weights {{4 RSTN1 RSTN2}}
The weight values must be positive integers. There is no fixed scale for the weights; each
group's capture probability is relative to the sum of all clock and reset group weights.
However, the weight comparator logic uses a 7-bit PRPG word. Thus, the most accurate
total weight values are powers of 2, from 2 to 128. For other total weight values, the weights
are remapped to comparator values between 0 and 127, which might perturb the
probabilities due to rounding errors.

You can also specify two special weight values, always_on and always_off, for clocks that
should always pulse or never pulse, respectively. These values do not affect the sum of all
numeric clock and reset group weights.
Configuring Self-Test Isolation Logic

The following topics describe how to configure logic that isolates your design from
surrounding logic during self-test operation:
Configuring Wrapper Chain Isolation Logic
Configuring User-Defined Test Point Isolation Logic
Configuring Wrapper Chain Isolation Logic

Wrapper chains inherently provide the isolation needed by self-test operation. If your design
already implements wrapper chains, no further action is needed. Otherwise, you can enable
and configure wrapper chains.
To use wrapper chains for self-test isolation, do the following:
1. Enable both the core wrapper and LogicBIST clients:
set_dft_configuration -wrapper enable -logicbist enable
2. Define global DFT signals, wrapper configuration settings, and LogicBIST configuration
settings.
Any logic between the I/O ports and wrapper chain cannot be tested by LogicBIST
self-test. To minimize such logic, either use the simple wrapper flow, or use the
maximized-reuse flow and specify a low value for the -depth_threshold option of the
set_wrapper_configuration command.
3. If the self-test design drives top-level logic that cannot tolerate pseudorandom output
data during self-test, specify safe values for the output wrapper cells:
# global:
set_wrapper_configuration -class core_wrapper \
-safe_state 0 ;# or 1
# per-port:
set_boundary_cell -class core_wrapper \
-ports port_list -safe_state 0 ;# or 1
4. Define the uncompressed wrapper modes, scan compression modes, and LogicBIST
self-test modes:
define_test_mode WRP_IF -usage wrp_if
define_test_mode WRP_OF -usage wrp_of

K-2015.06-SP4
define_test_mode DFTMAX -usage scan_compression

define_test_mode BIST -usage logicbist
5. When configuring the LogicBIST test mode, reference the inward-facing uncompressed
test mode as its base mode:
set_logicbist_configuration -test_mode BIST -base_mode WRP_IF ...
The LogicBIST test mode becomes an inward-facing mode that drives LogicBIST-generated
data into the input wrapper chain, and incorporates the captured output wrapper chain data
into the MISR. As with other DFT signals, LogicBIST-specific signals (LBIST_EN, START,
STATUS_0, and STATUS_1) are not wrapped.
See Also
Isolating the Self-Test Design Using Core Wrapping on page 2-15 for details on how
core wrapping provides design isolation
Example Core Insertion Script Using Core Wrapping on page 3-15 for an example
script
Configuring User-Defined Test Point Isolation Logic

If your design is very area-sensitive and is not already core-wrapped, you can isolate the
design using user-defined test points instead of a wrapper chain.
Note:
If the I/O ports in your design are mostly registered, a maximized-reuse wrapper chain
might require less area than adding test points.
To use user-defined test points for self-test isolation, do the following:
1. Choose an existing clock to use for the test-point registers.
If your design contains an OCC controller, use the OCC-controlled clock source as the
test point clock; DFT insertion uses the corresponding OCC-controlled clock for the test
points. If your design contains multiple OCC-controlled clocks with clock weights, choose
the clock that best meets your design requirements.
An existing clock is required because otherwise, the tool creates a separate test-point
clock, which can create cross-domain capture paths that introduce Xs into the design.
2. Determine (or create) a LogicBIST test-mode signal to be asserted only during
LogicBIST mode (and not manufacturing test modes). This signal cannot be used by test
points used for manufacturing test:
set_dft_signal -view spec -type TestMode -port TM_BIST
Do not include this port in the test-mode encodings defined with the define_test_mode
command.

3. Make a collection or list of all input ports that capture input data values. Do not include
clock, asynchronous set or reset, or DFT signals.
set list_of_functional_data_inputs ...
4. Specify user-defined force_01 test points to be inserted at these input ports:

# add force_01 test points to functional data inputs
# (non-clock, non-reset, non-DFT inputs)
set_test_point_element \
-type force_01 \
-clock_signal CLK \
-control_signal TM_LBIST \
$list_of_functional_data_inputs \
-test_points_per_source_or_sink 32
Here, the -test_points_per_source_or_sink option specifies how many force_01

test points share the same source data register. Larger values reduce area; smaller
values provide better input controllability.
The set_test_point_element command accepts only lists, not collections. If needed,
use the get_object_name command to convert a collection to a list.
5. Make a collection or list of all output ports that drive output data values. Do not include
output clock or DFT signals.
set list_of_functional_data_outputs ...
6. Specify user-defined observe test points to be inserted at these output ports:

# add observe test points to functional data outputs
# (non-clock, non-DFT outputs)
set_test_point_element \
-type observe \
-clock_signal CLK \
$list_of_functional_data_outputs \
-test_points_per_source_or_sink 32
Here, the -test_points_per_source_or_sink option specifies how many observe

test points share the same sink data register. For observe test points, you can usually set
this option to its maximum of 32 without impacting coverage.
See Also
Connecting LogicBIST Self-Test to Functional Design Logic on page 3-13 for details on
controlling these test points from the functional logic
Isolating the Self-Test Design Using User-Defined Test Points on page 2-16 for details
on how user-defined test points provide design isolation
Example Core Insertion Script Using User-Defined Test Points on page 3-16 for an
example script

K-2015.06-SP4
Inserting LogicBIST in Designs With Trailing-Edge Flip-Flops

The PRPG register in the LogicBIST decompressor is clocked on the leading edge. If your
design has trailing-edge flip-flops, you must enable beginning retiming registers by setting
the set_scan_configuration -add_test_retiming_flops option to begin_only (or
begin_and_end). If you do not do this, incorrect scan structures are built with no error or
warning.
The beginning retiming registers inserted between the LogicBIST decompressor and
trailing-edge head scan cells have a state-holding loop that is used during scan capture.
If you also enable ending retiming flip-flops, the ending retiming registers inserted between
trailing-edge tail scan cells and the LogicBIST compressor are regular non-state-holding
retiming registers. They are inserted even though the path to the leading-edge MISR
register would make timing without them, so a value of begin_only is preferred for minimal
area.
Previewing and Inserting the LogicBIST Implementation

After you have configured your LogicBIST implementation, use the preview_dft command
to preview the implementation. The preview report contains a LogicBIST section that
describes the user-specifiable values. For example,
****************************************
LogicBIST Compression
User signals information

****************************************
Shift counter data:

top_U_LogicBISTController_bist/shift_count_data = 4'b1000
Pattern counter data:
top_U_LogicBISTController_bist/user_pattern_count_data = 4'b0000
PRPG seed data:
top_U_decompressor_bist/user_prpg_seed =
32'b00000000000000000000000000000000
MISR signature data:
top_U_compressor_bist/user_misr_signature =
30'b000000000000000000000000000000
****************************************
The pattern counter, PRPG seed, and MISR signature value are set to all-zeros in the initial
implementation; these values are determined later in TetraMAX. The shift counter is
automatically set according to the longest scan chain length in LogicBIST mode.
When you are satisfied with your DFT configuration, run the insert_dft command. Do not
run an explicit incremental compile yet.

Previewing and Inserting the LogicBIST Implementation 3-8
Writing Out the LogicBIST Design Files

After DFT insertion, write out the design netlist, SPF, and testbench file using the following
commands:
# write out design netlist
write -format verilog -output top_no_seed_signature.vg -hierarchy
# write protocol for TetraMAX to calculate seed/signature

write_test_protocol -test_mode LBIST -output LBIST.spf
# write testbench for Verilog simulation to validate

# LogicBIST implementation
#
# (this command produces logicbist.stil)
write_test -format stil -output bist_tb
These files serve the following purposes:

The write_test_protocol command creates an SPF used by TetraMAX ATPG to
compute the seed and signature values in TetraMAX mode. This SPF does not simulate
the actual autonomous LogicBIST test process; instead, it asserts the TetraMAX mode
enable signal so that TetraMAX ATPG can access the LogicBIST configuration registers
through scan to evaluate seed values.
The write_test command creates a STIL pattern file that can be used to simulate the
LogicBIST logic in autonomous mode with the TetraMAX mode enable signal
deasserted.
Autonomous BIST operation cannot be simulated until the design netlist is updated with
seed, signature, and pattern count values, as described in Setting the Seed and
Signature Values in Synthesis on page 3-10.
Post-DFT DRC (running the dft_drc command after DFT insertion) is supported for
LogicBIST designs. DRC checking is also performed in the TetraMAX tool during seed and
signature calculation.
If desired, you can leave your synthesis session up while you generate seed and signature
values in TetraMAX, then return to the synthesis session to set the seed and signature
values.

Previewing and Inserting the LogicBIST Implementation 3-9
K-2015.06-SP4
Computing the Seed and Signature Values in TetraMAX

To calculate the seed and signature value in TetraMAX ATPG, use the initial netlist and
LogicBIST-mode SPF. For example,
read_netlist -library /project/libs/my_class.v
read_netlist top_no_seed_signature.vg
run_build top
# Enable LogicBIST DRC

set_drc -seq_comp_jtag_lbist_mode light_lbist
run_drc LBIST.spf
# Run LogicBIST ATPG for 133 patterns and 1 capture clock cycle
run_atpg -auto -jtag_lbist {1 133 1}
run_simulation
report_patterns -all
# write serial STIL file containing seed and signature values

write_patterns serial.stil -format stil -replace -unified -serial
The values provided to the -jtag_lbist option are: number of seed values (always 1),
pattern count, number of capture cycles (usually 1). The maximum pattern count value is
(2^pattern_count_width)-2, to allow for an additional load-only pattern at the beginning of
self-test.
The run_atpg command uses seed values from a pseudorandom sequence of seed values.
To evaluate a new seed value, run the run_atpg command again. Identical TetraMAX
sessions yield the same sequence of seed values.
After ATPG completes, the serial.stil pattern file contains the seed, signature, pattern
counter, and shift counter values for the test, provided in STIL annotation comments.
Note that the write_testbench command in the TetraMAX tool writes a testbench that uses
TetraMAX mode to externally access seed and signature values. It does not write a
testbench that tests autonomous LogicBIST operation, as the write_test command does.
See Also
SolvNet article 2220819, Identifying an Optimal Seed Value for the LogicBIST PRPG
for details on evaluating multiple seed values to find the best one
Setting the Seed and Signature Values in Synthesis

After you write the serial STIL pattern file from TetraMAX, you can use the file to hardcode
the seed, signature, and pattern counter constant values in your design. You can do this in

Computing the Seed and Signature Values in TetraMAX 3-10
the same DFT session where you wrote out the files for TetraMAX ATPG. If that session is
no longer running, reload the design from a .ddc file.
To set the constant values in the design to the values contained in the serial STIL file, use
the set_logicbist_constants command:
dc_shell> set_logicbist_constants -file_name serial.stil
Found LogicBIST controller for 'LBIST' test mode.
Obtained data from 'serial.stil' file.
Verifying shift counter value is set to '1011'...

Verified top_U_LogicBISTController_LBIST/shift_count_data[3] is set to logic 1
Setting pattern counter value to '000001100101'...
Setting PRPG seed value to '1101011000000100111100100000110'...
Setting MISR signature value to '100011110010000110000111111011'...
The command also verifies that the shift counter constant values (set by the insert_dft
command) match the values in the STIL file.
After setting the constants, write out the final netlist:
dc_shell> write -format verilog -output top.vg -hierarchy
Once you have set the constant values, the serial STIL pattern file is no longer needed. The
LogicBIST simulation is performed using only the testbench created by the write_test
command in the tool.
Note:
This automation works only for seed, signature, and pattern counter values that are set
to constants (the default). You must create your own initialization protocol to initialize any
programmable values implemented as described in Using Programmable LogicBIST
Configuration Values on page 4-1.
You can now run an incremental compile to optimize the DFT logic. For more information,
see Post-DFT Design Optimization on page 4-6.
See Also
SolvNet article 2231010, Setting the Seed and Signature Constant Values in a
LogicBIST Design to obtain the set_logicbist_constants Tcl procedure

Setting the Seed and Signature Values in Synthesis 3-11
K-2015.06-SP4
Simulating Autonomous BIST Operation

To simulate autonomous LogicBIST operation in VCS, create a testbench from the STIL file
generated by the write_test command in synthesis. To do this, use the stil2verilog
command:
% stil2verilog bist_tb.stil bist_tb
This generates a Verilog testbench file (bist_tb.v) and associated data file (bist_tb.dat). You
can now simulate autonomous operation using this testbench along with the final netlist.
An example VCS command line is as follows:
vcs \
-notice -Mupdate -timescale=1ns/10ps \
+nospecify +notimingcheck +tetramax +delay_mode_zero \
-l vcs_lbist.log \
-v libs/class.v \
bist_tb.v \
top.vg
./simv -l vcs_sim_lbist.log
For other simulators, see their documentation.

The resulting simulation should complete with no errors:
% ./simv -l vcs_sim_lbist.log
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version J-2014.12-SP2; Runtime version J-2014.12-SP2; Jun 23 15:34 2015
#############################################################################
MAX TB Version K-2015.06
Test Protocol File generated from original file "bist_tb.stil"
STIL file version: 1.0
#############################################################################
XTB: Starting serial simulation of 0 pattern

XTB: Simulation of 0 patterns completed with 0 mismatches (time: 6144800.00 ns,
cycles: 61448)
V C S S i m u l a t i o n R e p o r t
Time: 6144800 ns
If the design logic is modified, the simulation should complete with unexpected values on the
STATUS_0 output:
% ./simv -l vcs_sim_lbist.log
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version J-2014.12-SP2; Runtime version J-2014.12-SP2; Jun 23 15:34 2015

Simulating Autonomous BIST Operation 3-12
#############################################################################
MAX TB Version K-2015.06
Test Protocol File generated from original file "bist_tb.stil"
STIL file version: 1.0
#############################################################################
XTB: Starting serial simulation of 0 pattern

>>> Error during VectorStmt pattern 0
>>> At T=6144540.00 ns, V=61446, exp=0, got=1, signal STATUS_0
>>> Error during VectorStmt pattern 0
>>> At T=6144640.00 ns, V=61447, exp=0, got=1, signal STATUS_0
XTB: Simulation of 0 patterns completed with 2 mismatches (time: 6144800.00 ns,
cycles: 61448)
V C S S i m u l a t i o n R e p o r t
Time: 6144800 ns
See Also
Using MAX Testbench in TetraMAX Help for more information on the stil2verilog
command
Connecting LogicBIST Self-Test to Functional Design Logic

To connect LogicBIST self-test logic to your functional design logic, connect the signal pins
shown in Table 3-1 to your preexisting design logic.
Table 3-1 LogicBIST Self-Test Signals
Signal type Required Description

or optional
lbistEnable Required Enables autonomous self-test during mission mode
lbistStart Required Begins autonomous self-test
lbistStatus_0 Required Reports current self-test status (idle, running, pass, fail)
lbistStatus_1
lbistPatternCount Optional Specifies the number of self-test patterns to run
lbistShiftLength Optional Specifies the number of shift cycles in each pattern
lbistSeedValue Optional Specifies the initial seed value loaded into the PRPG
lbistSignatureValue Optional Specifies the expected final signature value of the MISR

Connecting LogicBIST Self-Test to Functional Design Logic 3-13
K-2015.06-SP4
Table 3-1 LogicBIST Self-Test Signals (Continued)
Signal type Required Description

or optional
lbistBurnInEnable Optional Enables burn-in mode using self-test logic
lbistBurnInStopOnFail Optional Specifies whether burn-in mode should stop or continue

upon failure
For LogicBIST signals connected by DFT insertion to input and output ports of the core
module, the connections should preexist (or be manually made) at the next hierarchical level
where the core is integrated, as shown in Figure 3-1.
Figure 3-1 Connecting LogicBIST Self-Test Port Signals at the Top Level
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For LogicBIST signals that connect to hookup pins inside the core module, the connections
are made inside the core itself during DFT insertion, as shown in Figure 3-2. The hookup
pins can be pins of leaf cells or hierarchical cells.
Figure 3-2 Connecting LogicBIST Self-Test Hookup Pin Signals Inside the Core
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You can use a mix of port-connected and hookup-pin-connected signals as needed.

If you have test points used only in self-test mode (and not in manufacturing test modes),
connect their test-mode control signal to the lbistEnable signal. This connection should

Connecting LogicBIST Self-Test to Functional Design Logic 3-14
preexist (or be manually made) prior to DFT insertion, as DFT insertion does not modify
existing test-mode signal connections.
You do not need to connect any scan-in, scan-out, or test-mode signals to your functional
design logic. LogicBIST self-test automatically enables any required DFT logic during
autonomous mode, as described in Enabling DFT Logic During Autonomous Self-Test on
page 2-17.
See Also
Isolating the Self-Test Design Using User-Defined Test Points on page 2-16 for details
on how user-defined test points provide design isolation
Example LogicBIST Scripts

This section provides the following example scripts:
Example Core Insertion Script Using Core Wrapping
Example Core Insertion Script Using User-Defined Test Points
Example Script to Automatically Set Seed and Signature Values
Example Core Insertion Script Using Core Wrapping

This example script uses core wrapping to isolate the core during LogicBIST operation.
read_verilog ./top.v
current_design top
link
compile -scan
# define DFT signals

set_dft_signal -view spec -type ScanDataIn -port {SI1 SI2}
set_dft_signal -view spec -type TestMode -port {LBIST_TM}
set_dft_signal -view existing_dft -type MasterClock -port CLK1 \
-timing {45 55}
-timing {45 55}
set_dft_signal -view existing_dft -type Reset -port RSTN -active 0
# enable clients
set_dft_configuration -logicbist enable -wrapper enable
# define and configure test modes

define_test_mode SCAN -usage wrp_if -encoding {LBIST_TM 0}
define_test_mode LBIST -usage logicbist -encoding {LBIST_TM 1}
set_scan_configuration -test_mode SCAN -chain_count 2 \

Example LogicBIST Scripts 3-15
K-2015.06-SP4
-clock_mixing mix_clocks
set_logicbist_configuration -test_mode LBIST -base_mode SCAN \
-chain_count 32 \
-pattern_counter_width 16 ;# maximum of 2^16 patterns
# preview and insert DFT

create_test_protocol
dft_drc
preview_dft -show all
insert_dft

# write test protocol for TetraMAX to calculate seed/signature


#
# (this command produces testbench.stil)
Example Core Insertion Script Using User-Defined Test Points

This example uses the all_functional_data_inputs and all_functional_data_outputs variables
to indicate the set of inputs and outputs to control and observe, respectively.
read_verilog ./top.v
current_design top
link
compile -scan
# define DFT signals

set_dft_signal -view spec -type ScanDataIn -port {SI1 SI2}
set_dft_signal -view spec -type TestMode -port {TM_LBIST}
-timing {45 55}
-timing {45 55}
set_dft_signal -view existing_dft -type Reset -port RSTN -active 0
# enable clients
set_dft_configuration -logicbist enable
# configure input and output test points

# (in place of using core wrapping)
set_test_point_element -type force_01 \
$all_functional_data_inputs \
-test_points_per_source_or_sink 32 \
-clock_signal CLK1 \

-control_signal TM_LBIST
set_test_point_element -type observe \
$all_functional_data_outputs \
-test_points_per_source_or_sink 32 \
-clock_signal CLK1
# define and configure test modes

define_test_mode SCAN -usage scan
define_test_mode LBIST -usage logicbist
set_scan_configuration -test_mode SCAN -chain_count 2 \
-clock_mixing mix_clocks
set_logicbist_configuration -test_mode LBIST -base_mode SCAN \
-chain_count 32 \
-pattern_counter_width 16 ;# maximum of 2^16 patterns
# preview and insert DFT

create_test_protocol
dft_drc
preview_dft -show all
insert_dft



#
Example Script to Automatically Set Seed and Signature Values

The following script excerpt shows how to automate TetraMAX seed and signature
computation, netlist modification, and testbench creation. The commands prior to the
insert_dft command are omitted.
Note:
Using the Tcl exec command requires the current process to be forked, which can
require a lot of memory when large designs are loaded.
# ...previous commands omitted...
insert_dft



K-2015.06-SP4

#
# create Verilog testbench file

#
# (this command produces bist_tb.v and bist_tb.dat)
exec stil2verilog -replace bist_tb.stil bist_tb
# generate seed and signature value in TetraMAX

#
# (this command produces serial.stil)
exec tmax -shell ./tmax_bist.tcl
# set seed and signature values in design and write out final netlist
set_logicbist_constants -file_name serial.stil
write -f verilog -h -o top.vg
quit
The following script is the tmax_bist.tcl script referenced by the preceding synthesis script.
read_netlist top_no_seed_signature.vg
run_build top

run_drc LBIST.spf
run_simulation

write_patterns serial.stil -format stil -replace -unified -serial
quit ;# required to resume execution in dc_shell

4
Advanced LogicBIST Configuration 4
This chapter describes advanced features that can be used while inserting LogicBIST
self-test circuitry into your design. These features can be used to improve self-test flexibility
and reduce the implementation area.
This chapter includes the following topics:
Using Programmable LogicBIST Configuration Values
Simplifying the MISR XOR Compressor
Simplifying the Weighted Capture Groups Comparator
Configuring the Clock-Gating Logic
Implementing Burn-In Mode
Post-DFT Design Optimization
Using Programmable LogicBIST Configuration Values

By default, the tool implements the LogicBIST logic with placeholder buses in the netlist for
the following values:
User seed value - tied to logic 0 (eventually computed by TetraMAX)
User signature value - tied to logic 0 (eventually computed by TetraMAX)
4-1
K-2015.06-SP4
User pattern value - tied to logic 0 (eventually computed by TetraMAX)

User shift value - automatically set to the longest shift chain length by DFT insertion (but
can be overridden if needed)
Instead of setting these to hardcoded constant values in the netlist, you can drive these from
ports or internal hookup pins so that the values are programmable. To do this, define DFT
signals using the following signal types:
set_dft_signal -view spec -type lbistSeedValue ...
set_dft_signal -view spec -type lbistSignatureValue ...
set_dft_signal -view spec -type lbistPatternCount ...
set_dft_signal -view spec -type lbistShiftLength ...
You can use the -port or -hookup_pin option when defining these signals. For each signal
type, define the individual signal bits in order of most significant bit to least-significant bit.
The most common application would be to drive the signals from existing design registers.
For example,
# define a 31-bit initial PRPG seed register
for {set i 30} {$i >= 0} {incr i -1} {
set_dft_signal -view spec -type lbistSeedValue \
-hookup_pin CONFIG/SEED_reg[${i}]
}
# define a 32-bit MISR expected signature register

for {set i 31} {$i >= 0} {incr i -1} {
set_dft_signal -view spec -type lbistSignatureValue \
-hookup_pin CONFIG/SIGNATURE_reg[${i}]
}
When you define internally driven LogicBIST configuration signals, the preview_dft
command reports the connections on a bitwise basis so you can confirm their correctness.
For example,
****************************************
LogicBIST Compression
User signals information

****************************************
Shift counter data: top_U_LogicBISTController_bist/shift_count_data = 4'b1000

Pattern counter data: top_U_LogicBISTController_bist/user_pattern_count_data = 4'b0000
SEED CONNECTIONS:
*****************
CONFIG/SEED_reg[0] connected to top_U_decompressor_bist/user_prpg_seed[0]
...
EXPECTED SIGNATURE CONNECTIONS:

*******************************
Chapter 4: Advanced LogicBIST Configuration

Using Programmable LogicBIST Configuration Values 4-2
CONFIG/SIGNATURE_reg[0] connected to top_U_compressor_bist/user_misr_signature[0]

...
Simplifying the MISR XOR Compressor

When the number of internal chains is equal to the MISR size, the XOR compressor inside
the LogicBIST compressor is automatically removed and a direct connection is performed
between the compressed scan chains and the MISR.
Set the following options of the set_logicbist_configuration command to the same
value to implement this simplification:
set_logicbist_configuration ... \
-chain_count chain_count_value \
-misr_width chain_count_value
There is no equivalent removal of the XOR phase shifter in the LogicBIST decompressor
because it is needed to remove correlations from the LFSR values.
Simplifying the Weighted Capture Groups Comparator

Weighted clock/reset capture groups use a seven-bit comparator/decoder driven by the first
seven bits of the clock chain (clk_chain_val[6:0]). Any arbitrary positive group weight values
can be specified, but the values are scaled (if needed) to a total weight of 128 for
implementation.
Thus, certain weight conventions simplify the comparator logic. For example,
Two groups, each with a weight of 50%, use comparator ranges that are 64 values wide,
which requires only clk_chain_val[6].
Groups using weights that are a multiple of 25% use comparator ranges that are 32
values wide, which requires only clk_chain_val [6:5].
Weight values that result in boundary (comparator) values with a longer sequence of
least-significant zeros, like 32 (7'b0100000) or 96 (7'b1100000), require less comparator
logic than boundary values with a shorter sequence of least-significant zeros, like 34
(7'b0100010) or 98 (7b'1100010).
If your design is area sensitive, you can consider this effect while determining weight values
that meet your coverage requirements.

Simplifying the MISR XOR Compressor 4-3
K-2015.06-SP4
Configuring the Clock-Gating Logic

The LogicBIST architecture uses clock gating for the following constructs to reduce area and
power consumption:
MISR
PRPG
Pattern counter
Shift counter
LogicBIST clock controller (external or OCC)
By default, the tool builds discrete clock-gating logic using separate latch and combinational
gate cells. To use integrated clock-gating cells (ICGs) instead, enable ICG insertion and
specify the desired ICG library cell using the following variables:
set_app_var test_occ_insert_clock_gating_cells true
set_app_var test_icg_p_ref_for_dft ICG_library_cell
Implementing Burn-In Mode

LogicBIST provides a burn-in mode feature that runs autonomous self-test continuously as
long as the START signal is asserted. The scan and capture activity stresses the tested logic
and causes continuous power draw during self-test. Power consumption can be controlled
by adjusting the clock frequency.
Burn-in operation is configured by two DFT signals, described in Table 4-1.
Table 4-1 Burn-In Configuration Configuration Signals and Behaviors
Self-test detected failure? lbistBurnInEnable lbistBurnInStopOnFail

signal value signal value
No 1 X
67$786B
67$786B
5811,1* 3$66 ,'/( 5811,1*

Configuring the Clock-Gating Logic 4-4
Table 4-1 Burn-In Configuration Configuration Signals and Behaviors (Continued)
Self-test detected failure? lbistBurnInEnable lbistBurnInStopOnFail

signal value signal value
Yes 1 0
67$786B
67$786B
5811,1* )$,/ ,'/( 5811,1*
Yes 1 1
67$786B
67$786B
5811,1* )$,/
When the lbistBurnInEnable signal is deasserted, the LogicBIST engine runs in its normal
mode of operation to completion, generating the pass or fail indication as described in The
STATUS_0 and STATUS_1 Signals on page 2-7.
The burn-in capability is not implemented by default. To implement it, specify the following
option:
dc_shell> set_logicbist_configuration -burn_in enable
Define the burn-in configuration signals on existing ports using the following signal types:
dc_shell> set_dft_signal -view spec \
-type lbistBurnInEnable -port my_burnin_enable
dc_shell> set_dft_signal -view spec \
-type lbistBurnInStopOnFail -port my_burnin_SOF
You can also define these signals on internal pins using the -hookup_pin option.
If you do not define these signals, the tool automatically creates them using the following
signal port names: burnin_mode, fail_mode.
The burn-in capability is implemented by modifying existing states in the BIST state machine
rather than adding states; the area overhead is negligible.

Implementing Burn-In Mode 4-5
K-2015.06-SP4
Post-DFT Design Optimization

LogicBIST compression provides some unique considerations in the synthesis flow. BIST is
often used in area-sensitive designs. Propagating the seed and signature values as
hardcoded constants into the design logic yields an area savings, but at the cost of no longer
being able to change their values (such as for a functional ECO).
These aspects of post-DFT optimization are described in more detail in the following topics:
Post-DFT Optimization and BIST Constants
Preserving the BIST Constants in a compile Flow
Preserving the BIST Constants in a compile_ultra Flow
Regenerating Seed and Signature Values after Design Changes
Ungrouping LogicBIST Blocks for Additional Area Reduction
Post-DFT Optimization and BIST Constants

LogicBIST compression requires that the values in Table 4-2 be specified in the design logic.
Table 4-2 User-Specified LogicBIST Constant Values
BIST value Hierarchical bused pins
PRPG seed design_U_decompressor_mode/user_prpg_seed[*]
MISR signature design_U_compressor_mode/user_misr_signature[*]
Pattern count design_U_LogicBISTController_mode/user_pattern_count_data[*]
Shift count
1 design_U_LogicBISTController_mode/shift_count_data[*]
1. This value is set by DFT insertion and does not need to be user-modified (unless the BIST mode
scan length is manually changed later in the flow). Accordingly, this bus name has no user_ prefix.
These values are set in the design after determining the values in TetraMAX ATPG, as
described in Setting the Seed and Signature Values in Synthesis on page 3-10.
By default, these BIST values are driven by constants. If post-DFT optimization propagates
these BIST constants into the design, they become permanently integrated into the logic
and their values cannot be changed, as shown in Figure 4-1.

Post-DFT Design Optimization 4-6
Figure 4-1 BIST Constant Propagation Into Block Logic
Q

E
Q
Q

E
Q

E
This prevents you from performing design ECOs later in the flow, which would require new
seed and signature values to be set in the design.
If you use programmable (register-driven) values as described in Using Programmable
LogicBIST Configuration Values on page 4-1, you do not need to worry about constant
propagation for those values.
Preserving the BIST Constants in a compile Flow

The compile command does not propagate constants into DFT-created blocks (which have
the is_test_circuitry attribute set to true) when boundary optimization is enabled. The
only way to propagate such constants is to ungroup the DFT blocks, via the ungroup,
set_ungroup, or compile -auto_ungroup command.
To preserve the BIST constants, do not ungroup the LogicBIST controller, decompressor, or
compressor blocks.
See Also
Ungrouping LogicBIST Blocks for Additional Area Reduction on page 4-9 for
information on ungrouping the LogicBIST blocks
Preserving the BIST Constants in a compile_ultra Flow

By default, the compile_ultra command propagates constants into blocks, even
DFT-created blocks (which have the is_test_circuitry attribute set to true). To preserve
the BIST constants while allowing full optimization for the rest of the logic, disable constant
propagation specifically on these pins, which a "user_" name prefix:
# disable constant propagation for BIST constants
# (these pins have a "user_" prefix)
set_compile_directives -constant_propagation false \

K-2015.06-SP4
[get_pins -of [get_cells -hier * -filter {is_hierarchical == true && \

is_test_circuitry == true}] -filter {name =~ user_*}]
# perform post-DFT optimization

compile_ultra -scan -incremental
These commands do not prevent constant propagation on the shift_count_data[*] bus

because the shift length set by the insert_dft command does not typically need to be
changed and can be optimized into the logic. To allow for functional ECOs that affect the
shift length, disable constant propagation on this bus too.
To propagate the constants later in the flow, ungroup the LogicBIST blocks or reenable
constant propagation for the pins, then perform an incremental compile.
See Also
Ungrouping LogicBIST Blocks for Additional Area Reduction on page 4-9 for
information on ungrouping the LogicBIST blocks
Regenerating Seed and Signature Values after Design Changes

TetraMAX ATPG runs the LogicBIST design in TetraMAX mode to compute the seed and
signature values. TetraMAX mode requires that the pattern counter be set to 0, which is true
after the insert_dft command completes, but not after the design has been updated.
The seed and signature values must be regenerated if either of the following occur:
Scan chain reordering or repartitioning in layout
Design logic ECO
You must zero out the pattern counter before regenerating new seed and signature values.
This process requires that the seed and signature constant values have not been
propagated in the design.
The following script shows how to regenerate and apply new seed and signature values to
an ECO-modified design. No timing or DFT constraints are needed for this process. You
reuse the original testbench to simulate the updated netlist.
# read netlist containing ECO change and pre-ECO seed/signature values
read_verilog top_eco_oldseedsig.vg
current_design top
link
# zero out the pattern counter so TetraMAX DRC mode works

set_logicbist_constants -zero_values
# write out the zero-pattern ECO netlist

write -format verilog -hierarchy -output top_eco_zeroed.vg

# generate seed and signature values for the ECO netlist

exec tmax -shell ./tmax_bist_eco.tcl
# set seed and signature values in design and write out final netlist
set_logicbist_constants -file_name serial_eco.stil
write -format verilog -hierarchy -output top_eco.vg
The following script is the tmax_bist_eco.tcl script referenced by the preceding synthesis
script.
read_netlist top_eco_zeroed.vg
run_build top

run_drc LBIST.spf
run_simulation

write_patterns serial_eco.stil -format stil -replace -unified -serial
quit ;# required to resume execution in dc_shell
See Also
SolvNet article 2231010, Setting the Seed and Signature Constant Values in a
LogicBIST Design to obtain the set_logicbist_constants Tcl procedure
The LogicBIST Operational Modes on page 2-6 for more information on TetraMAX
mode versus autonomous mode
Ungrouping LogicBIST Blocks for Additional Area Reduction

After DFT insertion and seed and signature setting, you can achieve significant area
reduction by grouping the LogicBIST controller, clock or OCC controller(s), and codec
together, then ungrouping the hierarchy inside that block. This allows the control logic to be
highly optimized between those blocks while still containing the logic within a block. You can
use this technique with the compile or compile_ultra command.
The following commands perform this ungrouping. Hierarchical clock-gating cells are left
grouped. This example assumes that all cells to be grouped exist at the top level. Change
the "bist" suffix in the filter expression to match your LogicBIST test mode name.

K-2015.06-SP4
Important:
Ungrouping propagates the BIST constants, which prevents future modifications to their
values. Use this only when the design is finalized (including scan reordering) or when
you can re-perform synthesis and DFT insertion if the design logic changes.
# group LogicBIST controller and OCC blocks together into a new
# block named "LogicBIST"
group -cell_name LogicBIST -design_name LogicBIST \
[get_cells * -filter {ref_name == LOGICBIST_CONTROLLER ||
ref_name =~ top_DFT_clk_mux_* || name =~ *compressor_bist}]
# flatten everything in the new LogicBIST block except hierarchical

# clock-gating cells
set_ungroup [get_cells -hierarchical -filter {is_hierarchical == true
&& full_name =~ LogicBIST/* && full_name !~ *clkgt*}]
# incrementally compile
compile_ultra -scan -incremental

5
LogicBIST Limitations and Known Issues 5
This chapter contains the limitations and known issues that apply to LogicBIST
compression.
This chapter contains the following topic:
LogicBIST Limitations and Known Issues
5-1
K-2015.06-SP4
LogicBIST Limitations and Known Issues

The following requirements, limitations, and known issues apply to LogicBIST compression:
LogicBIST settings are not stored in .ddc files; you must apply any
set_logicbist_configuration settings if you read a pre-DFT .ddc file back in.
Designs that capture X values are not supported.

If any scan chains have head flip-flops that are clocked on the trailing edge, you must
enable beginning retiming registers by setting the set_scan_configuration
-add_test_retiming_flops option to begin_only (or begin_and_end) to avoid scan
timing issues from the leading-edge-clocked PRPG register.
The LogicBIST test mode requires two user-defined scan-in signals; they are not
automatically created. These signals are used as regular scan signals in other test
modes.
Sharing scan-in ports with functional ports is not supported.
You can integrate a core that contains a LogicBIST test mode, but there is no automation
provided to access the LogicBIST functionality at the integration level.
For designs with OCC controllers,
A mix of non-OCC-controlled and internal OCC-controlled scan clock domains is not
supported. In this case, you must also control the port-driven clocks with an OCC
controller.
All OCC controllers must have the same clock chain length.
If you are using weighted clock capture groups, there must be at least seven clock
chain bits across all clock chains in the design.
Synchronous OCC controllers are not supported.
User-defined OCC controllers are not supported.
Existing OCC controllers inside DFT-inserted cores are not supported.
External (uncompressed) clock chains cannot be used in LogicBIST test modes.
Designs using DFTMAX Ultra compression require that external clock chains be used
in the DFTMAX Ultra test modes. In this case, you must explicitly define the external
clock chain using the set_scan_path command, using the -test_mode option to
specify the list of all non-LogicBIST test modes.
If any DFT signals use bused ports, the bus indexes must be ordered highest-to-lowest.
If you are using test points, you must specify an existing clock as the test point clock. You
cannot use the DFT-created default test-point clock.
Chapter 5: LogicBIST Limitations and Known Issues

LogicBIST Limitations and Known Issues 5-2
The following DFT features are not supported:

Pipelined scan data
Pipelined scan enable
DFT partitions
Multiple LogicBIST test modes
Domain-based scan enable
Terminal lock-up latches
In TetraMAX ATPG,
Diagnostics is not supported.
The -observe_file option of the run_atpg command is not supported.

K-2015.06-SP4

Glossary
ATPG
Automated Test Pattern Generation, the generation of scan data sequences used for
scan testing, with the goal of achieving as much test coverage as possible using the
smallest possible number of patterns. The test patterns contain nonfunctional data
selected to detect faults on nets in the design.
BIST
Built-in self-test, design-for-test logic where both the scan data generation and the scan
data comparison logic are included in the design.
Burn-in mode
A mode that runs autonomous self-test continuously. The scan and capture activity
stresses the tested logic and causes continuous power draw during self-test. Burn-in
operation can be configured to stop or continue if self-test fails.
Clock chain
A special scan chain segment associated with an on-chip clocking (OCC) controller
whose scanned-in values control the pulse sequence of a controlled clock.
Clock gating
A method of reducing power by shutting off clocks to circuits that are not being used.
Codec
The combination of the decompressor and compressor in a compressed scan flow. A
single design can have multiple codecs, but each codec consists of its own
decompressor/compressor pair.
Compressed scan
A scan methodology that uses more scan chains (called compressed scan chains) than
scan-in/scan-out pairs. A decompressor decompresses the scan-in data to drive the
greater number of scan chains. A compressor compresses the scan chain data to drive
GL-1
K-2015.06-SP4
the lesser number of scan-outs. The combination of the decompressor and compressor
wrapped around the scan chains is called the codec.
Compressed scan chains

In a compressed scan flow, the scan chains that are driven by the decompressor and
drive the compressor. There are a greater number of compressed scan chains than
scan-in/scan-out pairs.
Compressor
In a compressed scan flow, the part of a codec that compresses the scan chain data to
drive the lesser number of scan-outs.
Core wrapping
See wrapped core.
Decompressor
In a compressed scan flow, the part of a codec that decompresses the scan-in data to
drive the greater number of scan chains.
DFT
Design-For-Test, pertains to logic that helps the testability of a design.
DRC
Design Rule Checking, checking a design against a rule set that ensures good testability
and reporting any violations of those rules.
Leading edge
The first edge of a clock waveform definition. It is a rising edge for a return-to-zero clock,
and it is a falling edge for a return-to-one clock.
MISR
Multiple-input signature register, a recirculating shift register that XORs scan-captured
data values into the loop. After capturing all values, the MISR contains a signature value
for that test.
OCC controller
On-chip clocking controller, a DFT design structure that controls a free-running on-chip
clocking source (such as a PLL output clock) in test mode.
PLL
Phase-locked loop, an analog design block that creates a stable on-chip
latency-adjusted clock from a free-running (and possibly less stable) input clock.
Pre-DFT DRC
DRC checking run before DFT insertion, evaluates the readiness of the design for DFT
insertion. Certain types of pre-DFT DRC violations result in scan cells being excluded
from scan chains.
Glossary GL-2
Post-DFT DRC
DRC checking run after DFT insertion, evaluates the implemented DFT functionality of
the design for correct operation.
PRPG
Pseudo-random pattern generator, uses an LSFR and an XOR phase shifter to generate
a stream of pseudorandom data values that have the appearance of random values, but
are actually a function of a seed value.
Scan cell
A sequential cell that has both functional and scan-shift modes of operation.
Scan compression
See compressed scan.
Seed value
The initial value loaded into a PRPG. Different seed values result in different
pseudorandom value sequences.
Signature value
The final value present in the MISR. After self-test completes, the test passes if the
actual signature value (captured by the hardware) matches the expected signature
value (determined by the TetraMAX tool.
SPF
STIL Procedure File, a file written out by DFT Compiler to describe DFT aspects of the
design, such as: test ports, test clocks, primary input constraints, scan chains, codecs,
and test modes. It is used by TetraMAX ATPG (or other ATPG tool) for DRC and ATPG.
STIL
Standard Test Interface Language, documented in IEEE Std 1450, which is a language
used to describe the DFT capabilities of a design. It is a standard for simplifying the
number of test vector formats that automated test equipment (ATE) vendors and
computer-aided engineering (CAE) tool vendors must support.
Standard scan
A scan methodology in which there is a one-to-one relationship between each scan-in/
scan-out pair and each scan chain.
Weighted capture groups

An OCC-based capture method that uses comparator logic to enable one capture group
in each pattern, based on user-specified probabilities.
Wrapped core
A core that has a wrapper chain along the I/O boundary of the design. Wrapped cores
are used to implement hierarchical testing capability, which allows different hierarchy
levels of the design to be tested independently.
Chapter GL:
Glossary GL-3
K-2015.06-SP4
Wrapper chain
A special scan chain in a core-wrapped design that consists of wrapper cells along the I/
O boundary of the design. It can operate in inward-facing or outward-facing modes
during testing to isolate the logic inside the core from logic outside the core.
Glossary GL-4

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DFTMAX LogicBIST User Guide, Version K-2015.06-SP4 ii

Copyright Notice for the Line-Editing Library

DFTMAX LogicBIST User Guide, Version K-2015.06-SP4 iii

About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

2. The LogicBIST Architecture

External and Internal Clocks in the Same Design . . . . . . . . . . . . . . . . . . . . . . . 2-14

3. Using LogicBIST Compression

4. Advanced LogicBIST Configuration

Simplifying the MISR XOR Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

5. LogicBIST Limitations and Known Issues

About This User Guide

Courier Indicates syntax, such as write_file.

Courier italic Indicates a user-defined value in syntax, such as

Courier bold Indicates user inputtext you type verbatimin

[] Denotes optional arguments in syntax, such as

... Indicates that arguments can be repeated as many

| Indicates a choice among alternatives, such as

Ctrl+C Indicates a keyboard combination, such as holding

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such as

Contacting the Synopsys Technical Support Center

The LogicBIST Flow

Chapter 1: Introduction to LogicBIST

Chapter 1: Introduction to LogicBIST

Chapter 1: Introduction to LogicBIST

LogicBIST Architecture Overview

Figure 2-1 The LogicBIST Architecture

These components are described in the following sections:

The LogicBIST Decompressor

Figure 2-2 shows a simple example PRPG register.

Chapter 2: The LogicBIST Architecture

Figure 2-2 An Example PRPG Register

In the LogicBIST architecture, the PRPG operates as follows:

The LogicBIST Compressor

Chapter 2: The LogicBIST Architecture

Figure 2-3 An Example MISR Register

In the LogicBIST architecture, the MISR operates as follows:

The LogicBIST BIST Controller

Chapter 2: The LogicBIST Architecture

In the LogicBIST architecture, the LogicBIST controller operates as follows:

The LogicBIST Clock Controller

Chapter 2: The LogicBIST Architecture

The LogicBIST Control and Data Signals

The LogicBIST Operational Modes

The LBIST_EN and START Signals

Chapter 2: The LogicBIST Architecture

These signals are used in autonomous mode.

The STATUS_0 and STATUS_1 Signals

These signals are used in autonomous mode.

Chapter 2: The LogicBIST Architecture

,'/( 5811,1* 3$66 ,'/(

,'/( 5811,1* )$,/ ,'/(

The Scan-In and Scan-Out Signals

Chapter 2: The LogicBIST Architecture

Figure 2-7 Scan Chain Access to the LogicBIST Logic

LogicBIST Clock Control

Overview of Clock Configurations

Chapter 2: The LogicBIST Architecture

Chapter 2: The LogicBIST Architecture

Figure 2-9 External Clocks When LogicBIST Self-Test Is Active

OCC-Controlled Clocks With Default Capture Behavior

Chapter 2: The LogicBIST Architecture

In TetraMAX mode, the OCC controller is placed in the pll_bypass mode.

OCC-Controlled Clocks With Weighted Clock Capture Groups

Chapter 2: The LogicBIST Architecture

Figure 2-12 LogicBIST OCC Controller With Weighted Capture Groups

Chapter 2: The LogicBIST Architecture

Number of OCC clocks Minimum clock chain length

External and Internal Clocks in the Same Design

Chapter 2: The LogicBIST Architecture

Isolating the Design During LogicBIST Self-Test

Isolating the Self-Test Design Using Core Wrapping

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Chapter 2: The LogicBIST Architecture

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