STV8172A

Vertical deflection booster for

3 App TV/monitor applications with 70 V flyback generator

Features Figure 1. Heptawatt package

Power amplifier
Heptawatt
Flyback generator
(Plastic Package)
Stand-by control ORDER CODE: STV8172A
Output current up to 3.0 App
Thermal protection
Figure 2. STV8172A pin detail
Description Input (Non Inverting)
7
Designed for monitors and high performance TVs, 6 Output Stage Supply
5 Output
the STV8172A vertical deflection booster delivers
4 Ground
flyback voltages up to 70V. 3 Flyback Generator
2 Supply Voltage
The STV8172A operates with supplies up to 35V
1 Input (Inverting)
and provides up to 3 APP output current to drive
the yoke.
The STV8172A is offered in a Heptawatt plastic Tab connected
package. to pin 4

In double-supply applications, a stand-by state

will be reached by stopping the (+) supply alone.

Output Stage Flyback Supply

Supply Generator Voltage
6 3 2

Flyback
Generator
Non-Inverting
Input
7 +
Power 5 Output
Amplifier
Inverting
Input 1 -
Thermal
Protection

STV8172A
4
Ground or Negative Supply

November 2008 Rev 4 1/19

www.st.com 1
Contents STV8172A

Contents

1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 DC-coupled application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.2 Ripple rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 AC-coupled applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Application with differential-output drivers . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Centering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.2 Peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.3 Ripple rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.4 Secondary breakdown diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Lead-free packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/19
STV8172A Absolute maximum ratings

1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

Voltage

VS Supply voltage (pin 2) - Note 1 and Note 2 40 V

V5, V6 Flyback peak voltage - Note 2 70 V
V3 Voltage at Pin 3 - Note 2, Note 3 and Note 6 -0.4 to (VS + 3) V
V1, V7 Amplifier input voltage - Note 2, Note 6 and Note 7 - 0.4 to (VS + 2) or +40 V

Current

I0 (1) Output peak current at f = 50 to 200 Hz, t 10s - Note 4 5 A

I0 (2) Output peak current non-repetitive - Note 5 2 A
I3 Sink Sink current, t<1ms - Note 3 2 A
I3 Source Source current, t < 1ms 2 A
I3 Flyback pulse current at f=50 to 200 Hz, t10s - Note 4 5 A

ESD Susceptibility

ESD1 Human body model (100 pF discharged through 1.5 k) 2 kV

ESD2 EIAJ standard (200 pF discharged through 0 ) 300 V

Temperature

Ts Storage temperature -40 to 150 C

Tj Junction temperature +150 C

Note: 1 Usually the flyback voltage is slightly more than 2 x VS. This must be taken into
consideration when setting VS.
2 Versus pin 4
3 V3 is higher than VS during the first half of the flyback pulse.
4 Such repetitive output peak currents are usually observed just before and after the flyback
pulse.
5 This non-repetitive output peak current can be observed, for example, during the Switch-
On/Switch-Off phases. This peak current is acceptable providing the SOA is respected
(Figure 10 and Figure 11).
6 All pins have a reverse diode towards pin 4, these diodes should never be forward-biased.
7 Input voltages must not exceed the lower value of either VS + 2 or 40 volts.

3/19
Thermal data STV8172A

2 Thermal data

Table 2. Thermal data

Symbol Parameter Value Unit

RthJC Junction-to-case thermal resistance 3 C/W

TT Temperature for thermal shutdown 150 C
TJ Recommended max. junction temperature 120 C

4/19
STV8172A Electrical characteristics

3 Electrical characteristics

VS = 34 V, TAMB = 25C, unless otherwise specified.

Table 3. Electrical characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit Figure

Supply

Operating supply voltage

VS See note below(1) 10 35 V
range (V2-V4)
I2 Pin 2 quiescent current I3 = 0, I5 = 0 5 20 mA Figure 3
I3 = 0, I5 = 0, V6
I6 Pin 6 quiescent current 8 19 50 mA Figure 3
=35v

Input

I1 Input bias current V1 = 1 V, V7 = 2.2 V - 0.6 -1.5 A Figure 3

I7 Input bias current V1 = 2.2 V, V7 = 1 V - 0.6 -1.5 A

VIR Operating input voltage range 0 VS - 2 V

VI0 Offset voltage 2 mV
Offset drift versus
VI0/dt 10 V/C
temperature

Output

I0 Operating peak output current 0o<Tcase<125oC 1.25 A

Output saturation voltage to
V5L I5 = 1.25 A 0.9 1.6 V Figure 5
pin 4
Output saturation voltage to
V5H I5 = -1.25 A 1.5 2.2 V Figure 4
pin 6

Standby

V5STBY Output voltage in standby V1 = V7 = Vs = 0(2) Figure 6

Miscellaneous

G Voltage gain 80 dB
Diode forward voltage
VD5-6 I5 = 1.25 A 1.5 2.1 V
between pins 5-6
Diode forward voltage
VD3-2 I3 = 1.25 A 1.5 2.1 V
between pins 3-2
V3SL Saturation voltage on pin 3 I3 = 20 mA 0.4 1 V Figure 5
Saturation voltage to pin 2
V3SH I3 = -1.25 A 1.8 2.6 V
(2nd part of flyback)
1. In normal applications, the peak flyback voltage is slightly greater than 2 x (VS - V4). Therefore, (VS - V4) = 35 V is not
allowed without special circuitry.
2. Refer to Figure 6, standby condition.

5/19
Electrical characteristics STV8172A

Figure 3. Measurement of I1, I2 and I6

+Vs

I2 I6

2 6

7 5
2.2V 39k
STV8172A
S (a)
1 (b)
4
I1 5.6k
(a): I2 and I6 measurement
(b): I1 measurement 1V

Figure 4. Measurement of V5H

+Vs

2 6
V5H
7
2.2V
STV8172A 5

1 - I5
1V 4

Figure 5. Measurement of V3L and V5L

+Vs

I3 or I5
2 6
7 (b) (a)
1V 3
STV8172A
5
1
V3L V5L
2.2V 4

(a): V5L measurement

(b): V3L measurement

6/19
STV8172A Application hints

4 Application hints

The yoke can be coupled either in AC or DC.

4.1 DC-coupled application

When DC coupled (see Figure 6), the display vertical position can be adjusted with input
bias. On the other hand, 2 supply sources (VS and -VEE) are required.
A standby state will be reached by switching OFF the positive supply alone. In this state,
where both inputs are the same voltage as pin 2 or higher, the output will sink negligible
current from the deviation coil.

Figure 6. DC-coupled application

+Vs Output
470F 0.1F CF (47 to 100F) Voltage

6 3 2
Flyback Output
Generator Current
Vref Ip
Power
Amplifier
Vertical Position
Adjustment 7 +
5
1 -
R3 Thermal Yoke
VM Safety 1.5 Rd(*) Ly
0.22F

Vm
4
-VEE

470F 0.1F
R2

R1

Ly Ly
(*) recommended: ------------- < Rd < -------------
50s 20s

7/19
Application hints STV8172A

4.1.1 Application hints

For calculations, treat the IC as an op-amp, where the feedback loop maintains V1 = V7.

Centering
Display will be centered (null mean current in yoke) when voltage on pin 7 is (R1 is
negligible):
V +V R2
M m
V 7 = ------------------------ ----------------------
2 R 2 + R 3

Peak current
( VM Vm ) R2
I P = ----------------------------- -------------------
2 R 1 xR 3

Example: for Vm = 2 V, VM = 5 V and IP = 1 A

Choose R1 in the1 range, for instance R1=1
From equation of peak current:
R2 2 IP R1
2
------- = ------------------------------- = ---
R3 VM Vm 3

Then choose R2 or R3. For instance, if R2 = 10 k, then R3 = 15 k

Finally, the bias voltage on pin 7 should be:
VM + Vm 1 7 1
V 7 = ------------------------ ----------------- = ---- -------- = 1.4V
2 R 3 2 2.5
1 + -------
R2

8/19
STV8172A Application hints

4.1.2 Ripple rejection

When both ramp signal and bias are provided by the same driver IC, you can gain natural
rejection of any ripple caused by a voltage drop in the ground (see Figure 7), if you manage
to apply the same fraction of ripple voltage to both booster inputs. For that purpose, arrange
an intermediate point in the bias resistor bridge, such that (R8 / R7) = (R3 / R2), and connect
the bias filtering capacitor between the intermediate point and the local driver ground. Of
course, R7 should be connected to the booster reference point, which is the ground side of
R 1.

Figure 7. Ripple rejection

6 3 2
Flyback
Generator
Reference Power
Voltage Amplifier

7 +
R9 R8
R7 5
1 - Thermal Rd Yoke
Safety
Ly

Ramp
Signal R3
R2
R1
Driver
Ground Source of Ripple

9/19
Application hints STV8172A

4.2 AC-coupled applications

In AC-coupled applications (see Figure 8), only one supply (VS) is needed. The vertical
position of the scanning cannot be adjusted with input bias (for that purpose, usually some
current is injected or sunk with a resistor in the low side of the yoke).

Figure 8. AC-coupled application

+Vs Output
470F 0.1F CF (47 to 100F) Voltage

6 3 2
Flyback Output
Generator Current
Power Ip
Amplifier

7 +
5
1 -
R3 Thermal Yoke
Safety 1.5 Rd(*)
VM Ly

0.22F
Vm
4

R5 Cs R4
CL

Ly Ly R2
(*) recommended: ------------- < Rd < -------------
50s 20s R1

4.2.1 Application hints

Gain is defined as in the previous case:
VM Vm R2
I p = ------------------------ -----------------------
2 R1 R3

Choose R1 then either R2 or R3. For good output centering, V7 must fulfill the following
equation:
VS VM + Vm
-------- V 7 V 7 ------------------------ V
2 2 7
---------------------- = -------------------------------------- + -------
R4 + R5 R3 R2

10/19
STV8172A Application hints

or
1 1 VS V M + V m
V 7 ------- + ------- + ---------------------- =
1
R ------------------------------ + ------------------------
3 R 2
R 4 R5+ 2 ( R4 + R5 ) 2 R3

CS performs an integration of the parabolic signal on CL, therefore the amount of S

correction is set by the combination of CL and Cs.

4.3 Application with differential-output drivers

Certain driver ICs provide the ramp signal in differential form, as two current sources i+ and
i with opposite variations.

Figure 9. Using a differential-output driver

+Vs Output
470F 0.1F CF (47 to 100F) Voltage

6 3 2
Differential output Flyback Output
driver IC Generator Current
Power Ip
Amplifier
ip
+ 7
icm +
R7 5
1 - Thermal Yoke
Safety 1.5 Rd(*)
Ly
-ip
0.22F

icm -

4
-VEE

470F 0.1F
R2

R1
(*) recommended: Ly Ly
------------- < Rd < -------------
50s 20s

Some definitions:
icm is the common-mode current: 1
i cm = --- ( i + + i - )
2

at peak of signal, i+ = icm + ip and i = icm - ip, therefore the peak differential signal is
ip - (-ip) = 2 ip, and the peak-peak differential signal, 4ip.
The application is described in Figure 9 with DC yoke coupling. The calculations still rely on
the fact that V1 remains equal to V7.

11/19
Application hints STV8172A

4.3.1 Centering
When idle, both driver outputs provide icm and the yoke current should be null (R1 is
negligible), hence:

i cm R 7 = i cm R 2 therefore R 7 = R 2

4.3.2 Peak current

Scanning current should be IP when positive and negative driver outputs provide
respectively icm - ip and icm + ip, therefore

( i cm i ) R 7 = I p R 1 + ( i cm + i ) R 2

and since R7 = R2
Ip 2R 7
----- = -----------
i R1

Choose R1 in the 1 range, the value of R2 = R7 follows. Remember that i is one-quarter of

driver peak-peak differential signal! Also check that the voltages on the driver outputs
remain inside allowed range.
Example:
for icm = 0.4mA, i = 0.2mA (corresponding to 0.8mA of peak-peak differential current),
Ip = 1A
Choose R1 = 0.75, it follows R2 = R7 = 1.875k.

4.3.3 Ripple rejection

Make sure to connect R7 directly to the ground side of R1.

12/19
STV8172A Application hints

4.3.4 Secondary breakdown diagrams

Figure 10. Output transistor safe operating area (SOA) for secondary breakdown

The diagram has been arbitrarily limited to max I0 (2A).

Figure 11. Secondary breakdown temperature derating curve (ISB = secondary

breakdown current)

13/19
Mounting instructions STV8172A

5 Mounting instructions

The power dissipated in the circuit is removed by adding an external heatsink. With the
Heptawatt package, the heatsink is simply attached with a screw or a compression spring
(clip).
A layer of silicon grease inserted between heatsink and package optimizes thermal contact.
In DC-coupled applications we recommend to use a silicone tape between the device tab
and the heatsink to electrically isolate the tab.

Figure 12. Mounting examples

14/19
STV8172A Pin configuration

6 Pin configuration

Figure 13. Pins 1 and 7

2

1 7

Figure 14. Pins 3, 5 and 6

6
2 2

15/19
Package mechanical data STV8172A

7 Package mechanical data

Figure 15. 7-pin Heptawatt package

L
E
L1
M1

A M
C D
D1
L2 H2
L5 L3 F
E1
E

V4
L9

H3 G G1 G2

Dia.
F
L10 L4 H2

L11
L7
L6

Table 4. Heptawatt package

Dim. mm inches

Min. Typ. Max. Min. Typ. Max.

A 4.8 0.189

C 1.37 0.054

D 2.40 2.80 0.094 0.110

D1 1.20 1.35 0.047 0.053

E 0.35 0.55 0.014 0.022

E1 0.70 0.97 0.028 0.038

F 0.60 0.80 0.024 0.031

16/19
STV8172A Package mechanical data

Table 4. Heptawatt package (continued)

Dim. mm inches

G 2.34 2.54 2.74 0.095 0.100 0.105

G1 4.88 5.08 5.28 0.193 0.200 0.205

G2 7.42 7.62 7.82 0.295 0.300 0.307

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 16.70 16.90 17.10 0.657 0.668 0.673

L1 14.92 0.587

L2 21.24 21.54 21.84 0.386 0.848 0.860

L3 22.27 22.52 22.77 0.877 0.891 0.896

L4 1.29 0.051

L5 2.60 2.80 3.00 0.102 0.110 0.118

L6 15.10 15.50 15.80 0.594 0.610 0.622

L7 6.00 6.35 6.60 0.0236 0.250 0.260

L9 0.20 0.008

L10 2.10 2.70 0.082 0.106

L11 4.30 4.80 0.169 0.190

M 2.55 2.80 3.05 0.100 0.110 0.120

M1 4.83 5.08 5.33 0.190 0.200 0.210

V4 40 (Typ.)

Dia. 3.65 3.85 0.144 0.152

7.1 Lead-free packaging

To meet environmental requirements, ST offers these devices in ECOPACK packages.
These packages have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

17/19
Revision history STV8172A

8 Revision history

Table 5. Document revision history

Date Revision Changes

August 2003 1 First issue.

November 2003 1.1 Datasheet status changed to preliminary data.
December 2003 1.2 Modification to Figure 13.
June 2004 1.3 Datasheet status changed to datasheet.
February 2005 2 Updated Figure 9.
March 2005 3 Status changed to datasheet.
13-Nov-2008 4 Section 7.1 added, new template applied.

18/19
STV8172A

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19/19