Up Down Counter

TUTORIALS FOR MAX3000A CPLD
DEVICES
WEL LAB
6BIT-UP-DOWN-COUNTER
CONTENTS:
INTRODUCTION ..
GETTING STARTED.
DESIGN ENTRY.
PIN ASSIGNMENT.
PROGRAMMING CPLD DEVICE.
REFERENCES.
WEL LAB, IIT BOMBAY Page 2

INTRODUCTION:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. In practice, there are two
types of counters:
Up counters, which increase (increment) in value
Down counters, which decrease (decrement) in value
A counter that can change state in either direction, under the control of an
updown selector input, is known as an updown counter. When the
selector is in the up state, the counter increments its value, when the
selector is in the down state, the counter decrements the count.

GET STARTED:
You begin this tutorial by creating a new Quartus II project. A project is a
set of files that maintain information about your FPGA design. The
Quartus II Settings File (.qsf) and Quartus II Project File (.qpf) files are
the primary files in a Quartus II project. To compile a design or make pin
assignments, you must first create a project.
1. In the Quartus II software, Select File > New Project Wizard. The
Introduction page opens. See fig-1.
Fig-1
2. Click Next.

3. Enter the following information about your project:
a. What is the working directory for this project?
Enter a directory in which you will store your Quartus II project
files for this design, for example,
c:\altera\UpDownCounter.
b. What is the name of this project?
Type updown_counter.
c. What is the name of the top-level design entity for this project?
Type up_down_counter. See fig-2.
Note: File names, project names, and directories in the Quartus II

software cannot contain spaces.
And the name of top module in the program should be same as given
in the above window.
4. If you have any existing file of VHDL, or VERILOG HDL file then
you can add those files to your project by simply clicking () bar
and then click Add button and if you want to add more than one file
simply click Add All button. Otherwise leave it blank and click next
tab. In fig -3.
Fig-3
5. In the next step we have to select the FPGA or CPLD device which
we are using on our board (select MAX 3000A) as shown in fig -4
make all the settings as shown in the Fig-4.

Fig-4
Since our Cpld have 64 macro cells so select EPM3064ALC44-10

and then click NEXT.
6. There is no change in window of fig-5 and click NEXT.

Fig-5
7. Click next , summary of project and its details are shown in the next
window.fig-6

Fig-6

DESIGN ENTRY:
In the design entry phase, you use RTL or schematic entry to create
the logic to be implemented in the device. You also make pin
assignments, including pin placement information, and timing
constraints that might be necessary for building a functioning design.
In the design entry step you create a schematic or Block Design File
(.bdf) or Hdl file (Vhdl, Verilog) that is the top-level design. You can
add library of parameterized modules (LPM) functions and use
Verilog HDL code to add a logic block.
When creating your own designs, you can choose any of these
methods or a combination of them.
a. Choose File > New > Verilog Hdl File/Schematic File (see Fig-7)
to create a new file, Verilog.v file which you will save as the top-
level design.

Fig-7
b. Click OK.
c. Choose File > Save As and enter the following information (see
fig-8).
File name: shift_register.
Save as type: Verilog Hdl File(*.v).
Fig-8
d. Type the following Verilog HDL code into the blank
shift_register file and save it. (see fig -9).

/////////////////////////////////
module up_down_counter (out, up_down, clk , reset, data );
output [5:0] out;

input [5:0] data;
input up_down, clk, reset;
reg [5:0] out;
always @(posedge clk)

if (reset) begin
out <= 6'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule

Fig-9
Now click the start compilation button in tool menu as shown in
fig-9
e. If the simulation is successful then a green tick mark is displayed
in front of Compile Design in the task bar as shown below.

Fig-10

ASSIGNMENT OF PINS:
In this section, you will make pin assignments. Follow the steps given
below for making assignment.
1. Once the design is compiled, you can choose what pins to assign as
input/output from Pin Planner under the Assignments tab in the
Menu bar. It opens windows as shown below. Fig-11
After making the pin assignments recompile the design.
Fig-11
2. Re-run the compiler and make sure that there are no errors.
3. The pins which have been configured as input and output on the
board are listed. Onboard clock is on pin no 43.

Inputs Pin Outputs Pin No.
No.
LED1 24
SW1 4
LED2 25
SW2 5
LED3 26
SW3 6
LED4 27
SW4 8
LED5 28
SW5 9
LED6 29
SW6 11
LED7 31
SW7 12
LED8 33
SW8 14

PROGRAMMING OF CPLD :
1. For programming the CPLD device open the tool option and select
programmer a window will open as shown in fig(a) fig(b)
create the Serial Vector file (.svf) for programming device.
Fig(a)

Fig(b)
2. Run the JTAG shell it will display the window as shown below

3. Type out the command cable FT2232.
4. The detect command should show the IR length of the CPLD
connected followed by the details of the CPLD.
5. Since the CPLD is the only device in the JTAG chain, type the part
0 command. In case you have other devices connected to the JTAG
chain, you can choose the appropriate device by specifying the
corresponding part number.
6. The command svf <Address of the .svf file> will start

programming the CPLD.
7. Once the cursor returns, it shows that device is programmed.

References :
1. www.altera.com
2. www.asic-world.com
3. Fundamentals of Digital Logic with Verilog Design
(Stephen Brown ) 2E.
4. Digital Logic and Computer Design.

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TUTORIALS FOR MAX3000A CPLD

PROGRAMMING CPLD DEVICE.

WEL LAB, IIT BOMBAY Page 2

WEL LAB, IIT BOMBAY Page 3

WEL LAB, IIT BOMBAY Page 4

Note: File names, project names, and directories in the Quartus II

WEL LAB, IIT BOMBAY Page 6

Since our Cpld have 64 macro cells so select EPM3064ALC44-10

6. There is no change in window of fig-5 and click NEXT.

WEL LAB, IIT BOMBAY Page 7

WEL LAB, IIT BOMBAY Page 8

WEL LAB, IIT BOMBAY Page 9

WEL LAB, IIT BOMBAY Page 10

WEL LAB, IIT BOMBAY Page 11

output [5:0] out;

always @(posedge clk)

WEL LAB, IIT BOMBAY Page 12

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WEL LAB, IIT BOMBAY Page 14

After making the pin assignments recompile the design.

WEL LAB, IIT BOMBAY Page 15

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WEL LAB, IIT BOMBAY Page 17

WEL LAB, IIT BOMBAY Page 18

6. The command svf <Address of the .svf file> will start

7. Once the cursor returns, it shows that device is programmed.

WEL LAB, IIT BOMBAY Page 19

WEL LAB, IIT BOMBAY Page 20

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