COMPUTER

ORGANIZATIONAND
ARCHITECTURE

Slides Courtesy of Carl Hamacher,Computer Organization, Fifth edition,McGrawHill

 COMPUTER
ORGANISATIONAND
ARCHITECTURE
Thecomponentsfromwhichcomputersarebuilt,
i.e.,computerorganization.
Incontrast,computerarchitectureisthescienceof
integratingthosecomponentstoachievealevelof
functionalityandperformance.
Itisasifcomputerorganizationexaminesthe
lumber,bricks,nails,andotherbuildingmaterial
Whilecomputerarchitecturelooksatthedesignof
thehouse.
 UNIT-I INTRODUCTION

Evolution of Computer Systems

Computer Types
Functional units
Basic operational concepts
Bus structures
Memory location and addresses
Memory operations
Addressing modes
Design of a computer system
Instruction and instruction sequencing,
RISC versus CISC.
 INTRODUCTION

Thischapterdiscussesthecomputerhardware,
softwareandtheirinterconnection,anditalso
discussesconceptslikecomputertypes,
evolutionofcomputers,functionalunits,basic
operations,RISCandCISCsystems.
 BriefHistoryofComputer
Evolution

Twophases:
VLSI = Very Large
1. beforeVLSI 1945 1978 Scale Integration
ENIAC
IAS
IBM
PDP8
2. VLSI 1978 presentday
microprocessors!
Evolution of Computers
FIRSTGENERATION(1945
1955)
Programanddataresideinthesamememory
(storedprogramconcepts JohnvonNeumann)
ALPwasmadeusedtowriteprograms
Vacuumtubeswereusedtoimplementthefunctions
(ALU&CUdesign)
Magneticcoreandmagnetictapestoragedevicesare
used
Usingelectronicvacuumtubes,astheswitching
components
 SECONDGENERATION
(1955 1965)

TransistorwereusedtodesignALU&CU
HLLisused(FORTRAN)
ToconvertHLLtoMLLcompilerwereused
SeparateI/Oprocessorweredevelopedtooperatein
parallelwithCPU,thusimprovingtheperformance
Inventionofthetransistorwhichwasfaster,smaller
andrequiredconsiderablylesspowertooperate
 THIRDGENERATION
(19651975)
ICtechnologyimproved
ImprovedICtechnologyhelpedindesigninglowcost,high
speedprocessorandmemorymodules
Multiprogramming,pipeliningconceptswereincorporated
DOSallowedefficientandcoordinateoperationofcomputer
systemwithmultipleusers
Cacheandvirtualmemoryconceptsweredeveloped
Morethanonecircuitonasinglesiliconchipbecame
available
FOURTHGENERATION
(19751985)
CPU Termedasmicroprocessor
INTEL,MOTOROLA,TEXAS,NATIONAL
semiconductorsstarteddevelopingmicroprocessor
Workstations,microprocessor(PC)&Notebook
computersweredeveloped
Interconnectionofdifferentcomputerforbetter
communicationLAN,MAN,WAN
Computationalspeedincreasedby1000times
SpecializedprocessorslikeDigitalSignalProcessor
werealsodeveloped
BEYOND THE FOURTH GENERATION
(1985 TILL DATE)

ECommerce,E banking,homeoffice
ARM,AMD,INTEL,MOTOROLA
Highspeedprocessor GHzspeed
BecauseofsubmicronICtechnologylotof
addedfeaturesinsmallsize
 COMPUTERTYPES

Computersareclassifiedbasedonthe
parameterslike
Speedofoperation
Cost
Computationalpower
Typeofapplication
DESKTOPCOMPUTER

Processing&storageunits,visualdisplay&audiouits,
keyboards
StoragemediaHarddisks,CDROMs
Eg:Personalcomputerswhichisusedinhomesandoffices
Advantage:Costeffective,easytooperate,suitableforgeneral
purposeeducationalorbusinessapplication
NOTEBOOKCOMPUTER

Compactformofpersonalcomputer(laptop)
Advantageisportability
WORK STATIONS
More computational power than PC
Costlier
Used to solve complex problems which arises in
engineering application (graphics, CAD/CAM etc)

ENTERPRISE SYSTEM (MAINFRAME)

More computational power
Larger storage capacity
Used for business data processing in large organization
Commonly referred as servers or super computers
SERVER SYSTEM

Supports large volumes of data which frequently need to

be accessed or to be modified
Supports request response operation

SUPER COMPUTERS

Faster than mainframes

Helps in calculating large scale numerical and algorithm
calculation in short span of time
Used for aircraft design and testing, military application
and weather forecasting
HANDHELD
AlsocalledaPDA(Personal
DigitalAssistant).
Acomputerthatfitsintoa
pocket,runsonbatteries,and
isusedwhileholdingtheunit
inyourhand.
Typicallyusedasan
appointmentbook,address
book,calculator,andnotepad.
Canbesynchronizedwitha
personalmicrocomputerasa
backup.
 BasicTerminology

Computer Software
Adevicethatacceptsinput, Acomputerprogramthattells
processesdata,storesdata,and thecomputerhowtoperform
producesoutput,allaccordingto particulartasks.
aseriesofstoredinstructions.
Network
Hardware Twoormorecomputersand
Includestheelectronicand otherdevicesthatare
mechanicaldevicesthatprocess connected,forthepurposeof
thedata;referstothecomputer sharingdataandprograms.
aswellasperipheraldevices.
Peripheraldevices
Usedtoexpandthecomputers
input,outputandstorage
capabilities.
 BasicTerminology

Input
Whateverisputintoacomputersystem.
Data
Referstothesymbolsthatrepresentfacts,objects,orideas.
Information
Theresultsofthecomputerstoringdataasbitsandbytes;thewords,
numbers,sounds,andgraphics.
Output
Consistsoftheprocessingresultsproducedbyacomputer.
Processing
Manipulationofthedatainmanyways.
Memory
Areaofthecomputerthattemporarilyholdsdatawaitingtobeprocessed,
stored,oroutput.
Storage
Areaofthecomputerthatholdsdataonapermanentbasiswhenitisnot
immediatelyneededforprocessing.
 Basic Terminology

Assembly language program (ALP) Programs are written

using mnemonics

Mnemonic Instruction will be in the form of English like

form

Assembler is a software which converts ALP to MLL

(Machine Level Language)

HLL (High Level Language) Programs are written using

English like statements

Compiler - Convert HLL to MLL, does this job by reading

source program at once
 Basic Terminology
Interpreter Converts HLL to MLL, does this job
statement by statement

System software Program routines which aid the

user in the execution of programs eg: Assemblers,
Compilers

Operating system Collection of routines

responsible for controlling and coordinating all the
activities in a computer system
 ComputingSystems

Computershavetwokindsofcomponents:
Hardware,consistingofitsphysicaldevices
(CPU,memory,bus,storagedevices,...)
Software,consistingoftheprogramsithas
(Operatingsystem,applications,utilities,...)

Calvin College
FUNCTIONALUNITSOF
COMPUTER
InputUnit

OutputUnit

CentralprocessingUnit(ALUandControlUnits)

Memory

BusStructure
 TheBigPicture

Processor
Input
Control
Memory

ALU
Output

Since1946allcomputershavehad5components!!!
 IMPORTANT
Function SLIDE !

ALL computerfunctionsare:
DataPROCESSING
DataSTORAGE Data = Information
DataMOVEMENT
CONTROL Coordinates How
Information is Used

NOTHINGELSE!
INPUT UNIT:

Converts the external world data to a binary format, which

can be understood by CPU

Eg: Keyboard, Mouse, Joystick etc

OUTPUT UNIT:

Converts the binary format data to a format that a common

man can understand

Eg: Monitor, Printer, LCD, LED etc

CPU
The brain of the machine

Responsible for carrying out computational task

Contains ALU, CU, Registers

ALU Performs Arithmetic and logical operations

CU Provides control signals in accordance with some

timings which in turn controls the execution process

Register Stores data and result and speeds up the

operation
Example
Add R1, R2

T1 Enable R1

T2 Enable R2

T3 Enable ALU for addition operation

T4
 Control unit works with
a reference signal called
T1 processor clock

T2 Processor divides the

operations into basic
steps

R1 R2

Each basic step is

executed in one clock
cycle

R2
MEMORY

Stores data, results, programs

Two class of storage

(i) Primary (ii) Secondary

Two types are RAM or R/W memory and ROM read only memory

ROM is used to store data and program which is not going to

change.

Secondary storage is used for bulk storage or mass storage

 BasicOperationalConcepts

BasicFunctionofComputer
ToExecuteagiventaskaspertheappropriateprogram

Programconsistsoflistofinstructionsstoredin
memory
Interconnection between Processor and Memory
Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are

Two registers-MAR (Memory Address Register) and

MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
Instruction register (IR) : Hold the Instructions that is
currently being executed
Program counter: Points to the next instructions that is
to be fetched from memory
(PC) (MAR)( the contents
of PC transferred to MAR)

(MAR) (Address bus) Select a

particular memory location

Issues RD control signals

Reads instruction present in memory

and loaded into MDR

Will be placed in IR (Contents

transferred from MDR to IR)
Instruction present in IR will be decoded by
which processor understand what operation it
has to perform

Increments the contents of PC by 1, so that it

points to the next instruction address

If data required for operation is available in

register, it performs the operation

If data is present in memory following

sequence is performed
Address of the data MAR

MAR Address bus select memory

location where is issued RD signal

Reads data via data bus MDR

From MDR data can be directly routed to ALU

or it can be placed in register and then
operation can be performed

Results of the operation can be directed

towards output device, memory or register

Normal execution preempted (interrupt)

 Interrupt

AninterruptisarequestfromI/Odevicefor
servicebyprocessor
Processorprovidesrequestedserviceby
executinginterruptserviceroutine(ISR)
ContentsofPC,generalregisters,andsome
controlinformationarestoredinmemory.
WhenISRcompleted,processorrestored,so
thatinterruptedprogrammaycontinue
 BUS STRUCTURE
Connecting CPU and memory
The CPU and memory are normally connected by three
groups of connections, each called a bus: data bus, address
bus and control bus

Connecting CPU and memory using three buses

 BUS STRUCTURE
Group of wires which carries information form CPU to peripherals or
vice versa

Single bus structure: Common bus used to communicate between

peripherals and microprocessor

INPUT MEMORY PROCESSOR OUTPUT

SINGLE BUS STRUCTURE

Continued:-

To
improve performance multibus structure can be
used

In two bus structure : One bus can be used to fetch

instruction other can be used to fetch data, required
for execution.

Thus improving the performance ,but cost increases

 A2 A1 A0 Selected
CONTROL BUS location

0 0 0 0th Location
0 0 1 1st Location
0 1 0

W/R
CS RD 0 1 1
A0 PROCESSOR
A1 1 0 0
A2
1 0 1
ADDRESS BUS
1 1 0
D7 D0
D0 D7
1 1 1

DATA BUS
Cont:-

23 = 8 i.e. 3 address line is required to select 8

location

In general 2x = n where x number of address lines

(address bit) and n is number of location

Address bus : unidirectional : group of wires

which carries address information bits form
processor to peripherals (16,20,24 or more parallel
signal lines)
Cont:-

Databus: bidirectional : group of wires which

carries data information bit form processor to
peripherals and vice versa

Controlbus: bidirectional: group of wires

which carries control signals form processor to
peripherals and vice versa

Figure below shows address, data and control

bus and their connection with peripheral and
microprocessor
PERFORMANCE

Time taken by the system to execute a program

Parameters which influence the performance are

Clock speed

Type and number of instructions available

Average time required to execute an instruction

Memory access time

Power dissipation in the system

Number of I/O devices and types of I/O devices

connected

The data transfer capacity of the bus

 MEMORY LOCATIONS AND ADDRESSES
Main memory is the second major subsystem in a
computer. It consists of a collection of storage locations,
each with a unique identifier, called an address.

Data is transferred to and from memory in groups of

bits called words. A word can be a group of 8 bits, 16
bits, 32 bits or 64 bits (and growing).

If the word is 8 bits, it is referred to as a byte. The term

byte is so common in computer science that
sometimes a 16-bit word is referred to as a 2-byte word,
or a 32-bit word is referred to as a 4-byte word.
Figure 5.3 Main memory
 Address space

To access a word in memory requires an identifier. Although

programmers use a name to identify a word (or a collection
of words), at the hardware level each word is identified by an
address.

The total number of uniquely identifiable locations in

memory is called the address space.

For example, a memory with 64 kilobytes (16 address line

required) and a word size of 1 byte has an address space that
ranges from 0 to 65,535.
i
Memory addresses are defined using unsigned
binary integers.
Example 1
A computer has 32 MB (megabytes) of memory. How many bits
are needed to address any single byte in memory?
Solution
The memory address space is 32 MB, or 225 (25 220). This
means that we need log2 225, or 25 bits, to address each byte.

Example 2
A computer has 128 MB of memory. Each word in this computer
is eight bytes. How many bits are needed to address any single
word in memory?
Solution
The memory address space is 128 MB, which means 227.
However, each word is eight (23) bytes, which means that we
have 224 words. This means that we need log2 224, or 24 bits, to
address each word.
 Assignmentofbyteaddresses

LittleEndian(e.g.,inDEC,Intel)
loworderbytestoredatlowestaddress
byte0byte1byte2byte3

Eg:46,78,96,54(32bitdata)
HBYTE LBYTE

8000 54
8001 96
8002 78
8003
46
8004
|
 BigEndian

BigEndian(e.g.,inIBM,Motorolla,Sun,HP)
highorderbytestoredatlowestaddress
byte3byte2byte1byte0

Programmers/protocolsshouldbecareful
whentransferringbinarydatabetweenBig
EndianandLittleEndianmachines
 Incaseof16bitdata,alignedwordsbeginat
byteaddressesof0,2,4,.
Incaseof32bitdata,alignedwordsbeginat
byteaddressof0,4,8,.
Incaseof64bitdata,alignedwordsbeginat
byteaddressesof0,8,16,..
Insomecaseswordscanstartatanarbitrary
byteaddressalsothen,wesaythatword
locationsareunaligned
 MEMORYOPERATIONS

Today,generalpurposecomputers useasetofinstructionscalleda
program toprocessdata.

Acomputerexecutestheprogramtocreateoutputdatafrominput
data

Bothprograminstructionsanddataoperandsarestoredinmemory

Twobasicoperationsrequiresinmemoryaccess
Loadoperation(ReadorFetch)Contentsofspecified
memorylocationarereadbyprocessor
Storeoperation(Write) Datafromtheprocessorisstoredin
specifiedmemorylocation
 INSTRUCTIONSETARCHITECTURE:Complete
instructionsetoftheprocessor

BASIC4TYPESOFOPERATION:
Datatransferbetweenmemoryand
processorregister
Arithmeticandlogicoperation
Programsequencingandcontrol
I/Otransfer
 Registertransfernotation(RTN)
Transferbetweenprocessorregisters&memory,between
processorregister&I/Odevices

Memorylocations,registersandI/Oregisternamesare
identifiedbyasymbolicnameinuppercasealphabets

LOC,PLACE,MEMaretheaddressofmemorylocation
R1,R2,areprocessorregisters
DATA_IN,DATA_OUTareI/Oregisters
Contents of location is indicated by using square
brackets [ ]

RHS of RTN always denotes a values, and is

called Source

LHS of RTN always denotes a symbolic name

where value is to be stored and is called destination

Source contents are not modified

Destination contents are overwritten

 ExamplesofRTN
statements

R2[LOCN]

R4[R3]+[R2]
ASSEMBLYLANGUAGE
NOTATION(ALN)
RTNiseasytounderstandandbutcannotbe
usedtorepresentmachineinstructions
Mnemonicscanbeconvertedtomachine
language,whichprocessorunderstands
usingassembler
Eg:
1. MOVELOCN,R2
2. ADDR3,R2,R4
 TYPEOFINSTRUCTION

Threeaddressinstruction

Syntax: Operation source 1, source 2, destination

Eg: ADD D,E,F where D,E,F are memory
location
Advantage: Single instruction can perform the
complete operation
Disadvantage : Instruction code will be too large to
fit in one word location in memory
TWO ADDRESS INSTRUCTION
Syntax : Operation source, destination

Eg: MOVE E,F MOVE D,F

ADD D,F OR ADD E,F

Perform ADD A,B,C using 2 instructions

MOVE B,C
ADD A,C

Disadvantage: Single instruction is not sufficient to

perform the entire operation.
 ONEADDRESS
INSTRUCTION
Syntax Operationsource/destination
Inthistypeeitherasourceordestination
operandismentionedintheinstruction
Otheroperandisimpliedtobeaprocessor
registercalledAccumulator
Eg:ADDB(general)
LoadD;ACC[memlocation_D]
ADDE;ACC(ACC)+(E)
STOREF;memlocation_F(ACC)
 Zeroaddress
instruction

Locationofalloperandsaredefinedimplicitly

Operandsarestoredinastructurecalled
pushdownstack
 Continued

IfprocessorsupportsALUoperationsonedatainmemoryand
otherinregisterthentheinstructionsequenceis
MOVED,Ri
ADDE,Ri
MOVERi,F
IfprocessorsupportsALUoperationsonlywithregistersthen
onehastofollowtheinstructionsequencegivenbelow
LOADD,Ri
LOADE,Rj
ADDRi,Rj
MOVERj,F
 BasicInstructionCycle

Basiccomputeroperationcycle
Fetchtheinstruction frommemoryintoacontrol
register(PC)
Decodetheinstruction
Locatetheoperands usedbytheinstruction
Fetchoperands frommemory(ifnecessary)
Executetheoperation inprocessorregisters
Storetheresults intheproperplace
Gobacktostep1tofetchthenextinstruction
 INSTRUCTIONEXECUTION&STRIAGHTLINE
SEQUENCING
Address Contents

}
Begin execution here i Move A,R0
i+4 Add B,R0
3-instruction program
i+8 Move R0,C
. segment
.
.

A
.
.
.

B Data for Program

. C [A]+[B]
.

C
 PC Programcounter:holdtheaddressofthenext
instructiontobeexecuted
Straightlinesequencing:Iffetchingandexecutingof
instructionsiscarriedoutonebyonefrom
successiveaddressesofmemory,itiscalledstraight
linesequencing.
Majortwophaseofinstructionexecution
Instructionfetchphase:Instructionisfetchedform
memoryandisplacedininstructionregisterIR
Instructionexecutephase:ContentsofIRisdecoded
andprocessorcarriesouttheoperationeitherby
readingdatafrommemoryorregisters.
 BRANCHING

A straight line program for adding n

numbers
Using a loop to add n numbers
 BRANCHING
Branchinstructionarethosewhichchangesthe
normalsequenceofexecution.

Sequencecanbechangedeitherconditionallyor
unconditionally.

Accordinglywehaveconditional branchinstructions
andunconditionalbranchinstruction.

Conditionalbranchinstructionchangesthesequence
onlywhencertainconditionsaremet.

Unconditionalbranchinstructionchangesthe
sequenceofexecutionirrespectiveofconditionof
theresults.
 CONDITIONCODES
CONDITIONALCODEFLAGS:Theprocessorkeepstrackof
informationabouttheresultsofvariousoperationsfor
usebysubsequentconditionalbranchinstructions

N Negative1ifresultsareNegative
0ifresultsarePositive
Z Zero1ifresultsareZero
0ifresultsareNonzero
V Overflow1ifarithmeticoverflowoccurs
0nonoverflowoccurs
C Carry1ifcarryandfromMSBbit
0ifthereisnocarryfromMSBbit
Figure Format and different instruction types
 Processing the instructions
Simple computer, like most computers, uses machine cycles.

A cycle is made of three phases: fetch, decode and execute.

During the fetch phase, the instruction whose address is determined by

the PC is obtained from the memory and loaded into the IR. The PC is
then incremented to point to the next instruction.

During the decode phase, the instruction in IR is decoded and the

required operands are fetched from the register or from memory.

During the execute phase, the instruction is executed and the results are
placed in the appropriate memory location or the register.

Once the third phase is completed, the control unit starts the cycle again,
but now the PC is pointing to the next instruction.
The process continues until the CPU reaches a HALT instruction.
 TypesofAddressingModes
Thedifferentwaysinwhichthelocationoftheoperandis
specifiedinaninstructionarereferredtoasaddressing
modes

ImmediateAddressing
DirectAddressing
IndirectAddressing
RegisterAddressing
RegisterIndirectAddressing
RelativeAddressing
IndexedAddressing
 ImmediateAddressing
Operandisgivenexplicitlyintheinstruction
Operand=Value
e.g.ADD5
Add5tocontentsofaccumulator
5isoperand
Nomemoryreferencetofetchdata
Fast
Limitedrange

Instruction
opcode
operand
 DirectAddressing
Addressfieldcontainsaddressofoperand
Effectiveaddress(EA)=addressfield(A)
e.g.ADDA
AddcontentsofcellAtoaccumulator
LookinmemoryataddressAforoperand
Singlememoryreferencetoaccessdata
Noadditionalcalculationstoworkouteffectiveaddress
Limitedaddressspace
DirectAddressingDiagram

Instruction
Opcode Address A
Memory

Operand
 IndirectAddressing(1)

Memorycellpointedtobyaddressfield
containstheaddressof(pointerto)the
operand
EA=[A]
LookinA,findaddress(A)andlooktherefor
operand
e.g.ADD(A)
AddcontentsofcellpointedtobycontentsofAto
accumulator
 IndirectAddressing(2)

Largeaddressspace
2n wheren=wordlength
Maybenested,multilevel,cascaded
e.g.EA=(((A)))
Drawthediagramyourself
Multiplememoryaccessestofindoperand
Henceslower
 IndirectAddressingDiagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand
 RegisterAddressing(1)

Operandisheldinregisternamedinaddress
field
EA=R
Limitednumberofregisters
Verysmalladdressfieldneeded
Shorterinstructions
Fasterinstructionfetch
 RegisterAddressing(2)

Nomemoryaccess

Veryfastexecution

Verylimitedaddressspace

Multipleregistershelpsperformance
Requiresgoodassemblyprogrammingorcompiler
writing
RegisterAddressingDiagram

Instruction
Opcode Register Address R
Registers

Operand
 RegisterIndirect
Addressing
C.f.indirectaddressing
EA=[R]
Operandisinmemorycellpointedtoby
contentsofregisterR
Largeaddressspace(2n)
Onefewermemoryaccessthanindirect
addressing
 RegisterIndirect
AddressingDiagram
Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 IndexedAddressing
EA=X+[R]
Addressfieldholdtwovalues
X=constantvalue(offset)
R=registerthatholdsaddressofmemory
locations
orviceversa
`(Offsetgivenasconstantorintheindexregister)
Add20(R1),R2orAdd1000(R1),R2
IndexedAddressingDiagram

Instruction
Opcode Register R Constant Value
Memory

Registers

Pointer to Operand + Operand

 RelativeAddressing

Aversionofdisplacementaddressing
R=Programcounter,PC
EA=X+(PC)
i.e.getoperandfromXbytesawayfrom
currentlocationpointedtobyPC
c.flocalityofreference&cacheusage
 Autoincrementmode

Theeffectiveaddressoftheoperandisthe
contentsofaregisterspecifiedintheinstruction.
Afteraccessingtheoperand,thecontentsofthis
registerareautomaticallyincrementedtopoint
tothenextiteminthelist
EA=[Ri];IncrementRi (Ri)+
Eg:Add(R2)+,R0
 Autodecrementmode

Thecontentsofaregisterspecifiedinthe
instructionarefirstautomatically
decrementedandarethenusedasthe
effectiveaddressoftheoperand

DecrementRi;EA=[Ri] (Ri)
 AddressingArchitecture

MemorytoMemoryarchitecture
Alloftheaccessofaddressing>Memory
HaveonlycontrolregisterssuchPC
Toomanymemoryaccesses
RegistertoRegisterarchitecture
Allowonlyonememoryaddress
load,store instructions
RegistertoMemoryarchitecture
Programlengthsand#ofmemoryaccessestendtobeintermediate
betweentheabovetwoarchitectures
Singleaccumulatorarchitecture
Havenoregisterprofile
Toomanymemoryaccesses
Stackarchitecture
Datamanipulationinstructionsusenoaddress.
Toomanymemory(stack)accesses
Usefulforrapidinterpretationofhighlevellang.programsinwhichthe
intermediatecoderepresentationusesstackoperations.
 AddressingModes

Impliedmode
Theoperandisspecifiedimplicitlyinthedefinition
oftheopcode.
Immediatemode
Theactualoperandisspecifiedintheinstruction
itself.
AddressingModes(Summary)

Base register LDA #ADRS(R1) ACC <- M[R1+ADRS]

 InstructionSetArchitecture
RISC(ReducedInstructionSetComputer)Architectures
Memoryaccessesarerestrictedtoloadandstoreinstruction,anddata
manipulationinstructionsareregistertoregister.
Addressingmodesarelimitedinnumber.
Instructionformatsareallofthesamelength.
Instructionsperformelementaryoperations

CISC(ComplexInstructionSetComputer)Architectures
Memoryaccessisdirectlyavailabletomosttypesofinstruction.
Addressingmodearesubstantialinnumber.
Instructionformatsareofdifferentlengths.
Instructionsperformbothelementaryandcomplexoperations.
 InstructionSetArchitecture

RISC(ReducedInstructionSetComputer)
Architectures
Largeregisterfile
Controlunit:simpleandhardwired
pipelining

CISC(ComplexInstructionSetComputer)
Architectures
Registerfile:smallerthaninaRISC
Controlunit:oftenmicroprogrammed
Currenttrend
CISCoperation asequenceofRISClikeoperations
 CISCExamples

ExamplesofCISCprocessorsarethe
System/360(excludingthe'scientific'Model44),
VAX,
PDP11,
Motorola68000family
Intelx86architecturebasedprocessors.
 Pros

Emphasis on hardware
Includes multi-clock complex
instructions
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Small code sizes,
high cycles per second
Transistors used for storing
complex instructions
 Cons

Thatis,theincorporationofolderinstructionsets
intonewgenerationsofprocessorstendedtoforce
growingcomplexity.
ManyspecializedCISCinstructionswerenotused
frequentlyenoughtojustifytheirexistence.
BecauseeachCISCcommandmustbetranslatedby
theprocessorintotensorevenhundredsoflinesof
microcode,ittendstorunslowerthananequivalent
seriesofsimplercommands thatdonotrequireso
muchtranslation.
 RISCExamples

AppleiPods(customARM7TDMISoC)
AppleiPhone(SamsungARM1176JZF)
PalmandPocketPCPDAsandsmartphones(Intel
XScalefamily,SamsungSC32442 ARM9)
NintendoGameBoyAdvance(ARM7)
NintendoDS(ARM7,ARM9)
SonyNetworkWalkman(SonyinhouseARMbased
chip)
SomeNokiaandSonyEricssonmobilephones
 Pros

Emphasis on software
Single-clock,
reduced instruction only
Register to register:
"LOAD" and "STORE"
are independent instructions
Low cycles per second,
large code sizes
Spends more transistors
on memory registers
 Performance

The CISC approach attempts to

minimize the number of instructions
per program, sacrificing the number
of cycles per instruction. RISC does
the opposite, reducing the cycles per
instruction at the cost of the number
of instructions per program.
 CharacteristicsofRISCVsCISC
processors
No RISC CISC
1 Simple instructions taking one Complex instructions taking
cycle multiple cycles
2 Instructions are executed by Instructions are executed by
hardwired control unit microprogramed control unit
3 Few instructions Many instructions

4 Fixed format instructions Variable format instructions

5 Few addressing mode, and most Many addressing modes

instructions have register to
register addressing mode
6 Multiple register set Single register set

7 Highly pipelined Not pipelined or less pipelined

 SUMMARY

Computercomponentsanditsfunction
Evolutionandtypesofcomputer
Instructionandinstructionsequencing
Addressingmodes
RISCVsCISC
 REFERENCES

CarlHammacher,Computer
Organization,FifthEdition,McGrawHill
InternationalEdition,2002
P.PalChaudhuri,CompterOrganizationand
Design,2nd Edition,PHI,2003
WilliamStallings,Computerorganizationand
ArchitectureDesigningfor
Performance,PHI,2004