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Hdlusingverilog

Moore's law specifies that the number of transistors in a VLSI chip will increase exponentially with time. A test bench is required for simulation but not for mapping a design to an ASIC. Standard cell design has a fixed height for cells but the width can differ.

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VenkatGolla
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29 views3 pages

Hdlusingverilog

Moore's law specifies that the number of transistors in a VLSI chip will increase exponentially with time. A test bench is required for simulation but not for mapping a design to an ASIC. Standard cell design has a fixed height for cells but the width can differ.

Uploaded by

VenkatGolla
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
Download as doc, pdf, or txt
Download as doc, pdf, or txt
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1 point

What does Moores law specify?

The number of transistors in a VLSI chip will increase linearly with time.

The number of transistors in a VLSI chip will increase exponentially with time.

The power consumption in a VLSI chip will increase linearly with time.

None of the above.


1 point
Which of the following does not represent a behavioral representation for the function f = A . B + C?

The truth table of the function with output column (01010111)

A Verilog specification: assign f = (A & B) | C;

A netlist consisting of one 2-input AND and one 2-input OR gate

None of the above


1 point
Given a gate-level netlist represented by a graph, which of the following is not true for 4-input LUT mapping
in a typical FPGA?

The 4-input LUT is typically realized using a 16x1 SRAM unit.

Any circuit subgraph with up to 4 input edges and 1 output edge can be mapped to a LUT irrespective
of the number of vertices included therein.

In SRAM-based LUTs, the function of the LUT can be changed by downloading appropriate bit
patterns in the associated RAM locations.

None of the above


1 point
For which design style, the following statement is true?
The fabrication cost of a chip is C = C1 + C2, where C1 represents a cost that is
shared among several customers,
while C2 represents a cost that is to be separately borne by every customer.

Gate array

FPGA

Standard cell

Full custom
1 point
Which of the following is not true for standard cell based design?

i. The heights of the cells are fixed but the widths can be different.
ii. Any number of cells can be placed in a row.
iii. The number of cells that can be placed in a row is fixed.

iv. It requires more design effort as compared to full custom design.


ii. and iii.
ii. only

iii. and iv.

iii. only
1 point
Which of the following represents the correct ordering with respect to speed of circuits (fastest to slowest)?

Full custom, Gate array, Standard cell, FPGA

Full custom, Standard cell, FPGA, Gate array

Full custom, Gate array, FPGA, Standard cell

None of the above


1 point
Which of the following are true for structural design representation?

The design is represented as a netlist of gates.

The design is represented as a netlist of functional level modules.

The input-output functional behavior will be specified.

The assign statement in Verilog can be used to specify the design.


1 point
Which of the following statements are not true?

A test bench is required when we want to simulate a design.

When we map the design to an application specific integrated circuit, we do not need a test bench.

When we map the design to a field programmable gate array, we need a test bench.

Simulation means generation of a gate level netlist from a behavioral specification.


1 point
What function do the following Verilog module implement?

module guess (f, a, b, c);


input a,b,c;
output f;
wire t1, t2;
nand #1 G1 (t1,a,b);
or #1 G2 (t2,b,c);
and #1 G3 (f,t1,t2);
endmodule

f = a.b + a.c + b.c


f = a.b + b.c + c.a
f = a.b + b.c + c.a
None of the above
1 point
What function do the following Verilog module implement?
module guess (f, a, b, c);
input a,b,c;
output f;
wire t;
assign t = (a & b) | c;
assign f = a ^ t;
endmodule

f = a.b + a.b.c
f = a.c + a.b.c
f = a.c + a.b.c
None of the above
You may submit any number of times before the due date. The final submission will be considered for
grading.
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