74HC4052
74HC4052
74HC4052
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.
2. Features
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
80 (typical) at VCC VEE = 4.5 V
70 (typical) at VCC VEE = 6.0 V
60 (typical) at VCC VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical break before make built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4052
74HC4052D 40 C to +125 C SO16 plastic small outline package; 16 leads; body SOT109-1
width 3.9 mm
74HC4052DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
74HC4052N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC4052PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74HC4052BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
74HCT4052
74HCT4052D 40 C to +125 C SO16 plastic small outline package; 16 leads; body SOT109-1
width 3.9 mm
74HCT4052DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1
body width 5.3 mm
74HCT4052N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4052PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74HCT4052BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
5. Functional diagram
10 0 0
4
3
13 9 1
6 G4
1Z
1Y0 12
10 S0 1Y1 14 MDX
0 1
9 S1 1Y2 15 1 5
3
1Y3 11 2 2
2Y0 1 3 4
2Y1 5 12
2Y2 2 14
13
6 E 2Y3 4 15
2Z
11
001aah824
3 001aah825
nYn
VCC VEE
VCC VCC
VCC VEE
VEE nZ
from
logic
mnb043
VDD
16 13
1Z
12
1Y0
14
1Y1
15
1Y2
10
S0
11
1Y3
9 LOGIC
1-OF-4
S1 LEVEL
DECODER
CONVERSION
1
2Y0
6
E
5
2Y1
2
2Y2
4
2Y3
3
2Z
8 7
6. Pinning information
6.1 Pinning
74HC4052
74HC4052
74HCT4052
74HCT4052
16 VCC
2Y0
2Y0 1 16 VCC terminal 1
index area
1
2Y2 2 15 1Y2
2Y2 2 15 1Y2
2Z 3 14 1Y1
2Z 3 14 1Y1
2Y3 4 13 1Z 2Y3 4 13 1Z
9
VEE 7 10 S0
GND
S1
GND 8 9 S1 001aah823
7. Functional description
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VEE = GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +11.0 V
IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA
ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V - 20 mA
ISW switch current 0.5 V < VSW < VCC + 0.5 V - 25 mA
IEE supply current - 20 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [2] - 500 mW
P power dissipation per switch - 100 mW
[1] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE.
[2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
mnb044 mnb045
12 12
VCC GND
VCC GND (V)
10
(V)
8 8
operating area 6
operating area
4 4
0 0
0 4 8 12 0 4 8 12
VCC VEE (V) VCC VEE (V)
Fig 7. Guaranteed operating area as a function of the Fig 8. Guaranteed operating area as a function of the
supply voltages for 74HC4052 supply voltages for 74HCT4052
Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 continued
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4052: VCC GND = 4.5 V and 5.5 V, VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter Conditions Min Typ Max Unit
RON(rail) ON resistance (rail) Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 A [2] - - -
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 A - - 210
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 A - - 180
VCC = 4.5 V; VEE = 4.5 V; ISW = 1 000 A - - 160
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 A [2] - - -
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 A - - 240
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 A - - 210
VCC = 4.5 V; VEE = 4.5 V; ISW = 1 000 A - - 180
001aai068
100
(1)
RON
()
80
60 (2)
Vsw
V
(3)
40
VCC
from select Sn
input
20
nYn nZ
VCC
from select Sn
input Isw Isw
nYn nZ
A A
001aah827
VCC
HIGH
Sn
from select
input Isw
nYn nZ Vos
A
001aah828
Vis input 50 %
tPLH tPHL
Vos output 50 %
001aad555
VI
E, Sn inputs VM
0V
tPZL
tPLZ
Vos output 50 %
10 %
tPHZ tPZH
90 %
50 %
Vos output
001aae330
tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VI Vos RL S1
PULSE
DUT open
GENERATOR
RT CL
GND
VEE
001aae382
[1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.
[2] VI values:
a) For 74HC4052: VI = VCC
b) For 74HCT4052: VI = 3 V
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ).
[2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ).
VCC
Sn
10 F
nYn/nZ nZ/nYn
Vis Vos
VEE GND RL CL dB
001aah829
VCC
Sn
0.1 F
nYn/nZ nZ/nYn
Vis Vos
VEE GND RL CL dB
001aah871
001aae332
0
iso
(dB)
20
40
60
80
100
10 102 103 104 105 106
fi (kHz)
VCC
Sn
0.1 F RL
nYn/nZ nZ/nYn
Vis
VEE GND RL CL
VCC
Sn
nYn/nZ nZ/nYn
Vos
RL VEE GND RL CL dB
001aah873
Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers
Sn, E
Vct
nYn nZ
001aah913
Fig 19. Test circuit for measuring crosstalk between control input and any switch
VCC
Sn
10 F
nYn/nZ nZ/nYn
Vis Vos
VEE GND RL CL dB
001aah829
001aad551
5
Vos
(dB)
3
5
10 102 103 104 105 106
f (kHz)
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
99-12-27
SOT109-1 076E07 MS-012
03-02-19
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
D E A
X
c
y HE v M A
16 9
Q
A2 A
A1 (A 3)
pin 1 index
Lp
L
1 8 detail X
w M
e bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT338-1 MO-150
03-02-19
D ME
seating plane
A2 A
L A1
c
Z e w M
b1
(e 1)
b b2
16 9 MH
pin 1 index
E
1 8
0 5 10 mm
scale
UNIT
A A1 A2
b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 1.25 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 0.76
1.30 0.38 0.85 0.23 18.55 6.20 3.05 7.80 8.3
inches 0.068 0.021 0.049 0.014 0.77 0.26 0.14 0.32 0.39
0.17 0.02 0.13 0.1 0.3 0.01 0.03
0.051 0.015 0.033 0.009 0.73 0.24 0.12 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
95-01-14
SOT38-4
03-02-13
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT403-1 MO-153
03-02-18
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1
D B A
A
A1
E c
terminal 1 detail X
index area
terminal 1 C
e1
index area
e b v M C A B y1 C y
w M C
2 7
1 8
Eh e
16 9
15 10
Dh
X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max.
A1 b c D (1) Dh E (1) Eh e e1 L v w y y1
02-10-17
SOT763-1 --- MO-241 ---
03-01-27
14. Abbreviations
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
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[2] The term short data sheet is explained in section Definitions.
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information is available on the Internet at URL http://www.nxp.com.
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therefore such inclusion and/or use is at the customers own risk.
Draft The document is a draft version only. The content is still under
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use of such information. Limiting values Stress above one or more limiting values (as defined in
Short data sheet A short data sheet is an extract from a full data sheet the Absolute Maximum Ratings System of IEC 60134) may cause permanent
with the same product type number(s) and title. A short data sheet is intended damage to the device. Limiting values are stress ratings only and operation of
for quick reference only and should not be relied upon to contain detailed and the device at these or any other conditions above those given in the
full information. For detailed and full information see the relevant full data Characteristics sections of this document is not implied. Exposure to limiting
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18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 12
12 Additional dynamic characteristics . . . . . . . . 16
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17 Contact information. . . . . . . . . . . . . . . . . . . . . 26
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.