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'HVLJQRI%LW0,365,6&3URFHVVRU%DVHG Rq6Rf

This document describes the design of a 32-bit MIPS RISC processor based on an FPGA. It involves designing the core modules of a 32-bit RISC processor including instruction fetch, instruction decode, execution, data memory, and write back. The processor is designed using Verilog HDL, synthesized using Xilinx ISE 14.2, and simulated using QuestaSim 6.4C simulator. Key aspects of MIPS processor architecture are discussed such as its 5-stage pipeline, load/store architecture, and use of registers for operations.

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0% found this document useful (0 votes)
45 views5 pages

'HVLJQRI%LW0,365,6&3URFHVVRU%DVHG Rq6Rf

This document describes the design of a 32-bit MIPS RISC processor based on an FPGA. It involves designing the core modules of a 32-bit RISC processor including instruction fetch, instruction decode, execution, data memory, and write back. The processor is designed using Verilog HDL, synthesized using Xilinx ISE 14.2, and simulated using QuestaSim 6.4C simulator. Key aspects of MIPS processor architecture are discussed such as its 5-stage pipeline, load/store architecture, and use of registers for operations.

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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
Download as pdf or txt
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Department of Electronics and Communication Engineering
MIT, Aurangabad,Maharashtra,India

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