MPC7448 RISC Microprocessor Hardware Specifications: Freescale Semiconductor

Freescale Semiconductor Document Number: MPC7448EC
Technical Data Rev. 4, 3/2007
MPC7448
RISC Microprocessor
Hardware Specifications
This document is primarily concerned with the MPC7448, Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
which is targeted at networking and computing systems 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
applications. This document describes pertinent electrical and 3. Comparison with the MPC7447A, MPC7447,
physical characteristics of the MPC7448. For information MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . 7
4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
regarding specific MPC7448 part numbers covered by this
5. Electrical and Thermal Characteristics . . . . . . . . . . . . 9
document and part numbers covered by other documents, refer 6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
to Section 11, Part Numbering and Marking. For functional 7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
characteristics of the processor, refer to the MPC7450 RISC 8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29
9. System Design Information . . . . . . . . . . . . . . . . . . . 35
Microprocessor Family Reference Manual. 10. Document Revision History . . . . . . . . . . . . . . . . . . . 55
To locate any published updates for this document, refer to the 11. Part Numbering and Marking . . . . . . . . . . . . . . . . . . 57
website listed on the back cover of this document.
1 Overview
The MPC7448 is the sixth implementation of fourth-
generation (G4) microprocessors from Freescale. The
MPC7448, built on Power Architecture technology,
implements the PowerPC instruction set architecture
version 1.0 and is targeted at networking and computing
systems applications. The MPC7448 consists of a processor
core and a 1-Mbyte L2.
Figure 1 shows a block diagram of the MPC7448. The core is
a high-performance superscalar design supporting a
double-precision floating-point unit and a SIMD multimedia
unit. The memory storage subsystem supports the MPX bus
protocol and a subset of the 60x bus protocol to main memory
and other system resources.
Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.

2
Additional Features 128-Bit (4 Instructions)
Instruction Unit Instruction Queue Instruction MMU
Time Base Counter/Decrementer
Overview
Clock Multiplier (12-Word) SRs 128-Entry

Branch Processing Unit Fetcher
JTAG/COP Interface (Shadow) ITLB 32-Kbyte
Thermal/Power Management BTIC (128-Entry) CTR Tags
I Cache
Performance Monitor IBAT Array
Out-of-Order Issue of AltiVec Instr. BHT (2048-Entry) LR
Dispatch
Unit Data MMU
32-Kbyte
Completion Unit 96-Bit (3 Instructions)
128-Entry Tags
SRs D Cache
Completion Queue (Original) DTLB
(16-Entry) VR Issue GPR Issue FPR Issue
(4-Entry/2-Issue) (6-Entry/3-Issue) (2-Entry/1-Issue) DBAT Array
Reservation
Stations (2-Entry)
EA
Completes up Vector
to three Touch Load/Store Unit
instructions Queue PA
per clock Reservation Reservation
Reservation Vector Touch Engine Reservation
Reservation
Stations (2) Station
Station
Station + (EA Calculation) Stations (2)
VR File GPR File FPR File
16 Rename 16 Rename Finished L1 Castout 16 Rename

Buffers Buffers Stores Buffers
Reservation Reservation Reservation Reservation Integer Integer
Integer
Integer Floating-
Station Station Station Station Unit 2 Unit
Unit
Unit122 Point Unit
(3)
L1 Push + x
x +++
Vector Vector Vector Completed FPSCR
Vector
Permute Integer Integer Stores Load Miss
FPU 32-Bit 32-Bit 32-Bit 64-Bit 64-Bit
Unit Unit 2 Unit 1
128-Bit
128-Bit
Figure 1. MPC7448 Block Diagram

Memory Subsystem
L1 Store Queue
1-Mbyte Unified L2 Cache Controller System Bus Interface
(LSQ)
L1 Service Line Block 0 (32-Byte) Load
Block 1 (32-Byte)
Queues Queue (11) Bus Store Queue
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

L1 Load Queue (LLQ) Tags Status Status
Castout
Queue (5) /
L1 Load Miss (5) Push
L2 Store Queue (L2SQ) Queue (6)1
L2 Prefetch (3) L1 Castouts Snoop Push/
(4) Interventions
Instruction Fetch (2)
Bus Accumulator
Cacheable Store Miss (2)
36-Bit 64-Bit
Notes: The Castout Queue and Push Queue share resources such for a combined total of 6 entries. Address Bus Data Bus
The Castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.
Freescale Semiconductor
Features
2 Features
This section summarizes features of the MPC7448 implementation.
Major features of the MPC7448 are as follows:
High-performance, superscalar microprocessor
Up to four instructions can be fetched from the instruction cache at a time.
Up to three instructions plus a branch instruction can be dispatched to the issue queues at a
time.
Up to 12 instructions can be in the instruction queue (IQ).
Up to 16 instructions can be at some stage of execution simultaneously.
Single-cycle execution for most instructions
One instruction per clock cycle throughput for most instructions
Seven-stage pipeline control
Eleven independent execution units and three register files
Branch processing unit (BPU) features static and dynamic branch prediction
128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
the first four instructions in the target stream.
2048-entry branch history table (BHT) with 2 bits per entry for four levels of
predictionnot taken, strongly not taken, taken, and strongly taken
Up to three outstanding speculative branches
Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) instructions
Four integer units (IUs) that share 32 GPRs for integer operands
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
IU2 executes miscellaneous instructions, including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
Five-stage FPU and 32-entry FPR file
Fully IEEE Std. 754-1985compliant FPU for both single- and double-precision
operations
Supports non-IEEE mode for time-critical operations
Hardware support for denormalized numbers
Thirty-two 64-bit FPRs for single- or double-precision operands

Freescale Semiconductor 3
Features
Four vector units and 32-entry vector register file (VRs)

Vector permute unit (VPU)
Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).
Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm).
Vector floating-point unit (VFPU)
Three-stage load/store unit (LSU)
Supports integer, floating-point, and vector instruction load/store traffic
Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle
throughput
Four-cycle FPR load latency (single, double) with one-cycle throughput
No additional delay for misaligned access within double-word boundary
A dedicated adder calculates effective addresses (EAs).
Supports store gathering
Performs alignment, normalization, and precision conversion for floating-point data
Executes cache control and TLB instructions
Performs alignment, zero padding, and sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
Instructions can only be dispatched from the three lowest IQ entriesIQ0, IQ1, and IQ2.
A maximum of three instructions can be dispatched to the issue queues per clock cycle.
Space must be available in the CQ for an instruction to dispatch (this includes instructions that
are assigned a space in the CQ but not in an issue queue).
Rename buffers
16 GPR rename buffers
16 FPR rename buffers
16 VR rename buffers
Dispatch unit
Decode/dispatch stage fully decodes each instruction
Completion unit
Retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of
it have been completed, the instruction has finished executing, and no exceptions are pending
Guarantees sequential programming model (precise exception model)

4 Freescale Semiconductor
Features
Monitors all dispatched instructions and retires them in order

Tracks unresolved branches and flushes instructions after a mispredicted branch
Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
32-Kbyte, eight-way set-associative instruction and data caches
Pseudo least-recently-used (PLRU) replacement algorithm
32-byte (eight-word) L1 cache block
Physically indexed/physical tags
Cache write-back or write-through operation programmable on a per-page or per-block basis
Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
Caches can be disabled in software.
Caches can be locked in software.
MESI data cache coherency maintained in hardware
Separate copy of data cache tags for efficient snooping
Parity support on cache
No snooping of instruction cache except for icbi instruction
Data cache supports AltiVec LRU and transient instructions
Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
On-chip, 1-Mbyte, eight-way set-associative unified instruction and data cache
Cache write-back or write-through operation programmable on a per-page or per-block basis
Parity support on cache tags
ECC or parity support on data
Error injection allows testing of error recovery software
Separate memory management units (MMUs) for instructions and data
52-bit virtual address, 32- or 36-bit physical address
Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
Separate IBATs and DBATs (eight each) also defined as SPRs
Separate instruction and data translation lookaside buffers (TLBs)
Both TLBs are 128-entry, two-way set-associative and use an LRU replacement algorithm.
TLBs are hardware- or software-reloadable (that is, a page table search is performed in
hardware or by system software on a TLB miss).

Features
Efficient data flow

Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.
The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.
The L2 cache is fully pipelined to provide 32 bytes per clock every other cycle to the L1 caches.
As many as 16 out-of-order transactions can be present on the MPX bus.
Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
Hardware-enforced, MESI cache coherency protocols for data cache
Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power and thermal management
Dynamic frequency switching (DFS) feature allows processor core frequency to be halved or
quartered through software to reduce power consumption.
The following three power-saving modes are available to the system:
NapInstruction fetching is halted. Only the clocks for the time base, decrementer, and
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and then back to nap using a QREQ/QACK processor-system handshake
protocol.
SleepPower consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
Deep sleepWhen the part is in the sleep state, the system can disable the PLL. The system
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed upon exiting the deep
sleep state.
Instruction cache throttling provides control of instruction fetching to limit device temperature.
A new temperature diode that can determine the temperature of the microprocessor
Performance monitor can be used to help debug system designs and improve software efficiency.
In-system testability and debugging features through JTAG boundary-scan capability
Testability
LSSD scan design
IEEE Std. 1149.1 JTAG interface

Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441
Reliability and serviceability

Parity checking on system bus
Parity checking on the L1 caches and L2 data tags
ECC or parity checking on L2 data
3 Comparison with the MPC7447A, MPC7447, MPC7445,

and MPC7441
Table 1 compares the key features of the MPC7448 with the key features of the earlier MPC7447A,
MPC7447, MPC7445, and MPC7441. All are based on the MPC7450 RISC microprocessor and are
architecturally very similar. The MPC7448 is identical to the MPC7447A, but the MPC7448 supports 1
Mbyte of L2 cache with ECC and the use of dynamic frequency switching (DFS) with more bus-to-core
ratios.
Table 1. Microarchitecture Comparison
Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441
Basic Pipeline Functions

Logic inversions per cycle 18
Pipeline stages up to execute 5
Total pipeline stages (minimum) 7
Pipeline maximum instruction throughput 3 + branch
Pipeline Resources
Instruction buffer size 12
Completion buffer size 16
Renames (integer, float, vector) 16, 16, 16
Maximum Execution Throughput
SFX 3
Vector 2 (any 2 of 4 units)
Scalar floating-point 1
Out-of-Order Window Size in Execution Queues
SFX integer units 1 entry 3 queues
Vector units In order, 4 queues
Scalar floating-point unit In order
Branch Processing Resources
Prediction structures BTIC, BHT, link stack
BTIC size, associativity 128-entry, 4-way
BHT size 2K-entry
Link stack depth 8
Unresolved branches supported 3
Branch taken penalty (BTIC hit) 1
Minimum misprediction penalty 6

Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441
Execution Unit Timings (Latency-Throughput)

Aligned load (integer, float, vector) 3-1, 4-1, 3-1
Misaligned load (integer, float, vector) 4-2, 5-2, 4-2
L1 miss, L2 hit latency with ECC (data/instruction) 12/16
L1 miss, L2 hit latency without ECC (data/instruction) 11/15 9/13
SFX (add, sub, shift, rot, cmp, logicals) 1-1
Integer multiply (32 8, 32 16, 32 32) 4-1, 4-1, 5-2
Scalar float 5-1
VSFX (vector simple) 1-1
VCFX (vector complex) 4-1
VFPU (vector float) 4-1
VPER (vector permute) 2-1
MMUs
TLBs (instruction and data) 128-entry, 2-way
Tablewalk mechanism Hardware + software
Instruction BATs/data BATs 8/8 8/8 8/8 8/8 4/4
L1 I Cache/D Cache Features
Size 32K/32K
Associativity 8-way
Locking granularity Way
Parity on I cache Word
Parity on D cache Byte
Number of D cache misses (load/store) 5/2 5/1
Data stream touch engines 4 streams
On-Chip Cache Features
Cache level L2
Size/associativity 1-Mbyte/ 512-Kbyte/8-way 256-Kbyte/8-way
8-way
Access width 256 bits
Number of 32-byte sectors/line 2 2
Parity tag Byte Byte
Parity data Byte Byte
Data ECC 64-bit
Thermal Control
Dynamic frequency switching divide-by-two mode Yes Yes No No No
Dynamic frequency switching divide-by-four mode Yes No No No No
Thermal diode Yes Yes No No No

General Parameters
4 General Parameters
The following list summarizes the general parameters of the MPC7448:
Technology 90 nm CMOS SOI, nine-layer metal
Die size 8.0 mm 7.3 mm
Transistor count 90 million
Logic design Mixed static and dynamic
Packages Surface mount 360 ceramic ball grid array (HCTE)
Surface mount 360 ceramic land grid array (HCTE)
Surface mount 360 ceramic ball grid array with lead-free spheres (HCTE)
Core power supply 1.30 V (1700 MHz device)
1.25 V (1600 MHz device)
I/O power supply 1.5 V, 1.8 V, or 2.5 V
5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC7448.
5.1 DC Electrical Characteristics

The tables in this section describe the MPC7448 DC electrical characteristics. Table 2 provides the
absolute maximum ratings. See Section 9.2, Power Supply Design and Sequencing, for power
sequencing requirements.
Table 2. Absolute Maximum Ratings 1
Characteristic Symbol Maximum Value Unit Notes

Core supply voltage VDD 0.3 to 1.4 V 2
PLL supply voltage AVDD 0.3 to 1.4 V 2
Processor bus supply voltage I/O Voltage Mode = 1.5 V OVDD 0.3 to 1.8 V 3
I/O Voltage Mode = 1.8 V 0.3 to 2.2 3
I/O Voltage Mode = 2.5 V 0.3 to 3.0 3
Input voltage Processor bus Vin 0.3 to OV DD + 0.3 V 4
JTAG signals Vin 0.3 to OV DD + 0.3 V
Storage temperature range Tstg 55 to 150 C
C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. See Section 9.2, Power Supply Design and Sequencing for power sequencing requirements.
3. Bus must be configured in the corresponding I/O voltage mode; see Table 3.
4. Caution: V in must not exceed OVDD by more than 0.3 V at any time including during power-on reset except as allowed by
the overshoot specifications. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7448.

OV DD + 20%
OVDD + 5%
OVDD
VIH
VIL
GND
GND 0.3 V
GND 0.7 V
Not to Exceed 10%
of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7448 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7448 core voltage must always be provided at the nominal voltage
(see Table 4). The input voltage threshold for each bus is selected by sampling the state of the voltage
select pins at the negation of the signal HRESET. The output voltage will swing from GND to the
maximum voltage applied to the OVDD power pins. Table 3 provides the input threshold voltage settings.
Because these settings may change in future products, it is recommended that BVSEL[0:1] be configured
using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the
termination of this signal in the future, if necessary.
Table 3. Input Threshold Voltage Setting
BVSEL0 BVSEL1 I/O Voltage Mode 1 Notes
0 0 1.8 V 2, 3
0 1 2.5 V 2, 4
1 0 1.5 V 2
1 1 2.5 V 4
Notes:
1. Caution: The I/O voltage mode selected must agree with the OVDD voltages
supplied. See Table 4.
2. If used, pull-down resistors should be less than 250 .
3. The pin configuration used to select 1.8V mode on the MPC7448 is not compatible
with the pin configuration used to select 1.8V mode on the MPC7447A and earlier
devices.
4. The pin configuration used to select 2.5V mode on the MPC7448 is fully compatible
with the pin configuration used to select 2.5V mode on the MPC7447A and earlier
devices.

Table 4 provides the recommended operating conditions for the MPC7448 part numbers described by this
document; see Section 11.1, Part Numbers Fully Addressed by This Document, for more information.
See Section 9.2, Power Supply Design and Sequencing for power sequencing requirements.
Table 4. Recommended Operating Conditions1
Recommended Value
Unit Notes
Characteristic Symbol 1000 MHz 1420 MHz 1600 MHz 1700 MHz
Min Max Min Max Min Max Min Max
Core supply voltage VDD 1.15 V 50 mV 1.2 V 50 mV 1.25 V 50 mV 1.3 V +20/ V 3, 4, 5

50 mV
PLL supply voltage AVDD 1.15 V 50 mV 1.2 V 50 mV 1.25 V 50 mV 1.3 V +20/ V 2, 3, 4

50 mV
Processor I/O Voltage Mode = 1.5 V OVDD 1.5 V 5% 1.5 V 5% 1.5 V 5% 1.5 V 5% V 4
bus
supply I/O Voltage Mode = 1.8 V 1.8 V 5% 1.8 V 5% 1.8 V 5% 1.8 V 5% 4
voltage I/O Voltage Mode = 2.5 V 2.5 V 5% 2.5 V 5% 2.5 V 5% 2.5 V 5% 4
Input Processor bus Vin GND OVDD GND OVDD GND OVDD GND OVDD V
voltage
JTAG signals Vin GND OVDD GND OVDD GND OVDD GND OVDD
Die-junction temperature Tj 0 105 0 105 0 105 0 105 C

C 6
Notes:
1. These are the recommended and tested operating conditions.
2. This voltage is the input to the filter discussed in Section 9.2.2, PLL Power Supply Filtering, and not necessarily the voltage
at the AVDD pin, which may be reduced from V DD by the filter.
3. Some early devices supported voltage and frequency derating whereby VDD (and AVDD) could be reduced to reduce power
consumption. This feature has been superseded and is no longer supported. See Section 5.3, Voltage and Frequency
Derating, for more information.
4. Caution: Power sequencing requirements must be met; see Section 9.2, Power Supply Design and Sequencing.
5. Caution: See Section 9.2.3, Transient Specifications for information regarding transients on this power supply.
6. For information on extended temperature devices, see Section 11.2, Part Numbers Not Fully Addressed by This Document.

Table 5 provides the package thermal characteristics for the MPC7448. For more information regarding
thermal management, see Section 9.7, Power and Thermal Management Information.
Table 5. Package Thermal Characteristics1
Characteristic Symbol Value Unit Notes
Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board RJA 26 C/W
C/W 2, 3
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board RJMA 19 C/W
C/W 2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board RJMA 22 C/W
C/W 2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board RJMA 16 C/W
C/W 2, 4
Junction-to-board thermal resistance RJB 11 C/W

C/W 5
Junction-to-case thermal resistance RJC < 0.1 C/W

C/W 6
Notes:
1. Refer to Section 9.7, Power and Thermal Management Information, for details about thermal management.
2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
3. Per JEDEC JESD51-2 with the single-layer board horizontal
4. Per JEDEC JESD51-6 with the board horizontal
5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
6. This is the thermal resistance between die and case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1) with the calculated case temperature. The actual value of R JC for the part is less than 0.1C/W.
Table 6 provides the DC electrical characteristics for the MPC7448.

Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Nominal Bus
Characteristic Symbol Min Max Unit Notes
Voltage 1
Input high voltage 1.5 VIH OVDD 0.65 OVDD + 0.3 V 2

(all inputs)
1.8 OVDD 0.65 OVDD + 0.3
2.5 1.7 OVDD + 0.3
Input low voltage 1.5 VIL 0.3 OVDD 0.35 V 2

(all inputs)
1.8 0.3 OVDD 0.35
2.5 0.3 0.7
Input leakage current, all signals except Iin A 2, 3

BVSEL0, LSSD_MODE, TCK, TDI, TMS,
TRST:
Vin = OVDD 50
Vin = GND 50
Input leakage current, BVSEL0, Iin A 2, 6

LSSD_MODE, TCK, TDI, TMS, TRST:
Vin = OVDD 50
Vin = GND 2000

Table 6. DC Electrical Specifications (continued)

Nominal Bus
Characteristic Symbol Min Max Unit Notes
Voltage 1
High-impedance (off-state) leakage current: ITSI A 2, 3, 4

Vin = OVDD 50
Vin = GND 50
Output high voltage @ IOH = 5 mA 1.5 VOH OVDD 0.45 V
1.8 OVDD 0.45
2.5 1.8
Output low voltage @ IOL = 5 mA 1.5 VOL 0.45 V
1.8 0.45
2.5 0.6
Capacitance, All inputs Cin 8.0 pF 5

Vin = 0 V, f = 1 MHz
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. All I/O signals are referenced to OVDD.
3. Excludes test signals and IEEE Std. 1149.1 boundary scan (JTAG) signals
4. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for
example, both OVDD and VDD vary by either +5% or 5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. These pins have internal pull-up resistors.
Table 7 provides the power consumption for the MPC7448 part numbers described by this document; see
Section 11.1, Part Numbers Fully Addressed by This Document, for information regarding which part
numbers are described by this document. Freescale also offers MPC7448 part numbers that meet lower
power consumption specifications by adhering to lower core voltage and core frequency specifications.
For more information on these devices, including references to the MPC7448 Hardware Specification
Addenda that describe these devices, see Section 11.2, Part Numbers Not Fully Addressed by This
Document.
The power consumptions provided in Table 7 represent the power consumption of each speed grade when
operated at the rated maximum core frequency (see Table 8). Freescale sorts devices by power as well as
by core frequency, and power limits for each speed grade are independent of each other. Each device is
tested at its maximum core frequency only. (Note that Deep Sleep Mode power consumption is
independent of clock frequency.) Operating a device at a frequency lower than its rated maximum is fully
supported provided the clock frequencies are within the specifications given in Table 8, and a device
operated below its rated maximum will have lower power consumption. However, inferences should not
be made about a devices power consumption based on the power specifications of another (lower) speed
grade. For example, a 1700 MHz device operated at 1420 MHz may not exhibit the same power
consumption as a 1420 MHz device operated at 1420 MHz.
For all MPC7448 devices, the following guidelines on the use of these parameters for system design are
suggested. The Full-Power ModeTypical value represents the sustained power consumption of the device

when running a typical benchmark at temperatures in a typical system. The Full-Power ModeThermal
value is intended to represent the sustained power consumption of the device when running a typical code
sequence at high temperature and is recommended to be used as the basis for designing a thermal solution;
see Section 9.7, Power and Thermal Management Information for more information on thermal
solutions. The Full-Power ModeMaximum value is recommended to be used for power supply design
because this represents the maximum peak power draw of the device that a power supply must be capable
of sourcing without voltage droop. For information on power consumption when dynamic frequency
switching is enabled, see Section 9.7.5, Dynamic Frequency Switching (DFS).
Table 7. Power Consumption for MPC7448 at Maximum Rated Frequency
Die Junction Maximum Processor Core Frequency (Speed Grade, MHz)

Temperature Unit Notes
(Tj) 1000 MHz 1420 MHz 1600 MHz 1700 MHz
Full-Power Mode
Typical 65 C
C 15.0 19.0 20.0 21.0 W 1, 2
Thermal 105 C
C 18.6 23.3 24.4 25.6 W 1, 5
Maximum 105 C
C 21.6 27.1 28.4 29.8 W 1, 3
Nap Mode
Typical 105 C
C 11.1 11.8 13.0 13.0 W 1, 6
Sleep Mode
Typical 105 C
C 10.8 11.4 12.5 12.5 W 1, 6
Deep Sleep Mode (PLL Disabled)
Typical 105 C
C 10.4 11.0 12.0 12.0 W 1, 6
Notes:
1. These values specify the power consumption for the core power supply (VDD) at nominal voltage and apply to all valid
processor bus frequencies and configurations. The values do not include I/O supply power (OV DD) or PLL supply power
(AV DD). OVDD power is system dependent but is typically < 5% of VDD power. Worst case power consumption for
AVDD < 13 mW. Freescale also offers MPC7448 part numbers that meet lower power consumption specifications; for
more information on these devices, see Section 11.2, Part Numbers Not Fully Addressed by This Document.
2. Typical power consumption is an average value measured with the processor operating at its rated maximum processor
core frequency (except for Deep Sleep Mode), at nominal recommended VDD (see Table 4) and 65C while running the
Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. This parameter is not 100% tested but periodically
sampled.b
3. Maximum power consumption is the average measured with the processor operating at its rated maximum processor core
frequency, at nominal VDD and maximum operating junction temperature (see Table 4) while running an entirely
cache-resident, contrived sequence of instructions to keep all the execution units maximally busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As
a result, power consumption for this mode is not tested.
5. Thermal power consumption is an average value measured at the nominal recommended VDD (see Table 4) and 105 C
while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. This parameter is not 100% tested
but periodically sampled.
6. Typical power consumption for these modes is measured at the nominal recommended VDD (see Table 4) and 105 C in
the mode described. This parameter is not 100% tested but is periodically sampled.

5.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7448. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 5.2.1, Clock AC Specifications,
and tested for conformance to the AC specifications for that frequency. The processor core frequency,
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:5] signals, can be
dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum processor
core frequency; see Section 11, Part Numbering and Marking, for information on ordering parts. DFS is
described in Section 9.7.5, Dynamic Frequency Switching (DFS).
5.2.1 Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested
operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8, is
considered a practical maximum in a typical single-processor system. This does not exclude
multi-processor systems, but these typically require considerably more design effort to achieve the
maximum rated bus frequency. The actual maximum SYSCLK frequency for any application of the
MPC7448 will be a function of the AC timings of the microprocessor(s), the AC timings for the system
controller, bus loading, circuit board topology, trace lengths, and so forth, and may be less than the value
given in Table 8.

Table 8. Clock AC Timing Specifications

Maximum Processor Core Frequency (Speed Grade)
Characteristic Symbol 1000 MHz 1420 MHz 1600 MHz 1700 MHz Unit Notes
Min Max Min Max Min Max Min Max
Processor DFS mode disabled fcore 600 1000 600 1420 600 1600 600 1700 MHz 1, 8
core
frequency DFS mode enabled fcore_DF 300 500 300 710 300 800 300 850 9
VCO frequency fVCO 600 1000 600 1420 600 800 600 1700 MHz 1, 10
SYSCLK frequency fSYSCLK 33 200 33 200 33 200 33 200 MHz 1, 2, 8
SYSCLK cycle time tSYSCLK 5.0 30 5.0 30 5.0 30 5.0 30 ns 2
SYSCLK rise and fall time tKR, tKF 0.5 0.5 0.5 0.5 ns 3
SYSCLK duty cycle measured at tKHKL/ 40 60 40 60 40 60 40 60 % 4

OVDD/2 tSYSCLK
SYSCLK cycle-to-cycle jitter 150 150 150 150 ps 5, 6
Internal PLL relock time 100 100 100 100 s 7
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus)
frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:5] signal description in Section 9.1.1, PLL Configuration, for valid
PLL_CFG[0:5] settings.
2. Actual maximum system bus frequency is system-dependent. See Section 5.2.1, Clock AC Specifications.
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design
6. The SYSCLK drivers closed loop jitter bandwidth should be less than 1.5 MHz at 3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled.
fcore_DFS provides the maximum and minimum core frequencies when operating in a DFS mode.
9.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes
(divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum
frequencies stated for fcore.
10.Use of the DFS feature does not affect VCO frequency.

Figure 3 provides the SYSCLK input timing diagram.

CVIH
SYSCLK VM VM VM
CVIL
tKHKL tKR tKF
tSYSCLK
VM = Midpoint Voltage (OV DD/2)
Figure 3. SYSCLK Input Timing Diagram
5.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7448 as defined in Figure 4 and
Figure 5.
Table 9. Processor Bus AC Timing Specifications1
All Speed Grades

Parameter Symbol 2 Unit Notes
Min Max
Input setup times: ns

A[0:35], AP[0:4] tAVKH 1.5
D[0:63], DP[0:7] tDVKH 1.5
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4], tIVKH 1.5
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1] tMVKH 1.5 8
Input hold times: ns

A[0:35], AP[0:4] tAXKH 0
D[0:63], DP[0:7] tDXKH 0
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4], tIXKH 0
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1] tMXKH 0 8
Output valid times: ns

A[0:35], AP[0:4] tKHAV 1.8
D[0:63], DP[0:7] tKHDV 1.8
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST, tKHOV 1.8
TSIZ[0:2], TT[0:4], WT
TS tKHTSV 1.8
ARTRY, SHD[0:1] tKHARV 1.8
Output hold times: ns

A[0:35], AP[0:4] tKHAX 0.5
D[0:63], DP[0:7] tKHDX 0.5
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST, tKHOX 0.5
TSIZ[0:2], TT[0:4], WT
TS tKHTSX 0.5
ARTRY, SHD[0:1] tKHARX 0.5
SYSCLK to output enable tKHOE 0.5 ns 5

Table 9. Processor Bus AC Timing Specifications1 (continued)

All Speed Grades

Parameter Symbol 2 Unit Notes
Min Max
SYSCLK to output high impedance (all except TS, ARTRY, tKHOZ 1.8 ns 5
SHD0, SHD1)
SYSCLK to TS high impedance after precharge tKHTSPZ 1 tSYSCLK 3, 4, 5
Maximum delay to ARTRY/SHD0/SHD1 precharge tKHARP 1 tSYSCLK 3, 5, 6, 7
SYSCLK to ARTRY/SHD0/SHD1 high impedance after tKHARPZ 2 tSYSCLK 3, 5, 6, 7

precharge
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50- load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the
input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for
inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and precharged high
before returning to high impedance, as shown in Figure 6. The nominal precharge width for TS is tSYSCLK, that is, one clock
period. Since no master can assert TS on the following clock edge, there is no concern regarding contention with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impedance for a fraction of a cycle, then negated for up to an entire cycle
(crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for ARTRY is 1.0 tSYSCLK;
that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY.
Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning two cycles after TS.
Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
8. BMODE[0:1] and BVSEL[0:1] are mode select inputs. BMODE[0:1] are sampled before and after HRESET negation.
BVSEL[0:1] are sampled before HRESET negation. These parameters represent the input setup and hold times for each
sample. These values are guaranteed by design and not tested. BMODE[0:1] must remain stable after the second sample;
BVSEL[0:1] must remain stable after the first (and only) sample. See Figure 5 for sample timing.

Figure 4 provides the AC test load for the MPC7448.
Output Z0 = 50 OVDD/2
RL = 50
Figure 4. AC Test Load
Figure 5 provides the BMODE[0:1] input timing diagram for the MPC7448. These mode select inputs are
sampled once before and once after HRESET negation.
SYSCLK VM VM
HRESET
BMODE[0:1]
1st Sample 2nd Sample

VM = Midpoint Voltage (OVDD/2)
Figure 5. BMODE[0:1] Input Sample Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7448.
SYSCLK VM VM VM
tAVKH tAXKH
tIXKH
tIVKH
tMXKH
tMVKH
All Inputs
tKHAV tKHAX
tKHDV tKHDX
tKHOV tKHOX
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHOE
tKHOZ
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHTSPZ
tKHTSV
tKHTSX
tKHTSV
TS
tKHARPZ
tKHARV tKHARP
ARTRY, tKHARX
SHD0,
SHD1
Figure 6. Input/Output Timing Diagram

5.2.3 IEEE Std. 1149.1 AC Timing Specifications

Table 10 provides the IEEE Std. 1149.1 (JTAG) AC timing specifications as defined in Figure 8 through
Figure 11.
Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1
Parameter Symbol Min Max Unit Notes
TCK frequency of operation fTCLK 0 33.3 MHz
TCK cycle time tTCLK 30 ns
TCK clock pulse width measured at 1.4 V tJHJL 15 ns
TCK rise and fall times tJR and tJF 2 ns
TRST assert time tTRST 25 ns 2
Input setup times: ns 3

Boundary-scan data tDVJH 4
TMS, TDI tIVJH 0
Input hold times: ns 3

Boundary-scan data tDXJH 20
TMS, TDI tIXJH 25
Valid times: ns 4
Boundary-scan data tJLDV 4 20
TDO tJLOV 4 25
Output hold times: ns 4

Boundary-scan data tJLDX 30
TDO tJLOX 30
TCK to output high impedance: ns 4, 5

Boundary-scan data tJLDZ 3 19
TDO tJLOZ 3 9
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 7).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.

Figure 7 provides the AC test load for TDO and the boundary-scan outputs of the MPC7448.
Output Z0 = 50 OVDD/2
RL = 50
Figure 7. Alternate AC Test Load for the JTAG Interface
Figure 8 provides the JTAG clock input timing diagram.
TCLK VM VM VM
tJHJL tJR tJF

tTCLK
Figure 8. JTAG Clock Input Timing Diagram
Figure 9 provides the TRST timing diagram.
TRST VM VM
tTRST
Figure 9. TRST Timing Diagram
Figure 10 provides the boundary-scan timing diagram.
TCK VM VM
tDVJH
tDXJH
Boundary Input
Data Inputs Data Valid
tJLDV
tJLDX
Boundary
Data Outputs Output Data Valid
tJLDZ
Boundary
Data Outputs Output Data Valid

Figure 10. Boundary-Scan Timing Diagram

Figure 11 provides the test access port timing diagram.
TCK VM VM
tIVJH
tIXJH
TDI, TMS Input

Data Valid
tJLOV
tJLOX
TDO Output Data Valid
tJLOZ
TDO Output Data Valid

Figure 11. Test Access Port Timing Diagram
5.3 Voltage and Frequency Derating

Voltage and frequency derating is no longer supported for part numbers described by this document
beginning with datecode 0613. (See Section 11, Part Numbering and Marking, for information on date
code markings.) It is supported by some MPC7448 part numbers which target low-power applications; see
Section 11.2, Part Numbers Not Fully Addressed by This Document and the referenced MPC7448
Hardware Specification Addenda for more information on these low-power devices. For those devices
which previously supported this feature, information has been archived in the Chip Errata for the
MPC7448 (document order no. MPC7448CE).

Pin Assignments
6 Pin Assignments
Figure 12 (in Part A) shows the pinout of the MPC7448, 360 high coefficient of thermal expansion ceramic
ball grid array (HCTE) package as viewed from the top surface. Part B shows the side profile of the HCTE
package to indicate the direction of the top surface view.
Part A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Not to Scale
Part B
Substrate Assembly View
Encapsulant Die
Figure 12. Pinout of the MPC7448, 360 HCTE Package as Viewed from the Top Surface

Pinout Listings
7 Pinout Listings
Table 11 provides the pinout listing for the MPC7448, 360 HCTE package. The pinouts of the MPC7448
and MPC7447A are compatible, but the requirements regarding the use of the additional power and ground
pins have changed. The MPC7448 requires these pins be connected to the appropriate power or ground
plane to achieve high core frequencies; see Section 9.3, Connection Recommendations, for additional
information. As a result, these pins should be connected in all new designs.
Additionally, the MPC7448 may be populated on a board designed for a MPC7447 (or MPC7445 or
MPC7441), provided the core voltage can be made to match the requirements in Table 4 and all pins
defined as no connect for the MPC7447 are unterminated, as required by the MPC7457 RISC
Microprocessor Hardware Specifications. The MPC7448 uses pins previously marked no connect for the
temperature diode pins and for additional power and ground connections. The additional power and
ground pins are required to achieve high core frequencies and core frequency will be limited if they are
not connected; see Section 9.3, Connection Recommendations, for additional information. Because
these no connect pins in the MPC7447 360 pin package are not driven in functional mode, an MPC7447
can be populated in an MPC7448 board.
NOTE
Caution must be exercised when performing boundary scan test operations
on a board designed for an MPC7448, but populated with an MPC7447 or
earlier device. This is because in the MPC7447 it is possible to drive the
latches associated with the former no connect pins in the MPC7447,
potentially causing contention on those pins. To prevent this, ensure that
these pins are not connected on the board or, if they are connected, ensure
that the states of internal MPC7447 latches do not cause these pins to be
driven during board testing.
For the MPC7448, pins that were defined as the TEST[0:4] factory test signal group on the MPC7447A
and earlier devices have been assigned new functions. For most of these, the termination recommendations
for the TEST[0:4] pins of the MPC7447A are compatible with the MPC7448 and will allow correct
operation with no performance loss. The exception is BVSEL1 (TEST3 on the MPC7447A and earlier
devices), which may require a different termination depending which I/O voltage mode is desired; see
Table 3 for more information.
NOTE
This pinout is not compatible with the MPC750, MPC7400, or MPC7410
360 BGA package.

Pinout Listings
Table 11. Pinout Listing for the MPC7448, 360 HCTE Package
Signal Name Pin Number Active I/O Notes

A[0:35] E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4, V1, High I/O 2
J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1, B12,
C4, G10, B11
AACK R1 Low Input
AP[0:4] C1, E3, H6, F5, G7 High I/O 2
ARTRY N2 Low I/O 3
AVDD A8 Input
BG M1 Low Input
BMODE0 G9 Low Input 4
BMODE1 F8 Low Input 5
BR D2 Low Output
BVSEL0 B7 High Input 1, 6
BVSEL1 E10 High Input 1, 20
CI J1 Low Output
CKSTP_IN A3 Low Input
CKSTP_OUT B1 Low Output
CLK_OUT H2 High Output
D[0:63] R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, High I/O
W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9,
P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19,
V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17, W3,
V17, U4, U8, U7, R7, P6, R8, W8, T8
DBG M2 Low Input
DFS2 A12 Low Input 20, 21
DFS4 B6 Low Input 12, 20, 21
DP[0:7] T3, W4, T4, W9, M6, V3, N8, W6 High I/O
DRDY R3 Low Output 7
DTI[0:3] G1, K1, P1, N1 High Input 8
EXT_QUAL A11 High Input 9
GBL E2 Low I/O
GND B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10, J12,
K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13, N7, P3,
P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11, V15
GND A17, A19, B13, B16, B18, E12, E19, F13, F16, F18, G19, H18, J14, L14, 15
M15, M17, M19, N14, N16, P15, P19
GND_SENSE G12, N13 19
HIT B2 Low Output 7
HRESET D8 Low Input
INT D4 Low Input
L1_TSTCLK G8 High Input 9
L2_TSTCLK B3 High Input 10

Pinout Listings
Table 11. Pinout Listing for the MPC7448, 360 HCTE Package (continued)

LVRAM B10 12, 20, 22
NC (no connect) A6, A14, A15, B14, B15, C14, C15, C16, C17, C18, C19, D14, D15, D16, 11
D17, D18, D19, E14, E15, F14, F15, G14, G15, H15, H16, J15, J16, J17,
J18, J19, K15, K16, K17, K18, K19, L15, L16, L17, L18, L19
LSSD_MODE E8 Low Input 6, 12
MCP C9 Low Input
OVDD B4, C2, C12, D5, F2, H3, J5, K2, L5, M3, N6, P2, P8, P11, R4, R13, R16,
T6, T9, U2, U12, U16, V4, V7, V10, V14
OVDD_SENSE E18, G18 16
PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input
PLL_CFG[5] D10 High Input 9, 20
PMON_IN D9 Low Input 13
PMON_OUT A9 Low Output
QACK G5 Low Input
QREQ P4 Low Output
SHD[0:1] E4, H5 Low I/O 3
SMI F9 Low Input
SRESET A2 Low Input
SYSCLK A10 Input
TA K6 Low Input
TBEN E1 High Input
TBST F11 Low Output
TCK C6 High Input
TDI B9 High Input 6
TDO A4 High Output
TEA L1 Low Input
TEMP_ANODE N18 17
TEMP_CATHODE N19 17
TMS F1 High Input 6
TRST A5 Low Input 6, 14
TS L4 Low I/O 3
TSIZ[0:2] G6, F7, E7 High Output
TT[0:4] E5, E6, F6, E9, C5 High I/O
WT D3 Low Output
VDD H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13, M8,
M10, M12
VDD A13, A16, A18, B17, B19, C13, E13, E16, F12, F17, F19, G11, G16, 15
H14, H17, H19, M14, M16, M18, N15, N17, P16, P18

Pinout Listings
Table 11. Pinout Listing for the MPC7448, 360 HCTE Package (continued)

VDD_SENSE G13, N12 18
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals, and is configurable. (V DD supplies power to the
processor core, and AV DD supplies power to the PLL after filtering from VDD). To program the I/O voltage, see Table 3. If used,
the pull-down resistor should be less than 250 . Because these settings may change in future products, it is recommended
BVSEL[0:1] be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure
the termination of this signal in the future if necessary. For actual recommended value of Vin or supply voltages see Table 4.
2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OV DD.
3. These pins require weak pull-up resistors (for example, 4.7 K) to maintain the control signals in the negated state after they
have been actively negated and released by the MPC7448 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull-up resistor to OVDD or negation by HRESET (inverse of HRESET), to
ensure proper operation.
6. Internal pull up on die.
7. Not used in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7448 is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were
NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes.
12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. See Section 9.3, Connection Recommendations, for
more information.
16.These pins were OVDD pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OVDD and
are intended to allow an external device (such as a power supply) to detect the I/O voltage level present inside the device
package. If unused, it is recommended they be connected to test points to facilitate system debug; otherwise, they may be
connected directly to OV DD or left unconnected.
17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature
of the processor. These pins may be left unterminated if unused.
18.These pins are internally connected to VDD and are intended to allow an external device (such as a power supply) to detect
the processor core voltage level present inside the device package. If unused, it is recommended they be connected to test
points to facilitate system debug; otherwise, they may be connected directly to VDD or left unconnected.
19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground
voltage level present inside the device package. If unused, it is recommended they be connected to test points to facilitate
system debug; otherwise, they may be connected directly to GND or left unconnected.
20.These pins were in the TEST[0:4] factory test pin group on the MPC7447A, MPC7447, MPC7445, and MPC7441. They have
been assigned new functions on the MPC7448.
21.These pins can be used to enable the supported dynamic frequency switching (DFS) modes via hardware. If both are pulled
down, DFS mode is disabled completely and cannot be enabled via software. If unused, they should be pulled up to OVDD
to allow software control of DFS. See the MPC7450 RISC Microprocessor Family Reference Manual for more information.
22.This pin is provided to allow operation of the L2 cache at low core voltages and is for factory use only. See the MPC7450
RISC Microprocessor Family Reference Manual for more information.

Package Description
8 Package Description
The following sections provide the package parameters and mechanical dimensions for the HCTE
package.
8.1 Package Parameters for the MPC7448, 360 HCTE BGA

The package parameters are as provided in the following list. The package type is 25 25 mm, 360-lead
high coefficient of thermal expansion ceramic ball grid array (HCTE).
Package outline 25 25 mm
Interconnects 360 (19 19 ball array 1)
Pitch 1.27 mm (50 mil)
Minimum module height 2.32 mm
Maximum module height 2.80 mm
Ball diameter 0.89 mm (35 mil)
Coefficient of thermal expansion12.3 ppm/C

Package Description
8.2 Mechanical Dimensions for the MPC7448, 360 HCTE BGA

Figure 13 provides the mechanical dimensions and bottom surface nomenclature for the MPC7448, 360
HCTE BGA package.
2X
0.2 Capacitor Region
D B NOTES:
1. Dimensioning and
D3 D1 tolerancing per ASME
Y14.5M, 1994
A1 CORNER D2 2. Dimensions in millimeters.
A
3. Top side A1 corner index is a
0.15 A metalized feature with
1
various shapes. Bottom side

A1 corner is designated with
a ball missing from the array.
E3
E E4
E2 Millimeters
E1
Dim Min Max
A 2.32 2.80
2X
A1 0.80 1.00
0.2
D4 A2 0.70 0.90
C
1 2 3 4 5 6 7 8 9 10 111213141516 171819 A3 0.6
W
V b 0.82 0.93
U
T
D 25.00 BSC
R
P
D1 11.3
N
M A3
D2 8.0
L
K D3 6.5
J
H A2 D4 7.2 7.4
G
F A1 e 1.27 BSC
E
D
A E 25.00 BSC
C
B 0.35 A E1 11.3
A
E2 8.0
e 360X b E3 6.5
0.3 A B C E4 7.9 8.1
0.15 A
Figure 13. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7448,
360 HCTE BGA Package

Package Description
8.3 Package Parameters for the MPC7448, 360 HCTE LGA

The package parameters are as provided in the following list. The package type is 25 25 mm, 360 pin
high coefficient of thermal expansion ceramic land grid array (HCTE).
Pad diameter 0.89 mm (35 mil)

Package Description
8.4 Mechanical Dimensions for the MPC7448, 360 HCTE LGA

HCTE LGA package.
2X
D B NOTES:
1. Dimensioning and
Y14.5M, 1994
A1 CORNER D2 2. Dimensions in millimeters
A
1

a pad missing from the array.
E3
E E4
E2 Millimeters
E1
Dim Min Max
A 1.52 1.80
2X
A1 0.70 0.90
0.2
D4 A2 0.6
C
1 2 3 4 5 6 7 8 9 10 111213141516 171819 b 0.82 0.93
W
V D 25.00 BSC
U
T
D1 11.3
R
P
D2 8.0
N
M A2
D3 6.5
L
K D4 7.2 7.4
J
H A1 e 1.27 BSC
G
F E 25.00 BSC
E
D
A E1 11.3
C
B 0.35 A E2 8.0
A
E3 6.5
e 360X b E4 7.9 8.1
0.3 A B C
0.15 A
360 HCTE LGA Package

Package Description
8.5 Package Parameters for the MPC7448, 360 HCTE

RoHS-Compliant BGA
The package parameters are as provided in the following list. The package type is 25 25 mm, 360-lead
high coefficient of thermal expansion ceramic ball grid array (HCTE) with RoHS-compliant lead-free
spheres.
Ball diameter 0.75 mm (30 mil)

Package Description
8.6 Mechanical Dimensions for the MPC7448, 360 HCTE

RoHS-Compliant BGA
HCTE BGA package with RoHS-compliant lead-free spheres.
2X
D B NOTES:
1. Dimensioning and
Y14.5M, 1994
A1 CORNER D2 2. Dimensions in millimeters.
A
1

a ball missing from the array.
4. Dimension A1 represents the
E3 collapsed sphere diameter.
E E4
E2 Millimeters
E1
Dim Min Max
A 1.92 2.40
2X 4
A1 0.40 0.60
0.2
D4 A2 0.70 0.90
C
1 2 3 4 5 6 7 8 9 10 111213141516 171819 A3 0.6
W
V b 0.60 0.90
U
T
D 25.00 BSC
R
P
D1 11.3
N
M A3
D2 8.0
L
K D3 6.5
J
H A2 D4 7.2 7.4
G
F A1 e 1.27 BSC
E
D
A E 25.00 BSC
C
B 0.35 A E1 11.3
A
E2 8.0
e 360X b E3 6.5
0.3 A B C E4 7.9 8.1
0.15 A
360 HCTE RoHS-Compliant BGA Package

System Design Information
9 System Design Information

This section provides system and thermal design requirements and recommendations for successful
application of the MPC7448.
9.1 Clocks
The following sections provide more detailed information regarding the clocking of the MPC7448.
9.1.1 PLL Configuration

The MPC7448 PLL is configured by the PLL_CFG[0:5] signals. For a given SYSCLK (bus) frequency,
the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL
configuration for the MPC7448 is shown in Table 12. In this example, shaded cells represent settings that,
for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with Table 8.
When enabled, dynamic frequency switching (DFS) also affects the core frequency by halving or
quartering the bus-to-core multiplier; see Section 9.7.5, Dynamic Frequency Switching (DFS), for more
information. Note that when DFS is enabled the resulting core frequency must meet the adjusted minimum
core frequency requirements (fcore_DFS) described in Table 8. Note that the PLL_CFG[5] is currently used
for factory test only and should be tied low, and that the MPC7448 PLL configuration settings are
compatible with the MPC7447A PLL configuration settings when PLL_CFG[5] = 0.
Table 12. MPC7448 Microprocessor PLL Configuration Example
Example Core and VCO Frequency in MHz
Bus (SYSCLK) Frequency

PLL_CFG[0:5]
Bus-to-Core Core-to-VCO
Multiplier 5 Multiplier 5 33.3 50 66.6 75 83 100 133 167 200
MHz MHz MHz MHz MHz MHz MHz MHz MHz
010000 2x 6 1x
6
100000 3x 1x 600
6
101000 4x 1x 667 800
101100 5x 1x 667 835 1000
100100 5.5x 1x 733 919 1100
110100 6x 1x 600 800 1002 1200
010100 6.5x 1x 650 866 1086 1300
001000 7x 1x 700 931 1169 1400
000100 7.5x 1x 623 750 1000 1253 1500
110000 8x 1x 600 664 800 1064 1336 1600
011000 8.5x 1x 638 706 850 1131 1417 1700
011110 9x 1x 600 675 747 900 1197 1500
011100 9.5x 1x 633 712 789 950 1264 1583
101010 10x 1x 667 750 830 1000 1333 1667
100010 10.5x 1x 700 938 872 1050 1397

Table 12. MPC7448 Microprocessor PLL Configuration Example (continued)
Example Core and VCO Frequency in MHz
Bus (SYSCLK) Frequency

PLL_CFG[0:5]
Bus-to-Core Core-to-VCO
Multiplier 5 Multiplier 5 33.3 50 66.6 75 83 100 133 167 200
MHz MHz MHz MHz MHz MHz MHz MHz MHz
100110 11x 1x 733 825 913 1100 1467

000000 11.5x 1x 766 863 955 1150 1533
101110 12x 1x 600 800 900 996 1200 1600
111110 12.5x 1x 625 833 938 1038 1250 1667
010110 13x 1x 650 865 975 1079 1300
111000 13.5x 1x 675 900 1013 1121 1350
110010 14x 1x 700 933 1050 1162 1400
000110 15x 1x 750 1000 1125 1245 1500
110110 16x 1x 800 1066 1200 1328 1600
000010 17x 1x 850 1132 1275 1417 1700
001010 18x 1x 600 900 1200 1350 1500
001110 20x 1x 667 1000 1332 1500 1666
010010 21x 1x 700 1050 1399 1575
011010 24x 1x 800 1200 1600
111010 28x 1x 933 1400
001100 PLL bypass PLL off, SYSCLK clocks core circuitry directly
111100 PLL off PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:5] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
frequencies which are not useful, not supported, or not tested for by the MPC7448; see Section 5.2.1, Clock AC
Specifications, for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the
bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at half the
frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9). The result
will be that the processor bus frequency will be one-half SYSCLK, while the internal processor is clocked at SYSCLK
frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7448 regardless of the SYSCLK input.
5. Applicable when DFS modes are disabled. These multipliers change when operating in a DFS mode. See Section 9.7.5,
Dynamic Frequency Switching (DFS) for more information.
6. Bus-to-core multipliers less than 5x require that assertion of AACK be delayed by one or two bus cycles to allow the
processor to generate a response to a snooped transaction. See the MPC7450 RISC Microprocessor Reference Manual for
more information.

9.1.2 System Bus Clock (SYSCLK) and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8
considers short-term (cycle-to-cycle) jitter only and the clock generators cycle-to-cycle output jitter
should meet the MPC7448 input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the MPC7448 is compatible with spread spectrum sources if the recommendations
listed in Table 13 are observed.
Table 13. Spread Spectrum Clock Source Recommendations
Parameter Min Max Unit Notes
Frequency modulation 50 kHz 1
Frequency spread 1.0 % 1, 2
Notes:
1. Guaranteed by design
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
frequencies, must meet the minimum and maximum specifications given in Table 8.
It is imperative to note that the processors minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated core or bus frequency should avoid violating the stated limits by using
down-spreading only.
9.2 Power Supply Design and Sequencing

The following sections provide detailed information regarding power supply design for the MPC7448.
9.2.1 Power Supply Sequencing

The MPC7448 requires its power rails and clock to be applied in a specific sequence to ensure proper
device operation and to prevent device damage. The power sequencing requirements are as follows:
AVDD must be delayed with respect to VDD by the RC time constant of the PLL filter circuit
described in Section 9.2.2, PLL Power Supply Filtering. This time constant is nominally 100 s.
OVDD may ramp anytime before or after VDD and AVDD.
Additionally, the following requirements exist regarding the application of SYSCLK:
The voltage at the SYSCLK input must not exceed VDD until VDD has ramped to 0.9 V.
The voltage at the SYSCLK input must not exceed OVDD by more 20% during transients (see
overshoot/undershoot specifications in Figure 2) or 0.3 V DC (see Table 2) at any time.

These requirements are shown graphically in Figure 16.
no restrictions between OVDD and VDD

OVDD
VDD
0.9 V AVDD
100 s (nominal) delay from VDD to AVDD
limit imposed by OVDD if VDD ramps up first
limit imposed by VDD if OVDD ramps up first
0.9 V
SYSCLK
Figure 16. MPC7448 Power Up Sequencing Requirements
Certain stipulations also apply to the manner in which the power rails of the MPC7448 power down, as
follows:
OVDD may ramp down any time before or after VDD.
The voltage at the SYSCLK input must not exceed VDD once VDD has ramped down below 0.9 V.
The voltage at the SYSCLK input must not exceed OVDD by more 20% during transients (see
overshoot/undershoot specifications in Figure 2) or 0.3 V DC (see Table 2) at any time.

no restrictions between VDD and OVDD

OVDD
VDD
AVDD
0.9 V
no restrictions between VDD and AVDD

limit imposed by OVDD if OVDD ramps down first
limit imposed by VDD if VDD ramps down first
0.9 V
SYSCLK
note also restrictions between SYSCLK and OVDD
Figure 17. MPC7448 Power Down Sequencing Requirements
There is no requirement regarding AVDD during power down, but it is recommended that AVDD track VDD
within the RC time constant of the PLL filter circuit described in Section 9.2.2, PLL Power Supply
Filtering (nominally 100 s).
9.2.2 PLL Power Supply Filtering

The AVDD power signal is provided on the MPC7448 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. The circuit shown in Figure 18
using surface mount capacitors with minimum effective series inductance (ESL) is strongly recommended.
In addition to filtering noise from the AVDD input, it also provides the required delay between VDD and
AVDD as described in Section 9.2.1, Power Supply Sequencing.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the device footprint.
10
VDD AVDD
2.2 F 2.2 F
Low ESL Surface Mount Capacitors

GND
Figure 18. PLL Power Supply Filter Circuit

9.2.3 Transient Specifications

The ensure the long-term reliability of the device, the MPC7448 requires that transients on the core power
rail (VDD) be constrained. The recommended operating voltage specifications provided in Table 4 are DC
specifications. That is, the device may be operated continuously with VDD within the specified range
without adversely affecting the devices reliability. Excursions above the stated recommended operation
range, including overshoot during power-up, can impact the long-term reliability of the device. Excursions
are described by their amplitude and duration. Duration is defined as the time period during which the VDD
power plane, as measured at the VDD_SENSE pins, will be within a specific voltage range, expressed as
percentage of the total time the device will be powered up over the device lifetime. In practice, the period
over which transients are measured can be any arbitrary period of time that accurately represents the
expected range of processor and system activity. The voltage ranges and durations for normal operation
and transients are described in Table 14.
Table 14. VDD Power Supply Transient Specifications
At recommended operating temperatures. See Table 4.
Voltage Range (V)

Permitted
Voltage Region Notes
Duration 1
Min Max
Normal VDD minimum VDD maximum 100% 2
Low Transient VDD maximum 1.35 V 10% 2, 3
High Transient 1.35 V 1.40 V 0.2% 4
Notes:
1. Permitted duration is defined as the percentage of the total time the device is powered on that the VDD
power supply voltage may exist within the specified voltage range.
2. See Table 4 for nominal VDD specifications.
3. To simplify measurement, excursions into the High Transient region are included in this duration.
4. Excursions above the absolute maximum rating of 1.4 V are not permitted; see Table 2.
Note that, to simplify transient measurements, the duration of the excursion into the High Transient region
is also included in the Low Transient duration, so that only the time the voltage is above each threshold
must be considered. Figure 19 shows an example of measuring voltage transients.
T
1.40 V
High Transient
1.35 V
Low Transient
VDD (maximum)
VDD (nominal) Normal

A C
VDD (minimum)
B
A + B < T 10%
C < T 0.2%
Figure 19. Voltage Transient Example

9.2.4 Decoupling Recommendations

Due to the MPC7448 dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC7448 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC7448 system, and the MPC7448 itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer use sufficient decoupling
capacitors, typically one capacitor for every VDD pin, and a similar amount for the OVDD pins, placed as
close as possible to the power pins of the MPC7448. It is also recommended that these decoupling
capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB, using short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance. Orientations where connections are made along
the length of the part, such as 0204, are preferable but not mandatory. Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale
microprocessors, multiple small capacitors of equal value are recommended over using multiple values of
capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors are 100330 F (AVX TPS tantalum or Sanyo OSCON).
9.3 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unless otherwise noted, unused active low inputs should be tied to OVDD and unused active high
inputs should be connected to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7448.
For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a system
originally designed for one of these devices to the MPC7448, the new power and ground signals (formerly
NC, see Table 11) may be left unconnected if the core frequency is 1 GHz or less. Operation above 1 GHz
requires that these additional power and ground signals be connected, and it is strongly recommended that
all new designs include the additional connections. See also Section 7, Pinout Listings, for additional
information.
The MPC7448 provides VDD_SENSE, OVDD_SENSE, and GND_SENSE pins. These pins connect
directly to the power/ground planes in the device package and are intended to allow an external device to
measure the voltage present on the VDD, OVDD and GND planes in the device package. The most common
use for these signals is as a feedback signal to a power supply regulator to allow it to compensate for board
losses and supply the correct voltage at the device. (Note that all voltage parameters are specified at the
pins of the device.) If not used for this purpose, it is recommended that these signals be connected to test
points that can be used in the event that an accurate measurement of the voltage at the device is needed
during system debug. Otherwise, these signals should be connected to the appropriate power/ground
planes on the circuit board or left unconnected.

9.4 Output Buffer DC Impedance

The MPC7448 processor bus drivers are characterized over process, voltage, and temperature. To measure
Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each resistor is
varied until the pad voltage is OVDD/2. Figure 20 shows the driver impedance measurement.
OVDD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 20. Driver Impedance Measurement
The output impedance is the average of two componentsthe resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,
SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then
becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value.
Then, Z0 = (RP + RN)/2.
Table 15 summarizes the signal impedance results. The impedance increases with junction temperature
and is relatively unaffected by bus voltage.
Table 15. Impedance Characteristics
At recommended operating conditions. See Table 4
Impedance Processor Bus Unit

Z0 Typical 3342
Maximum 3151
9.5 Pull-Up/Pull-Down Resistor Requirements

The MPC7448 requires high-resistive (weak: 4.7-K) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7448 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being factory test pins must be pulled up to OVDD or down to GND to ensure
proper device operation. The pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the
pins that must be pulled down to GND are L1_TSTCLK and TEST[4]. The CKSTP_IN signal should

likewise be pulled up through a pull-up resistor (weak or stronger: 4.71 K) to prevent erroneous
assertions of this signal.
In addition, the MPC7448 has one open-drain style output that requires a pull-up resistor (weak or
stronger: 4.71 K) if it is used by the system. This pin is CKSTP_OUT.
BVSEL0 and BVSEL1 should not be allowed to float, and should be configured either via pull-up or
pull-down resistors or actively driven by external logic. If pull-down resistors are used to configure
BVSEL0 or BVSEL1, the resistors should be less than 250 (see Table 11). Because PLL_CFG[0:5]
must remain stable during normal operation, strong pull-up and pull-down resistors (1 K or less) are
recommended to configure these signals in order to protect against erroneous switching due to ground
bounce, power supply noise, or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7448
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7448 or by other receivers in the system. These signals can be pulled up
through weak (10-K) pull-up resistors by the system, address bus driven mode enabled (see the
MPC7450 RISC Microprocessor Family Users Manual for more information on this mode), or they may
be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.
Preliminary studies have shown the additional power draw by the MPC7448 input receivers to be
negligible and, in any event, none of these measures are necessary for proper device operation. The
snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If address or data parity is not used by the system, and respective parity checking is disabled through HID1,
the input receivers for those pins are disabled and do not require pull-up resistors, therefore they may be
left unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused
and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking
is enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OVDD
through a weak pull-up resistor. If the MPC7448 is in 60x bus mode, DTI[0:3] must be pulled low to GND
through weak pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups or require that those signals be otherwise driven by the system during inactive periods. The data
bus signals are D[0:63] and DP[0:7].
9.6 JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 standard specification, but is typically provided on all processors that implement the
PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK
and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted
during power-on reset. Because the JTAG interface is also used for accessing the common on-chip
processor (COP) function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 21 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0- isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. Although Freescale recommends that the COP header be designed into the system as shown in
Figure 21, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 21 adds many benefitsbreakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interfaceand
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 21; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 21 is common to all known emulators.
The QACK signal shown in Figure 21 is usually connected to the bridge chip or other system control logic
in a system and is an input to the MPC7448 informing it that it can go into the quiescent state. Under
normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7448
must see this signal asserted (pulled down). While shown on the COP header, not all emulator products
drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal.
Additionally, some emulator products implement open-drain type outputs and can only drive QACK
asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is
not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down
operation, QACK should be merged through logic so that it also can be driven by the bridge or system
logic.

SRESET
From Target SRESET
Board Sources HRESET
HRESET 6
(if any)
QACK
HRESET 10 K
13 OVDD
SRESET 10 K
11 OVDD
10 K
OVDD
10 K
OVDD
05
1 2 TRST TRST 6
4
3 4 VDD_SENSE
6 OVDD
5 6 2 K 10 K
5 1
OVDD
7 8 CHKSTP_OUT
15 CHKSTP_OUT
9 10 10 K
OVDD
11 12 Key 10 K
14 2 OVDD
KEY
13 No Pin CHKSTP_IN
8 CHKSTP_IN
COP Header
15 16 TMS
9 TMS
COP Connector TDO
1 TDO
Physical Pin Out TDI
3 TDI
TCK
7 TCK
QACK
2 QACK
10 NC OV DD
2 K 3 10 K
12 NC
OV DD
16 10 K 4
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7448. Connect
pin 5 of the COP header to OV DD with a 10-K pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0- isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the
processor in order to fully control the processor as shown above.
Figure 21. JTAG Interface Connection

9.7 Power and Thermal Management Information

This section provides thermal management information for the high coefficient of thermal expansion
(HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level designthe heat sink, airflow, and thermal interface material. The MPC7448 implements
several features designed to assist with thermal management, including DFS and the temperature diode.
DFS reduces the power consumption of the device by reducing the core frequency; see Section 9.7.5.1,
Power Consumption with DFS Enabled, for specific information regarding power reduction and DFS.
The temperature diode allows an external device to monitor the die temperature in order to detect excessive
temperature conditions and alert the system; see Section 9.7.4, Temperature Diode, for more
information.
To reduce the die-junction temperature, heat sinks may be attached to the package by several
methodsspring clip to holes in the printed-circuit board or package, and mounting clip and screw
assembly (see Figure 22); however, due to the potential large mass of the heat sink, attachment through the
printed-circuit board is suggested. In any implementation of a heat sink solution, the force on the die
should not exceed ten pounds (45 Newtons).
HCTE BGA Package
Heat Sink
Heat Sink
Clip
Thermal
Interface Material
Printed-Circuit Board
Figure 22. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options
NOTE
A clip on heat sink is not recommended for LGA because there may not be
adequate clearance between the device and the circuit board. A through-hole
solution is recommended, as shown in Figure 23.

HCTE LGA Package

Heat Sink
Heat Sink
Clip
Thermal
Interface Material
Figure 23. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options
There are several commercially-available heat sinks for the MPC7448 provided by the following vendors:
Aavid Thermalloy 603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech 408-567-8082
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
Calgreg Thermal Solutions 888-732-6100
60 Alhambra Road, Suite 1
Warwick, RI 02886
Internet: www.calgregthermalsolutions.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Tyco Electronics 800-522-6752
Chip Coolers
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.tycoelectronics.com
Wakefield Engineering 603-635-2800
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

9.7.1 Internal Package Conduction Resistance

For the exposed-die packaging technology described in Table 5, the intrinsic conduction thermal resistance
paths are as follows:
The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die)
The die junction-to-board thermal resistance
Figure 24 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance Radiation Convection
Heat Sink
Thermal Interface Material
Internal Resistance Die/Package

Die Junction
Package/Leads
External Resistance Radiation Convection

(Note the internal versus external package resistance.)
Figure 24. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach
material (or thermal interface material), and, finally, to the heat sink, where it is removed by forced-air
convection.
Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected
for a first-order analysis. Thus, the thermal interface material and the heat sink conduction/convective
thermal resistances are the dominant terms.
9.7.2 Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip
mechanism, Figure 25 shows the thermal performance of three thin-sheet thermal-interface materials
(silicone, graphite/oil, fluoroether oil), a bare joint, and a joint with thermal grease as a function of contact
pressure. As shown, the performance of these thermal interface materials improves with increasing contact
pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare
joint results in a thermal resistance approximately seven times greater than the thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board
(see Figure 22). Therefore, synthetic grease offers the best thermal performance due to the low interface
pressure and is recommended due to the high power dissipation of the MPC7448. Of course, the selection

of any thermal interface material depends on many factorsthermal performance requirements,

manufacturability, service temperature, dielectric properties, cost, and so on.
Silicone Sheet (0.006 in.)
2 Bare Joint
Fluoroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
1.5
0.5
0
0 10 20 30 40 50 60 70 80
Contact Pressure (psi)
Figure 25. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interfaces. Heat sink adhesive materials
should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration
requirements. There are several commercially available thermal interfaces and adhesive materials
provided by the following vendors:
The Bergquist Company 800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
Dow-Corning Corporation 800-248-2481
Corporate Center
P.O. Box 994.
Midland, MI 48686-0994
Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc. 888-642-7674

10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
Laird Technologies - Thermal 888-246-905
(formerly Thermagon Inc.)
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.lairdtech.com
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
9.7.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = Ti + Tr + (RJC + Rint + Rsa) Pd
where:
Tj is the die-junction temperature
Ti is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
RJC is the junction-to-case thermal resistance
Rint is the adhesive or interface material thermal resistance
Rsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in
Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ti)
may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to
10 C. The thermal resistance of the thermal interface material (Rint) is typically about 1.1 C/W. For
example, assuming a Ti of 30 C, a Tr of 5 C, an HCTE package RJC = 0.1, and a power consumption
(Pd) of 25.6 W, the following expression for Tj is obtained:
Die-junction temperature: Tj = 30 C + 5 C + (0.1 C/W + 1.1 C/W + sa) 25.6
For this example, a Rsavalue of 1.53 C/W or less is required to maintain the die junction temperature
below the maximum value of Table 4.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technologies, one should exercise caution when only using this metric in determining thermal management
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operating temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power consumption, a
number of factors affect the final operating die-junction temperatureairflow, board population (local
heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level
interconnect technology, system air temperature rise, altitude, and so on.

Due to the complexity and variety of system-level boundary conditions for today's microelectronic
equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)
may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as
well as system-level designs.
For system thermal modeling, the MPC7448 thermal model is shown in Figure 26. Four volumes represent
this device. Two of the volumes, solder ball-air and substrate, are modeled using the package outline size
of the package. The other two, die and bump-underfill, have the same size as the die. The silicon die should
be modeled 8.0 7.3 0.86 mm3 with the heat source applied as a uniform source at the bottom of the
volume. The bump and underfill layer is modeled as 8.0 7.3 0.07 mm3collapsed in the z-direction with
a thermal conductivity of 5.0 W/(m K) in the z-direction. The substrate volume is 25 25 1.14 mm3
and has 9.9 W/(m K) isotropic conductivity in the xy-plane and 2.95 W/(m K) in the direction of the
z-axis. The solder ball and air layer are modeled with the same horizontal dimensions as the substrate and
is 0.8 mm thick. For the LGA package the solder and air layer is 0.1 mm thick, but the material properties
are the same. It can also be modeled as a collapsed volume using orthotropic material properties:
0.034 W/(m K) in the xy-plane direction and 11.2 W/(m K) in the direction of the z-axis.
Conductivity Value Unit

Die
Die (8.0 7.3 0.86 mm 3)
z Bump and Underfill
Temperature-
Silicon W/(m K) Substrate
dependent
Solder and Air
Bump and Underfill (8.0 7.3 0.07 mm3)
Side View of Model (Not to Scale)
kz 5.0 W/(m K)
x
Substrate (25 25 1.14 mm3)
kx 9.9 W/(m K)
Substrate
ky 9.9
kz 2.95
Solder Ball and Air (25 25 0.8 mm3) Die

kx 0.034 W/(m K)
ky 0.034
kz 11.2
y
Top View of Model (Not to Scale)
Figure 26. Recommended Thermal Model of MPC7448

9.7.4 Temperature Diode

The MPC7448 has a temperature diode on the microprocessor that can be used in conjunction with other
system temperature monitoring devices (such as Analog Devices, ADT7461). These devices use the
negative temperature coefficient of a diode operated at a constant current to determine the temperature of
the microprocessor and its environment. For proper operation, the monitoring device used should
auto-calibrate the device by canceling out the VBE variation of each MPC7448s internal diode.
The following are the specifications of the MPC7448 on-board temperature diode:
Vf > 0.40 V
Vf < 0.90 V
Operating range 2300 A
Diode leakage < 10 nA @ 125C
Ideality factor over 5150 A at 60C: n = 1.0275 0.9%
Ideality factor is defined as the deviation from the ideal diode equation:
qVf
___
Ifw = Is e nKT 1
Another useful equation is:
KT I
VH VL = n __ ln __
H
1
q IL
Where:
Ifw = Forward current
Is = Saturation current
V d = Voltage at diode
V f = Voltage forward biased
V H = Diode voltage while IH is flowing
V L = Diode voltage while IL is flowing
IH = Larger diode bias current
IL = Smaller diode bias current
q = Charge of electron (1.6 x 10 19 C)
n = Ideality factor (normally 1.0)
K = Boltzmans constant (1.38 x 1023 Joules/K)
T = Temperature (Kelvins)
The ratio of IH to IL is usually selected to be 10:1. The previous equation simplifies to the following:
VH VL = 1.986 104 nT

Solving for T, the equation becomes:
VH VL
__________
nT =
1.986 104
9.7.5 Dynamic Frequency Switching (DFS)

The DFS feature in the MPC7448 adds the ability to divide the processor-to-system bus ratio by two or
four during normal functional operation. Divide-by-two mode is enabled by setting the HID1[DFS2] bit
in software or by asserting the DFS2 pin via hardware. The MPC7448 can be returned for full speed by
clearing HID1[DFS2] or negating DFS2. Similarly, divide-by-four mode is enabled by setting
HID1[DFS4] in software or by asserting the DFS4 pin. In all cases, the frequency change occurs in 1 clock
cycle and no idle waiting period is required to switch between modes. Note that asserting either DFS2 or
DFS4 overrides software control of DFS, and that asserting both DFS2 and DFS4 disables DFS
completely, including software control. Additional information regarding DFS can be found in the
MPC7450 RISC Microprocessor Family Reference Manual. Note that minimum core frequency
requirements must be observed when enabling DFS, and the resulting core frequency must meet the
requirements for fcore_DFS given in Table 8.
9.7.5.1 Power Consumption with DFS Enabled

Power consumption with DFS enabled can be approximated using the following formula:
fDFS
PDFS = ___
f
(P PDS) + PDS
Where:
PDFS = Power consumption with DFS enabled
fDFS = Core frequency with DFS enabled
f = Core frequency prior to enabling DFS
P = Power consumption prior to enabling DFS (see Table 7)
PDS = Deep sleep mode power consumption (see Table 7)
The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.
9.7.5.2 Bus-to-Core Multiplier Constraints with DFS

DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:5] during hard reset. The
complete listing is shown in Table 16. Shaded cells represent DFS modes that are not available for a
particular PLL_CFG[0:5] setting. Should software or hardware attempt to transition to a multiplier that is
not supported, the device will remain at its current multiplier. For example, if a transition from
DFS-disabled to an unsupported divide-by-2 or divide-by-4 setting is attempted, the bus-to-core multiplier
will remain at the setting configured by the PLL_CFG[0:5] pins. In the case of an attempted transition from
a supported divide-by-2 mode to an unsupported divide-by-4 mode, the device will remain in divide-by-2
mode. In all cases, the HID1[PC0-5] bits will correctly reflect the current bus-to-core frequency multiplier.

Table 16. Valid Divide Ratio Configurations
DFS divide-by-2 mode enabled DFS divide-by-4 mode enabled

DFS mode disabled
(HID1[DFS2] = 1 or DFS2 = 0) (HID1[DFS4] = 1 or DFS4 = 0)
Bus-to-Core Multiplier
Bus-to-Core
Configured by Bus-to-Core
HID1[PC0-5] 3 HID1[PC0-5] 3 Multiplier HID1[PC0-5] 3
PLL_CFG[0:5] Multiplier
(see Table 12)
2x 4 010000 N/A (unchanged) 1 unchanged 1 N/A (unchanged) 1 unchanged 1
3x 4 100000 N/A (unchanged) 1 unchanged 1 N/A (unchanged) 1 unchanged 1
4x 4 101000 2x 4 010000 N/A (unchanged) 1 unchanged 1
5x 101100 2.5x 4 010101 N/A (unchanged) 1 unchanged 1
5.5x 100100 2.75x 4 110101 2 N/A (unchanged) 1 unchanged 1
6x 110100 3x 4 100000 N/A (unchanged) 1 unchanged 1
7x 001000 3.5x 4 110101 N/A (unchanged) 1 unchanged 1
8x 110000 4x 4 101000 4 2x 4 010000
9x 011110 4.5x 4 011101 2.25x 4 010000 2
10x 101010 5x 101100 2.5x 4 010101
10.5x 100010 5.25x 101100 2 N/A (unchanged) 1 unchanged 1
11x 100110 5.5x 100100 2.75x 4 010101 2
12x 101110 6x 110100 3x 4 100000
13x 010110 6.5x 010100 3.25x 4 100000 2
13.5x 111000 6.75 010100 2 N/A (unchanged) 1 unchanged 1
14x 110010 7x 001000 3.5x 4 110101
15x 000110 7.5x 000100 3.75x 4 110101 2
16x 110110 8x 110000 4x 4 101000
17x 000010 8.5x 011000 4.25x 4 101000 2
18x 001010 9x 011110 4.5x 4 011101
20x 001110 10x 101010 5x 101100
21x 010010 10.5x 100010 5.25x 101100 2

Document Revision History
Table 16. Valid Divide Ratio Configurations (continued)
DFS divide-by-2 mode enabled DFS divide-by-4 mode enabled

DFS mode disabled
(HID1[DFS2] = 1 or DFS2 = 0) (HID1[DFS4] = 1 or DFS4 = 0)
Bus-to-Core Multiplier
Bus-to-Core
Configured by Bus-to-Core
HID1[PC0-5] 3 HID1[PC0-5] 3 Multiplier HID1[PC0-5] 3
PLL_CFG[0:5] Multiplier
(see Table 12)
24x 011010 12x 101110 6x 110100
28x 111010 14x 110010 7x 001000
Notes:
1. DFS mode is not supported for this combination of DFS mode and PLL_CFG[0:5] setting. As a result, the processor
will ignore these settings and remain at the previous multiplier, as reflected by the HID1[PC0-PC5] bits.
2. Though supported by the MPC7448 clock circuitry, multipliers of n.25x and n.75x cannot be expressed as valid PLL
configuration codes. As a result, the values displayed in HID1[PC0-PC5] are rounded down to the nearest valid PLL
configuration code. However, the actual bus-to-core multiplier is as stated in this table.
3. Note that in the HID1 register of the MPC7448, the PC0, PC1, PC2, PC3, PC4, and PC5 bits are bits 15, 16, 17, 18,
19, and 14 (respectively). See the MPC7450 RISC Microprocessor Reference Manual for more information.
4. Special considerations regarding snooped transactions must be observed for bus-to-core multipliers less than 5x.
See the MPC7450 RISC Microprocessor Reference Manual for more information.
9.7.5.3 Minimum Core Frequency Requirements with DFS

In many systems, enabling DFS can result in very low processor core frequencies. However, care must be
taken to ensure that the resulting processor core frequency is within the limits specified in Table 8. Proper
operation of the device is not guaranteed at core frequencies below the specified minimum fcore.
10 Document Revision History

Table 17 provides a revision history for this hardware specification.
Table 17. Document Revision History
Revision Date Substantive Change(s)
4 3/2007 Table 19: Added 800 MHz processor frequency.
3 10/2006 Section 9.7, Power and Thermal Management Information: Updated contact information.
Table 18, Table 20, and Table 19: Added Revision D PVR.
Table 19: Added 600 processor frequency, additional product codes, date codes for 1400 processor
frequency, and footnotes 1 and 2.
Table 20: Added PPC product code and footnote 1.
Table 19 and Table 20: Added Revision D information for 1267 processor frequency.

Document Revision History
Table 17. Document Revision History (continued)
Revision Date Substantive Change(s)
2 Table 6: Added separate input leakage specification for BVSEL0, LSSD_MODE, TCK, TDI, TMS, TRST
signals to correctly indicate leakage current for signals with internal pull-up resistors.
Section 5.1: Added paragraph preceding Table 7 and edited notes in Table 7 to clarify core frequencies at
which power consumption is measured.
Section 5.3: Removed voltage derating specifications; this feature has been made redundant by new
device offerings and is no longer supported.
Changed names of TypicalNominal and TypicalThermal power consumption parameters to Typical
and Thermal, respectively. (Name change onlyno specifications were changed.)
Table 11: Revised Notes 16, 18, and 19 to reflect current recommendations for connection of SENSE pins.
Section 9.3: Added paragraph explaining connection recommendations for SENSE pins. (See also Table
11 entry above.)
Table 19: Updated table to reflect changes in specifications for MC7448xxnnnnNC devices.
Table 9: Changed all instances of TT[0:3] to TT[0:4]
Removed mention of these input signals from output valid times and output hold times:
AACK, CKSTP_IN, DT[0:3]
Figure 17: Modified diagram slightly to correctly show constraint on SYSCLK ramping is related to VDD
voltage, not AVDD voltage. (Diagram clarification only; no change in power sequencing requirements.)
Added Table 20 to reflect introduction of extended temperature devices and associated hardware
specification addendum.
1 Added 1600 MHz, 1420 MHz, and 1000 MHz devices

Section 4: corrected die size
Table 2: Revised Note 4 to consider overshoot/undershoot and combined with Note 5.
Table 4: Revised operating voltage for 1700 MHz device from 50 mV to +20 mV / 50 mV.
Table 7: Updated and expanded table to include Typical Nominal power consumption.
Table 11: Added voltage derating information for 1700 MHz devices; this feature is not supported at this
time for other speed grades.
Added transient specifications for VDD power supply in Section 9.2.3, added Table 15 and Figure 19 and
renumbered subsequent tables and figures.
Moved Decoupling Recommendations from Section 9.4 to Section 9.2.4 and renumbered subsequent
sections.
Section 9.2.1: Revised power sequencing requirements.
Section 9.7.4: Added thermal diode ideality factor information (previously TBD).
Table 17: Expanded table to show HID1 register values when DFS modes are enabled.
Section 11.2: updated to include additional N-spec device speed grades
Tables 18 and 19: corrected PVR values and added MC product code prefix
0 Initial public release.

Part Numbering and Marking
11 Part Numbering and Marking

Ordering information for the part numbers fully covered by this specification document is provided in
Section 11.1, Part Numbers Fully Addressed by This Document. Note that the individual part numbers
correspond to a maximum processor core frequency. For available frequencies, contact a local Freescale
sales office. In addition to the processor frequency, the part numbering scheme also includes an application
modifier that may specify special application conditions. An optional specification modifier may also
apply for parts to indicate a specific change in specifications, such as support for an extended temperature
range. Finally, each part number contains a revision level code that refers to the die mask revision number.
Section 11.2, Part Numbers Not Fully Addressed by This Document, lists the part numbers that do not
fully conform to the specifications of this document. These special part numbers require an additional
document called a hardware specification addendum.
11.1 Part Numbers Fully Addressed by This Document

Table 18 provides the Freescale part numbering nomenclature for the MPC7448 part numbers fully
addressed by this document. For information regarding other MPC7448 part numbers, see Section 11.2,
Part Numbers Not Fully Addressed by This Document.
Table 18. Part Numbering Nomenclature
xx 7448 xx nnnn L x
Product Part Processor Application
Package Revision Level
Code Identifier Frequency Modifier
MC 7448 HX = HCTE BGA 1700 L: 1.3 V +20/50 mV C: 2.1; PVR = 0x8004_0201

PPC 1 VS = RoHS LGA 0 to 105 C D: 2.2; PVR = 0x8004_0202
VU = RoHS BGA
1600 L: 1.25 V 50 mV
0 to 105 C
1420 L: 1.2 V 50 mV
0 to 105 C
1000 L: 1.15 V 50 mV
0 to 105 C
Notes:
1. The P prefix in a Freescale part number designates a Pilot Production Prototype as defined by Freescale SOP 3-13. These
parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written
authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the
fact that product changes may still occur as pilot production prototypes are shipped.

11.2 Part Numbers Not Fully Addressed by This Document

Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate hardware specification addenda which supplement and supersede this document. As
such parts are released, these specifications will be listed in this section.
Table 19. Part Numbers Addressed by MC7448xxnnnn Nx Series Hardware Specification Addendum
(Document Order No. MPC7448ECS01AD)
xx 7448 xx nnnn N x
Product Part Processor
Package Application Modifier Revision Level
Code Identifier Frequency
MC 7448 HX = HCTE BGA 1400 N: 1.15 V 50 mV C: 2.1; PVR = 0x8004_0201
VS = RoHS LGA 0 to 105 C D: 2.2; PVR = 0x8004_0202
VU = RoHS BGA (date code 0613 and later) 2
MC 1400 N: 1.1 V 50 mV
PPC1 0 to 105 C
(date code 0612 and prior) 2
MC 1267 N: 1.1 V 50 mV
PPC1 Revision C only 0 to 105 C
MC 1267 N: 1.05 V 50 mV
PPC1 Revision D only 0 to 105 C
MC 1250 N: 1.1 V 50 mV
PPC1 0 to 105 C
MC 1000 N: 1.0 V 50 mV
PPC1 867 0 to 105 C
800
667
600
Notes:
1. The P prefix in a Freescale part number designates a Pilot Production Prototype as defined by Freescale SOP 3-13. These
parts have only preliminary reliability and characterization data. Before pilot production prototypes can be shipped, written
authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the
fact that product changes may still occur as pilot production prototypes are shipped.
2. Core voltage for 1400 MHz devices currently in production (date code of 0613 and later) is 1.15 V 50 mV; all such devices
have the MC product code. The 1400 MHz devices with date code of 0612 and prior specified core voltage of 1.1 V 50 mV;
this includes all 1400 MHz devices with the PPC product code. See Section 11.3, Part Marking, for information on part
marking.

Table 20. Part Numbers Addressed by MC7448Txxnnnn Nx Series Hardware Specification Addendum
(Document Order No. MPC7448ECS02AD)
xx 7448 T xx nnnn N x
Product Part Specificatio Processor Application
Package Revision Level
Code Identifier n Modifier Frequency Modifier
MC 7448 T = Extended HX = HCTE BGA 1400 N: 1.15 V 50 mV C: 2.1; PVR = 0x8004_0201

PPC1 Temperature 40 to 105 C D: 2.2; PVR = 0x8004_0202
Device
1267 N: 1.1 V 50 mV
Revision C only 40 to 105 C
1267 N: 1.05 V 50 mV
Revision D only 40 to 105 C
1000 N: 1.0 V 50 mV
40 to 105 C
Notes:
1. The P prefix in a Freescale part number designates a Pilot Production Prototype as defined by Freescale SOP 3-13.
These parts have only preliminary reliability and characterization data. Before pilot production prototypes can be shipped,
written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status
and the fact that product changes may still occur as pilot production prototypes are shipped.
11.3 Part Marking

Parts are marked as the example shown in Figure 27.
xx7448
xxnnnnNx
AWLYYWW
MMMMMM
YWWLAZ
7448
BGA/LGA
Notes:
AWLYYWW is the test code, where YYWW is the date code (YY = year, WW = work week)
MMMMMM is the M00 (mask) number.
YWWLAZ is the assembly traceability code.
Figure 27. Part Marking for BGA and LGA Device

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Document Number: MPC7448EC

Rev. 4
3/2007

MPC7448 RISC Microprocessor Hardware Specifications: Freescale Semiconductor

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MPC7448 RISC Microprocessor Hardware Specifications: Freescale Semiconductor

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Freescale Semiconductor Document Number: MPC7448EC

Technical Data Rev. 4, 3/2007

Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.

Clock Multiplier (12-Word) SRs 128-Entry

16 Rename 16 Rename Finished L1 Castout 16 Rename

Figure 1. MPC7448 Block Diagram

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Four vector units and 32-entry vector register file (VRs)

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Monitors all dispatched instructions and retires them in order

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Efficient data flow

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Reliability and serviceability

3 Comparison with the MPC7447A, MPC7447, MPC7445,

Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441

Basic Pipeline Functions

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Table 1. Microarchitecture Comparison (continued)

Microarchitectural Specs MPC7448 MPC7447A MPC7447 MPC7445 MPC7441

Execution Unit Timings (Latency-Throughput)

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

5 Electrical and Thermal Characteristics

5.1 DC Electrical Characteristics

Characteristic Symbol Maximum Value Unit Notes

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Figure 2 shows the undershoot and overshoot voltage on the MPC7448.

Figure 2. Overshoot/Undershoot Voltage

BVSEL0 BVSEL1 I/O Voltage Mode 1 Notes

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Min Max Min Max Min Max Min Max

Core supply voltage VDD 1.15 V 50 mV 1.2 V 50 mV 1.25 V 50 mV 1.3 V +20/ V 3, 4, 5

PLL supply voltage AVDD 1.15 V 50 mV 1.2 V 50 mV 1.25 V 50 mV 1.3 V +20/ V 2, 3, 4

Die-junction temperature Tj 0 105 0 105 0 105 0 105 C

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Characteristic Symbol Value Unit Notes

Junction-to-board thermal resistance RJB 11 C/W

Junction-to-case thermal resistance RJC < 0.1 C/W

Table 6 provides the DC electrical characteristics for the MPC7448.

Input high voltage 1.5 VIH OVDD 0.65 OVDD + 0.3 V 2

2.5 1.7 OVDD + 0.3

Input low voltage 1.5 VIL 0.3 OVDD 0.35 V 2

2.5 0.3 0.7

Input leakage current, all signals except Iin A 2, 3

Input leakage current, BVSEL0, Iin A 2, 6

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Table 6. DC Electrical Specifications (continued)

High-impedance (off-state) leakage current: ITSI A 2, 3, 4

Output high voltage @ IOH = 5 mA 1.5 VOH OVDD 0.45 V

1.8 OVDD 0.45

Output low voltage @ IOL = 5 mA 1.5 VOL 0.45 V

Capacitance, All inputs Cin 8.0 pF 5

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Die Junction Maximum Processor Core Frequency (Speed Grade, MHz)

Deep Sleep Mode (PLL Disabled)

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

5.2 AC Electrical Characteristics

5.2.1 Clock AC Specifications

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Table 8. Clock AC Timing Specifications

Maximum Processor Core Frequency (Speed Grade)

Min Max Min Max Min Max Min Max

SYSCLK frequency fSYSCLK 33 200 33 200 33 200 33 200 MHz 1, 2, 8

SYSCLK cycle time tSYSCLK 5.0 30 5.0 30 5.0 30 5.0 30 ns 2

SYSCLK duty cycle measured at tKHKL/ 40 60 40 60 40 60 40 60 % 4

SYSCLK cycle-to-cycle jitter 150 150 150 150 ps 5, 6

Internal PLL relock time 100 100 100 100 s 7

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Figure 3 provides the SYSCLK input timing diagram.

5.2.2 Processor Bus AC Specifications

All Speed Grades

Input setup times: ns

Input hold times: ns

Output valid times: ns

Output hold times: ns