32 bit RISC Processor

Abstract
To design 32 bit RISC processor. Develop VHDL code to implement the processor on
Cyclone board. Here we develop a simple multi-cycle processor. The top-down approach
is used in the design process. The processor is divided into two major parts—control unit
and datapath, which are independently developed and integrated to get the overall
processor.

By
G.Dinesh
Roll no:03425
Contents

1. Overview of Microprocessor
2. RISC vs CISC Processor
3. RISC processor Implementation—Single Cycle and Multi Cycle
processor.
4. Processor—top level entity
I. Instruction Format
II. Control unit
III. Datapath
a. ALU
b. ALU controller
c. Memory
d. Register file
e. Mux-32
f. Mux-5
g. Mux_sel
h. Pc Register
i. Instruction Register
j. Instruction split
k. Extender
5. Cyclone EP1C6 devices
Overview of Microprocessor:

The circuit for the microprocessor can be divided into two parts: the datapath and the
control unit as shown in the figure.

The datapath is responsible for the actual execution of all operations performed by the
microprocessor such as the addition inside the arithmetic logic unit (ALU). The datapath
also includes the registers for the temporary storage of your data. The functional units
inside the datapath (ALU, shifter, etc.) and the registers are connected together with
multiplexers and buses to form one unit, the datapath.

Even though the datapath is capable of performing all the operations of the
microprocessor, it cannot, however, do it on its own. In order for the datapath to execute
the operations automatically, the control unit is required. The control unit, also known as
the controller, controls the operations of the datapath, and therefore, the operations of the
entire microprocessor. The controller is a finite state machine (FSM) because it is a
machine that executes by going from one state to another, and the fact that there are only
a finite number of states for the machine to go to. The controller is made up of three
parts: the next-state logic, the state memory, and the output logic. The purpose of the
state memory is to remember the current state that the FSM is in. The next-state logic is
the circuit for determining what the next state ought to be for the machine. And the
output logic is the circuit for generating the actual control signals for controlling the
datapath.

Every digital logic circuit, regardless of whether it is part of the control unit or the
datapath, is categorized as either a combinational circuit or a sequential circuit. A
combinational circuit is one where the output of the circuit is dependent only on the
current inputs to the circuit. For example, an adder circuit is a combinational circuit. It
takes two numbers as inputs. When given the two inputs, the adder outputs the sum of the
two numbers as the output. A sequential circuit, on the other hand, is dependent not only
on the current inputs but also on all the previous inputs. In other words, a sequential
circuit has to remember its past history.

Design:

Digital circuits can be designed at any one of several abstraction levels. Designing at the
transistor level, which is the lowest level, we would be dealing with discrete transistors
and connecting them together to form the circuit. The next level up in the abstraction is
the gate level. At this level we are working with logic gates to build the circuit. At the
gate level, we can also specify the circuit using either a truth table or a Boolean equation.
Using logic gates, a designer usually creates combinational and sequential components to
be used in building larger circuits. In this way a very large circuit such as a
microprocessor can be built in a hierarchical fashion. Design methodologies have shown
that solving a problem hierarchically is always easier than trying to solve the entire
problem as a whole. These combinational and sequential components are used at the
register-transfer level in building the datapath and the control unit in the
microprocessor. At the register-transfer level, we are concerned about how the data is
transferred between the various registers and functional units to realize or solve the
problem at hand. Finally, at the highest level, which is the behavioral level, we construct
the circuit by describing the behavior or operation of the circuit using a hardware
description language.
Here we would be using VHDL to describe the circuit, at Register-level.
RISC vs CISC
A Complex Instruction Set Computer (CISC) provides a large and powerful range of
instructions, which is less flexible to implement. For example, the 8086 microprocessor
family has these instructions:

JA Jump if Above
JAE Jump if Above or Equal
JB Jump if Below
...
JPO Jump if Parity Odd
JS Jump if Sign
JZ Jump if Zero

There are 32 jump instructions in the 8086, and the 80386 adds more. The primary goal
of CISC architecture is to complete a task in as few lines of assembly as possible. This is
achieved by building processor hardware that is capable of understanding and executing a
series of operations.

Reduced Instruction Set Computer (RISC) only use simple instructions. As these are
much simpler, they can be implemented directly in silicon, so will run at the maximum
possible speed. There are only two Jump instructions in the ARM processor - Branch and
Branch with Link.

Most modern CISC processors, such as the Pentium, uses a fast RISC core with an
interpreter sitting between the core and the instruction.

Advantages of RISC processor:

• It has fewer instructions, and the design will be less complicated.

• RISC processor requires fewer transistors than comparable CISC processors.
• Faster execution of the instructions.

In spite of above advantages RISC processor has the disadvantage that the program
would be lengthy. Software for RISC processors must handle more operations than
traditional CISC [Complex Instruction Set Computer] processors.

RISC processor Implementation—Single Cycle and Multi

Cycle processor
RISC processor can be implemented in any of the following ways
• Single-Cycle processor
• Multi-Cycle processor
In Single cycle processor execution of any instruction takes only one clock cycle.
Though, this is easy to implement, it has a primary disadvantage that cycle time is
decided by instruction that takes longest time to execute.

In Multi cycle processor, each instruction is divided to number of small parts, each of
which is executed in one clock cycle. Datapath is portioned in to equal size chuncks, to
minimize the cycle time.It has advantage that each instruction doesn’t require to take
same amount of time. So, cycle time is decided by datapath and control path
combinational delay.

In the following pages, we would develop a Multi cycle 32 bit RISC processor. Here we
would be using top-down approach.

Processor:

It is the top level design entity which comprises of datapath and control unit. It
structurally combines controller and datapath.

Entity:

Here InstrWr is active high signal that is used to write instructions and data into the
memory asynchronously. Instr_data<31:0> is data or instruction to be written, and
Instradr<31:0> is address of the location.

VHDL Code:
--The following package code is given in appendix.
use work.cpu_lib.ALL;--this includes a package, which defines various data types used in
--the program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity processor is
port(clk:in std_logic;
InstrWr:in std_logic;
Instradr:in std_logic_vector(size downto 0);
Instr_data:in std_logic_vector(size downto 0);
r:out std_logic_vector(size downto 0));--defining the ports
end processor;

architecture Behavioral of processor is

--Including the Control unit

component control_unit is
port(opcode:in std_logic_vector(5 downto 0);
equal:in std_logic;
clk: in std_logic;
IorD : out std_logic;
MemWr : out std_logic;
MemRd : out std_logic;
IRwr : out std_logic;
RegDst :out std_logic;
RegWr : out std_logic;
ExtOp : out std_logic;
MemtoReg :out std_logic;
ALUSelA :out std_logic;
ALUSelB : out std_logic_vector(1 downto 0);
ALUOp : out std_logic_vector(2 downto 0);
PCSrc: out std_logic
);
end component;

--Datapath
component datapath is
Port ( IorD : in std_logic;
MemWr : in std_logic;
MemRd : in std_logic;
InstrWr:in std_logic;
IRwr : in std_logic;
RegDst : in std_logic;
RegWr : in std_logic;
ExtOp : in std_logic;
MemtoReg : in std_logic;
 ALUSelA : in std_logic;
ALUSelB : in std_logic_vector(1 downto 0);
ALUOp : in std_logic_vector(2 downto 0);
PCSrc: in std_logic;
clock: in std_logic;
Instradr:in std_logic_vector(size downto 0);
Instr_data:in std_logic_vector(size downto 0);
op:out std_logic_vector(5 downto 0);
Eq:out std_logic;
result:out std_logic_vector(size downto 0));
end component;

--Declaring the signals to connect Control unit and Datapath Structurally

signal IorD : std_logic;--to select the read address for memory

signal MemWr :std_logic; --Memory write signal
signal MemRd : std_logic;--Memory read signal
signal IRwr : std_logic; --Instruction reg write
signal RegDst : std_logic; --To select from Rt and Rd
signal RegWr : std_logic; --Register write signal
signal ExtOp : std_logic; --to select the type of extension
signal MemtoReg : std_logic;--select whether to write from memory or from ALu_out
signal ALUSelA : std_logic; --select the type of input to alu (pc or from regfile)
signal ALUSelB :std_logic_vector(1 downto 0);--select the second input to ALU
signal ALUOp : std_logic_vector(2 downto 0);
--input to alu controller to generate necessary controll signal
signal PCSrc: std_logic;--to indicate when to write to the pcreg
signal op:std_logic_vector(5 downto 0);--opcode
signal Eq: std_logic;--goes high when both inputs of alu are equalbegin
--Giving proper signals to Control unit
a0:datapath port map(
IorD,MemWr,MemRd,InstrWr,IRwr,RegDst,RegWr,Extop,MemtoReg,ALUSelA,ALUS
elB,ALUOp,PCSRc,clk,Instradr,Instr_data,op,Eq,r
);

--Generating signals for Datapath, Takes status signals from datapath as input
a1:control_unit port map(
op,Eq,clk,IorD,MemWr,MemRd,IRwr,RegDst,REgWr,Extop,MemtoReg,ALUSelA,ALU
SelB,ALUop,PCSrc
);
end Behavioral;
Schematic:

Instruction Format:

One of the important things that we must decide before starting the processor design is
the instruction format and the number of instruction. For RISC processors the number of
instructions is less.

Here, 32 bit instruction format is being considered.

The Instruction Format can be divided into 3 categories, as follows.

The different fields are
• op: operation of the instruction
• rs,rt,rd: the source and destination register specifiers.
• shamt: the shift amount.
• funct:selects the variant of the operation in the op field
• addres/immediate:address offset or immediate value
• target address:target address of the jump instruction

The following table indicates the decoding logic for the various opcodes.

Opcode Instruction operation

000000 R-type
101101 Or-immediate
100011 Load word
101011 Store word
000100 Branch instruction

For R-type instruction the type of instruction operation depends on the last 6-bits that is
on funct bits. The type of operation is as indicated below.

Funct<5:0> Instruction operation

100000 Add
100010 Subtract
100100 And
100101 Or

The immediate value or address offset is either sign extended or zero-extended as

required. Most often immediate value is zero-extended, where as address is sign-
extended.

Control Unit:

The control unit is a sequential circuit in which its outputs are dependent on both its
current and past inputs. This history of past inputs is stored in the state memory and is
said to represent the state of the circuit. Thus, the circuit changes from one state to the
next when the content of the memory changes. Depending on the current state of the
circuit and the input signals, the next-state logic will determine what the next state ought
to be by changing the content of the state memory. Hence, a sequential circuit executes
by going through a sequence of states. Since the state memory is finite, therefore the total
number of different states that the circuit can go to is also finite. This is not to be
confused with the fact that the sequence length can be infinitely long. However, because
of the reason of having only a finite number of states, a sequential circuit is also referred
to as a finite-state machine (FSM).

Control unit takes inputs opcode and equal from datapath and generates required control
signals to the datapath.

State Diagram:
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control_unit is
port(opcode:in std_logic_vector(5 downto 0);
 equal:in std_logic;
clk: in std_logic;
IorD : out std_logic;
MemWr : out std_logic;
MemRd : out std_logic;
IRwr : out std_logic;
RegDst :out std_logic;
RegWr : out std_logic;
ExtOp : out std_logic;
MemtoReg :out std_logic;
ALUSelA :out std_logic;
ALUSelB : out std_logic_vector(1 downto 0);
ALUOp : out std_logic_vector(2 downto 0);
PCSrc: out std_logic
);
end control_unit;

architecture Behavioral of control_unit is

signal st:std_logic_vector(3 downto 0):="0000";

begin
process(clk)
begin

if clk'event and clk='1' then

case st is
--Fetch the instruction
when "0000" =>
IorD<='0';
MemRd<='1';
MemWr<='0';
IRWr<='1';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='0';
ALUSelB<="00";
ALUop<="000";
PCSrc<='1';

st<="0001";
--decode the instruction

when "0001" =>

 IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';
--generate the next state depending on the opcode
case opcode is
when "000000" =>
st<="0100";
when "101101" =>
st<="1101";
when "001101" =>
st<="0110";
when "100011" =>
st<="1000";
when "101011" =>
st<="1011";
when "000100" =>
st<="0010";
when others =>
st<="0000";

end case;
--branch instruction
when "0010" =>
IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="001";
PCSrc<='0';
--check if both operands are equal
if equal='1' then
 st<="0011";
else
st<="0000";
end if;
--Beq increment the pc by the immediate value
when "0011" =>
IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='1';
MemtoReg<='0';
ALUSelA<='0';
ALUSelB<="01";
ALUop<="000";
PCSrc<='1';

st<="0000";
--R-type instruction
when "0100" =>
IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='1';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="100";
PCSrc<='0';

st<="0101";
--store the result of the R-type in regfile R[Rd]
when "0101" =>
IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='1';
RegWr<='1';
Extop<='0';
MemtoReg<='0';
 ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';

st<="0000";
--Or immediate instruction
--zero extend the immediate value and perform or operation
when "0110" =>
IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="11";
ALUop<="010";
PCSrc<='0';

st<="0111";
--store the result in regfile

when "0111" =>

IorD<='0';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='1';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';

st<="0000";
--Load word instruction
--calucalate the memory location address
when "1000" =>
IorD<='1';
MemRd<='1';
MemWr<='0';
 IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='1';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="11";
ALUop<="000";
PCSrc<='0';

st<="1001";
--Fetch the data from the memory location
when "1001" =>
IorD<='1';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='1';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';

st<="1010";
--write the data to the regfile
when "1010" =>
IorD<='1';
MemRd<='0';
MemWr<='0';
IRWr<='0';
RegDst<='0';
RegWr<='1';
Extop<='0';
MemtoReg<='1';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';

st<="0000";
--store word instruction
--calucalate the memory location address
when "1011" =>
 IorD<='0';
MemRd<='0';
MemWr<='1';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='1';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="10";
ALUop<="000";
PCSrc<='0';

st<="1100";
--write the value from busB to the memory
when "1100" =>
IorD<='1';
MemRd<='0';
MemWr<='1';
IRWr<='0';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='1';
ALUSelB<="01";
ALUop<="111";
PCSrc<='0';

st<="0000";

when others =>

IorD<='1';
MemRd<='1';
MemWr<='0';
IRWr<='1';
RegDst<='0';
RegWr<='0';
Extop<='0';
MemtoReg<='0';
ALUSelA<='0';
ALUSelB<="00";
ALUop<="000";
PCSrc<='1';
st<="0001";
end case;
end if;
end process;
end Behavioral;

Schematic:
Datapath:

The datapath is responsible for the manipulation of data. It includes (1) functional units
such as adders, shifters, multipliers, ALUs, and comparators, (2) registers and other
memory elements for the temporary storage of data, and (3) buses and multiplexers for
the transfer of data between the different components in the datapath. External data can
be entered into the datapath through the data input lines.

In order for the datapath to function correctly, appropriate control signals must be
asserted at the right time. Control signals are needed for all the select and control lines for
all the components used in the datapath. This includes all the select lines for multiplexers,
ALU and other functional units having multiple operations, all the read/write enable
signals for registers and register files, address lines for register files, and memory. The
operation of the datapath is determined by which control signals are asserted and at what
time. In a microprocessor, these control signals are generated by the control unit.

In return, the datapath needs to supply status signals back to the control unit in order for
it to operate correctly. These status signals are usually from the output of comparators.
The comparator tests for a given logical condition between two values. These values can
be obtained either from memory elements, directly from the output of functional units, or
hardwired as constants. These status signals provide input information for the control unit
to determine what operation to perform next. For example, in a branch equal instruction,
the status signal will tell the control unit whether jumps or not. Since the datapath
performs all the functional operations of a microprocessor, and the microprocessor is for
solving problems, therefore the datapath must be able to perform all the operations
required to solve the given problem. Datapath design is also referred to as the register-
transfer level (RTL) design.

Datapath is structural combination of the following components.

• ALU
• Multiplexer (32 bit and 5 bit) of 2 input,1 output
• Multiplexer (32 bit ) – 4 input ,1 output
• Register-file which consist of 32 registers, each of 32 bits.
• Memory—which consists of 32 locations, each of 32 bits long.
• Extender which does either sign-extension or zero-extension
• Some registers to store temporary data
o Instruction register—to store the instruction
o ALU_out –to store the output of alu.
o Pcreg—to store the program counter.

In the following pages, we would take up each and discuss.

Block Diagram:
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity for datapath

entity datapath is
 Port ( IorD : in std_logic;
MemWr : in std_logic;
MemRd : in std_logic;
InstrWr:in std_logic;
IRwr : in std_logic;
RegDst : in std_logic;
RegWr : in std_logic;
ExtOp : in std_logic;
MemtoReg : in std_logic;
ALUSelA : in std_logic;
ALUSelB : in std_logic_vector(1 downto 0);
ALUOp : in std_logic_vector(2 downto 0);
PCSrc: in std_logic;
clock: in std_logic;
Instradr:in std_logic_vector(size downto 0);
instr_data:in std_logic_vector(size downto 0);
op:out std_logic_vector(5 downto 0);
Eq:out std_logic;
result:out std_logic_vector(size downto 0));
end datapath;

architecture Behavioral of datapath is

--The following would include the necessary components

--32x32 Register file
component regfile is
Port ( Ra : in std_logic_vector(raddr downto 0);
Rb : in std_logic_vector(raddr downto 0);
Rw : in std_logic_vector(raddr downto 0);
RegWr : in std_logic;
clk : in std_logic;
busW:in std_logic_vector(size downto 0);
busA : out std_logic_vector(size downto 0);
busB : out std_logic_vector(size downto 0));
end component;

--Extender

component extender is
Port ( imm : in std_logic_vector(bsize downto 0);
extop : in std_logic;
y : out std_logic_vector(size downto 0));
end component;

--32 bit ALU

component alu is
Port ( a : in std_logic_vector(size downto 0);
b : in std_logic_vector(size downto 0);
aluctr : in std_logic_vector(2 downto 0);
equal : out std_logic;
result : out std_logic_vector(size downto 0));
end component;

component mux32 is
Port ( a : in std_logic_vector(size downto 0);
b : in std_logic_vector(size downto 0);
s : in std_logic;
y : out std_logic_vector(size downto 0));
end component;

--mux to select between Rt and Rd

component mux5 is
Port ( a : in std_logic_vector(raddr downto 0);
b : in std_logic_vector(raddr downto 0);
s : in std_logic;
y : out std_logic_vector(raddr downto 0));
end component;

--mux to select the type of input toALU

component mux_sel is
Port ( b : in std_logic_vector(size downto 0);
c : in std_logic_vector(size downto 0);
d : in std_logic_vector(size downto 0);
s : in std_logic_vector(1 downto 0);
q : out std_logic_vector(size downto 0));
end component;

--Memory

component memory is
Port ( Memwr : in std_logic;
Memrd : in std_logic;
InstWr: in std_logic;
clk : in std_logic;
Radr : in std_logic_vector(size downto 0);
Wradr : in std_logic_vector(size downto 0);
Instradr: in std_logic_vector(size downto 0);
instr_data:in std_logic_vector(size downto 0);
data_in : in std_logic_vector(size downto 0);
 data_out : out std_logic_vector(size downto 0));
end component;

--Instruction Register

component instr_reg is
Port ( a : in std_logic_vector(size downto 0);
IRWr:in std_logic;
clk : in std_logic;
inst : out std_logic_vector(size downto 0));
end component;

component shft is
Port ( a : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;

component ALUout is
Port ( a : in std_logic_vector(size downto 0);
q : out std_logic_vector(size downto 0));
end component;

component instr_spilt is
Port ( instr : in std_logic_vector(31 downto 0);
op:out std_logic_vector(5 downto 0);
Rs : out std_logic_vector(4 downto 0);
Rt : out std_logic_vector(4 downto 0);
Rd : out std_logic_vector(4 downto 0);
func:out std_logic_vector(5 downto 0);
imm16 : out std_logic_vector(15 downto 0));
end component;

component ALU_control is
Port ( func : in std_logic_vector(5 downto 0);
ALU_op : in std_logic_vector(2 downto 0);
ALU_ctr : out std_logic_vector(2 downto 0));
end component;

component pcreg is
port( pcin :in std_logic_vector(size downto 0);
PcSrc: in std_logic;
clk: in std_logic;
 pcout : out std_logic_vector(size downto 0));
end component;

signal m1:std_logic_vector(size downto 0);

signal dout:std_logic_vector(size downto 0);--output from memory
signal instr:std_logic_vector(size downto 0);--output from instruction register
signal Rs,Rt,Rdd,Rd:std_logic_vector(4 downto 0);
signal busA,busB,busW:std_logic_vector(size downto 0); --busA,busB outputs from
regfile
--busW is input to the regfile
signal ext_out:std_logic_vector(size downto 0);--output from extender
signal alu_ina,alu_inb:std_logic_vector(size downto 0);--inputs to alu
signal ext_s_out:std_logic_vector(size downto 0);--output from shifter
signal alu_out,aluout_r:std_logic_vector(size downto 0);
signal aluctr:std_logic_vector(2 downto 0);--input to the alu
signal imm16:std_logic_vector(15 downto 0);--immediate value or address
signal func:std_logic_vector(5 downto 0); --Function bits
signal pc:std_logic_vector(size downto 0):="00000000000000000000000000000000";
--program counter

--aluout_r is the output of the alu_out register

--aluout is the input to the aluout register
--Extender 1 for sign ext and 0 for zero ext

begin
a:pcreg port map (alu_out,PcSrc,clock,pc);
s0:mux32 port map(pc,aluout_r,IorD,m1);
s1: memory port
map(Memwr,MemRd,InstrWr,clock,m1,aluout_r,Instradr,Instr_data,busB,dout);
s2: instr_reg port map(dout,IRWr,clock,instr);
s3: instr_spilt port map(instr,op,Rs,Rt,Rd,func,imm16);
s4: mux5 port map(Rt,Rd,RegDst,Rdd);
s5: regfile port map (Rs,Rt,Rdd,Regwr,clock,busW,busA,busB);
s6: mux32 port map (aluout_r,dout,MemtoReg,busW);
s9: extender port map(imm16,ExtOp,ext_out);
s10: mux32 port map(pc,busA,ALUSelA,alu_ina);
s11: shft port map(ext_out,ext_s_out);
s12: mux_sel port map(busB,ext_s_out,ext_out,ALUSelB,alu_inb);
s13: ALU_control port map(func,ALUop,aluctr);
s14: alu port map(alu_ina,alu_inb,aluctr,Eq,alu_out);
s15: aluout port map (alu_out,aluout_r);
s18:result<=aluout_r;

end Behavioral;
Schematic of Datapath:
Simulation:

The following is simulation for

ALU

ALU is the major block in the datapath that performs all the required operations.

ALUctr Operation
000 Add
001 Subtract
010 Or
011 And
100 Nop
In implementing the ALU, we are using VHDL functions.
ALU works without any clock.
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is
Port ( a : in std_logic_vector(size downto 0);
b : in std_logic_vector(size downto 0);
aluctr : in std_logic_vector(2 downto 0);
equal : out std_logic;
result : out std_logic_vector(size downto 0));
end alu;

architecture Behavioral of alu is

begin
process(a,b,aluctr)
variable t:std_logic_vector(size downto 0); --temporary variable
variable r :std_logic_vector(size downto 0);--result
begin
t:=a-b;

case t is

when "00000000000000000000000000000000" =>

equal<='1';
when others =>
equal<='0';

end case;
 case aluctr is

when "000" => --Addition

r:=a+b;
when "001" => --Subtraction
r:=a-b;
when "010" => --Or
r:=a or b;
when "011" => --And
r:= a and b;
when "100" => --Noperatoin
result<=r;
when others =>
r:="00000000000000000000000000000000";
end case;
result<=r;
end process;

end Behavioral;
Schematic:

Simulation:
ALU Controller:
It generates the control signals for ALU depending on ALU-op. It works without the
clock.

Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_control is
Port ( func : in std_logic_vector(5 downto 0);
ALU_op : in std_logic_vector(2 downto 0);
ALU_ctr : out std_logic_vector(2 downto 0));
end ALU_control;

architecture Behavioral of ALU_control is

begin
process(func,ALU_op)
begin
case ALU_op is

when "000" =>--add

ALU_ctr<="000";
when "001" =>--subtract
ALU_ctr<= "001";
when "010" =>--or
ALU_ctr<="010";
when "011" =>--and
 ALU_ctr<="011";
when "100" =>--R-type instruction
case func is
when "100000" =>--add
ALU_ctr<="000";
when "100010" =>--subtract
ALU_ctr<="001";
when "100100" =>--or
ALU_ctr<="011";
when "100101" =>--and
ALU_ctr<="010";
when others=>--nop
ALU_ctr<="100";
end case;
when "111" =>--nop
ALU_ctr<="100";
when others =>
ALU_ctr<="100";
end case;

end process;

end Behavioral;
Schematic:

Memory:

Memory here is consisting of 32 locations and each is of 32 bit long. It has both read and
write signals. There are other signals for writing instructions into the memory. Memory
read operation doesn’t require any clock edge while memory write requires an active
clock edge.
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity memory is
Port ( Memwr : in std_logic;
 Memrd : in std_logic;
InstWr: in std_logic;
clk : in std_logic;
Radr : in std_logic_vector(size downto 0);
Wradr : in std_logic_vector(size downto 0);
Instradr: in std_logic_vector(size downto 0); --address to write the instruction
instr_data:in std_logic_vector(size downto 0);--Instruction or data to be written
data_in : in std_logic_vector(size downto 0); --Data input to memory
data_out : out std_logic_vector(size downto 0));--data out from memory
end memory;

architecture Behavioral of memory is

type memory is array (size downto 0) of std_logic_vector(size downto 0);

signal ram:mem:=--Initializing memory by default values

(x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00
000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0000000
0",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0
0000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"000000
00",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");

begin
process(clk,InstWr,Instradr,Instr_data,Radr)
begin

if clk'event and clk='1' then –check for active clock edge

if Memwr='1' then
ram(CONV_INTEGER(Wradr(mem_size-1 downto 0)))<=data_in;
data_out<="00000000000000000000000000000000";
end if;

end if;

If InstWr='1' then—write the instructions asynchronously

ram(CONV_INTEGER(Instradr(mem_size-1 downto 0)))<=instr_data;
end if;

data_out<=ram(CONV_INTEGER(Radr(mem_size-1 downto 0)));

end process;
end Behavioral;

Schematic:
In the above schematic “Instradr” and “Instr_data” are omitted as, it gives synthesis
problem because of two clocks.

Regfile:

Like, memory it also doesn’t require clock to read, but requires clock to write to the
register. Here Regfile of 32 register, each of 32 bits long is implemented. Regwr should
be high, when writing to the register.

Ra—Source register….its value will be output on busA

Rb—Source register….its value will be output on busB
Rw—Destination Register…the value on busW will be written to it on active clock edge
and when Regwr=’1’;

Entity:
VHDL Code:

use work.cpu_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity regfile is
Port ( Ra : in std_logic_vector(4 downto 0);
Rb : in std_logic_vector(4 downto 0);
Rw : in std_logic_vector(4 downto 0);
RegWr : in std_logic;
clk : in std_logic;
busW:in std_logic_vector(size downto 0);
busA : out std_logic_vector(size downto 0);
busB : out std_logic_vector(size downto 0));
end regfile;

architecture Behavioral of regfile is

signal regarray:reg_file:=--Initializing the ram with default values

(x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00
000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0000000
0",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0
0000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"000000
00",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process(Ra,Rb,Rw,RegWr,clk,busW)
variable addr_a,addr_b,addr_w:integer;

begin

addr_a:=CONV_INTEGER(Ra);
addr_b:=CONV_INTEGER(Rb);
addr_w:=CONV_INTEGER(Rw);
busA<=regarray(addr_a); --Read R[Ra]
busB<=regarray(addr_b);--Read R[Rb]

if clk'event and clk='1' then—wait for active clock edge

if Regwr='1' then—see if write signal is active
regarray(addr_w)<=busW;--write the data
end if;
end if;
end process;

end Behavioral;
Schematic:

Here two rams are resulted because we are using three address to address 32
register.
Mux-32:

Mux-32 has two 32 bit input and one select line, to output one of them. This doesn’t
require any clock edge.
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux32 is
Port ( a : in std_logic_vector(size downto 0);
b : in std_logic_vector(size downto 0);
s : in std_logic;
y : out std_logic_vector(size downto 0));
end mux32;

architecture Behavioral of mux32 is

begin
process(a,b,s)

begin

case s is
when '0' =>--select a input
y<=a;
when '1' =>--select b input
y<=b;
when others =>
 y<="00000000000000000000000000000000";
end case;
end process;

end Behavioral;

Schematic:

Mux 5:
It has two 5 bit inputs and one select line, to select the output. It works without any clock
edge.

Entity:

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux5 is
Port ( a : in std_logic_vector(4 downto 0);
b : in std_logic_vector(4 downto 0);
s : in std_logic;
y : out std_logic_vector(4 downto 0));
end mux5;
architecture Behavioral of mux5 is

begin
process(a,b,s)
begin
case s is
when '0' =>
y<=a;
when '1' =>
y<=b;
when others =>
y<="00000";
end case;
end process;
end Behavioral;

Schematic:

Mux_sel:

It takes four input and two select lines(ALUSelB) and outputs one of them. It doesn’t
require any clock edge. One input is the default value of ‘1’ required to increment pc.
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_sel is
Port (
b : in std_logic_vector(size downto 0);
c : in std_logic_vector(size downto 0);
d : in std_logic_vector(size downto 0);
s : in std_logic_vector(1 downto 0);
q : out std_logic_vector(size downto 0));
end mux_sel;

architecture Behavioral of mux_sel is

begin
process(b,c,d,s)
begin
case s is
when "00" =>--output the value 1—required to increment pc
q<="00000000000000000000000000000001";
when "01" =>--output the value b—value on busB
q<=b;
when "10" =>--output the value c—connected to the output of shifter.
q<=c;
 when "11" =>--output the value d—connected to the output of extender
q<=d;
when others =>
q<="00000000000000000000000000000000";
end case;
end process;

end Behavioral;

Schematic:
PC Register:

It is used to hold the value of pc (program counter). PcSrc, signal is used to indicate when
to write the next value of pc. It works on rising edge of the clock.
Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pcreg is
port(pcin:in std_logic_vector(size downto 0);
PcSrc: in std_logic;
clk: in std_logic;
pcout: out std_logic_vector(size downto 0));
end pcreg;

architecture Behavioral of pcreg is

--load pc with the initialize value of 0
signal pc:std_logic_vector(size downto 0):="00000000000000000000000000000000";

begin
process(clk)
begin
if clk'event and clk='1' then—wait for rising clock edge
if PcSrc='1' then—to know when to load next pc value
pc<=pcin;
end if;
end if;
 end process;

pcout<=pc;--continuously output the value present in pc

end Behavioral;

Schematic:

Instruction Register:

The instruction fetched during the begging of the instruction execution must be held until
the execution of the instruction is completed. This is done by instruction register. This
writes the value from memory when IRwr=’1’ and on the falling clock edge.

Entity:
VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity instr_reg is
Port ( a : in std_logic_vector(size downto 0);
IRWr:in std_logic;
clk : in std_logic;
inst : out std_logic_vector(size downto 0));
end instr_reg;

architecture Behavioral of instr_reg is

--load instr_reg with the default value.
signal instrreg:std_logic_vector(size downto 0 )
:=”0000000000000000000000000000000”;
begin
process(clk)

begin
if clk'event and clk='0' then –check for falling clock edge.
If IRWr='1' then—condition for writing to the register
instrreg<=a;
end if;
end if;
end process;
inst<=instrreg;--output the value present in the register.
end Behavioral;
Schematic:
Instruction spilt:

It continuously takes the instruction from instruction register and splits them to various
parts as given in the instruction format. It doesn’t require a clock.

op<=instr(31 downto 26);

Rs<=instr(25 downto 21);
Rt<=instr(20 downto 16);
Rd<=instr(15 downto 11);
func<=instr(5 downto 0);
imm16<=instr(15 downto 0);

Entity:

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity instr_spilt is
Port ( instr : in std_logic_vector(31 downto 0);
op:out std_logic_vector(5 downto 0);
Rs : out std_logic_vector(4 downto 0);
Rt : out std_logic_vector(4 downto 0);
Rd : out std_logic_vector(4 downto 0);
 func:out std_logic_vector(5 downto 0);
imm16 : out std_logic_vector(15 downto 0));
end instr_spilt;

architecture Behavioral of instr_spilt is

begin

op<=instr(31 downto 26);

Rs<=instr(25 downto 21);
Rt<=instr(20 downto 16);
Rd<=instr(15 downto 11);
func<=instr(5 downto 0);
imm16<=instr(15 downto 0);

end Behavioral;
Schematic:
Extender:

This extenders either the given immediate 16 bit value to 32 bit either as sign extension
or as zero extension depending on the value of Extop (1—for sign extension and 0 –for
zero extension). It works without any clock. The output from extender goes as input to
mux_sel and to the shifter.

Entity:

VHDL Code:

use work.cpu_lib.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity extender is
Port ( imm : in std_logic_vector(bsize downto 0);
extop : in std_logic;
y : out std_logic_vector(size downto 0));
end extender;

architecture Behavioral of extender is

begin
process(imm,extop)
variable sign:std_logic;--sign of the given input
variable t:std_logic_vector(size downto 0);--temporary variable
begin

case extop is
when '0' =>--zero extension
y(size downto bsize+1)<="0000000000000000";
y(bsize downto 0)<=imm;
 when '1' => --sign extension
sign:=imm(bsize);

for i in bsize+1 to size loop

t(i):=sign;
end loop;

t(bsize downto 0):=imm;

y<=t;
when others =>
y<="00000000000000000000000000000000";
end case;

end process;

end Behavioral;

Schematic:
Implementation(Cyclone EP1C6):

The processor designed above is implemented on cyclone (EP1C6) board. The following
would discuss this device.

EP1C6 Devices:

The EP1C6, a member of the Cyclone device family, provides 6,523 registers; 92,160
memory bits; and 5,980 logic elements. The Cyclone device meets the low-voltage
requirements of 1.5-V applications and supports multiple I/O standards including LVDS
(low-voltage differential signaling), LVTTL, LVCMOS, PCI, SSTL-3 Class I & II,
and SSTL-2 Class I & II.

The EP1C6 is available in 144-pin TQFP packages with 92 I/O pins, 240-pin QFP
packages with 181 I/O pins, and 256-pin FineLine BGA packages (See Note (12)). The
device has 5,980 logic elements grouped into 598 LABs. These LABs are arranged into
20 rows and 32 columns. The embedded memory consists of one column of M4K
memory blocks, containing a total of 92,160 RAM bits. Each M4K block can implement
shift registers and various types of memory with or without parity bits, including dual-
port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers.
Each I/O element contains a bidirectional I/O buffer and three registers for complete
embedded bidirectional single data rate transfer. The I/O element contains individual
input, output, and output enable registers. The input register provides fast setup times, the
output register provides fast clock-to-output times, and the output enable register
provides fast clock-to-output enable times. The EP1C6 also contains four dedicated clock
pins and eight dual-purpose clock pins for large fan-out control signals. In addition, the
EP1C6 contains two phase-locked loops (PLLs), which provide general purpose clocking
with clock multiplication and phase shifting as well as high-speed outputs for high-speed
differential I/O support.

The EP1C6 also supports ICR and JTAG BST. The EP1C6 JTAG Instruction Register
length is 10; the Boundary-Scan Register length is 582; and the JTAG ID code is
0x020820DD.

The following table displays the pin-out information for EP1C6 devices:

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Row I/O 0 LVDS14p/INIT_DONE4 1 IOC_X0_Y20_N0 D4 1 1

Row I/O 1 LVDS14n 4 1 IOC_X0_Y20_N1 C3 2 2
Row I/O 2 LVDS13p/CLKUSR 4 1 IOC_X0_Y19_N0 C2 3 3
Row I/O 3 LVDS13n 4 1 IOC_X0_Y19_N1 B1 4 4
X0Y19SUB_LOC2 4 VREF0B1 - 1 IOC_X0_Y19_N2 G5 5 5
Row I/O 5 - 4 1 IOC_X0_Y18_N0 F4 6 6
Row I/O 6 LVDS12p/DQ0L0 4 1 IOC_X0_Y18_N1 D3 7 7 DQ
Row I/O 7 LVDS12n/DQ0L1 4 1 IOC_X0_Y18_N2 E4 8 - DQ
Row I/O 8 DPCLK1/DQS0L 4 1 IOC_X0_Y17_N0 F5 11 10 DQ
Row I/O 9 LVDS11p/DQ0L2 4 1 IOC_X0_Y17_N1 E3 12 - DQ
Row I/O 10 LVDS11n/DQ0L3 4 1 IOC_X0_Y17_N2 D2 13 - DQ
Row I/O 11 LVDS10p 4 1 IOC_X0_Y16_N0 E2 14 -
Row I/O 12 LVDS10n 4 1 IOC_X0_Y16_N1 D1 15 -
Row I/O 13 LVDS9p 4 1 IOC_X0_Y16_N2 F3 16 -
Row I/O 14 LVDS9n 4 1 IOC_X0_Y15_N0 G3 17 -
Row I/O 15 LVDS8p 4 1 IOC_X0_Y15_N1 F2 18 -
Row I/O 16 LVDS8n 4 1 IOC_X0_Y14_N0 E1 19 -
Row I/O 17 LVDS7p 4 1 IOC_X0_Y14_N1 G2 20 -
Row I/O 18 LVDS7n/DM0L 4 1 IOC_X0_Y14_N2 F1 21 - DM
X0Y13SUB_LOC0 19 VREF1B1 - 1 IOC_X0_Y13_N0 H5 23 11
Row I/O 20 nCSO 19 1 IOC_X0_Y13_N1 G4 24 12
Dedicated
21 DATA0 - 1 IOC_X0_Y12_N0 H2 25 13
Programming
Dedicated
22 nCONFIG - 1 IOC_X0_Y12_N1 H3 26 14
Programming
Dedicated Clock 23 CLK0/LVDSCLK1p 19 1 IOC_X0_Y12_N2 G1 28 16
Dedicated Clock 24 CLK1/LVDSCLK1n 19 1 IOC_X0_Y11_N0 H1 29 17

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Dedicated
25 nCEO - 1 IOC_X0_Y11_N1 H4 32 20
Programming
Dedicated
26 nCE - 1 IOC_X0_Y11_N2 J4 33 21
Programming
Dedicated
27 MSEL0 - 1 IOC_X0_Y10_N0 J3 34 22
Programming
Dedicated
28 MSEL1 - 1 IOC_X0_Y10_N1 J2 35 23
Programming
Dedicated
29 DCLK - 1 IOC_X0_Y10_N2 K4 36 24
Programming
Row I/O 30 ASDO 19 1 IOC_X0_Y9_N0 K3 37 25
Row I/O 31 PLL1_OUTp 19 1 IOC_X0_Y8_N0 J1 38 26
Row I/O 32 PLL1_OUTn 19 1 IOC_X0_Y8_N1 K2 39 27
Row I/O 33 - 45 1 IOC_X0_Y7_N0 L3 41 -
Row I/O 34 LVDS6p 45 1 IOC_X0_Y7_N1 K1 42 -
Row I/O 35 LVDS6n 45 1 IOC_X0_Y7_N2 L1 43 -
Row I/O 36 LVDS5p 45 1 IOC_X0_Y6_N0 L2 44 -
Row I/O 37 LVDS5n 45 1 IOC_X0_Y6_N1 M1 45 -
Row I/O 38 LVDS4p 45 1 IOC_X0_Y5_N0 N1 46 -
Row I/O 39 LVDS4n 45 1 IOC_X0_Y5_N1 M2 47 -
Row I/O 40 LVDS3p/DQ0L4 45 1 IOC_X0_Y4_N0 N2 48 - DQ
Row I/O 41 LVDS3n/DQ0L5 45 1 IOC_X0_Y4_N1 M3 49 - DQ
Row I/O 42 DPCLK0/DQS1L 45 1 IOC_X0_Y4_N2 L5 50 28
Row I/O 43 LVDS2p/DQ0L6 45 1 IOC_X0_Y3_N0 M4 53 - DQ
Row I/O 44 LVDS2n/DQ0L7 45 1 IOC_X0_Y3_N1 N3 54 - DQ
X0Y3SUB_LOC2 45 VREF2B1 - 1 IOC_X0_Y3_N2 K5 55 31
Row I/O 46 - 45 1 IOC_X0_Y2_N0 L4 56 32
Row I/O 47 LVDS1p 45 1 IOC_X0_Y2_N1 R1 57 33
Row I/O 48 LVDS1n 45 1 IOC_X0_Y2_N2 P2 58 34
Row I/O 49 LVDS0p 45 1 IOC_X0_Y1_N0 P3 59 35
Row I/O 50 LVDS0n 45 1 IOC_X0_Y1_N1 N4 60 36

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Column I/O 51 LVDS71p 60 4 IOC_X2_Y0_N2 R2 61 37

Column I/O 52 LVDS71n 60 4 IOC_X2_Y0_N1 T2 62 38
Column I/O 53 LVDS70p 60 4 IOC_X2_Y0_N0 R3 63 -
Column I/O 54 LVDS70n 60 4 IOC_X4_Y0_N2 P4 64 -
Column I/O 55 LVDS69p 60 4 IOC_X4_Y0_N1 R4 65 39
Column I/O 56 LVDS69n 60 4 IOC_X4_Y0_N0 T4 66 40
Column I/O 57 LVDS68p/DQ1B7 60 4 IOC_X6_Y0_N2 R5 67 41 DQ
Column I/O 58 LVDS68n/DQ1B6 60 4 IOC_X6_Y0_N1 P5 68 42 DQ
Column I/O 59 DPCLK7/DQS1B 60 4 IOC_X6_Y0_N0 M5 73 47 DQ
X8Y0SUB_LOC2 60 VREF2B4 - 4 IOC_X8_Y0_N2 M6 74 48
Column I/O 61 LVDS67p 60 4 IOC_X8_Y0_N1 N5 75 49
Column I/O 62 LVDS67n/DQ1B5 60 4 IOC_X8_Y0_N0 N6 76 - DQ
Column I/O 63 LVDS66p/DQ1B4 60 4 IOC_X10_Y0_N2 P6 77 - DQ
Column I/O 64 LVDS66n 60 4 IOC_X10_Y0_N1 R6 78 -
Column I/O 65 - 60 4 IOC_X10_Y0_N0 M7 79 -
Column I/O 66 LVDS65p 60 4 IOC_X12_Y0_N2 T6 80 -
Column I/O 67 LVDS65n 60 4 IOC_X12_Y0_N1 R7 81 -
Column I/O 68 LVDS64p 60 4 IOC_X12_Y0_N0 P7 82 -
Column I/O 69 LVDS64n 60 4 IOC_X14_Y0_N2 N7 83 -
Column I/O 70 LVDS63p 60 4 IOC_X14_Y0_N1 R8 84 50
Column I/O 71 LVDS63n 60 4 IOC_X14_Y0_N0 T8 85 51
Column I/O 72 LVDS62p 75 4 IOC_X16_Y0_N2 N8 86 52
Column I/O 73 LVDS62n 75 4 IOC_X16_Y0_N1 P8 87 53
Column I/O 74 - 75 4 IOC_X16_Y0_N0 M8 88 -
X20Y0SUB_LOC2 75 VREF1B4 - 4 IOC_X20_Y0_N2 M10 93 56
Column I/O 76 LVDS61p/DM1B 75 4 IOC_X20_Y0_N1 R9 94 57 DM
Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25
No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Column I/O 77 LVDS61n 75 4 IOC_X20_Y0_N0 T9 95 58

Column I/O 78 LVDS60p 75 4 IOC_X22_Y0_N2 P9 96 -
Column I/O 79 LVDS60n 75 4 IOC_X22_Y0_N1 N9 97 -
Column I/O 80 LVDS59p 75 4 IOC_X22_Y0_N0 R10 98 -
Column I/O 81 LVDS59n 75 4 IOC_X24_Y0_N2 T11 99 59
Column I/O 82 LVDS58p 75 4 IOC_X24_Y0_N1 N10 100 -
Column I/O 83 LVDS58n 75 4 IOC_X24_Y0_N0 P10 101 -
Column I/O 84 LVDS57p 89 4 IOC_X26_Y0_N2 R11 102 -
Column I/O 85 LVDS57n 89 4 IOC_X26_Y0_N1 P11 103 -
Column I/O 86 LVDS56p 89 4 IOC_X26_Y0_N0 N11 104 -
Column I/O 87 LVDS56n 89 4 IOC_X28_Y0_N2 N12 105 -
Column I/O 88 - 89 4 IOC_X28_Y0_N1 M9 106 60
X28Y0SUB_LOC0 89 VREF0B4 - 4 IOC_X28_Y0_N0 M11 107 61
Column I/O 90 DPCLK6/DQS0B 89 4 IOC_X30_Y0_N2 M12 108 62
Column I/O 91 LVDS55p/DQ1B3 89 4 IOC_X30_Y0_N1 P12 113 67 DQ
Column I/O 92 LVDS55n/DQ1B2 89 4 IOC_X30_Y0_N0 R12 114 68 DQ
Column I/O 93 LVDS54p/DQ1B1 89 4 IOC_X32_Y0_N2 T13 115 69 DQ
Column I/O 94 LVDS54n/DQ1B0 89 4 IOC_X32_Y0_N1 R13 116 70 DQ
Column I/O 95 LVDS53p 89 4 IOC_X32_Y0_N0 R14 117 -
Column I/O 96 LVDS53n 89 4 IOC_X34_Y0_N2 P13 118 -
Column I/O 97 LVDS52p 89 4 IOC_X34_Y0_N1 T15 119 71
Column I/O 98 LVDS52n 89 4 IOC_X34_Y0_N0 R15 120 72
Row I/O 99 LVDS51n 105 3 IOC_X35_Y1_N1 N13 121 73
Row I/O 100LVDS51p 105 3 IOC_X35_Y1_N0 P14 122 74
Row I/O 101LVDS50n 105 3 IOC_X35_Y2_N2 P15 123 75
Row I/O 102LVDS50p 105 3 IOC_X35_Y2_N1 R16 124 76

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Row I/O 103LVDS49n/DQ1R7 105 3 IOC_X35_Y2_N0 N15 125 77 DQ

Row I/O 104LVDS49p 105 3 IOC_X35_Y3_N2 N16 126 78
X35Y3SUB_LOC1 105VREF2B3 - 3 IOC_X35_Y3_N1 K12 127 79
Row I/O 106DQ1R6 105 3 IOC_X35_Y3_N0 K14 128 - DQ
Row I/O 107DPCLK5/DQS1R 105 3 IOC_X35_Y4_N2 L12 131 82 DQ
Row I/O 108LVDS48n/DQ1R5 105 3 IOC_X35_Y4_N1 N14 132 DQ1R5DQ
Row I/O 109LVDS48p/DQ1R4 105 3 IOC_X35_Y4_N0 M13 133 84 DQ
Row I/O 110LVDS47n 105 3 IOC_X35_Y5_N1 M14 134 85
Row I/O 111LVDS47p 105 3 IOC_X35_Y5_N0 L13 135 -
Row I/O 112LVDS46n 105 3 IOC_X35_Y6_N1 M15 136 -
Row I/O 113LVDS46p 105 3 IOC_X35_Y6_N0 M16 137 -
Row I/O 114LVDS45n 105 3 IOC_X35_Y7_N1 L14 138 -
Row I/O 115LVDS45p 105 3 IOC_X35_Y7_N0 L15 139 -
Row I/O 116LVDS44n 105 3 IOC_X35_Y8_N1 L16 140 -
Row I/O 117LVDS44p 105 3 IOC_X35_Y8_N0 K16 141 -
Row I/O 118PLL2_OUTn 128 3 IOC_X35_Y9_N1 K15 143 -
Row I/O 119PLL2_OUTp 128 3 IOC_X35_Y9_N0 J16 144 -
Dedicated
120CONF_DONE - 3 IOC_X35_Y10_N2K13 145 86
Programming
Dedicated
121nSTATUS - 3 IOC_X35_Y10_N1J13 146 87
Programming
JTAG 122TCK - 3 IOC_X35_Y10_N0J14 147 88
JTAG 123TMS - 3 IOC_X35_Y11_N1J15 148 89
JTAG 124TDO - 3 IOC_X35_Y11_N0H15 149 90
Dedicated Clock 125CLK3/LVDSCLK2n 128 3 IOC_X35_Y12_N2H16 152 92
Dedicated Clock 126CLK2/LVDSCLK2p 128 3 IOC_X35_Y12_N1G16 153 93
JTAG 127TDI - 3 IOC_X35_Y12_N0H14 155 95
X35Y13SUB_LOC2 128VREF1B3 - 3 IOC_X35_Y13_N2H12 156 96

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Row I/O 129LVDS43n/DM1R 145 3 IOC_X35_Y13_N1G14 158 - DM

Row I/O 130LVDS43p 145 3 IOC_X35_Y13_N0G13 159 -
Row I/O 131LVDS42n 145 3 IOC_X35_Y14_N1G15 160 -
Row I/O 132LVDS42p 145 3 IOC_X35_Y14_N0F16 161 -
Row I/O 133LVDS41n 145 3 IOC_X35_Y15_N2F14 162 -
Row I/O 134LVDS41p 145 3 IOC_X35_Y15_N1F13 163 -
Row I/O 135LVDS40n 145 3 IOC_X35_Y15_N0F15 164 -
Row I/O 136LVDS40p 145 3 IOC_X35_Y16_N2E16 165 -
Row I/O 137LVDS39n 145 3 IOC_X35_Y16_N1E15 166 -
Row I/O 138LVDS39p 145 3 IOC_X35_Y16_N0D16 167 97
Row I/O 139LVDS38n 145 3 IOC_X35_Y17_N2D15 168 98
Row I/O 140LVDS38p/DQ1R3 145 3 IOC_X35_Y17_N1E14 169 99 DQ
Row I/O 141DPCLK4/DQS0R 145 3 IOC_X35_Y17_N0F12 170 100
Row I/O 142LVDS37n/DQ1R2 145 3 IOC_X35_Y18_N2E13 173 - DQ
Row I/O 143LVDS37p/DQ1R1 145 3 IOC_X35_Y18_N1D14 174 - DQ
Row I/O 144DQ1R0 145 3 IOC_X35_Y18_N0H13 175 103 DQ
X35Y19SUB_LOC2 145VREF0B3 - 3 IOC_X35_Y19_N2G12 176 104
Row I/O 146LVDS36n 145 3 IOC_X35_Y19_N1B16 177 105
Row I/O 147LVDS36p 145 3 IOC_X35_Y19_N0C15 178 106
Row I/O 148LVDS35n 145 3 IOC_X35_Y20_N1C14 179 107
Row I/O 149LVDS35p 145 3 IOC_X35_Y20_N0D13 180 108
Column I/O 150LVDS34n 159 2 IOC_X34_Y21_N0B15 181 109
Column I/O 151LVDS34p 159 2 IOC_X34_Y21_N1A15 182 110
Column I/O 152LVDS33n 159 2 IOC_X34_Y21_N2B14 183 -
Column I/O 153LVDS33p 159 2 IOC_X32_Y21_N0C13 184 -
Column I/O 154LVDS32n/DQ0T0 159 2 IOC_X32_Y21_N1B13 185 111 DQ

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Column I/O 155LVDS32p/DQ0T1 159 2 IOC_X32_Y21_N2A13 186 112 DQ

Column I/O 156LVDS31n/DQ0T2 159 2 IOC_X30_Y21_N0B12 187 DQ0T2 DQ
Column I/O 157LVDS31p/DQ0T3 159 2 IOC_X30_Y21_N1C12 188 114 DQ
Column I/O 158DPCLK3/DQS0T 159 2 IOC_X30_Y21_N2E12 193 119 DQ
X28Y21SUB_LOC0 159VREF0B2 - 2 IOC_X28_Y21_N0E11 194 120
Column I/O 160- 159 2 IOC_X28_Y21_N1E9 195 121
Column I/O 161LVDS30n 159 2 IOC_X28_Y21_N2D12 196 -
Column I/O 162LVDS30p 159 2 IOC_X26_Y21_N0D11 197 -
Column I/O 163LVDS29n 159 2 IOC_X26_Y21_N1C11 198 -
Column I/O 164LVDS29p 159 2 IOC_X26_Y21_N2B11 199 -
Column I/O 165LVDS28n 173 2 IOC_X24_Y21_N0A11 200 -
Column I/O 166LVDS28p 173 2 IOC_X24_Y21_N1B10 201 -
Column I/O 167LVDS27n 173 2 IOC_X24_Y21_N2C10 202 122
Column I/O 168LVDS27p 173 2 IOC_X22_Y21_N0D10 203 -
Column I/O 169LVDS26n 173 2 IOC_X22_Y21_N1A9 204 -
Column I/O 170LVDS26p 173 2 IOC_X22_Y21_N2B9 205 -
Column I/O 171LVDS25n/DM0T 173 2 IOC_X20_Y21_N0D9 206 123 DM
Column I/O 172LVDS25p 173 2 IOC_X20_Y21_N1C9 207 124
X20Y21SUB_LOC2 173VREF1B2 - 2 IOC_X20_Y21_N2E10 208 125
Column I/O 174- 173 2 IOC_X16_Y21_N0E8 213 -
Column I/O 175LVDS24n 173 2 IOC_X16_Y21_N1C8 214 128
Column I/O 176LVDS24p 173 2 IOC_X16_Y21_N2D8 215 129
Column I/O 177LVDS23n 188 2 IOC_X14_Y21_N0A8 216 130
Column I/O 178LVDS23p 188 2 IOC_X14_Y21_N1B8 217 131
Column I/O 179LVDS22n 188 2 IOC_X14_Y21_N2D7 218 -
Column I/O 180LVDS22p 188 2 IOC_X12_Y21_N0C7 219 -

Function Pad Secondary VRefI/O Pad 256-Pin 240- 144- 25

No. Function Pad BankLocation FineLine Pin Pin DQ
PQFP TQFP

Column I/O 181LVDS21n 188 2 IOC_X12_Y21_N1B7 220 -

Column I/O 182LVDS21p 188 2 IOC_X12_Y21_N2A6 221 -
Column I/O 183- 188 2 IOC_X10_Y21_N0E7 222 -
Column I/O 184LVDS20n 188 2 IOC_X10_Y21_N1B6 223 -
Column I/O 185LVDS20p 188 2 IOC_X10_Y21_N2C6 224 -
Column I/O 186LVDS19n 188 2 IOC_X8_Y21_N0 D6 225 -
Column I/O 187LVDS19p 188 2 IOC_X8_Y21_N1 D5 226 132
X8Y21SUB_LOC2 188VREF2B2 - 2 IOC_X8_Y21_N2 E6 227 133
Column I/O 189DPCLK2/DQS1T 188 2 IOC_X6_Y21_N0 E5 228 134
Column I/O 190LVDS18n/DQ0T4 188 2 IOC_X6_Y21_N1 C5 233 139 DQ
Column I/O 191LVDS18p/DQ0T5 188 2 IOC_X6_Y21_N2 B5 234 140 DQ
Column I/O 192LVDS17n/DQ0T6 188 2 IOC_X4_Y21_N0 A4 235 141 DQ
Column I/O 193LVDS17p/DQ0T7 188 2 IOC_X4_Y21_N1 B4 236 142 DQ
Column I/O 194LVDS16n 188 2 IOC_X4_Y21_N2 C4 237 -
Column I/O 195LVDS16p 188 2 IOC_X2_Y21_N0 B3 238 -
Column I/O 196LVDS15n/DEV_OE 188 2 IOC_X2_Y21_N1 A2 239 143
Column I/O 197LVDS15p/DEV_CLRn 188 2 IOC_X2_Y21_N2 B2 240 144

Power, Ground, and No-Connect Pins for 256-Pin FineLine

Function Pin Name (I/O Bank)

VCCIO4 L7(3) L10(3) T3(3) T14(3)

VCCIO3 C16(2) K11(2) P16(2)
VCCIO2 A3(1) A14(1) F7(1) F10(1)
VCCIO1 C1 G6 P1
VCCINT A7 A10 G8 G10 H7 H9
T7 T10
VCCA_PLL2 H11
VCCA_PLL1 H6
GNDG_PLL2 J12
GNDG_PLL1 J5
GNDA_PLL2 J11
GNDA_PLL1 J6
GND A1 A5 A12 A16 F6 F8
G11 H8 H10 J7 J9 K6
L9 L11 T1 T5 T12 T16

Power, Ground, and No-Connect Pins for 240-Pin PQFP

Function Pin Name (I/O Bank)

VCCIO4 70(3) 92(3) 112(3)

VCCIO3 130(2) 157(2) 172(2)
VCCIO2 189(1) 209(1) 231(1)
VCCIO1 9 22 51
VCCINT 72 90 110 191 211 229
VCCA_PLL2 154
VCCA_PLL1 27
GNDG_PLL2 150
GNDG_PLL1 31
GNDA_PLL2 151
GNDA_PLL1 30
GND 10 40 52 69 71 89 91
142 171 190 192 210 212 230

Power, Ground, and No-Connect Pins for 144-Pin TQFP

Function Pin Name (I/O Bank)

VCCIO4 44(3) 66(3)

VCCIO3 81(2) 102(2)
VCCIO2 115(1) 137(1)
VCCIO1 8 29
VCCINT 46 55 64 117 126 135
VCCA_PLL2 94
VCCA_PLL1 15
GNDG_PLL2 91
GNDG_PLL1 19
GNDA_PLL2 -
GNDA_PLL1 18
GND 9 30 43 45 54 63
118 127 136 138