FS FSQ510
FS FSQ510
January 2009
Pulse-by-Pulse Current Limit Compared with discrete MOSFET and PWM controller
solutions, the FSQ510 (H or M) can reduce total cost,
Protection Functions: Overload Protection (OLP), component count, size and weight; while simultaneously
Internal Thermal Shutdown (TSD) with Hysteresis increasing efficiency, productivity, and system reliability.
Under-Voltage Lockout (UVLO) with Hysteresis This device provides a platform for cost-effective designs
of a valley switching flyback converters.
Internal Startup Circuit
Internal High-Voltage SenseFET: 700V
Built-in Soft-Start: 5ms
Applications
Auxiliary Power Supplies for LCD TV, LCD Monitor,
Personal Computer, and White Goods
Ordering Information
(1)
Output Power Table
Operating
Part Current RDS(ON) 230VAC 15%(2) 85-265VAC Replaces
Package Eco Junction
Number Limit (MAX) (3) Open (3) Open Devices
Status Temperature Adapter (4) Adapter (4)
Frame Frame
FSQ510 7-DIP FSD210B
FSQ510H 8-DIP RoHS -40 to +130C 320mA 32 5.5W 9W 4W 6W FSD210DH
FSQ510M 7-MLSOP FSD210BM
AC
IN
Vstr
D
VS
Sync -PWM GND
Vfb Vcc
200 ns
delay
UVLO VREF
0.7V / 0.1V 8.7V / 6.7V
VREF VREF
Idelay IFB
OSC
3
Vfb S Q
(2) 6R
R R
360ns
LEB
Rsense
0.85V / 0.75V (0.4V)
S/S
5ms
OLP
S
TSD Q
4.7V
A/R R
Vstr D
Vfb Vcc
FSQ510H
Sync GND
GND GND
Pin Definitions
7-Pin 8-Pin Name Description
1, 2 4, 5, 6 GND This pin is the control ground and the SenseFET source.
This pin is internally connected to the inverting input of the PWM
comparator. The collector of an opto-coupler is typically tied to this
3 2 Vfb pin. For stable operation, a capacitor should be placed between this
pin and GND. If the voltage of this pin reaches 4.7V, the overload
protection triggers, which shuts down the FPS.
This pin is internally connected to the sync-detect comparator for
4 3 Sync valley switching. In normal valley-switching operation, the threshold of
the sync comparator is 0.7V/0.1V.
This pin is the positive supply input. This pin provides internal
5 7 VCC
operating current for both startup and steady-state operation.
7 8 D High-voltage power SenseFET drain connection.
This pin is connected directly, or through a resistor, to the high-
voltage DC link. At startup, the internal high-voltage current source
8 1 Vstr supplies internal bias and charges the external capacitor connected
to the VCC pin. Once VCC reaches 8.7V, the internal current source is
disabled.
Thermal Impedance
TA=25C unless otherwise specified. Items are tested with the standards JESD 51-2 and 51-10 (DIP).
1.20 1.20
1.15 1.15
1.10 1.10
Normalized
Normalized
1.05 1.05
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125
Temperature [] Temperature []
Figure 4. Operating Frequency (fOSC) vs. TA Figure 5. Peak Current Limit (ILIM) vs. TA
1.20 1.20
1.15 1.15
1.10 1.10
Normalized
Normalized
1.05 1.05
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125
Temperature [] Temperature []
Figure 6. Start Threshold Voltage (VSTART) vs. TA Figure 7. Stop Threshold Voltage (VSTOP) vs. TA
1.20 1.20
1.15 1.15
1.10 1.10
Normalized
Normalized
1.05 1.05
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125
Temperature [] Temperature []
Figure 8. Shutdown Feedback Voltage (VSD) vs. TA Figure 9. Maximum Duty Cycle (DMAX) vs. TA
1.20 1.20
1.15 1.15
1.10 1.10
Normalized
Normalized
1.05 1.05
1.00 1.00
0.95 0.95
0.90 0.90
0.85 0.85
0.80 0.80
-40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125
Temperature [] Temperature []
Figure 10. Feedback Source Current (IFB) vs. TA Figure 11. Shutdown Delay Current (IDELAY) vs. TA
1.20
1.15
1.10
Normalized
1.05
1.00
0.95
0.90
0.85
0.80
-40 -25 0 25 50 75 100 125
Temperature []
Vref Vref
Ca
Idelay I FB VS signal
ICH
OLP R sense
VSD
Vref
6.7V/
VCC good
8.7V Figure 14. Valley Switching Pulse-Width
Internal Modulation (VS-PWM) Circuit
Bias
3. Synchronization: The FSQ510 (H or M) employs a
valley-switching technique to minimize the switching
Figure 13. Startup Block noise and loss. The basic waveforms of the valley
switching converter are shown in Figure 15. To
2. Feedback Control: This device employs current- minimize the MOSFET switching loss, the MOSFET
mode control, as shown in Figure 14. An opto-coupler should be turned on when the drain voltage reaches its
(such as the FOD817) and shunt regulator (such as the minimum value, as shown in Figure 15. The minimum
KA431) are typically used to implement the feedback drain voltage is indirectly detected by monitoring the
network. Comparing the feedback voltage with the VCC winding voltage, as shown in Figure 15.
B B
ON ON
T smax=10.6 s
Ids
Ids IDS
A
tB=7.6s
T s_A
Vds
IDS IDS
B
tB=7.6s
time
Switching Switching T s_B
disabled disabled
t1 t2 t3 t4
frequency has minimum and maximum values. Figure 20. Switching Frequency Range of the
Advanced Valley Switching
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
9.83
9.00
6.67
6.096
8.255
7.61
0.33 MIN
(0.56) 3.60
3.00 0.356
2.54 0.20
0.56
0.355
1.65 9.957
1.27 7.87
7.62
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
MKT-MLSOP07ArevA
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.