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    Resume: Email Id: Phone No: 9951612691

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    vlokesh007
    K.Veera Mani Ayyappa seeks a position to acquire new knowledge and sharpen skills while achieving organizational and individual goals. He has a B.Tech in ECE from Sri Vasavi Institute of Engineering and Technology with a percentage of 77.33%. His technical skills include Core Java and design tools like VHDL and MATLAB. As a project leader, he designed a low power multi-bit ALU using clock gating which reduced power consumption by up to 93.75%. His strengths include adaptability, working under pressure, and self-motivation. He has participated in NSS volunteer work and presented technical papers.

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    Resume: Email Id: Phone No: 9951612691

    Uploaded by

    vlokesh007
    18 views2 pages
    K.Veera Mani Ayyappa seeks a position to acquire new knowledge and sharpen skills while achieving organizational and individual goals. He has a B.Tech in ECE from Sri Vasavi Institute of Engineering and Technology with a percentage of 77.33%. His technical skills include Core Java and design tools like VHDL and MATLAB. As a project leader, he designed a low power multi-bit ALU using clock gating which reduced power consumption by up to 93.75%. His strengths include adaptability, working under pressure, and self-motivation. He has participated in NSS volunteer work and presented technical papers.

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    Java Sample Resume

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    Ayappa Resume

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    K.Veera Mani Ayyappa seeks a position to acquire new knowledge and sharpen skills while achieving organizational and individual goals. He has a B.Tech in ECE from Sri Vasavi Institute of Engineering and Technology with a percentage of 77.33%. His technical skills include Core Java and design tools like VHDL and MATLAB. As a project leader, he designed a low power multi-bit ALU using clock gating which reduced power consumption by up to 93.75%. His strengths include adaptability, working under pressure, and self-motivation. He has participated in NSS volunteer work and presented technical papers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    18 views2 pages

    Resume: Email Id: Phone No: 9951612691

    Uploaded by

    vlokesh007
    K.Veera Mani Ayyappa seeks a position to acquire new knowledge and sharpen skills while achieving organizational and individual goals. He has a B.Tech in ECE from Sri Vasavi Institute of Engineering and Technology with a percentage of 77.33%. His technical skills include Core Java and design tools like VHDL and MATLAB. As a project leader, he designed a low power multi-bit ALU using clock gating which reduced power consumption by up to 93.75%. His strengths include adaptability, working under pressure, and self-motivation. He has participated in NSS volunteer work and presented technical papers.

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    of 2

    RESUME

    K.VEERA MANI AYYAPPA Email id : [email protected]

    Phone no: 9951612691

    OBJECTIVE:
    To work in an organization where I can acquire new knowledge and sharpen my
    skills and put my efforts or achieving organization as well as individual goals.

    ACADEMIC QUALIFICATIONS:

    Qualification Institute Name Board Year of Percentage


    Completion of Marks
    B.Tech Sri Vasavi Institute of Engineering
    (ECE) JNTUK 2016 77.33%
    and Technology,Nandamuru.

    Indrakiladri junior college


    Intermediate BIE 2012 79%
    Machilipatnam
    (MPC)
    Sri sai public school
    10th SSC 2010 65%
    Machilipatnam.

    TECHNICAL SKILLS:

    Languages : Core Java


    Design Tools : VHDL , MAT Lab
    PROJECT:

    Title : Design of Low Power MULTI-BIT ALU by Using Clock Gating


    Roll : project leader

    Softwares Used : Xilinx version 14.4

    Description : The clock gating generally reduces the consumed amount of power when
    compared to normal implementation. Clock power reduces 60% of total dynamic power.
    Theoretically, we can reduce at a maximum of 93.75% of dynamic power. This clock
    gating internally contains 2 types that are latch based and latch free clock gating in which
    88.23% can be reduced using latch based and 70.5% can be reduced using latch free
    clock gating. Proposed flip-flops use new gating techniques that reduce power dissipation
    deactivating the clock signal. The advantage of power reduction is hardware design of the
    same circuit can be done at 40 nm and can be implemented using RTL and TTL level
    HDL model simulator

    STRENGTHS:

    Can easily adaptive To anytype Of Situations.


    Ability to Work Under any Situation.
    Positive attitude and Self Confidence.
    Self-Motivative.

    CO CURRICULAR ACTIVITIES:

    Participated as NSS Volunteer in 2014 Elections conducted by Government of Andhra Pradesh


    Presented paper on the topic Night vision technology at DMS SVH college of engineering

    PERSONAL PROFILE:

    Fathers Name : k.venkateswara Rao


    Mother`s Name : k.Raghavamma
    Date of Birth : 23th may 1995
    Languages known : English , Telugu
    Address : D.No:15/207-14-1 , Devuducheruvu road
    Anandapeta , Machilipatnam,
    Pincode : 521002

    DECLARATION:

    I declare all the information that I presented above is true up to my knowledge.

    Date: signature
    Place: (k.veera mani ayyappa)

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