1

Classification of Designs
1.1 INTRODUCTION

To fulfill their purpose, most buildings must be divided into rooms of various proportions that are
connected by halls, doors, and stairs. The organization and proportions are the duty of the architect. But
the architecture of a building is more that engineering: it must also express a fundamental desire for beauty,
ideals, and aspirations. This is analogous to the architectural design of computers.

Computer architecture is concerned with the selection of basic building blocks (such as processor, memory,
and input/output subsystems) and the way that these blocks interact with each other. A computer architect
selects and interconnects the blocks based on making trade-offs among a set of criteria, such as visible
characteristics, cost, speed, and reliability. The architecture of a computer should specify what functions
the computer performs and even the speed and data items with which those functions are accomplished.

Computer architecture is changing rapidly and has advanced a great deal in a very short time. As a result,
computers are becoming more powerful and more flexible each year. Today, a single chip performs
operations 100,000 times faster than a computer that would have been as large as a movie theater 40 years
ago.

Significant Historical Computers. John Atanasoff and his assistant, Clifford Berry, are credited with
building the first electronic computer at Iowa State University in 1939, which they named the ABC
(Atanasoff-Berry Computer). It was not large compared to the computers that would soon follow, and it
was built solely for the purpose of solving tedious physics equations, not for general purposes. Today, it
would be called a calculator, rather than a computer. Still, its design was based on binary arithmetic, and
its memory consisted of capacitors that were periodically refreshed, much like modern dynamic random
access memory (RAM).

A second important development occurred during World War II when John Mauchly from University of
Pennsylvania, who knew the U.S. government was interested in building a computer for military purposes,
received a grant from the U.S. Army for just that reason. With the help of J. Presper Eckert, he build the
ENIAC (Electronic Numerical Integrator and Calculator). Mauchly and Eckert were unable to complete
the ENIAC until 1946, a year after the war was over. One reason may have been its size and complexity.
The ENIAC contained over 18,000 vacuum tubes and weighed 30 tons. It was able to perform around 5000
additions per second. Although the ENIAC is important from a historical prospective, it was hugely
inefficient because each instruction had to be programmed manually by humans working outside the
machine.

In 1949, the world's first stored-program computer, called the Electronic Delay Storage Automatic
Calculator (EDSAC), was built by Maurice Wilkes of England's Cambridge University. This computer
used about 3000 vacuum tubes and was able to perform around 700 additions per second. The EDSAC was
based on the discovery of the mathematician John von Neumann. Von Neumann discovered the concept
of storing program instructions in memory along with the data on which those instructions operate. The
design of EDSAC was a vast improvement over the prior machines (such as the ENIAC) that required
rewiring to be reprogrammed.

In 1951, the Remington-Rand Corporation built the first commercialized derivative of the EDSAC, called
the UNIVersal Automatic Computer (UNIVAC I). The UNIVAC I was sold to the U.S. Bureau of the
Census, where it was used 24 hours a day, seven days a week. Similar to EDSAC, this machine was also
made of vacuum tubes; however, it was able to perform nearly 4000 additions per second.
Computer generations. The UNIVAC I and the machines that were built within the period of late 1940s
and mid 1950s are often referred to as the first generation of computers. In 1955, near the end of the first-
generation period, the IBM 704 was produced and became a commercial success. The IBM 704 used
parallel binary arithmetic circuits and a floating-point unit to significantly boost arithmetic speed-up over
traditional arithmetic logic units (ALU). Although the IBM 704 had advanced arithmetic operations, the
input/output (I/O) operations were still slow, thus bottlenecking the ALU from computing independently of
slow I/O operations. To reduce the bottleneck, I/O processors (later called channels) were introduced in
subsequent models of the IBM 704 and its successor, the IBM 709. I/O processors were used to process
reading and printing of data from and to the slow I/O devices. An I/O processor could print blocks of data
from main memory while the ALU could continue working. Because the printing occurred while the ALU
continued to work, this process became known as a spool (simultaneous print operation on line).

From 1958 to 1964, the second generation of computers was developed based on transistor technology.
The transistor, which was invented in 1947, was a breakthrough that enabled the replacement of vacuum
tubes. A transistor could perform most of the functions of a vacuum tube, but was much smaller in size,
much faster, and much more energy efficient. As a result, a second generation of computers emerged.
During this phase, IBM reengineered its 709 to use transistor technology and named it the IBM 7090. The
7090 was able to calculate close to 500,000 additions per second. It was very successful and IBM sold
about 400 units.

In 1964, the third generation of computers was born. This new generation was based on integrated circuit
(IC) technology, which was invented in 1957. An IC device is a tiny chip of silicon that hosts many
transistors and other circuit components. The silicon chip is encased in a sturdy ceramic (or other
nonconductive) material. Small metallic legs that extrude from the IC plug into the computer's circuit
board, connecting the encased chip to the computer. Through the last three decades, refinements of this
device have made it possible to construct faster and more flexible computers. Processing speed has
increased by an order of magnitude each year. In fact, the ways in which computers are structured, the
procedures used to design them, the trade-offs between hardware and software, and the design of
computational algorithms have all been affected by the advent and development of integrated circuits and
will continue to be greatly affected by the coming changes in this technology.

An IC may be classified according to the number of transistors or gates imprinted on its silicon chip. Gates
are simple switching circuits that, when combined, form the more complex logic circuits that allow the
computer to perform the complicated tasks now expected. Two basic gates in common usage, for example,
are the NAND and NOR gates. These gates have a simple design and may be constructed from relatively
few transistors. Based on the circuit complexity, ICs are categorized into four classes: SSI, MSI, LSI, and
VLSI. SSI (small-scale integration) chips contain 1 to10 gates; MSI (medium-scale integration) chips
contain 10 to100 gates; LSI (large-scale integration) chips contain 100 to100,000 gates; and VLSI (very
large-scale integration) chips include all ICs with more than 100,000 gates. The LSI and VLSI technologies
have moved computers from the third to new generations. The computers that were developed within 1972
to 1990 are referred to as the fourth generation of computers; from 1991 to present is referred to as fifth
generation.

Today, a VLSI chip can contain millions of transistors. They are expected to contain more than 100 million
transistors by the year 2000. One main factor contributing to this increase in integrated circuits is the effort
that has been invested in the development of computer-aided design (CAD) systems for IC design. CAD
systems are able to simplify the design process by hiding the low-level circuit theory and physical details of
the device, thereby allowing the designer to concentrate on functionality and ways of optimizing the design.

The progress in increasing the number of transistors on a single chip continues to augment the
computational power of computer systems, in particular that of the small systems (Personal Computers and
workstations). Today, as a result of improvements in these small systems, it is becoming more economical
to construct large systems by utilizing small systems processors. This allows some large systems companies
to use the high-performance, inexpensive processors already on the market so that they do not have to
spend thousands or millions of dollars for developing traditional large systems processor units. (The term
performance refers to the effective speed and the reliability of a device.) The large systems firms are now
placing more emphasis on developing systems with multiple processors for certain applications or general
purposes. When a computer has multiple processors, they may operate simultaneously, parallel to each
other. Functioning this way, the processors may work independently on different tasks, or process different
parts of the same task. Such a computer is referred to as a parallel computer or parallel machine.

There are many reasons for this trend toward parallel machines, the most common of which is to increase
overall computer power. Although the advancement of the semiconductor and VLSI technology has
substantially improved performance of single processor machines, these machines are still not fast enough
to perform certain applications within a reasonable time period, such as biomedical analysis, aircraft
testing, real-time pattern recognition, real-time speech recognition, and systems of partial differential
equations. Another reason for the trend is the physical limitations in VLSI technology and the fact that
basic physical laws limit the maximum speed of the processors' clock which governs how quickly
instructions can be executed. One giga-hertz (one clock cycle every billionth of a second) may be an
absolute limit that can be obtained for the clock speed.

In addition to faster speed, some parallel computers provide more reliable systems than do single processor
machines. If a single processor on the parallel system fails, the system can still operate (at a slightly
diminished capacity), whereas if the processor on a uniprocessor system fails, the whole system fails.
Parallel computers have built-in redundancy, meaning that many processors may be capable of performing
the same task. Computers with a high degree of redundancy are more reliable and robust and are said to be
fail-safe machines. Such machines are used in situations where failure would be catastrophic. Computers
that control shuttle launches or monitor nuclear power production are good examples.

The preceding advantages of parallel computers have led many companies to design such systems.
Today, numerous parallel computers are commercially available, and there will be many more in the near
future. The following section represents a classification of such machines.

1.2 TAXONOMIES OF PARALLEL ARCHITECTURES

One of the most well known taxonomies of computer architectures is called Flynn's taxonomy. Michael
Flynn [FLY 72] classifies architectures into four categories based on the presence of single or multiple
streams of instructions and data. (An instruction stream is a set of sequential instructions to be executed by
a single processor, and the data stream is the sequential flow of data required by the instruction stream.)
Flynn's four categories are as follows;

1. SISD (single instruction stream, single data stream). This is the von Neumann concept of serial
computer design in which only one instruction is executed at any time. Often, SISD is referred to
as a serial scalar computer. All SISD machines utilize a single register, called the program
counter, that enforces serial execution of instructions. As each instruction is fetched from memory,
the program counter is updated to contain the address of the next instruction to be fetched and
executed in serial order. Few, if any, pure SISD computers are currently manufactured for
commercial purposes. Even personal computers today utilize small degrees of parallelism to
achieve greater efficiency. In most situations, they are able to execute two or more instructions
simultaneously.

2. MISD (multiple instruction stream, single data stream). This implies that several instructions are
operating on a single piece of data. There are two ways to interpret the organization of MISD-type
machines. One way is to consider a class of machines that would require that distinct processing
units receive distinct instructions operating on the same data. This class of machines has been
challenged by many computer architects as impractical (or impossible), and at present there are no
working examples of this type. Another way is to consider a class of machines in which the data
flows through a series of processing units. Highly pipelined architectures, such as systolic arrays
and vector processors, are often classified under this machine type. Pipeline architectures perform
vector processing through a series of stages, each of which performs a particular function and
 produces an intermediate result. The reason that such architectures are labeled as MISD systems is
that elements of a vector may be considered to belong to the same piece of data, and all pipeline
stages represent multiple instructions that are being applied to that vector.

3. SIMD (single instruction stream, multiple data stream). This implies that a single instruction is
applied to different data simultaneously. In machines of this type, many separate processing units
are invoked by a single control unit. Like MISD, SIMD machines can support vector processing.
This is accomplished by assigning vector elements to individual processing units for concurrent
computation. Consider the payroll calculation (hourly wage rate * hours worked) for 1000
workers. On an SISD machine, this task would require 1000 sequential loop iterations. On an
SIMD machine, this calculation could be performed in parallel, simultaneously, on 1000 different
data streams (each representing one worker).

4. MIMD (multiple instruction stream, multiple data stream). This includes machines with several
processing units in which multiple instructions can be applied to different data simultaneously.
MIMD machines are the most complex, but they also hold the greatest promise for efficiency
gains accomplished through concurrent processing. Here concurrency implies that not only are
multiple processors operating simultaneously, but multiple programs (processes) are being
executed in the same time frame, concurrent to each other, as well.

Flynn's classification can be described by an analogy from the manufacture of automobiles. SISD is
analogous to the manufacture of an automobile by just one person doing all the various tasks, one at a time.
MISD can be compared to an assembly line where each worker performs one specialized task or set of
specialized tasks on the results of the previous workers accomplishment. Workers perform the same
specialized task for each result given to them by the previous worker, similar to an automobile moving
down an assembly line. SIMD is comparable to several workers performing the same tasks concurrently.
After all workers are finished, another task is given to the workers. Each worker constructs an automobile
by himself doing the same task at the same time. Instructions for the next task are given to each worker at
the same time and from the same source. MIMD is like SIMD except the workers do not perform the same
task concurrently, each constructs an automobile independently following his own set of instructions.

Flynn's classification has proved to be a good method for the classification of computer architectures for
almost three decades. This is evident by its widespread use by computer architects. However,
advancements in computer technologies have created architectures that cannot be clearly defined by Flynn's
taxonomy. For example, it does not adequately classify vector processors (SIMD and MISD) and hybrid
architectures. To overcome this problem, several taxonomies have been proposed [DAS 90, HOC 87, SKI
88, BEL 92]. Most of these proposed taxonomies preserve the SIMD and MIMD features of Flynn's
classification. These two features provide useful shorthand for characterizing many architectures.

Figure 1.1 shows a taxonomy that represents some of the features of the proposed taxonomies. This
taxonomy is intended to classify most of the recent architectures, but is not intended to represent a
complete characterization of all parallel architectures.
Figure 1.1. Classification of parallel processing architectures.

As shown in Figure 1.1, the MIMD class of computers is further divided into four types of parallel
machines: multiprocessors, multicomputers, multi-multiprocessors, and data flow machines. For the SIMD
class, it should be noted that there is only one type, called array processors. The MISD class of machines is
divided into two types of architectures: pipelined vector processors and systolic arrays. The remaining
parallel architectures are grouped under two classes: hybrid machines and special-purpose processors.
Each of these architectures is explained next.

The multiprocessor can be viewed as a parallel computer consisting of several interconnected processors
that can share a memory system. The processors can be set up so that each is running a different part of a
program or so that they are all running different programs simultaneously. A block diagram of this
architecture is shown in Figure 1.2. As shown, a multiprocessor generally consists of n processors and m
memory modules (for some n>1 and m>0). The processors are denoted as P1, P2, ..., and Pn, and memory
modules as M1, M2, ..., and Mm. The interconnection network (IN) connects each processor to some subset
of the memory modules. A transfer instruction causes data to be moved from each processor to the
memory to which it is connected. To pass data between two processors, a programmed sequence of data
transfers, which moves the data through intermediary memories and processors, must be executed.

Figure 1.2 Block diagram of a multiprocessor.

In contrast to the multiprocessor, the multicomputer can be viewed as a parallel computer in which each
processor has its own local memory. In multicomputers the main memory is privately distributed among
the processors. This means that a processor only has direct access to its local memory and cannot address
the local memories of other processors. This local, private addressability is an important characteristic that
distinguishes multicomputers from multiprocessors. A block diagram of this architecture is shown in
Figure 1.3. In this figure, there are n processing nodes (PNs), and each PN consists of a processor and a
local memory. The interconnection network connects each PN to some subset of the other PNs. A transfer
instruction causes data to be moved from each PN to one of the PNs to which it is connected. To move
data between two PNs that cannot be directly connected by the interconnection network, the data must be
passed through intermediary PNs by executing a sequence of data transfers.

Figure 1.3 Block diagram of a multicomputer.

The multi-multiprocessor combines the desired features of multiprocessors and multicomputers. It can be
viewed as a multicomputer in which each processing node is a multiprocessor.

In the data flow architecture an instruction is ready for execution when data for its operands have been
made available. Data availability is achieved by channeling results from previously executed instructions
into the operands of waiting instructions. This channeling forms a flow of data, triggering instructions to
be executed. Thus instruction execution avoids the controlled program counter type of flow found in the
von Neumann machine.

Data flow instructions are purely self-contained; that is, they do not address variables in a global shared
memory. Rather, they carry the values of variables with themselves. In a data flow machine, the execution
of an instruction does not affect other instructions ready for execution. In this way, several ready
instructions may be executed simultaneously, thus leading to the possibility of a highly concurrent
computation.

Figure 1.4 is a block diagram of a data flow machine. Instructions, together with their operands, are kept in
the instruction and data memory (I&D). Whenever an instruction is ready for execution, it is sent to one of
the processing elements (PEs) through the arbitration network. Each PE is a simple processor with limited
local storage. The PE, upon receiving an instruction, computes the required operation and sends the result
through the distribution network to the destination in the memory.

Figure 1.4 Block diagram of a data flow machine.

Figure 1.5 represents the generic structure of an array processor. An array processor consists of a set of
processing nodes (PNs) and a scalar processor that are operating under a centralized control unit. The
control unit fetches and decodes instructions from the main memory and then sends them either to the
scalar processor or the processing nodes, depending on their type. If a fetched instruction is a scalar
instruction, it is sent to the scalar processor; otherwise, it is broadcast to all the PNs. All the PNs execute
the same instruction simultaneously on different data stored in their local memories. Therefore, an array
processor requires just one program to control all the PNs in the system, making it unnecessary to duplicate
program codes at each PN. For example, an array processor can be defined in terms of a grid in which each
intersection represents a PN and the lines between intersections are communication paths. Each PN in the
array can send (receive) data to (from) the four surrounding PNs. A processor, known as a control unit,
handles the decisions on what operation the PNs are to do during each processing cycle, as well as data
transfer between the PNs.

Figure 1.5. Block diagram of an array processor.

The idea behind an array processor is to exploit parallelism in a given problem's data set rather than to
parallelize the problem's sequence of instruction execution. Parallel computation is realized by assigning
each processor to a data partition. If the data set is a vector, then a partition would simply be a vector
element. Array processors increase performance by operating on all data partitions simultaneously. They
are able to perform arithmetic or logical operations on vectors. For this reason, they are also referred to as
vector processors.

A pipelined vector processor is able to process vector operands (streams of continuous data) effectively.
This is the primary difference between an array or vector processor and a pipelined vector processor. Array
processors are instruction driven, while pipelined vector processors are driven by streams of continuous
data. Figure 1.6 represents the basic structure of a pipelined vector processor. There are two main
processors: a scalar processor and a vector processor. Both rely on a separate control unit to provide
instructions to execute. The vector processor handles execution of vector instructions by using pipelines,
and the scalar processor deals with the execution of scalar instructions. The control unit fetches and
decodes instructions from the main memory, and then sends them either to scalar processor or vector
processor, depending on their type.
Figure 1.6. Block diagram of a pipelined vector processor.

Pipelined vector processors make use of several memory modules to supply the pipelines with a continuous
stream of data. Often, a vectorizing compiler is used to arrange the data into a stream that can then be used
by the hardware.

Figure 1.7 represents a generic structure of a systolic array. In a systolic array there are a large number of
identical processing elements (PEs). Each PE has limited local storage, and in order not to restrict the
number of PEs placed in an array, each PE is only allowed to be connected to neighboring PEs through
interconnection networks. Thus, all PE's are arranged in a well organized pipelined structure such as a
linear or two-dimensional array. In a systolic array the data items and/or partial results flow through the
PEs during execution time consisting of several processing cycles. At each processing cycle, some of the
PEs perform the same relatively simple operation (like multiplication and addition) on their data items, and
send these items and/or partial results to other neighboring PEs.

Figure 1.7. Block diagram of a systolic array.

Hybrid architectures incorporate features of different architectures to provide better performance for
parallel computations. In general, there are two types of parallelism for performing parallel computations:
control parallelism and data parallelism. In control parallelism two or more operations are performed
simultaneously on different processors. In data parallelism the same operation is performed on many data
partitions by many processors simultaneously. MIMD machines are ideal for implementation of control
parallelism. They are suited for problems which require different operations to be performed on separate
data simultaneously. In an MIMD computer, each processor independently executes its own sequence of
instructions. On the other hand, SIMD machines are ideal for implementation of data parallelism. They are
suited for problems in which the same operation can be performed on different portions of the data
simultaneously. MISD machines are also suited for data parallelism. They support vector processing
through pipeline design.

In practice, the greatest rewards have come from data parallelism. This is because data parallelism exploits
parallelism in proportion to the quantity of data involved in the computation. However, sometimes it is
impossible to exploit fully the data parallelism inherent in many application programs, and so it becomes
necessary to use both control and data parallelism. For example, some application programs may perform
best when divided into subparts where each subpart makes use of data parallelism and all subparts together
make use of control parallelism in the form of a pipeline. One group of processors gather data and perform
some preliminary computations. They then pass their result to a second group of processors that do more
intense computations on the result. The second group then passes their result to a third group of processors,
where the final result is obtained. Thus, a parallel computer that incorporates features of both MIMD and
SIMD (or MISD) architectures is able to solve a broad range of problems effectively.

An example of a special purpose device is an artificial neural network (ANN). Artificial neural networks
consist of a large number of processing elements operating in parallel. They are promising architectures for
solving some of the problems that the von Neumann computer performs poorly, such as emulating natural
information and recognizing patterns. These problems require enormous amounts of processing to achieve
human-like performance. ANNs utilize one technique for obtaining the processing power required: using
large numbers of processing elements operating in parallel. They are capable of learning, adaptive to
changing environments, and able to cope with serious disruptions.

Figure 1.8 represents a generic structure of an artificial neural network. Each PE mimics some of the
characteristics of the biological neuron. It has a set of inputs and one or more outputs. To each input a
numerical weight is assigned. This weight is analogous to the synaptic strength of a biological neuron. All
the inputs of a PE are multiplied by their weights and then are summed to determine the activation level of
the neuron. Once the activation level is determined, a function, referred to as activation function, is applied
to produce the output signal. The combined outputs from a preceding layer become the inputs for the next
layer where they are again summed and evaluated. This process is repeated until the network has been
traversed and some decision is reached.

Figure 1.8. Block diagram of an artificial neural network.

Unlike von Neumann design where the primary element of computation is processor, in ANNs is the
connectivity between the PEs. For a given problem, we would like to determine the correct values for the
weights in order the network be able to perform necessary computation. Often, finding the proper values
for weights is done by iterative adjustment of the weights in a manner to improve network performance.
The rule of adjustment of the weights is referred to as learning rule, and the whole process of obtaining the
proper weights is called learning.

Another example of a special purpose device results from the design of a processor based on fuzzy logic.
Fuzzy logic is concerned with formal principles of approximate reasoning, while classical two-valued logic
(true/false) is concerned with formal principles of reasoning. Fuzzy logic attempts to deal effectively with
the complexity of human cognitive processes and it overcomes some of the inconveniences associated with
classical two-valued logic which tend not to reflect true human cognitive processes. It is making its way
through many applications ranging from home appliances to decision support systems. Although software
implementation of fuzzy logic in itself provides good results for some applications, dedicated fuzzy
processors, called fuzzy logic accelerators, are required for implementing high-performance applications.

1.3 Performance and Quality Measurements

Performance of a computer refers to its effective speed and its hardware/software reliability. In general, it
is unreasonable to expect that a single number could characterize performance. This is because
performance of a computer depends on the interactions of a variety of its components, and the fact that
different users are interested in different aspects of a computer's ability,
One of the measurements that are commonly used to represent performance of a computer is MIPS (million
instructions per second). The notion MIPS represents the speed of a computer by indicating the number of
"average instructions" that it can execute per second [SER_86]. To understand the meaning of "average
instruction", let's consider the inverse of MIPS measure, i.e. execution time of an average instruction. The
execution time of an average instruction can be calculated by using frequency and execution time for each
instruction class. By tracing execution of a large number of benchmark programs, it is possible to
determine how often an instruction is likely to be used in a program. As an example, let's assume that
Figure 1.9 represents the frequency of instructions that occur in a program. Note that in this figure, the
execution time of the instructions of each class is represented in terms of cycles per instruction (CPI). The
CPI denotes the number of clock cycles that a processor requires to execute a particular instruction.
Different processors may require different number of clock cycles to execute the same type of instruction.
Assuming a clock cycle takes t nanoseconds, the execution time of an instruction can be expressed as CPI*t
nanoseconds. Now, considering Figure 1.9, the execution time of an average instruction can be represented
as:

S IFi*CPIi*t, where i is an instruction class.

all i
Thus:
1
MIPS =_____________________________ * 1000.
S IFi*CPIi*t

In the above expression, a reasonable MIPS rating is obtained by finding the average execution time of
each class of instructions and weighting that average by how often each class of instructions is used.

Figure 1.9. An example for calculating MIPS rate.

Although MIPS rating can give us a rough idea of how fast a computer can operate, it is not a good
representative for computers that perform scientific and engineering computation such as vector processors.
For such computers is important to measure the number of floating-point operations that they can execute
per second. To indicate such a number, FLOPS (floating-point operations per second) notation is often
used. Mega FLOPS (MFLOPS) stands for million floating-point operations per second, and giga FLOPS
(GFLOPS) stands for billions of floating-point operations per second.

MIPS and FLOPS figures are useful for comparing members of the same architectural family. They are not
a good representative for comparing computers with different instruction sets and different clock cycles.
This is because programs may be translated into different number of instructions on different computers.
Besides MIPS and FLOPS, often other measurements are used in order to have a better picture of the
system. The most commonly used are: throughput, utilization, response time, memory bandwidth, memory
access time, and memory size.

Throughput of a processor is a measure that indicates the number of programs (tasks or requests) the
processor can execute per unit of time.

Utilization of a processor refers to the fraction of time the processor is busy executing programs. It is the
ratio of busy time and total elapsed time over a given period.

Response time is the time interval between the time a request is issued for service and the time the service
is completed. Sometimes response time is referred to as turnaround time.

Memory bandwidth indicates the number of memory words that can be accessed per unit time.

Memory access time is the average time that takes the processor to access the memory, usually expressed in
terms of nanoseconds (ns).

Memory size indicates capacity of the memory, usually expressed in terms of megabytes (Mbytes). It is an
indication of the volume of data that the memory can hold.

In addition to the above performance measurements, there are a number of quality factors that have also
influence over the success of a computer. Some of these factors are: generality, ease of use, expandability,
and compatibility.

Generality is a measure that determines the range of applications for an architecture. Some architectures are
good for scientific purposes and some good for business applications. It is more marketable when the
architecture supports variety of applications.

Ease of Use is a measure of how easy is for the system programmer to develop software (such as: operating
system and compiler) for the architecture.

Expandability is a measure of how easy is to add to the capabilities of an architecture, such as, processors,
memory, I/O devices.

Compatibility is a measure of how compatible the architecture is with previous computers of the same
family.

Reliability is a measure that indicates the probability of faults or the mean time between errors.

The above measures and properties are usually used to characterize capability of computer systems. Every
year, these measures and properties are enhanced with better hardware/software technology, innovative
architectural features, and efficient resources management.

1.4 Outline of the Following Chapters

Chapter 2 describes the typical implementation techniques used in von Neumann machines. The main
elements of a datapath as well as the hardwired and microprogramming techniques for implementing
control functions are discussed. Next, a hierarchical memory system is presented. The architectures of a
memory cell, interleaved memory, an associative memory, and a cache memory, are given. Virtual
memory is also discussed. Finally, interrupts and exception events are addressed.

Chapter 3 details the various types of pipelined processors in terms of their advantages and disadvantages
based on such criteria as processor overhead and implementation costs. Instruction pipelining and
arithmetic pipelining along with methods for maximizing the utilization of a pipeline are discussed.
Chapter 4 discusses the properties of RISC and CISC architectures. In addition, the main elements of
several microprocessors are explained.

Chapter 5 deals with several aspects of the interconnection networks used in modern (and theoretical)
computers. Starting with basic definitions and terms relative to networks in general, the coverage proceeds
to static networks, their different types and how they function. Next, several dynamic networks are
analyzed. In this context, the properties of non-blocking, rearrangeable, and blocking networks are
mentioned. Some elements of network designs are also explored to give the reader an understanding of
their complexity.

Chapter 6 details the architectures of multiprocessors, multicomputers, and multi-multiprocessors. To

present some of the most common interconnections used, the architectures of some state of the art parallel
computers are discussed and compared.

Chapter 7 discusses the issues involved in parallel programming and development of parallel algorithms for
multiprocessors and multicomputers. Various approaches to developing a parallel algorithm are explained.
Algorithm structures such as synchronous structure, asynchronous structure, and pipeline structure are
described. A few terms related to performance measurement of parallel algorithms are presented. Finally,
examples of parallel algorithms illustrating different structures are given.

Chapter 8 describes the structure of two parallel architectures: data flow machines and systolic arrays. For
each class of architectures various design methodologies represented. A general method is given for
mapping an algorithm to a systolic array.

Chapter 9 examines the neuron together with the dynamics of neural processing, and surveys some of the
well known proposed artificial neural networks. Also, it describes the basic features of the multiple-valued
logic. Finally, it explains the use of fuzzy logic in control systems and discusses an architecture for this
theory.