PRELIMINARY TECHNICAL DATA

a Energy Metering IC
with Pulse Output
Preliminary Technical Data ADE7755*
FEATURES The ADE7755 is a high accuracy electrical energy measurement
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036 IC. The part specifications surpass the accuracy requirements as
Less than 0.1% Error over a Dynamic Range of quoted in the IEC1036 standard. See Analog Devices Appli-
500 to 1 cation Note AN-559 for a description of an IEC1036 watt-hour
The ADE7755 Supplies Average Real Power on the meter reference design based on the AD7755.
Frequency Outputs F1 and F2 The only analog circuitry used in the ADE7755 is in the ADCs
The High-Frequency Output CF Is Intended for and reference circuit. All other signal processing (e.g., multipli-
Calibration and Supplies Instantaneous Real Power cation and filtering) is carried out in the digital domain. This
Pin Compatible with AD7755 with Synchronous CF and approach provides superior stability and accuracy over extremes
F1/F2 Outputs in environmental conditions and over time.
The Logic Output REVP Can Be Used to Indicate a
Potential Miswiring or Negative Power The ADE7755 supplies average real power information on the
Direct Drive for Electromechanical Counters and low-frequency outputs F1 and F2. These logic outputs may be
Two Phase Stepper Motors (F1 and F2) used to directly drive an electromechanical counter or interface
A PGA in the Current Channel Allows the Use of Small to an MCU. The CF logic output gives instantaneous real power
Values of Shunt and Burden Resistance information. This output is intended to be used for calibration
Proprietary ADCs and DSP Provide High Accuracy over purposes or for interfacing to an MCU.
Large Variations in Environmental Conditions and The ADE7755 includes a power supply monitoring circuit on the
Time AVDD supply pin. The ADE7755 will remain in a reset condition
On-Chip Power Supply Monitoring until the supply voltage on AVDD reaches 4 V. If the supply falls
On-Chip Creep Protection (No Load Threshold) below 4 V, the ADE7755 will also be reset and no pulses will be
On-Chip Reference 2.5 V  8% (30 ppm/C Typical) issued on F1, F2, and CF.
with External Overdrive Capability
Internal phase matching circuitry ensures that the voltage and
Single 5 V Supply, Low Power (15 mW Typical)
current channels are phase matched whether the HPF in Chan-
Low Cost CMOS Process
nel 1 is on or off. An internal no-load threshold ensures that the
GENERAL DESCRIPTION ADE7755 does not exhibit any creep when there is no load.
The ADE7755 is pin compatible with the AD7755. The only The ADE7755 is available in a 24-lead SSOP package.
difference between the ADE7755 and the AD7755 is that the
ADE7755 features a synchronous CF and F1/F2 outputs under
all load conditions.

FUNCTIONAL BLOCK DIAGRAM

G0 G1 AVDD AGND AC/DC DVDD DGND

ADE7755
POWER
SUPPLY MONITOR
PHASE SIGNAL
CORRECTION PROCESSING
V1P ...110101... BLOCK
ADC 
V1N PGA HPF LPF
1, 2, 8, 16
MULTIPLIER
V2P ...11011001...
ADC
V2N
DIGITAL-TO-FREQUENCY
CONVERTER RESET
2.5V 4k

REFERENCE

REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2

*U.S. Patents 5,745,323, 5,760,617, 5,862,069, and 5,872,469.

REV. PrA
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 2002

This datasheet has been downloaded from http://www.digchip.com at this page

 PRELIMINARY TECHNICAL DATA
(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference,
ADE7755SPECIFICATIONS CLKIN = 3.58 MHz, T MIN to TMAX = 40C to +85C.)

Parameter Specifications Unit Test Conditions/Comments

1, 2
ACCURACY
Measurement Error1 on Channel 1 Channel 2 with Full-Scale Signal ( 660 mV), 25C
Gain = 1 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 2 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 8 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 16 0.1 % Reading typ Over a Dynamic Range 500 to 1
Phase Error1 Between Channels Line Frequency = 45 Hz to 65 Hz
V1 Phase Lead 37
(PF = 0.8 Capacitive) 0.1 Degrees() max AC/DC = 0 and AC/DC = 1
V1 Phase Lag 60
(PF = 0.5 Inductive) 0.1 Degrees() max AC/DC = 0 and AC/DC = 1
AC Power Supply Rejection 1 AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
Output Frequency Variation (CF) 0.2 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz
Ripple on AVDD of 200 mV rms @ 100 Hz
DC Power Supply Rejection1 AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
Output Frequency Variation (CF) 0.3 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
AVDD = DVDD = 5 V 250 mV
ANALOG INPUTS See Analog Inputs section
Maximum Signal Levels 1 V max V1P, V1N, V2N, and V2P to AGND
Input Impedance (DC) 390 k min CLKIN = 3.58 MHz
Bandwidth (3 dB) 14 kHz typ CLKIN/256, CLKIN = 3.58 MHz
ADC Offset Error1, 2 25 mV max Gain = 1, See Terminology and Performance Graphs
Gain Error1 7 % Ideal typ External 2.5 V Reference, Gain = 1
V1 = 470 mV dc, V2 = 660 mV dc
Gain Error Match1 0.2 % Ideal typ External 2.5 V Reference
REFERENCE INPUT
REFIN/OUT Input Voltage Range 2.7 V max 2.5 V + 8%
2.3 V min 2.5 V 8%
Input Impedance 3.2 k min
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.5 V
Reference Error 200 mV max
Temperature Coefficient 30 ppm/C typ
ppm/C max
CLKIN Note All Specifications for CLKIN of 3.58 MHz
Input Clock Frequency 4 MHz max
1 MHz min
LOGIC INPUTS3
SCF, S0, S1, AC/DC,
RESET, G0, and G1
Input High Voltage, VINH 2.4 V min DVDD = 5 V 5%
Input Low Voltage, VINL 0.8 V max DVDD = 5 V 5%
Input Current, IIN 3 A max Typically 10 nA, VIN = 0 V to DVDD
Input Capacitance, CIN 10 pF max
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH ISOURCE = 10 mA
4.5 V min DVDD = 5 V
Output Low Voltage, VOL ISINK = 10 mA
0.5 V max DVDD = 5 V
CF and REVP
Output High Voltage, VOH ISOURCE = 5 mA
4 V min DVDD = 5 V
Output Low Voltage, VOL ISINK = 5 mA
0.5 V max DVDD = 5 V

2 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
Parameter Specifications Unit Test Conditions/Comments
POWER SUPPLY For Specified Performance
AVDD 4.75 V min 5 V 5%
5.25 V max 5 V + 5%
DVDD 4.75 V min 5 V 5%
5.25 V max 5 V + 5%
AIDD 3 mA max Typically 2 mA
DIDD 2.5 mA max Typically 1.5 mA
NOTES
1
See Terminology section for explanation of specifications.
2
See Plots in Typical Performance Graphs.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.

(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz, TMIN to
TIMING CHARACTERISTICS1, 2 T MAX = 40C to +85C.)

Parameter Specifications Unit Test Conditions/Comments

3
t1 275 ms F1 and F2 Pulsewidth (Logic Low)
t2 See Table III sec Output Pulse Period. See Transfer Function section.
t3 1/2 t2 sec Time between F1 Falling Edge and F2 Falling Edge
t43, 4 90 ms CF Pulsewidth (Logic High)
t5 See Table IV sec CF Pulse Period. See Transfer Function section.
t6 CLKIN/4 sec Minimum Time between F1 and F2 Pulse
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.
4
The CF pulse is always 18 s in the high-frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* Storage Temperature Range . . . . . . . . . . . . 65C to +150C

(TA = 25C unless otherwise noted.) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V 24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112C/W
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Lead Temperature, Soldering
Analog Input Voltage to AGND Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215C
V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . 6 V to +6 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
Reference Input Voltage to AGND . . 0.3 V to AVDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause perma-
Digital Input Voltage to DGND . . . 0.3 V to DVDD + 0.3 V nent damage to the device. This is a stress rating only; functional operation of the
Digital Output Voltage to DGND . . 0.3 V to DVDD + 0.3 V device at these or any other conditions above those listed in the operational
Operating Temperature Range sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C

ORDERING GUIDE

Model Package Description Package Options

ADE7755ARS Shrink Small Outline Package RS-24
EVAL-ADE7755EB ADE7755 Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the ADE7755 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. PrA 3
 PRELIMINARY TECHNICAL DATA
ADE7755
t1

F1
.t 6
.t 2

F2 .t 3

t4 .t 5

CF

Figure 1. Timing Diagram for Frequency Outputs

PIN CONFIGURATION

DVDD 1 24 F1

AC/DC 2 23 F2

AVDD 3 22 CF

NC 4 21 DGND

V1P 5 20 REVP
ADE7755
V1N 6
TOP VIEW 19 NC
V2N 7 (Not to Scale) 18 CLKOUT

V2P 8 17 CLKIN

RESET 9 16 G0

REFIN/OUT 10 15 G1

AGND 11 14 S0

SCF 12 13 S1

NC = NO CONNECT

4 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7755.
The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be
decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor.
2 AC/DC High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (Current Channel).
A logic one on this pin enables the HPF. The associated phase response of this filter has been inter-
nally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be enabled in
power metering applications.
3 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7755.
The supply should be maintained at 5 V 5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should
be decoupled to AGND with a 10 F capacitor in parallel with a ceramic 100 nF capacitor.
4, 19 NC No Connect
5, 6 V1P, V1N Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with
a maximum differential signal level of 470 mV for specified operation. Channel 1 also has a PGA,
and the gain selections are outlined in Table I. The maximum signal level at these pins is 1 V with
respect to AGND. Both inputs have internal ESD protection circuitry. An overvoltage of 6 V can be
sustained on these inputs without risk of permanent damage.
7, 8 V2N, V2P Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is 660 mV for specified operation. The maxi-
mum signal level at these pins is 1 V with respect to AGND. Both inputs have internal ESD
protection circuitry, and an overvoltage of 6 V can also be sustained on these inputs without risk of
permanent damage.
9 RESET Reset Pin for the ADE7755. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the ADE7755 internal registers.
10 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V 8% and a typical temperature coefficient of 30 ppm/C. An external reference source may
also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F
ceramic capacitor and 100 nF ceramic capacitor.
11 AGND This provides the ground reference for the analog circuitry in the ADE7755, i.e., ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters and current and voltage transducers. For good
noise suppression, the analog ground plane should only connected to the digital ground plane at one
point. A star ground configuration will help to keep noisy digital currents away from the analog circuits.
12 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table IV shows how the calibration frequencies are selected.
13, 14 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Selecting
a Frequency for an Energy Meter Application section.
15, 16 G1, G0 These logic inputs are used to select one of four possible gains for Channel 1, i.e., V1. The possible
gains are 1, 2, 8, and 16. See Analog Input section.
17 CLKIN An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the ADE7755. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and
33 pF (ceramic) should be used with the gate oscillator circuit.
18 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the ADE7755. The CLKOUT Pin can drive one CMOS load when an external clock is supplied at
CLKIN or by the gate oscillator circuit.
20 REVP This logic output will go logic high when negative power is detected, i.e., when the phase angle between
the voltage and current signals is greater that 90. This output is not latched and will be reset when
positive power is once again detected. The output will go high or low at the same time as a pulse is
issued on CF.

REV. PrA 5
 PRELIMINARY TECHNICAL DATA
ADE7755
Pin No. Mnemonic Description
21 DGND This provides the ground reference for the digital circuitry in the ADE7755, i.e., multiplier, filters, and
digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The
digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and
digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane should
only be connected to the digital ground plane at one point only, e.g., a star ground.
22 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous real power informa-
tion. This output is intended to be used for calibration purposes. Also see SCF Pin description.
23, 24 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs
can be used to directly drive electromechanical counters and two phase stepper motors. See Transfer
Function section.

TERMINOLOGY ADC OFFSET ERROR

MEASUREMENT ERROR This refers to the dc offset associated with the analog inputs to
The error associated with the energy measurement made by the the ADCs. It means that with the analog inputs connected to
ADE7755 is defined by the following formula: AGND, the ADCs still see a small dc signal (offset). The offset
decreases with increasing gain in Channel V1. This specification
Energy Registered by the ADE7755 True Energy
Percentage Error = 100% is measured at a gain of 1. At a gain of 16, the dc offset is typi-
True Energy
cally less than 1 mV. However, when the HPF is switched on,
the offset is removed from the current channel and the power
PHASE ERROR BETWEEN CHANNELS
calculation is not affected by this offset.
The HPF (High-Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
GAIN ERROR
response between channels, a phase correction network is also
The gain error of the ADE7755 is defined as the difference between
placed in Channel 1. The phase correction network matches the
the measured output frequency (minus the offset) and the ideal
phase to within 0.1 over a range of 45 Hz to 65 Hz and 0.2
output frequency. It is measured with a gain of 1 in Channel V1.
over a range 40 Hz to 1 kHz. See Figures 4 and 5.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7755 transfer
POWER SUPPLY REJECTION
function (see Transfer Function section).
This quantifies the ADE7755 measurement error as a percent-
age of the reading when the power supplies are varied.
GAIN ERROR MATCH
For the ac PSR measurement, a reading at nominal supplies The gain error match is defined as the gain error (minus the off-
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced set) obtained when switching between a gain of 1 and a gain of 2,
onto the supplies and a second reading obtained under the same 8, or 16. It is expressed as a percentage of the output frequency
input signal levels. Any error introduced is expressed as a obtained under a gain of 1. This gives the gain error observed
percentage of the reading (see Measurement Error definition). when the gain selection is changed from 1 to 2, 8, or 16.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.

6 REV. PrA
 PRELIMINARY TECHNICAL DATA
Typical Performance CharacteristicsADE7755
0.5 0.5

0.4 40C 0.4

40C
0.3 0.3

0.2 0.2 PF = 1
GAIN = 16
0.1 0.1 ON-CHIP REFERENCE
% ERROR

% ERROR
+25C +25C
0.0 0.0

0.1 0.1
+85C
0.2 0.2 +85C
0.3 0.3
PF = 1
0.4 GAIN = 1 0.4
ON-CHIP REFERENCE
0.5 0.5
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Amps Amps

TPC 1. Error as a % of Reading (Gain = 1) TPC 4. Error as a % of Reading (Gain = 16)

0.5 0.6
PF = 0.5
40C GAIN = 1
0.4
ON-CHIP REFERENCE
0.4
0.3 40C PF = 0.5
0.2
0.2
0.1
% ERROR

% ERROR
+25C +25C PF = 1
0.0 0.0

0.1 +25C PF = 0.5

+85C 0.2
0.2
+85C PF = 0.5
0.3
0.4
PF = 1
0.4 GAIN = 2
ON-CHIP REFERENCE
0.5 0.6
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Amps Amps

TPC 2. Error as a % of Reading (Gain = 2) TPC 5. Error as a % of Reading (Gain = 1)

0.6 0.6
PF = 0.5
0.5 40C GAIN = 2
ON-CHIP REFERENCE
0.4
0.4 40C PF = 0.5

0.3
PF = 1 0.2
0.2 GAIN = 8
% ERROR

% ERROR

ON-CHIP REFERENCE +25C PF = 1

0.1 0.0
+25C
0.0
+25C PF = 0.5
0.2
0.1 +85C

0.2 +85C PF = 0.5

0.4
0.3

0.4 0.6
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Amps Amps

TPC 3. Error as a % of Reading (Gain = 8) TPC 6. Error as a % of Reading (Gain = 2)

REV. PrA 7
 PRELIMINARY TECHNICAL DATA
ADE7755
0.8 0.4
PF = 0.5
PF = 1
GAIN = 8
0.6 0.3 GAIN = 16
ON-CHIP REFERENCE
40C PF = 0.5 EXTERNAL REFERENCE
40C
0.4 0.2

0.2 0.1
% ERROR

% ERROR
+25C PF = 1 +25C
0.0 0.0

0.2 +25C PF = 0.5 0.1

+85C
0.4 0.2
+85C PF = 0.5
0.6 0.3

0.8 0.4
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Amps Amps

TPC 7. Error as a % of Reading (Gain = 8) TPC 10. Error as a % of Reading over Temperature
with an External Reference (Gain = 16)

0.4 0.8

0.2 40C PF = 0.5 0.6

PF = 1
0.0 0.4
+25C PF = 1
% ERROR

% ERROR

0.2 0.2
+25C PF = 0.5 PF = 0.5

0.4 0.0

+85C PF = 0.5
0.6 0.2

0.8 PF = 0.5 0.4

GAIN = 16
ON-CHIP REFERENCE
1.0 0.6
0.01 0.1 1 10 100 45 50 55 60 65 70 75
Amps FREQUENCY Hz

TPC 8. Error as a % of Reading (Gain = 16) TPC 11. Error as a % of Reading over Frequency

VDD

10F 100nF 100nF 10F

0.4 40A TO
40mA AVDD AC/DC DVDD U3 K7
PF = 1 NC F1
0.3 GAIN = 2 1k

EXTERNAL REFERENCE V1P F2
500
U1
33nF ADE7755 CF
0.2 1.5m

40C 10m
1k
REVP
V1N K8
NC PS2501-1
0.1 33nF 33pF
% ERROR

+25C 1k
CLKOUT

0.0 V2N Y1
3.58MHz 33pF
33nF CLKIN VDD
0.1 1M
G0
+85C V2P GAIN
33nF G1 SELECT 10k

220V 1k

0.2
S0
REFIN/OUT
0.3 S1
10F 100nF
SCF
0.4 RESET AGND DGND 10nF 10nF 10nF
0.01 0.1 1 10 100
Amps
NC = NO CONNECT
VDD

TPC 9. Error as a % of Reading over Temperature TPC 12. Test Circuit for Performance Curves
with an External Reference (Gain = 2)

8 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
16 30
DISTRIBUTION CHARACTERISTICS DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101 NUMBER POINTS: 101
14 MINIMUM: 9.78871 MINIMUM: 2.48959
MAXIMUM: 7.2939 GAIN = 1 25 MAXIMUM: 5.81126
MEAN: 1.73203 TEMPERATURE = 25C MEAN: 1.26847 GAIN = 8
12 STD. DEV: 3.61157 TEMPERATURE = 25C
STD. DEV: 1.57404
20
PHASE Degrees

PHASE Degrees
10

8 15

6
10
4

5
2

0 0
15 9 3 3 9 15 15 9 3 3 9 15
FREQUENCY Hz FREQUENCY Hz

TPC 13. Channel 1 Offset Distribution (Gain = 1) TPC 16. Channel 1 Offset Distribution (Gain = 8)

18 35
DISTRIBUTION GAIN = 2 DISTRIBUTION CHARACTERISTICS
CHARACTERISTICS TEMPERATURE = 25C NUMBER POINTS: 101
16
NUMBER POINTS: 101 30 MINIMUM: 1.96823
MINIMUM: 5.61779 MAXIMUM: 5.71177
14 MAXIMUM: 6.40821 MEAN: 1.48279 GAIN = 16
MEAN: 0.01746 STD. DEV: 1.47802 TEMPERATURE = 25C
25
12 STD. DEV: 2.35129
PHASE Degrees

10 PHASE Degrees 20

8 15

6
10
4
5
2

0 0
15 9 3 3 9 15 15 9 3 3 9 15
FREQUENCY Hz FREQUENCY Hz

TPC 14. Channel 1 Offset Distribution (Gain = 2) TPC 17. Channel 1 Offset Distribution (Gain = 16)

0.5 0.5

0.4 0.4
5.25V 5.25V
0.3 0.3

0.2 0.2

0.1 0.1
5V 5V
% ERROR

% ERROR

0 0

0.1 0.1

0.2 0.2
4.75V
4.75V
0.3 0.3

0.4 0.4

0.5 0.5

0.6 0.6
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Amps Amps

TPC 15. PSR with Internal Reference (Gain = 16) TPC 18. PSR with External Reference (Gain = 16)

REV. PrA 9
 PRELIMINARY TECHNICAL DATA
ADE7755
THEORY OF OPERATION the voltage by 60. If we assume the voltage and current wave-
The two ADCs digitize the voltage signals from the current and forms are sinusoidal, the real power component of the instanta-
voltage transducers. These ADCs are 16-bit second order neous power signal (i.e., the dc term) is given by:
sigma-delta with an oversampling rate of 900 kHz. This analog
V I
input structure greatly simplifies transducer interfacing by
providing a wide dynamic range for direct connection to the
2 cos 60

o
( )
transducer and also by simplifying the antialiasing filter design. This is the correct real power calculation.
A programmable gain stage in the current channel further facili-
tates easy transducer interfacing. A high-pass filter in the current INSTANTANEOUS INSTANTANEOUS
POWER SIGNAL REAL POWER SIGNAL
channel removes any dc component from the current signal.
This eliminates any inaccuracies in the real power calculation
due to offsets in the voltage or current signals (see HPF and
VI
Offset Effects section). 2

The real power calculation is derived from the instantaneous

power signal. The instantaneous power signal is generated by a 0V
direct multiplication of the current and voltage signals. In order CURRENT
to extract the real power component (i.e., the dc component), VOLTAGE
the instantaneous power signal is low-pass filtered. Figure 2
illustrates the instantaneous real power signal and shows how the INSTANTANEOUS INSTANTANEOUS
POWER SIGNAL REAL POWER SIGNAL
real power information can be extracted by low-pass filtering the
instantaneous power signal. This scheme correctly calculates real
power for nonsinusoidal current and voltage waveforms at all
VI
power factors. All signal processing is carried out in the digital cos(60)
2
domain for superior stability over temperature and time. 0V

DIGITAL-TO-
FREQUENCY VOLTAGE CURRENT
HPF
F1 60
CH1 PGA ADC

LPF F2

MULTIPLIER DIGITAL-TO-
Figure 3. DC Component of Instantaneous Power Signal
FREQUENCY Conveys Real Power Information PF < 1
CH2 ADC
 CF Nonsinusoidal Voltage and Current
The real power calculation method also holds true for nonsinu-
INSTANTANEOUS INSTANTANEOUS REAL soidal current and voltage waveforms. All voltage and current
POWER SIGNAL p(t) POWER SIGNAL waveforms in practical applications will have some harmonic
VI p(t) = i(t)v(t) content. Using the Fourier Transform, instantaneous voltage
WHERE:
VI
and current waveforms can be expressed in terms of their
v(t) = Vcos(t)
VI
i(t) = Icos(t) 2 harmonic content.
2 VI
p(t) =
2
{1+cos (2t)}

TIME
v(t ) = VO + 2 Vh sin(ht + h) (1)
h0

Figure 2. Signal Processing Block Diagram where:

v(t) is the instantaneous voltage
The low-frequency output of the ADE7755 is generated by VO is the average value
accumulating this real power information. This low frequency Vh is the rms value of voltage harmonic h
inherently means a long accumulation time between output and
pulses. The output frequency is therefore proportional to the h is the phase angle of the voltage harmonic
average real power. This average real power information can, in
turn, be accumulated (e.g., by a counter) to generate real energy
information. Because of its high output frequency and shorter i(t ) = IO + 2 Ih sin(ht + h) (2)
h0
integration time, the CF output is proportional to the instanta-
neous real power. This is useful for system calibration purposes where:
that would take place under steady load conditions. i(t) is the instantaneous current
Power Factor Considerations IO is the dc component
The method used to extract the real power information from the Ih is the rms value of current harmonic h
instantaneous power signal (i.e., by low-pass filtering) is still and
valid even when the voltage and current signals are not in phase. h is the phase angle of the current harmonic
Figure 3 displays the unity power factor condition and a DPF
(Displacement Power Factor) = 0.5, i.e., current signal lagging

10 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
Using Equations 1 and 2, the real power P can be expressed in Table I. Gain Selection for Channel 1
terms of its fundamental real power (P1) and harmonic real
power (PH). Maximum
G1 G0 Gain Differential Signal
P = P1 + PH
0 0 1 470 mV
where: 0 1 2 235 mV
P1 = V1 I1 cos 1 1 0 8 60 mV
(3) 1 1 16 30 mV
1 = 1 1
Channel V2 (Voltage Channel )
and: The output of the line voltage transducer is connected to the
ADE7755 at this analog input. Channel V2 is a fully differential
PH = Vh Ih cos h
h 1 voltage input. The maximum peak differential signal on
(4)
h = h h Channel 2 is 660 mV. Figure 5 illustrates the maximum
signal levels that can be connected to the ADE7755 Channel 2.
As can be seen from Equation 4 above, a harmonic real power
component is generated for every harmonic, provided that har- V2

monic is present in both the voltage and current waveforms. +660mV

The power factor calculation has previously been shown to be V2P
accurate in the case of a pure sinusoid; therefore the harmonic DIFFERENTIAL INPUT
660mV MAX PEAK V2
real power must also correctly account for the power factor V2N
VCM
since it is made up of a series of pure sinusoids. COMMON-MODE VCM
100mV MAX
Note that the input bandwidth of the analog inputs is 14 kHz
AGND
with a master clock frequency of 3.5795 MHz. 660mV

ANALOG INPUTS Figure 5. Maximum Signal Levels, Channel 2

Channel V1 (Current Channel )
The voltage output from the current transducer is connected to
Channel 2 must be driven from a common-mode voltage, i.e.,
the ADE7755 here. Channel V1 is a fully differential voltage
the differential voltage signal on the input must be referenced to
input. V1P is the positive input with respect to V1N.
a common mode (usually AGND). The analog inputs of the
The maximum peak differential signal on Channel 1 should be ADE7755 can be driven with common-mode voltages of up to
less than 470 mV (330 mV rms for a pure sinusoidal signal) for 100 mV with respect to AGND. However, best results are
specified operation. Note that Channel 1 has a programmable achieved using a common mode equal to AGND.
gain amplifier (PGA) with user selectable gain of 1, 2, 8, or 16
Typical Connection Diagrams
(see Table I). These gains facilitate easy transducer interfacing.
Figure 6 shows a typical connection diagram for Channel V1. A
V1
CT (current transformer) is the current transducer selected for this
example. Notice the common-mode voltage for Channel 1 is
+470mV AGND and is derived by center tapping the burden resistor to
V1P
AGND. This provides the complementary analog input signals
DIFFERENTIAL INPUT
470mV MAX PEAK V1 V1N
for V1P and V1N. The CT turns ratio and burden resistor Rb
VCM are selected to give a peak differential voltage of 470 mV/Gain
COMMON-MODE
100mV MAX
VCM at maximum load.
AGND
470mV Rf
CT V1P

Cf
470mV V1N
Figure 4. Maximum Signal Levels, Channel 1, Gain = 1 Rb
GAIN

The diagram in Figure 4 illustrates the maximum signal levels IP AGND Rf Cf

on V1P and V1N. The maximum differential voltage is 470 mV PHASE NEUTRAL
divided by the gain selection. The differential voltage signal on
the inputs must be referenced to a common mode, e.g., AGND. Figure 6. Typical Connection for Channel 1
The maximum common-mode signal is 100 mV as shown in
Figure 4.

REV. PrA 11
 PRELIMINARY TECHNICAL DATA
ADE7755
Figure 7 shows two typical connections for Channel V2. The first HPF and Offset Effects
option uses a PT (potential transformer) to provide complete Figure 9 shows the effect of offsets on the real power calculation.
isolation from the power line. In the second option, the An offset on Channel 1 and Channel 2 will contribute a dc
ADE7755 is biased around the neutral wire, and a resistor divider component after multiplication. Since the dc component is
provides a voltage signal that is proportional to the line voltage. extracted by the LPF, it will accumulate as real power. If not
Adjusting the ratio of Ra, Rb, and VR is also a convenient way of properly filtered, dc offsets will introduce error to the energy
carrying out a gain calibration on the meter. accumulation. This problem is easily avoided by enabling the
HPF (i.e., Pin AC/DC is set logic high) in Channel 1. By
CT Rf V2P removing the offset from at least one channel, no error compo-
Cf
nent can be generated at dc by the multiplication. Error terms
660mV
V2N at cos(t) are removed by the LPF and the digital-to-frequency
Rf conversion (see Digital-to-Frequency Conversion section).
Cf

{V cos (t) + V } {I cos ( t) + I } =

AGND
PHASE NEUTRAL OS OS

V I
( ) ( )
Ra* Cf
+ VOS IOS + VOS I cos t + IOS Vcos t
Rb*
2
660mV V2P
V I
VR*
Rf V2N
+
2
cos 2t ( )
Cf
PHASE NEUTRAL *Ra >> Rb + VR
*Rb + VR = Rf

Figure 7. Typical Connections for Channel 2 DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL
VOS  I OS POWER CALCULATION
POWER SUPPLY MONITOR VI
The ADE7755 contains an on-chip power supply monitor. The 2
Analog Supply (AVDD) is continuously monitored by the ADE7755.
If the supply is less than 4 V 5%, the ADE7755 will be reset.
This is useful to ensure correct device start-up at power-up and
IOS  V
power-down. The power supply monitor has built in hysteresis
VOS  I
and filtering. This gives a high degree of immunity to false trig-
gering due to noisy supplies. 0  2
FREQUENCY RAD/S
In Figure 8, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is about 5%. The power supply and Figure 9. Effect of Channel Offset on the Real Power
decoupling for the part should be such that the ripple at AVDD Calculation
does not exceed 5 V 5% as specified for normal operation. The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
AVDD
activated. Figures 10 and 11 show the phase error between chan-
5V nels with the compensation network activated. The ADE7755 is
4V
phase compensated up to 1 kHz as shown. This will ensure correct
active harmonic power calculation even at low power factors.

0V
TIME

INTERNAL
RESET RESET ACTIVE RESET

Figure 8. On-Chip Power Supply Monitor

12 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
0.30 Figure 12 shows the instantaneous real power signal at the
output of the CPF, which still contains a significant amount of
0.25
instantaneous power information, i.e., cos (2 t). This signal is
0.20
then passed to the digital-to-frequency converter where it is
integrated (accumulated) over time to produce an output frequency.
PHASE Degrees

0.15 This accumulation of the signal will suppress or average out any
non dc components in the instantaneous real power signal. The
0.10
average value of a sinusoidal signal is zero. Hence, the frequency
0.05 generated by the ADE7755 is proportional to the average real
power. Figure 12 shows the digital-to-frequency conversion for
0 steady load conditions, i.e., constant voltage and current.
0.05
F1

FREQUENCY
0.10 DIGITAL-TO-
0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY
FREQUENCY Hz
F1

V F2
Figure 10. Phase Error between Channels (0 Hz to 1 kHz) LPF
TIME
MULTIPLIER
DIGITAL-TO-
FREQUENCY FOUT

FREQUENCY
0.30 I
 CF

0.25 LPF TO EXTRACT

REAL POWER
VI (DC TERM)
0.20 2
TIME
PHASE Degrees

0.15 cos(2t)
ATTENUATED BY LPF

0.10

0.05 
0 2
FREQUENCY RAD/S
0
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
0.05

0.10
Figure 12. Real Power-to-Frequency Conversion
40 45 50 55 60 65 70
FREQUENCY Hz
As can be seen in the diagram, the frequency output CF is seen
Figure 11. Phase Error between Channels (40 Hz to 70 Hz) to vary over time, even under steady load conditions. This
frequency variation is primarily due to the cos (2 t) component
DIGITAL-TO-FREQUENCY CONVERSION in the instantaneous real power signal. The output frequency on
As previously described, the digital output of the low-pass filter CF can be up to 2048 times higher than the frequency on F1
after multiplication contains the real power information. How- and F2. This higher output frequency is generated by accumu-
ever, since this LPF is not an ideal brick wall filter implemen- lating the instantaneous real power signal over a much shorter
tation, the output signal also contains attenuated components time while converting it to a frequency. This shorter accumula-
at the line frequency and its harmonics, i.e., cos(h t) where tion period means less averaging of the cos (2 t) component.
h = 1, 2, 3, and so on. As a consequence, some of this instantaneous power signal passes
through the digital-to-frequency conversion. This will not be a
The magnitude response of the filter is given by:
problem in the application. When CF is used for calibration
1 purposes, the frequency should be averaged by the frequency
| H ( f )| = (5)
1 + ( f / 8.9 Hz ) counter. This will remove any ripple. If CF is measuring energy,
e.g., in a microprocessor-based application, the CF output
For a line frequency of 50 Hz this would give an attenuation of should also be averaged to calculate power. Because the outputs
the 2w (100 Hz) component of approximately 22 dBs. The F1 and F2 operate at a much lower frequency, more averaging
dominating harmonic will be at twice the line frequency, i.e., of the instantaneous real power signal is carried out. The result
cos (2 t), and this is due to the instantaneous power signal. is a greatly attenuated sinusoidal content and a virtually ripple-
free frequency output.

REV. PrA 13
 PRELIMINARY TECHNICAL DATA
ADE7755
Interfacing the ADE7755 to a Microcontroller for Energy Power Measurement Considerations
Measurement Calculating and displaying power information will always have
The easiest way to interface the ADE7755 to a microcontroller some associated ripple that will depend on the integration period
is to use the CF high-frequency output with the output frequency used in the MCU to determine average power and also the load.
scaling set to 2048 F1, F2. This is done by setting SCF = 0 For example, at light loads, the output frequency may be 10 Hz.
and S0 = S1 = 1 (see Table IV). With full-scale ac signals on the With an integration period of two seconds, only about 20 pulses
analog inputs, the output frequency on CF will be approximately will be counted. The possibility of missing one pulse always exists,
5.5 kHz. Figure 13 illustrates one scheme that could be used to since the ADE7755 output frequency is running asynchronously
digitize the output frequency and carry out the necessary to the MCU timer. This would result in a one-in-twenty (or
averaging mentioned in the previous section. 5%) error in the power measurement.

CF TRANSFER FUNCTION
FREQUENCY
RIPPLE
Frequency Outputs F1 and F2
The ADE7755 calculates the product of two voltage signals (on
AVERAGE 10% Channel 1 and Channel 2) and then low-pass filters this product
FREQUENCY
to extract real power information. This real power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, e.g., 0.34 Hz maximum
TIME for ac signals with S0 = S1 = 0 (see Table III). This means that
the frequency at these outputs is generated from real power
MCU
information accumulated over a relatively long period of time.
ADE7755
COUNTER The result is an output frequency that is proportional to the
CF average real power. The averaging of the real power signal is
implicit to the digital-to-frequency conversion. The output
REVP* UP/DOWN
frequency or pulse rate is related to the input voltage signals by
the following equation.
TIMER
8.06 V 1 V 2 Gain F 1 4
Freq =
2
*REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR VREF
DIRECTION OF ENERGY FLOW IS NEEDED
where:
Figure 13. Interfacing the ADE7755 to an MCU
Freq = Output frequency on F1 and F2 (Hz)
As shown, the frequency output CF is connected to an MCU V1 = Differential rms voltage signal on Channel 1 (Volts)
counter or port. This will count the number of pulses in a given V2 = Differential rms voltage signal on Channel 2 (Volts)
integration time that is determined by an MCU internal timer.
Gain = 1, 2, 8, or 16, depending on the PGA gain selection
The average power proportional to the average frequency is
made using logic inputs G0 and G1
given by:
VREF = The reference voltage (2.5 V 8%) (Volts)
Counter
Average Frequency = Average Real Power = F14 = One of four possible frequencies selected by using the
Timer logic inputs S0 and S1see Table II
The energy consumed during an integration period is given by: Table II. F14 Frequency Selection

Counter S1 S0 F14 (Hz) XTAL/CLKIN*

Energy = Average Power Time = Time = Counter
Time 0 0 1.7 3.579 MHz/221
0 1 3.4 3.579 MHz/220
For the purpose of calibration, this integration time can be 10 to 1 0 6.8 3.579 MHz/219
20 seconds to accumulate enough pulses to ensure correct aver- 1 1 13.6 3.579 MHz/218
aging of the frequency. In normal operation, the integration time
can be reduced to one or two seconds depending, for example, NOTE
*F14 is a binary fraction of the master clock and therefore will vary if the speci-
on the required undate rate of a display. With shorter integra- fied CLKIN frequency is altered.
tion times on the MCU, the amount of energy in each update
may still have some small amount of ripple, even under steady
load conditions. However, over a minute or more, the measured
energy will have no ripple.

14 REV. PrA
 PRELIMINARY TECHNICAL DATA
ADE7755
Example 1 pulse rate, the frequency at this logic output is proportional to
Thus if full-scale differential dc voltages of +470 mV and 660 mV the instantaneous real power. As is the case with F1 and F2, the
are applied to V1 and V2 respectively (470 mV is the maximum frequency is derived from the output of the low-pass filter after
differential voltage that can be connected to Channel 1, and multiplication. However, because the output frequency is high,
660 mV is the maximum differential voltage that can be connected this real power information is accumulated over a much shorter
to Channel 2), the expected output frequency is calculated as time. Hence, less averaging is carried out in the digital-to-
follows: frequency conversion. With much less averaging of the real
power signal, the CF output is much more responsive to power
Gain = 1, G0 = G1 = 0
fluctuations (see Figure 2, signal processing block diagram).
F14 = 1.7 Hz, S0 = S1 = 0
V1 = +470 mV dc = 0.47 V (rms of dc = dc) Table IV. Maximum Output Frequency on CF
V2 = 660 mV dc = 0.66 V (rms of dc = |dc|) SCF S1 S0 F14 (Hz) CF Max for AC Signals (Hz)
VREF = 2.5 V (nominal reference value) 1 0 0 1.7 128 F1, F2 = 43.52
NOTE: If the on-chip reference is used, actual output frequencies 0 0 0 1.7 64 F1, F2 = 21.76
may vary from device to device due to reference tolerance of 8%. 1 0 1 3.4 64 F1, F2 = 43.52
0 0 1 3.4 32 F1, F2 = 21.76
8.06 0.47 0.66 1 1.7 1 1 0 6.8 32 F1, F2 = 43.52
Freq = = 0.68
2.52 0 1 0 6.8 16 F1, F2 = 21.76
Example 2 1 1 1 13.6 16 F1, F2 = 43.52
In this example, with ac voltages of 470 mV peak applied to 0 1 1 13.6 2048 F1, F2 = 5.57 kHz
V1 and 660 mV peak applied to V2, the expected output
frequency is calculated as follows: SELECTING A FREQUENCY FOR AN ENERGY METER
Gain = 1, G0 = G1 = 0 APPLICATION
As shown in Table II, the user can select one of four frequencies.
F14 = 1.7 Hz, S0 = S1 = 0
This frequency selection determines the maximum frequency on
V1 = rms of 470 mV peak ac = 0.47/2 volts F1 and F2. These outputs are intended to be used to drive the
V2 = rms of 660 mV peak ac = 0.66/2 volts energy register (electromechanical or other). Since only four
different output frequencies can be selected, the available fre-
VREF = 2.5 V (nominal reference value) quency selection has been optimized for a meter constant of
NOTE: If the on-chip reference is used, actual output frequencies 100 imp/kWhr with a maximum current of between 10 A and
may vary from device to device due to reference tolerance of 8%. 120 A. Table V shows the output frequency for several maxi-
mum currents (IMAX) with a line voltage of 220 V. In all cases
8.06 0.47 0.66 1 1.7
Freq = = 0.34 the meter constant is 100 imp/kWhr.
2 2 2.52
As can be seen from these two example calculations, the maxi- Table V. F1 and F2 Frequency at 100 imp/kWhr
mum output frequency for ac inputs is always half of that for dc
IMAX F1 and F2 (Hz)
input signals. Table III shows a complete listing of all maximum
output frequencies. 12.5 A 0.076
25 A 0.153
Table III. Maximum Output Frequency on F1 and F2 40 A 0.244
60 A 0.367
Max Frequency Max Frequency
80 A 0.489
S1 S0 for DC Inputs (Hz) for AC Inputs (Hz)
120 A 0.733
0 0 0.68 0.34
0 1 1.36 0.68
1 0 2.72 1.36 The F14 frequencies allow complete coverage of this range of
1 1 5.44 2.72 output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on Channel 2 (voltage) should
be set to half scale to allow for calibration of the meter constant.
Frequency Output CF The current channel should also be no more than half scale
The pulse output CF (Calibration Frequency) is intended for when the meter sees maximum load. This will allow over current
use during calibration. The output pulse rate on CF can be up signals and signals with high crest factors to be accommodated.
to 2048 times the pulse rate on F1 and F2. The lower the F14 Table VI shows the output frequency on F1 and F2 when both
frequency selected, the higher the CF scaling (except for the analog inputs are half scale. The frequencies listed in Table
high-frequency mode SCF = 0, S1 = S0 = 1). Table IV shows VI align very well with those listed in Table V for maximum load.
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high

REV. PrA 15
 PRELIMINARY TECHNICAL DATA
ADE7755
Table VI. F1 and F2 Frequency with Half-Scale AC Inputs The high-frequency CF output is intended to be used for com-
munications and calibration purposes. CF produces a 90 ms-wide
Frequency on F1 and F2 active high pulse (t4) at a frequency proportional to active
S1 S0 F14 CH1 and CH2 Half-Scale AC Inputs power. The CF output frequencies are given in Table IV. As in
0 0 1.7 0.085 Hz the case of F1 and F2, if the period of CF (t5) falls below 180 ms,
0 1 3.4 0.17 Hz the CF pulsewidth is set to half the period. For example, if the CF
1 0 6.8 0.34 Hz frequency is 20 Hz, the CF pulsewidth is 25 ms.
1 1 13.6 0.68 Hz NOTE: When the high-frequency mode is selected, (i.e., SCF = 0,
S1 = S0 = 1), the CF pulsewidth is fixed at 18 s. Therefore, t4 will
When selecting a suitable F14 frequency for a meter design, the always be 18 s, regardless of the output frequency on CF.
frequency output at IMAX (maximum load) with a meter constant
of 100 imp/kWhr should be compared with Column 4 of Table NO LOAD THRESHOLD
VI. The frequency that is closest in Table VI will determine the The ADE7755 also includes a no load threshold and start-
best choice of frequency (F14). For example, if a meter with a up current feature that will eliminate any creep effects in the
maximum current of 25 A is being designed, the output frequency meter. The ADE7755 is designed to issue a minimum output
on F1 and F2 with a meter constant of 100 imp/kWhr is 0.153 Hz frequency on all modes except when SCF = 0 and S1 = S0 = 1.
at 25 A and 220 V (from Table V). Looking at Table VI, the The no-load detection threshold is disabled on this output mode
closest frequency to 0.153 Hz in column four is 0.17 Hz. to accommodate specialized application of the ADE7755. Any
Therefore, F2 (3.4 Hzsee Table II) is selected for this design. load generating a frequency lower than this minimum frequency
Frequency Outputs will not cause a pulse to be issued on F1, F2, or CF. The mini-
Figure 1 shows a timing diagram for the various frequency outputs. mum output frequency is given as 0.0014% of the full-scale
The outputs F1 and F2 are the low-frequency outputs that can output frequency for each of the F14 frequency selections (see
be used to directly drive a stepper motor or electromechanical Table II). For example, an energy meter with a meter constant
impulse counter. The F1 and F2 outputs provide two alternat- of 100 imp/kWhr on F1 and F2 using F2 (3.4 Hz), the maximum
ing low going pulses. The pulsewidth (t1) is set at 275 ms and the output frequency at F1 or F2 would be 0.0014% of 3.4 Hz or
time between the falling edges of F1 and F2 (t3) is approxi- 4.76 105 Hz. This would be 3.05 103 Hz at CF (64 F1 Hz).
mately half the period of F1 (t2). If, however, the period of In this example, the no-load threshold is equivalent to 1.7 W of
F1 and F2 falls below 550 ms (1.81 Hz), the pulsewidth of F1 load or a start-up current of 8 mA at 220 V. IEC1036 states that
and F2 is set to half of their period. The maximum output fre- the meter must start up with a load current equal to or less than
quencies for F1 and F2 are shown in Table III. 0.4% Ib. For a 5A (Ib) meter, 0.4% Ib is equivalent to 20mA.
The start-up current of this design therefore satisfies the IEC
requirement. As illustrated from this example, the choice of
F1F4 and the ratio of the stepper motor display will determine
the start-up current.

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

24-Lead Shrink Small Outline Package

(RS-24)

0.328 (8.33)
0.318 (8.08)

24 13

0.311 (7.9) 0.212 (5.38)

0.301 (7.64) 0.205 (5.207)

1 12

0.078 (1.98) PIN 1 0.07 (1.78)

0.068 (1.73) 0.066 (1.67)

8
0.008 (0.203) 0.0256 0.015 (0.38)
SEATING 0.009 (0.229)
0
0.037 (0.94)
(0.65)
0.002 (0.050) BSC 0.010 (0.25) PLANE
0.005 (0.127) 0.022 (0.559)

16 REV. PrA