D. Cao, S. Jiang and F. Z.

Peng, "Optimal Design of a Multilevel Modular Capacitor-Clamped DCDC Converter," in IEEE Transactions on
Power Electronics, vol. 28, no. 8, pp. 3816-3826, Aug. 2013. doi: 10.1109/TPEL.2012.2231438
3816 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Optimal Design of a Multilevel Modular

Capacitor-Clamped DCDC Converter
Dong Cao, Member, IEEE, Shuai Jiang, Student Member, IEEE, and Fang Zheng Peng, Fellow, IEEE

AbstractMagnetic-less multilevel dcdc converters attract (above 250 C) except magnetic cores [2][5]. Therefore, the
much attention in automotive industry due to their small size, high magnetic-less multilevel switched-capacitor dcdc converters
efficiency, and high temperature operation features. A multilevel- attract much attention for automotive applications.
modular capacitor-clamped dcdc converter (MMCCC) is one of
the most promising topologies among them with simple control Since the 1970s, switched-capacitor dcdc converters have
and reduced switch current stress. This paper presents the opti- been investigated due to small size, lightweight, and good in-
mal design considerations for an MMCCC to achieve the highest tegration features for power supply on chip [6]. Conventional
efficiency and the smallest size. In order to design the converter switched-capacitor dcdc converters mainly concentrate on the
with the highest efficiency, the analytical power loss equation of an low power conversion area for portable electronic equipment ap-
MMCCC should be derived. By considering the stray inductance in
the circuit, the optimal design approach should be divided into two plications [7]. Due to the structure limitation, the output voltage
cases, overdamped case and underdamped case. The converter can fine regulation of the switched-capacitor dcdc converter is the
be designed to achieve high efficiency in both cases by varying cir- major challenge in these applications. Many methods have been
cuit parameters. If the circuit is designed in overdamped case, huge proposed to achieve the output voltage regulation, but the con-
electrolytic capacitor bank has to be used to achieve high efficiency, verter efficiency has been sacrificed. These proposed methods
which will increase the total converter size. If the circuit is designed
in underdamped case, small-size multilayer ceramic capacitor can could be used in low power conversion area [7][19], [46], [47].
be utilized due to the low capacitance requirement. Although rel- On the other hand, in order to achieve high efficiency, several
atively high switching frequency is required in underdamped case zero-current switching (ZCS) techniques by inserting a reso-
due to practical considerations, zero-current switching (ZCS) can nant inductor in the switched-capacitor circuits have been pro-
be achieved for all the switching devices which minimize the con- posed [20][24]. However, adding a relatively big magnetic core
verter switching loss. Therefore, the optimal design point of an
MMCCC with the smallest size and the highest efficiency should into the switched-capacitor circuits to achieve soft switching is
be selected at the underdamped case with ZCS for all the switches. a contradiction by itself. The small size, good integration, and
Simulation results are provided to validate the design. A prototype high temperature operation features of the switched-capacitor
of an MMCCC by using the proposed optimal design procedure circuits will be lost [25], [26].
is built. Experimental results of this optimal designed MMCCC In high power automotive applications, some other switched-
prototype are provided to demonstrate the validity of the proposed
method. capacitor circuits, or multilevel dcdc converters are proposed
[2], [27][31]. The power rating of these multilevel dcdc con-
Index TermsAutomotive, capacitor-clamp switched capacitor verters varies from 1 to 55 kW. In order to achieve a high
dcdc, multilevel, modular.
efficiency design of the multilevel dcdc converter, many de-
sign methods and efficiency analysis have been proposed in the
I. INTRODUCTION literature [2], [27][29], [31], [32]. By designing these hard-
switched multilevel dcdc converters properly, the converter
N RECENT years, due to the prosperous development of
I the hybrid electric vehicle or battery electric vehicle in au-
tomotive industry, the high efficiency, high power density, and
efficiency can be up to 98% in 1-kW power level and up to
99% in 10-kW power level. But most of the design methods
only consider capacitor charging energy loss, or the influence
high temperature operated dcdc converter is required [1]. The caused by the capacitor ESR and switch turn-ON resistance
recently developed silicon carbide switching devices and ce- [27], [29]. The parasitic inductance caused by the circuit layout
ramic capacitors are able to operate at very high temperature and the switching device package may influence the converter
efficiency significantly [2]. By properly considering the stray
inductance, high-efficiency multilevel dcdc converter can be
Manuscript received September 10, 2011; revised February 8, 2012, June 10, designed [2].
2012, and September 3, 2012; accepted November 14, 2012. Date of current However, the conversion ratio of aforementioned traditional
version January 18, 2013. Recommended for publication by Associate Editor
F. Wang. multilevel dcdc converters is limited to 2 or 3. With the in-
D. Cao was with the Department of Electrical and Computer Engineering, crease of conversion ratio, these multilevel dcdc converters
Michigan State University, East Lansing, MI 48824 USA. He is now with Ford will suffer high conduction loss, high switching loss, high turn
Motor Company, Dearborn, MI 48120 USA (e-mail: [email protected]).
S. Jiang and F. Z. Peng are with the Department of Electrical and Computer OFF current, and serious voltage overshoot problems. In order
Engineering, Michigan State University, East Lansing, MI 48824 USA (e-mail: to solve the problems of these traditional multilevel dcdc con-
[email protected]; [email protected]). verter, a multilevel-modular capacitor-clamped dcdc converter
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. (MMCCC) is proposed [33][37]. To further reduce the switch-
Digital Object Identifier 10.1109/TPEL.2012.2231438 ing loss, capacitor size and to achieve high efficiency and power

0885-8993/$31.00 2012 IEEE

CAO et al.: OPTIMAL DESIGN OF A MULTILEVEL MODULAR CAPACITOR-CLAMPED DCDC CONVERTER 3817

Fig. 1. (a) 4X MMCCC with three modules main circuit structure considering the stray inductance. (b) Gate signals of the MMCCC with two switching states.

density of the MMCCC, the ZCS-MMCCC is proposed. [38], semiconductor switching devices achieving ZCS. The detailed
[39]. By designing the switching frequency and capacitance analysis and explanation of the two cases are provided in the
properly, the circuit parasitic inductor of MMCCC can be uti- next two sections. Since the capacitance requirement is low in
lized to resonate with the capacitor. In this case, ZCS for all the the underdamped case, small size and low capacitance multi-
switching devices can be realized. Similarly, by utilizing the par- layer ceramic capacitors can be employed for the design. In
asitic inductance in the circuit, many other ZCS multilevel dcdc both cases, the converter can be designed to achieve the highest
converters are proposed with the efficiency up to 98% [40], [41]. efficiency, but in the underdamped case, the total capacitor size
Many other switched capacitor circuits with ZCS have also is much smaller. Therefore, the underdamped case with ZCS
been proposed using the similar strategy [48][52]. Although of all the switches can be considered more optimal than the
the ZCS-MMCCC effectively reduces the switching loss and other case in terms of efficiency and power density. The proto-
capacitor size through resonating, it may suffer higher device type based on this optimal case has been built; the experimental
conduction loss and gate drive loss than the hard-switched MM- results with efficiency curves are provided to demonstrate the
CCC due to the sinusoidal conduction current and the increased validity of the proposed optimal design method.
switching frequency. The detailed loss analysis and profound
design of hard-switched MMCCC are not addressed in the lit-
erature. By considering the stray inductance, the hard-switched
MMCCC may be designed as the traditional multilevel dcdc II. MMCCC OPERATING PRINCIPLE AND POWER
converter to reach high efficiency too. The detailed loss analysis LOSS ANALYSIS
and design comparison of the hard-switched MMCCC and ZCS- In this section, the operating principle of the MMCCC is re-
MMCCC should be done. Some optimization design methods of viewed. The power loss of the switching device and the capacitor
switched-capacitor dcdc converter have also been proposed re- is analyzed. The method of minimizing the total power loss is
cently, but none of them considers the stray inductance influence discussed.
in the circuit [42][44]. Fig. 1(a) shows the 4X MMCCC main circuit structure con-
This paper presents the optimal design considerations for sidering parasitic inductance with three module blocks as an
the MMCCC to obtain the design parameters with the small- example for operation analysis. The conversion ratio of the
est size and the highest efficiency. The power loss analysis of 4X MMCCC is 4. The operating principle can be easily ex-
the MMCCC considering the switching devices gate drive loss, panded to the NX MMCCC case with N 1 module blocks
conduction loss, switching loss, and the capacitor conduction because of the modular structure of the circuit. Fig. 1(b)
loss is proposed; the loss estimation equations are derived. By shows the gate signals of the MMCCC. There are only two
considering the influence of the parasitic inductance present in gate signals of the MMCCC. The two gate signals of the
the circuit, the equivalent circuit of each switching states of the MMCCC are complementary with 50% duty cycle.
MMCCC becomes a second-order series RLC circuit. The min- There are only two switching states of the MMCCC.
imum power loss can then be determined by four design param- Fig. 2 shows the simplified equivalent circuits of the 4X
eters, equivalent stray inductance, equivalent resistance, capaci- MMCCC in two switching states. LS 1 LS 4 are the equiva-
tance, and switching frequency. With the change of these param- lent parasitic inductance in each current loop. Fig. 2(a) shows
eters, the solutions of the second-order differential equation of the case when the switches SP 1 SP 5 are turned ON. In this
series RLC circuit are in different forms. The optimal design ap- switching state, the capacitor C1 is charged by the input voltage
proach should also be divided into two different cases to discuss, source, the capacitor C3 is charged by the input voltage source
overdamped case and underdamped case. In both cases, there in series with the capacitor C2 . Fig. 2(b) shows the case when
exists an optimal design point with minimal power loss by vary- the switches SN 1 SN 5 are turned ON. In this switching state,
ing design parameters. In overdamped case, the optimal design the capacitor C2 is charged by the input voltage source in series
point happens when the switching current is quasi-square, the with the capacitor C1 , the capacitor C4 is charged by the input
switching frequency is low, and the capacitance is designed large voltage source in series with the capacitor C3 . In the following
enough by using large electrolytic capacitor bank. In the under- part, the switching device and the capacitor power loss will be
damped case, the optimal design point happens when switching analyzed. The power loss caused by control chip is small enough
frequency equals to the RLC resonant frequency, with all the to be neglected.
3818 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 2. Simplified equivalent circuits of the 4X MMCCC. (a) Switching state I when switches S P 1 S P 5 are ON. (b) Switching state II when switches
S N 1 S N 5 are ON.

freewheeling diode. The duration time of iD decreasing to zero

is tf , and the turn OFF switching loss of the device is Psw o .
Due to the influence of the parasitic inductance, the switch turn
OFF current may not be zero. And the turn OFF switching loss of
this device can be considered as an inductive load, the turn OFF
switching loss should be calculated using (4). The total switch-
ing loss of the device is Psw . So, the switching loss during turn
ON and OFF can be estimated by
 t 1   
ID VDS
Psw on = t VDS t fS
Fig. 3. MOSFET drainsource voltage and drain current for switching loss 0 t1 t1
analysis.
1
= ID VDS t1 fS (3)
6
A. Switching Device Power Loss 1
Psw o = VDS ID (t2 + tf ) fS (4)
1) Conduction Loss: Assume that all the switching devices 2
are MOSFETs. The rms value of switch current is IS rm s , the Psw = Psw on + Psw o . (5)
turn-ON resistance of the device is Ron , and the conduction
loss of switching device is PS con . Thus, the switching device
conduction loss can be estimated as follows:
2
B. Capacitor Power Loss
PS con = IS rm s Ron . (1)
Assume the rms current through the capacitor is IC rm s , the
2) Gate Drive Loss: Assume that the gate drive voltage of capacitor ESR is RESR . The capacitor C1 C4 power loss is
the MOSFET is VGS , the switching frequency is fS , the total gate PC con , so the power loss caused by the capacitor ESR can be
charge of the device is Qg , and the gate drive loss of switching calculated, as shown in (6). The input capacitor Cin rms current
device is PS drv . Thus, the switching device gate drive loss is IC in rm s and the power loss is PCin con . The input capacitor
can be estimated using the following equation considering the power loss can also be calculated in a similar manner, as shown
turn-ON and turn-OFF gate drive loss: in (7)
2
PS drv = VGS Qg fS . (2) PC con = IC rm s RESR (6)
2
3) Switching Loss: Fig. 3 shows the device drainsource PCin con = ICin rm s RESR . (7)
voltage and drain current for switching loss analysis [45]. Be-
cause of the special structure of the circuit, the turn OFF switch- C. Total Power Loss
ing loss can be considered the same as the inductive load. On Assume the conversion ratio is N . The total power loss of
the other hand, the turn ON switching loss should be consid- the converter is Ploss , which is the sum of (3N 2) switching
ered as the LC load. Assume the drainsource voltage of the devices power loss, N capacitors power loss with the input
device is VDS , the duration of VDS decreasing to zero is t1 during capacitor power loss, which can be estimated by
the switch turn-ON process. This duration t1 is affected by the
Miller effect due to the gate resistor Rg and the reverse capacitor Ploss = (3N 2) (PS con + PS drv + Psw )
Crss . The turn ON process ends when VDS reaches zero voltage,
+ N PC con + PC in con . (8)
and the turn ON switching loss of the device is Psw on . When
the switch is turned ON, the switch initial current is zero, the In order to minimize the total power loss, each part of (8) should
turn ON process of this circuit can be considered as LC load be minimized. The device gate drive loss is related to the gate
due to the circuit structure, the turn ON switching loss should drive voltage, total gate charge, and the switching frequency. The
be calculated using (3). The duration time of VDS increases to rms value of the switch drain current IS rm s , the switch drain
the highest value during the switch turn-OFF process is t2 . The current ID , and the rms value of capacitor current IC rm s will
duration t2 is also caused by the Miller effect. After that, the vary due to the value of capacitance, stray inductance, switching
drain current iD begins to decrease due to the conduction of frequency, the switch turn ON resistance, and the capacitor ESR.
CAO et al.: OPTIMAL DESIGN OF A MULTILEVEL MODULAR CAPACITOR-CLAMPED DCDC CONVERTER 3819


switching loop L = LS . C can be considered as the value
of all the capacitance in series in one switching loop. R can
be considered as the sum of all the turn ONresistance and the
capacitor ESR in one switching loop, R = Ron + RESR . In
every switching state, the circuit behavior can be considered as
the step response of this series RLC circuit. The initial value of
capacitor voltage is VC , and the initial valueof inductor cur-
Fig. 4. Unified equivalent circuit of the MMCCC for power loss estimation. rent is zero. The natural frequency is 0 = 1/LC, and the
damping ratio is = R C/L/2. So, the capacitor voltage can
be calculated using the following differential equations in (9).
The value of R, L, and C will vary due to different design. The
solution of the previous differential equation should be divided
into two cases, overdamped case and underdamped case with
different types of roots. The critical damped case is very similar
to overdamped case, which will not be discussed in detail here

Fig. 5. Simplified equivalent circuit for switching current calculation. dvC (t) d2 vC (t)
vC (t) + RC + LC
dt dt2
So, the device and the capacitor should be chosen properly to dvC (t)
= Vin , vC (0) = VC , (0) = 0. (9)
minimize the total power loss. dt
In every switching state, the simplified equivalent circuits of
the MMCCC can be considered as a series RLC circuit, as shown
in Fig. 4. Switch conduction loss is modeled using Ron and the A. Overdamped Case ( > 1, or R2 C > 4L)
capacitor power loss is modeled using RESR . By using high When the damping ratio of the circuit is larger than 1, the
capacitance electrolytic capacitor and low switching frequency, circuit works in overdamped case. So, in the overdamped case,
the MMCCC can be designed in overdamped situation. In this the capacitor voltage can be calculated as shown in (10). Since
case, the current waveform of the switch is quasi-square, and the capacitor current in one switching state is the same with the
the switching loss should be considered. By using low capaci- switch current, so the switch current can be calculated as shown
tance multilayer ceramic capacitor (MLCC) and high switching in (11)
frequency, the MMCCC can be designed in underdamped situ- 2
VC Vin 
ation with ZCS. In this situation, the current waveform of the vC (t) =  (0 ( 2 1)e 0 ( + 1)t
switch is half sinusoid, and the capacitor current waveform is 20 2 1
sinusoid. With the same power to be delivered, the sinusoid cur-  2
rent has a larger rms value than the quasi-square current. So, the + 0 ( + 2 1)e 0 ( 1)t ) + Vin (10)
switch conduction loss is larger in this case. The gate drive loss dvC (t)
is also increased due to the increased switching frequency. But, iS (t) = iC (t) = C . (11)
dt
the switching loss is eliminated in this case, and the MLCC has
better performance in terms of ESR than electrolytic capacitor. Plug the capacitor voltage (10) into the (11), the capacitor cur-
So, the conduction loss caused by the capacitor ESR can also be rent in one switching period, or the switch current can be calcu-
reduced in the underdamped situation. In order to estimate the lated as follows:
total power loss of the MMCCC correctly, two different cases (VC Vin )C0  0 ( 2 1)t
iS (t) =  e
should be considered and designed, respectively, to achieve the 2 2 1
optimal design of the MMCCC. Detailed design considerations 2 
will be discussed in the next section. e 0 ( + 1)t . (12)
In order to design the MMCCC operating in the overdamped
III. OPTIMAL DESIGN CONSIDERATIONS
case, the stray inductance should be designed as small as pos-
According to the previous analysis, the MMCCC can be de- sible to satisfy the inequality R2 C > 4L. If the stray induc-
signed in either overdamped or underdamped situations. By tance can be minimized, the energy stored in the stray induc-
proper design, either of them may achieve high efficiency. In tance can be minimized. The turn OFF voltage overshoot across
this section, the switching current shape and switching current the device can also be minimized. For example, to design an
rms value in two different cases will be analyzed and calculated. MMCCC with power rating from several hundred watts to tens
So, the conduction loss of the two cases can be compared exactly. of kilowatts, the stray inductance in a normal design should be
The total power loss and other design issues will be compared in the range of several nano-henries to tens of nano-henries. The
and discussed between the two cases too. Fig. 5 shows the sim- stray inductance in the circuit majorly comes from the switch-
plified equivalent circuit used for switching current calculation. ing device internal stray inductance, capacitor ESL, and busbar
L can be considered as the sum of the stray inductance, in one stray inductance. And the total capacitor ESR and the switch
3820 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

circuit parameters. The value of the switch rms current can de-
termine the total conduction loss of the switch and the capacitor
in one switching state. In order to minimize the total conduc-
tion loss of the switch and the capacitor, the switch rms current
should be minimized. The current amplitude for both IS ave
and IS rm s is the same constant value as shown in (14) and (16)
which is related to capacitor voltage, input voltage, switching
frequency, capacitance, and damping factor. Therefore, the ra-
tio of rms current over average current can be defined as r, as
shown in (17). This ratio can be considered as the normalized
switch rms current, which is irrelevant to the output power. By
Fig. 6. (a) Normalized switching current waveforms with the decrease of estimating this ratio, the optimal R, L, and C parameter and
capacitance. (b) Normalized switching current waveforms with the increase of
resistance. switching frequency fS with minimum conduction loss can be
found. The ratio of switch current turn OFF over average current
is defined as Io , as shown in (18). This ratio can be considered
turn ON resistance value are usually about several milliohms. as the normalized switch turn OFF current, which is related to
So, in order to satisfy the overdamped condition R2 C > 4L, switching loss. The circuit parameter, R, L, and C and switch-
the capacitance value should be in the tens of millifarads range, ing frequency fS should be selected carefully to minimize r and
high capacitance electrolytic capacitors should to be used to Io , Equations (13) to (18) as shown at the bottom of the page.
achieve small size. With the same capacitance value, the film In order to minimize the total power loss, the total conduction
and ceramic capacitors are larger than electrolytic capacitor. loss, switching loss, and gate drive loss have to be minimized.
Fig. 6(a) shows the normalized switch current with the change The minimum conduction loss in the overdamped situation hap-
of capacitance. With the decrease of capacitance, the switch when the switching current is quasi-square and r is equal to
pens
current will drop faster, which will cause higher rms value of 2. At this time, Io is equal to 2. If r can be designed at about
switch current, so the capacitance should be designed as large as 2 by using proper circuit parameter at relative low switching
possible. Fig. 6(b) shows the normalized switch current with the frequency (less than 10 kHz), the conduction loss can be mini-
change of resistance. With the increase of resistance, the max- mized, the switching loss and gate drive loss will not be signifi-
imum converter power transfer capability will drop. Although cant due to the relatively low switching frequency, and one of the
R and C can be designed to any value to meet the R2 C > 4L optimal design points can be achieved. Table I shows an exam-
condition, large capacitance with small resistance is preferred ple of the circuit design parameters for an MMCCC in the hun-
in the converter design. dreds watt to tens of kilowatts range. All the capacitance, resis-
The switching device average current IS ave in one switching tance, and inductance value in the table satisfy the overdamped
period can be calculated as (13) and (14), and the rms current condition, which is R2 C > 4L. In the following analysis, the
IS rm s in one switching period can be calculated as (15) and design comparison will be based on this example using the cir-
(16). TS is the switching period. For a certain output power, cuit parameter in Table I. The normalized switch rms current
the value of the switch average current is determined, although r can be considered as a function with four different variables
the shape of the switch current may vary according to different as shown in (17), and the minimal value of r can be achieved

 Ts / 2
1
IS ave (R, L, C, fs ) = iS (t)dt (13)
TS 0
 

 

1 Ts / 2
(VC Vin ) C0 0 2 1 t 0 + 2 1 t
IS ave (R, L, C, fs ) =  e e dt (14)
TS 0 2 2 1
 
Ts / 2
1
IS rm s (R, L, C, fs ) = i2S (t)dt (15)
TS 0

  Ts / 2
 
2 
2  2
 1 (VC Vin ) C0 1 t + 1 t
IS rm s (R, L, C, fs ) =   e 0 e 0 dt (16)
TS 0 2 2 1

IS rm s
r (R, L, C, fs ) = (17)
IS ave
 
iS Ts/2
Io (R, L, C, fs ) = (18)
IS ave
CAO et al.: OPTIMAL DESIGN OF A MULTILEVEL MODULAR CAPACITOR-CLAMPED DCDC CONVERTER 3821

TABLE I
CIRCUIT PARAMETER EXAMPLES FOR POWER LOSS ANALYSIS

Fig. 8. (a) Normalized switch rms current r and turn OFF current Io versus
switching frequency, when C = 160 mF, R = 10 m, and L s changed from
10 to 2 nH.

Fig. 7. (a) Normalized switch rms current r and turn OFF current Io versus
switching frequency, when C = 160 mF, R = 2 m, and L s changed from 10
Fig. 9. (a) Normalized switch rms current r and turn OFF current Io versus
to 2 nH.
switching frequency, when C = 10 mF, R = 2 m, and L s changed from 10
to 2 nH.
by varying these variables. For the visualization convenience,
two variables R and C will be selected as constant value while than the case in Fig. 7 with 2-m internal resistance. Therefore,
the curve of r will be shown with the change of the other two to design the MMCCC with highest efficiency, the internal resis-
variables L and fS . tance should be minimized without a doubt. When the switching
Fig. 7 shows the normalized switch rms current r and switch devices and the capacitor bank are selected, which means the
turn OFF current Io versus switching frequency when C = capacitance and the internal resistance are determined, the stray
160 mF, R = 2 m, and Ls changed from 10 to 2 nH. When the inductance should be designed as small as possible to minimize
Ls = 2 nH, r reaches the minimum value. And the minimum conduction loss and switching loss, as shown in Figs. 7 and 8.
value of r does change much when Ls is changed from 10 to With relatively low stray inductance, both the conduction loss
2 nH, as shown in Fig. 7(a). The optimal switching frequency and the switching loss are smaller than the case with higher
for this case is from 5 to 10 kHz. When the switching frequency stray inductance. The proper switching frequency should be se-
is less than 5 kHz, the conduction loss increases very fast. The lected properly to make a tradeoff between the conduction loss
switch turn OFF current will increase with the increase of the and the switching loss. As shown in Fig. 7(a), with the smallest
switching frequency as shown in Fig. 7(b). Although there ex- stray inductance, the optimal switching frequency with minimal
ists two switching frequency with the same conduction loss, as conduction loss happens at about 9.5 kHz. With the reduction
shown in Fig. 7(a), the low switching frequency design point is in switching frequency, the conduction loss will increase sig-
preferred with relatively lower turn OFF current and switching nificantly. On the other hand, the switching loss will reduce
loss, as shown in Fig. 7(b). Fig. 8 shows the similar curve as according to the switching frequency as shown in Fig. 7(b), so
shown in Fig. 7 by changing the resistance from 2 to 10 m. The the optimal switching frequency should happen with the switch-
optimal switching frequency range in this case with low con- ing frequency less than 9.5 kHz. In the practical implementation,
duction loss is extended from 1 to 10 kHz as shown in Fig. 8(a). after the stray inductance has been minimized by the circuit lay-
And the optimal switching frequency should also be designed at out, the optimal switching frequency can be found out by testing
the low switching frequency point which is about 1 kHz or even the converter efficiency in various switching frequencies. This
lower since the switching loss and gate drive loss can be mini- switching frequency-dependent efficiency feature has also been
mized. The optimal switching frequency is reduced in this case verified by other papers based on different multilevel circuit
with relatively low r and Io compared with the case shown in topologies [29], [32].
Fig. 7. However, the total R in the circuit still needs to be mini- Figs. 9 and 10 show the similar case as shown in Figs. 7 and
mized to design the MMCCC, since the conduction loss of the 8 with reduced capacitance. When the capacitance is reduced
case in Fig. 8 with 10-m resistance is increased by five times from 160 to 10 mF, high switching frequency has to be used
3822 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 10. (a) Normalized switch rms current r and turn OFF current Io versus
switching frequency, when C = 10 mF, R = 10 m, and L s changed from 10
to 2 nH.

to reach the minimum conduction loss as shown in Figs. 9(a)

and 10(a). However, in this case, the switching loss and gate
drive loss will be about ten times higher than the previous case
with higher capacitance. Although the conduction loss can be
designed at similar level with different capacitance, high ca-
pacitance is preferred in the design with less switching loss.
As shown in Fig. 9(b), when the switching frequency is less Fig. 11. Capacitor C 1 voltage (V C 1 ), capacitor C 4 voltage V o , and switch
current I_S, when C = 160 mF, R = 10 m, L s = 10 nH, and fs = 7 kHz.
than 9 kHz, the turn OFF current is almost zero, ZCS may be
achieved in this case. However, r is already much higher than
/2, which means the conductional loss in this case will be
higher than the underdamped case with sinusoid current wave-
form. Besides, since the capacitance in the overdamped case
is in the 10 s mF range, electrolytic capacitor has to be used.
And more electrolytic capacitors in parallel mean low turn ON
resistance.
Therefore, to design the MMCCC in the overdamped case,
many electrolytic capacitors in parallel with high capacitance,
low resistance, and low stray inductance operating at low switch-
ing frequency are preferred in the design to reach high efficiency.
However, many electrolytic capacitors in parallel will increase
the total converter size which is a major disadvantage to design
the MMCCC in this case. Figs. 1113 show some simulation
results of device switching current and capacitor voltage at dif-
ferent design parameters. Fig. 11 shows the case with 160-mF
capacitor and 7-kHz switching frequency. According to the sim-
ulation result, the normalized rms current r is 1.418, and the
normalized turn OFF current Io is about 1.9 which verifies the
calculated results shown in Fig. 8. Similarly, Fig. 12 shows the
case when r is 2.15, and the Io is about 0. Fig. 13 shows the
case when r is 1.437, and Io is about 1.8.

B. Underdamped Case ( < 1, or R2 C < 4L) Fig. 12. Capacitor C 1 voltage (V C 1 ), capacitor C 4 voltage V o , and switch
current I_S, when C = 10 mF, R = 10 m, L s = 10 nH, and fs = 2 kHz.
When the damping ratio of the circuit is less than 1, the
MMCCC can also be designed at the underdamped case with
resonate switch current. In this case, the stray inductance does
not need to be minimized purposely. For example, to design the design of other parameters easier. The resistance should also
the MMCCC in the hundreds watts to tens of kilowatts range be in the range of several milliohms. The resonant capacitance
with the same rating of aforementioned overdamped case, and should be chosen in the 10 s F range, which is very easy to
the stray inductance could be in the range of tens to hundreds be achieved using MLCC. And the switching frequency is only
nano-henry. By proper circuit layout, the parasitic inductance of in the 10 s kHz range to match the resonant frequency. In the
different modules can be designed with the same value to make underdamped case, the capacitor voltage and the switch current
CAO et al.: OPTIMAL DESIGN OF A MULTILEVEL MODULAR CAPACITOR-CLAMPED DCDC CONVERTER 3823

Fig. 13. Capacitor C 1 voltage (V C 1 ), capacitor C 4 voltage V o , and switch

current I_S, when C = 10 mF, R = 10 m, L s = 10 nH, and fs = 40 kHz. Fig. 14. Normalized switch current (a) when switching frequency is smaller
than resonant frequency, (b) when switching frequency is the same as the res-
onant frequency, and (c) when switching frequency is larger than the resonant
can be calculated as shown in frequency.
 
t
vC (t) = e (VC Vin ) cos (d t) + sin (d t) analysis method shown in the overdamped case, the switching
d
loss of the case shown in Fig. 14(c) will be significant. Since the
dvC (t) stray inductance in the underdamped case is relatively large, the
+ Vin , iS (t) = C . (19)
dt energy stored in the stray inductance may cause serious volt-
age overshoot across the devices. Therefore, the optimal design
In this case, the switching current becomes a damped sinu-
point of the underdamped case should be the case shown in
soid waveform.
= R/2L, which is the neper frequency, and
Fig. 14(b) with ZCS for all the switching devices.
d = 02 2 , which is the natural resonant frequency.
Fig. 14(a)(c) shows the switch current in three cases when
IV. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
the switching frequency is smaller, equal to or larger than the
resonant frequency. Obviously, with the same average current, A 150-W 520 V 4X MMCCC prototype operating at the
the case shown in Fig. 14(a) has largest rms value of switch underdamped case with ZCS for all switches has been built.
current, because the switch current will resonant to the negative The switching frequency is about 45 kHz. The stray inductance
part, which means the power will flow back to the input during LS 1 = 250 nH, LS 2 = LS 3 = 2LS 1 , LS 4 should be designed a
this period. When the switching frequency is equal to the res- little smaller than LS 2 and LS 3 due to the influence of the output
onant frequency, ZCS for all the switches can be achieved, as current. The switching devices are two 30 V 180 A MOSFETs
shown in Fig. 14(b). The normalized rms current r is equal to IPB009N03 L from infineon connected in parallel. Resonant ca-
/2 in this case which is only 11% higher than the best case in pacitor are ten 100 V 4.7 F MLCC C57507R2A475 K from
overdamped condition with r equals to 2. The conduction loss TDK in parallel. Since the MOSFETs IPB009N03 L turn ON re-
in this case is about 23% larger than the quasi-square current sistance is about 0.9 m, the parasitic resistance of two device in
waveform under overdamped condition. However, the switching parallel is about 0.45 m. The ESR of the C57507R2A475 K
loss is eliminated in this case, the total power loss in this case is about 6 m; the parasitic resistance of ten capacitor in paral-
may be designed similar to the overdamped case. Since only lel is about 0.6 m. The length of the stray inductance LS 1 is
low capacitance ceramic capacitors are needed in this case, the about 25 cm, and the cross-section area of the stray inductance
total converter size is reduced significantly than the overdamped is similar to AWG 16 wire. The parasitic resistance of the stray
case. By designing the MMCCC in the underdamped case, the inductance LS 1 is about 3.29 m. According to Fig. 2, there
total converter sized can be minimized without increasing to- maybe many devices or resonant capacitors in series, so, the
tal power loss. The electromagnetic interference can also be damping ratio for the first loop can be calculated accordingly,
reduced since all the switches can achieve ZCS. Although the which is about 0.0328. The damping ratio for other switching
rms value switch current r of the case shown in Fig. 14(c) is loops can also be calculated using the similar method. Input ca-
slight smaller than the case shown in Fig. 14(b) using the similar pacitors are 14 6.3 V 470 F conductive polymer aluminum solid
3824 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 15. Gate drive signals of S P and S N . Fig. 16. Voltage and current waveforms of S P 1 .

electrolytic capacitors PLE0J471MDO1 from nichicon con-

nected in parallel. Gate drive voltage is 15 V.
To design this circuit, the capacitor should be chosen first
according to the capacitor voltage ripple requirement. If the
capacitor voltage ripple is less than 100%, it is not a factor
to change the circuit efficiency. The capacitor voltage ripple
can be selected in a more practical way according to different
application. If the capacitance for all the capacitors are selected
equally, the absolute value of the capacitor voltage ripple are all
the same, due to the same amplitude of the capacitor current.
Thus, the first capacitor voltage ripple should be less than 100%,
in order to operate the circuit properly. In this prototype, the
first capacitor C1 voltage ripple is selected about 40% of its
average voltage. Since the circuit stray inductance is already Fig. 17. Zoomed in voltage and current waveforms of S P 1 .
determined by the circuit layout. The corresponding optimal
switching frequency can be achieved by tuning the switching
frequency. Similar design guidelines can be referred to the [39].
Although only a 150 W prototype is built here, the proposed idea
can be easily extended to high-current low-voltage automotive
application. In such applications, the low-voltage high-current
ceramic capacitors can be obtained easily, and high-current low-
voltage MOSFETs module up to 150 V and 600 A can also be
obtained. Up to 55 kW dcdc converter using similar circuits
has already been built and tested [2], [30], [31].
Figs. 1518 show the experimental waveforms of the afore-
mentioned prototype. Fig. 15 shows the complementary gate
drive signals of SP and SN with about 49% duty cycle due to
some dead time. Fig. 16 shows the gate drive voltage, drain
Fig. 18. Measured and calculated efficiency.
source voltage and switch current of SP 1 . The ZCS of switch
has been achieved. Fig. 17 shows the zoomed in waveforms
of the switch SP 1 turn OFF transient, which indicates that the
switch achieves ZCS during turn OFF. But there still exists some will not be shown here. Fig. 18 shows the measured efficiency
high-frequency resonant current, as shown in Fig. 17 caused by curve using Yokogawa WT1600 digital power meter of the 4X
the resonant of the stray inductance and the switch parasitic ca- MMCCC designed at the underdamped case with ZCS, and the
pacitance. Since the parasitic capacitance across the switching estimated efficiency using the power loss analysis of (8). The
devices is usually low, and the residual current of the stray induc- deviation observed between the measured and calculated effi-
tance is around zero, the high-frequency resonant current will ciency is because the temperature factor is not considered during
not have a high amplitude, as shown in Fig. 17 (<2 A). From the calculation, and there exists some equipment tolerance error
the experiment results, we can derive that the switch SP 1 can which is about 0.5% during the measurement. Fig. 19 shows the
achieve ZCS in both turn ON and turn OFF. Other switches photo of a 630 W 560 V 12X ZCS-MMSCC prototype of the
have the voltage and current waveforms similar to SP 1 which proposed circuit.
CAO et al.: OPTIMAL DESIGN OF A MULTILEVEL MODULAR CAPACITOR-CLAMPED DCDC CONVERTER 3825

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fault tolerant feature in a 5-kW multilevel dc-dc converter with modular received the outstanding presentation award at Applied Power Electronics Con-
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