VHDL - Xilinx Exercises Compilation

VHDL EXERCISES COMPILATION
By
Nicko D. Casi/ ECE-4
MICROELECTRONICS TRACK 3
Bachelor of Science in
Electronics Engineering
PROBLEM I: COUNTER
Create a Counter based from XILINX Quick Start Tutorial using VHDL
Language. When Clock =1, then the counter would count to 15 but when the
Clock=0, then the counter would count down from where it started.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if
instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is

signal count_int : std_logic_vector(3 downto 0) :=
"0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
SIMULATION:
PROBLEM II: ANDING
Create a two 8-bit inputs that would do an ANDing operation.
VHDL Code:
library IEEE;
---- Uncomment the following library declaration if

instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
entity sample is
Port ( ina : in STD_LOGIC_VECTOR (7 downto 0);
inb : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
outa : out STD_LOGIC_VECTOR (7 downto 0));
end sample;
architecture Behavioral of sample is
begin
process(clk)
begin
if clk='1' and clk'event then
outa <= ina and inb;
end if;
end process;
end Behavioral;
SIMULATION:
PROBLEM III: ADDITION
Perform the addition of two 8-bit inputs.
VHDL Code:
library IEEE;
-- Uncomment the following library declaration if --

instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
entity addition is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end addition;
architecture Behavioral of addition is
begin
process (clk)
begin
if clk = '1' and clk'event then
Y <= A + B;
end if;
end process;
end Behavioral;
SIMULATION:
PROBLEM IV: SUBTRACTION
Perform the subtraction of two 8-bit inputs.
VHDL Code:
library IEEE;

instantiating
--library UNISIM;
entity subtract is
clk : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (7 downto 0));
end subtract;
architecture Behavioral of subtract is
begin
process (clk,A,B)
begin
if clk ='1' and clk'event then
Y <= A - B;
end if;
end process;
end Behavioral;
SIMULATION:
PROBLEM V: DIVISION
Perform the division of two 8-bit inputs.
VHDL Code:
library IEEE;

instantiating
--library UNISIM;
entity division_in is
clk : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (7 downto 0);
err : out STD_LOGIC);
end division_in;
architecture Behavioral of division_in is
begin
process(clk)
begin
Y <=
conv_std_logic_vector(conv_integer(A)/conv_integer(B),8
);
err <= '0';
end if;
if B = 0 then
err <= '1';
end if;
end process;
end Behavioral;
SIMULATION
PROBLEM VI: BCD TO DECIMAL
Determine if the input of 12-bits is valid for converting to BCD. If each 4-bit
of the 12-bit input is less than 10, then it is BCD thus, the error is equal to zero and
the output display the BCD of the input. If one or all of the 4-bits in a 12-bit input is
greater than or equal to 10, then the error is equal to one and no BCD output will be
displayed.
VHDL Code:
library IEEE;

instantiating
--library UNISIM;
entity bcd is
clk : in STD_LOGIC;
B : out STD_LOGIC_VECTOR (9 downto 0);
end bcd;
architecture Behavioral of bcd is
begin
process(clk)
begin

if (conv_integer(A(11 downto 8)) >= 10) or
(conv_integer(A(7 downto 4)) >= 10)
or (conv_integer(A(3 downto 0)) >=10)
then
err <= '1';
else
B <=
conv_std_logic_vector(100*(conv_integer(A(11 downto
8)))
+ 10*(conv_integer(A(7 downto 4))) +
(conv_integer(A(3 downto 0))),10);
err <= '0';
end if;
end if;
end process;
end Behavioral;
SIMULATION:
PROBLEM VI: DECIMAL TO BCD
Convert the 10-bit input decimal (Max of 1023) to Binary-Coded-Decimal.

Hint: Use the Modulo function.
VHDL Code:
library IEEE;
entity dec_to_bcd is
Port ( Ina : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
Outa : out STD_LOGIC_VECTOR (15 downto 0);
end dec_to_bcd;
architecture Behavioral of dec_to_bcd is
begin
process (clk)
begin
if (conv_integer(Ina) >= 1024) then
err <= '1';
else
Outa(15 downto 12) <=
conv_std_logic_vector((conv_integer(Ina) / 1000),4);
Outa(11 downto 8) <=
conv_std_logic_vector((conv_integer(Ina) / 100)MOD
10,4);
Outa(7 downto 4) <=
conv_std_logic_vector((conv_integer(Ina) / 10)MOD 10,4);
Outa(3 downto 0) <=
conv_std_logic_vector((conv_integer(Ina))MOD 10,4);
end if;
end if;
end process;
end Behavioral;
SIMULATION:
PROBLEM VII: COUNTING THE NUMBER OF ONES
With the input of 16-bits, create a program where the output displays the
number of ones. Hint: use Loop.
VHDL Code:
library IEEE;
entity count_ones is
Port ( ones : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
number_of_ones : out integer);
-- err : out STD_LOGIC);
end count_ones;
architecture Behavioral of count_ones is
begin
process (clk, ones)
variable c: integer;
begin
c:=0;
ones1: for i in 0 to 15 loop
if (ones(i)='1') then
c:=c+1;
end if;
end loop ones1;
end if;
number_of_ones<=c;
end process;
end Behavioral;
SIMULATION:

VHDL - Xilinx Exercises Compilation

Uploaded by

Copyright:

Available Formats

VHDL - Xilinx Exercises Compilation

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VHDL - Xilinx Exercises Compilation

Uploaded by

Copyright:

Available Formats

VHDL EXERCISES COMPILATION

Nicko D. Casi/ ECE-4

architecture Behavioral of counter is

Create a two 8-bit inputs that would do an ANDing operation.

---- Uncomment the following library declaration if

architecture Behavioral of sample is

Perform the addition of two 8-bit inputs.

-- Uncomment the following library declaration if --

architecture Behavioral of addition is

Perform the subtraction of two 8-bit inputs.

---- Uncomment the following library declaration if

architecture Behavioral of subtract is

Perform the division of two 8-bit inputs.

---- Uncomment the following library declaration if

architecture Behavioral of division_in is

---- Uncomment the following library declaration if

architecture Behavioral of bcd is

if clk='1' and clk'event then

Convert the 10-bit input decimal (Max of 1023) to Binary-Coded-Decimal.

architecture Behavioral of dec_to_bcd is

architecture Behavioral of count_ones is

You might also like