Electrical Thin Film Physics

and Process Technology

- Ch. 4 : CVD and Dielectric
Thin Film

授課教師: 劉柏村 教授
國立交通大學光電工程所
1
 CVD Oxide vs. Grown Oxide

SiO2
SiO2
Si Si Si

Grown film Bare silicon Deposited film

2
 CVD Oxide vs. Grown Oxide
Grow CVD

• Oxygen is from gas • Both oxygen and silicon

phase are from gas phase
• Silicon from substrate • Deposit on substrate
• Oxide grow into silicon surface
• Higher quality • Lower temperature
• Higher growth rate

3
 Dielectric Thin Film Applications
• Multi-level metal interconnection
• CVD and SOG plus CVD dielectrics
• Shallow trench isolation (STI)
• Sidewall spacer for salicide, LDD, and the
source/drain diffusion buffer
• The passivation dielectric (PD)
• Dielectric ARC for feature size < 0.25 mm
4
 Dielectric Thin Film Applications
• Inter layer dielectric, or ILD, include PMD and
IMD
• Pre-metal dielectric: PMD
– normally PSG or BPSG
– Temperature limited by thermal budget
• Inter-metal dielectric: IMD
– USG or FSG
– Normally deposited around 400 C
5
 Nitride PD2
Oxide
Metal 2, Al•Cu Al•Cu
PD1
ARC
W USG
IMD or
ILD2
Metal 1, Al•Cu
PMD or
W WCVD
ILD1 BPSG

STI n+ n+ USG p+ p+ STI

P-well N-well
Sidewall
spacer P-epi TiN
P-wafer CVD

6
 Dielectric Processes

An N-layer metal interconnection IC chip with

STI, the minimum number of dielectric process is:

Dielectric layer = 1 +1 + 1 + (N-1) + 1 = N+3

STI spacer PMD IMD PD

7
 CVD
• Chemical Vapor Deposition

• Chemical gases or vapors react on the surface of

solid, produce solid byproduct on the surface in
the form of thin film. Other byproducts are
volatile and leave the surface.

8
 CVD Applications
FILMS PRECURSORS

Si (poly) SiH4 (silane)

Semiconductor SiCl2H 2 (DCS)
Si (epi) SiCl3H (TCS)
SiCl4 (Siltet)
LPCVD SiH4, O2
SiO2 (glass) PECVD SiH4, N2O
Dielectrics PECVD Si(OC2H5) 4 (TEOS), O2
LPCVD TEOS
APCVD&SACVDTM TEOS, O3 (ozone)
Oxynitride SiH4, N2O, N2, NH3
PECVD SiH 4, N2 , NH3
Si3N4 LPCVD SiH 4, N2 , NH3
LPCVD C8H22N2Si (BTBAS)
W (Tungsten) WF6 (Tungsten hexafluoride), SiH4, H2
WSi2 WF6 (Tungsten hexafluoride), SiH4, H2
Conductors TiN Ti[N (CH3) 2]4 (TDMAT)
Ti TiCl4
Cu
9
 CVD
• Gas or vapor phase precursors are introduced into the reactor
• Precursors across the boundary layer and reach the surface
• Precursors adsorb on the substrate surface
• Adsorbed precursors migrate on the substrate surface
• Chemical reaction on the substrate surface
• Solid byproducts form nuclei on the substrate surface
• Nuclei grow into islands
• Islands merge into the continuous thin film
• Other gaseous byproducts desorb from the substrate surface
• Gaseous byproducts diffuse across the boundary layer
• Gaseous byproducts flow out of the reactor.
10
 Precursors
Showerhead

Forced
convection
region

Boundary
Byproducts Reactants
layer
Pedestal
Wafer
11
 Deposition Process

Precursor arrives surface Migrate on the surface

Nucleation:
React on the surface
Island formation
12
 Deposition Process

Islands grow,
Islands grow cross-section

Islands merge Continuous thin film

13
 CVD Processes
• Atmospheric Pressure Chemical Vapor Deposition
(APCVD)
• Low Pressure Chemical Vapor Deposition (LPCVD)
• Plasma-Enhanced Chemical Vapor Deposition
(PECVD)
• High-Density Plasma Chemical Vapor Deposition
(HDPCVD)

14
 APCVD vs. LPCVD
APCVD:
• Chemical Vapor Deposition
• Gases introduce  react on
the surface. If take place in the
gas stream. (particulate forms
and causes pinholes)
LPCVD:
• If liquid source, a carrier gas
such as hydrogen (nitrogen or
argon) is bubbled through the
liquid source and carrier the
source vapor to the reaction
chamber.
• APCVD: cold wall;
• LPCVD: hot wall
15
 APCVD
• CVD process taking place at atmospheric pressure
• It is a cold wall reactor, the wafers are heated by using a graphite
susceptor which is heated by RF induction. (simple)
• This minimizes deposition on the reactor walls since only the susceptor
and wafers are hot.
• APCVD O3-TEOS oxide process is widely used in the semiconductor
industry, especially in STI and PMD

Continuous APCVD reactor: N2 製程氣體 N2

晶圓
晶圓

Heater

傳送帶清 傳送帶(conveyor belt) 16

潔裝置 排氣孔
 CVD Dynamics

• Steps: 1. transport, 2. diffusion, 3. adsorption, 4. surface reaction

(migration, reaction, nucleation, nuclei grow, & islands merge) ,
5. desorption, 6. by-product diffusion, 7. transport of byproducts.
17
 Surface Reaction (I)

Precursor arrives surface Migrate on the surface

React on the surface Nucleation:

Island formation
18
 Surface Reaction (II)

Islands grow,
Islands grow cross-section

Islands merge Continuous thin film

19
 Mass Delivery
• Step 2 is mass transfer of reactants through the boundary layer
• F1= hG(CG-CS), where (CG-CS) is the difference in concentration of the
reactant species ( in molecules cm-3), and hG is the mass transfer
coefficient ( in cm sec-1). Here, assuming hG constant.
• F2 = kSCS, where kS is the chemical surface reaction rate (in cm sec-1)
and CS is the concentration of the reacting species at the surface (in cm-3).
• Assuming steady state deposition F = F1= F2 ,
k S -1 F k h C v: growth rate of the film
C s  CG (1  ) v  S G G or deposition rate (cm sec-1)
hG N k s  hG N F: reactant flux (molecules cm-2sec-1)
N: the number of atoms incorporated
per unit volume in the film;
or film density (cm-3)

F1 : reactant flux from the gas phase to the wafer

(in molecules cm-2 sec-1)
F2: reactant flux consumed by the reaction at surface
20
 Mass Delivery (cont.)
CG PG Y : mole fraction of incorporating species in gas phase
Y  CG: reactant concentration in gas phase
CT PTotal CT : concentration of total molecules in gas phase

• If kS << hG , v = [CT/N]kSY, it is the surface reaction controlled case.

If ks >> hG , the v = [CT/N]hGY, it is the mass transfer, or gas phase
diffusion controlled case.
• Both regimes have constant growth rate, this is because the reaction
always occurs at the growing surface.

21
 Mass Delivery (cont.)
• The temperature dependence of the surface reaction controlled case
is Arrhenius. The mass transfer coefficient, hG, is insensitive to
temperature.
• When the deposition occurs in the mass transfer controlled regime
(high temperatures), the deposition rate is relatively constant with
temperature.
• Mass transfer control: the flow of the gas over the wafers and
transport of the reactant to the surface are very important. See Fig.9-
4 (a), the wafers must usually be placed face up and edge to edge in
the chamber and that equal deposition rates are achieved.
• Surface reaction control (i.e., lower temperature): the process is
sensitive to temperature, the mass transfer through the boundary
layer is not as important. So the wafers may be stacked face to face
[Fig. 9-4 (b)]. 22
 Mass Delivery (cont.)

• For all reactant gases, same slope (Ea: 1.6 eV) suggesting that the rate limiting
surface reaction process is the same for each of the different sources and may be
related to the desorption of hydrogen atoms from the Si surface.
• Epitaxial Si conventionally at higher temperature to ensure that all the Si atoms
being deposited are incorporated into lattice sites in order to obtain a single-
crystal thin film. (mass transfer regime, where gas-phase processes are important.)
• On the other hand, poly-Si is usually deposited at low temperature and in the
surface reaction regime 23
Surface (Chemical) Reaction Rate

C.R. = A exp (-Ea/kT)

Ea
Precursor

 Byproduct

24
 Surface-Reaction-Limited Regime

• Chemical reaction rate can’t match precursor

diffusion and adsorption rates; precursors pile up
on the substrate surface and wait their turn to react.
• D.R. = C.R. [B] [C] []…
• Deposition rate is very sensitive to temperature

25
 Mass-Transport-Limited Regime

• When the surface chemical reaction rate is high

enough, the chemical precursors react immediately
when they adsorb on the substrate surface.
• Deposition rate = D dn/dx [B] [C] []…
• Deposition rate is insensitive to temperature
• Mainly controlled by gas flow rates

26
 Deposition Regimes
Mass-transport-limited Surface-reaction-
regime limited regime
ln D.R.

Slope = -E a /k

Gas-phase-nucleation
regime

1/ T
27
 Deposition Rage Regimes
Deposition rate

Dep. rate
insensitive to
temperature
Dep. rate
sensitive to
temperature

Temperature
28
 CVD Reactor Deposition Regime
• Most single wafer process reactors are designed
in mass-transport-limited regime
• It is easier to control the gas flow rate
• Plasma or unstable chemicals such as ozone are
used to achieve mass-transport-limited-regime at
relatively low temperature

29
 Momentum Delivery

 According to Fick first diffusion law:

stagnant boundary layer s
C C DG
F1  - DG  - DG  (CG - CS )  hG (CG - CS )
x x  S
 DG is the diffusion coefficient of the reacting species across the boundary layer
in the gas phase, hence hG=DG/s . m x 1/ 2
 S ( x)  ( )
hG is not necessarily constant. U 30
 Momentum Delivery

• To compensate for both the boundary-layer variation and depletion effects, a change in
reactor geometry is needed. Tilted wafer susceptor decreases the cross sectional area,
which causes the gas velocity to increases, then reduces the s.
• In LPCVD, temperature gradient (5o-25o) along the tube is used.
• In APCVD, gas is injected straight down from the above.
• CVD cannot be used for alloy, such as Al (2% Cu) due to unwanted reactions between
the different reactant species, or precursors. Usually, alloy is deposited by PVD. 31
 LPCVD

• Longer MFP
• Good step coverage & uniformity
• Vertical loading of wafer
• Fewer particles and increased productivity
• Less dependence on gas flow
• Vertical and horizontal furnace

32
Horizontal Conduction-Convection-
heated LPCVD
• Adaptation of horizontal tube furnace

– Low pressure: from 0.25 to 2 Torr

– Used mainly for polysilicon, silicon dioxide and
silicon nitride films
– Can process 200 wafers per batch

33
 LPCVD System
Pressure
Sensor Wafers

Heating Coils
Loading To Pump
Door

Quartz
Process Gas Inlet Wafer Boat Tube

Center Zone
Temperature
Flat Zone
Distance
34
 LPCVD (cont.)
• In LPCVD, a vacuum pump is needed to reduce and control the
pressure, usually in 0.25-2.0 torr range. (@300-900°C). Since it is a
surface control, the temperature must be controlled typically  1°C,
this is easily achieved in hot wall furnaces.
• To compensate the depletion, a 5-25°C temperature gradient is used
to speeds up the reaction rate toward the back of the tube. A
alternate reactant gases are injected at regular intervals down the
tube.
• Additional advantage for LPCVD: less autodoping occurs, little or
no carrier or dilutant gas is needed, fewer gas-phase reactions,
hence fewer particulate. Too low pressure will causes too low
deposition rate.

35
Step Coverage, Pressure and Surface
Mobility

APCVD LPCVD
High mobility
No mobility No mobility

36
 PECVD
• Developed when silicon nitride replaced silicon
dioxide for passivation layer.
• After depositing oxide on Al, temperature must be
less than about 450°C. (Al vaporized).
• PECVD by plasma, deposition can occur at
temperatures much lower
• High deposition rate at relatively low temp.
• RF induces plasma field in deposition gas
• Stress control by RF
• Chamber plasma clean.
37
 Plasma Enhanced CVD System
Process RF power
gases
Process
chamber
Plasma
Wafer

By-products to Heated plate

the pump
• Plasma, is sustained by applying a high electric field, often at 13.56 MHz,
to a low pressure gas (between 50 mtorr and 5 torr), creating ions and free electrons.
The plasma is sustained when high-energy electrons strike and ionize atoms and molecules.
• It includes ionized and excited molecules (or atoms), neutral and ionized fragments of
38
broken-up molecules, including free radicals
 PECVD (cont.)
• The net result from the plasma-induced fragmentation, free radical
generation, and ion bombardment is that the surface processes and
deposition can occur at much lower temperatures than in nonplasma
systems.
• The complexity and nonequilibrium  nonstoichimetric
compositions of the films (Si- or O-rich SiO2),
• Incorporation of H2, O2, and N2 is common and can result in
outgassing, peeling, or cracking of the film during subsequent
processing.
• Film density and stress may also vary, depending on the conditions
of the deposition.

39
 HDPCVD
Microwave
• HDP CVD : a very high-density plasma
and a separate RF bias applied on the
Magnet substrate.
coils Plasma • The high-density plasma can be
generated by a variety of sources,
Wafer
Magnetic including Electron Cyclotron
field line Resonance (ECR) and Inductive
Coupled Plasma (ICP). Temperature
is around 150°C at 1-10 mtorr.
E-chuck Bias RF • The ion bombardment raises the
substrate temperature and cooling is
Helium
needed <400°C.
ECR Chamber 40
 Electron Cyclotron Resonance
(ECR)
1. ECR is the coupling of microwave energy at the natural resonance
frequence of an electron gas in the presence of a static magnetic field.
電子迴旋共振是在靜磁場下使電子的迴旋頻率與微波共振而將為波
的能量耦合在一起
2. Resonance occurs when the electron cyclotron frequency equals the
excitation frequency.
共振在電子迴旋頻率與微波頻率相同時發生
ω＝eB/me
3. At the common microwave frequency of 2.45GHz,resonance occurs at the
B＝873Gauss.

41
 ECR-CVD
The spiral motion confines the electron 此一向外的螺旋形運動把電子侷限於氣體中.
to the gas, resulting in fewer diffusion 使得很少的電子擴散至腔壁而損失
losses to the wall at low pressures.
As a result, the electron can acquire
high energy before experiencing a
collision.結果電子在產生碰撞前可獲得高
能量。
Operation at low pressure allows efficient E
coupling of energy to the electrons so that Electron
ion/neutral collision are of sufficient trajectory
energy to induce ionization. B
在低壓下操作可使能量有效地耦合至電子此足夠
的能量才能在與氣體分子或離子碰撞中產生游離。
ECR effect is reduced at higher pressures
because increasing collision frequency
prevent electrons from achieving high energies.
在高壓下ECR效應會減低，因為碰撞頻率會增加
使得電子無法獲得較高的能量。 42
 High Density Inductively-Coupled
RF Reactors
• The time varying inductive magnetic field will induce an electric field.
• Lower voltage then capacitive-coupled reactors.
• Low pressure operation.(typical:1-10 m Torr)
• for a review see: J. Hopwood, Plasma Source Sci. Technol(1992) 109-116

B
 E  - 43
t
Inductively Coupled Plasma Chamber

Inductive coils Ceramic cover

Source RF

Plasma Wafer
Chamber body

E-chuck Bias RF
Helium

44
 High Density Plasma CVD

• HDP-CVD: deposition and sputtering etch at the

same time.
• USG for STI application
• USG and FSG for IMD applications
• PMD for PMD application

45
 High-Density Plasma CVD
• HDP-CVD: deposition and sputtering etch at the same time.
• Dep/etch/dep gap fill needs two chambers
• Narrower gaps may need more dep/etch cycles to fill
• A tool can deposit and sputtering etch simultaneously would
be greatly helpful
• USG for STI application
• USG and FSG for IMD applications
• PMD for PMD application

46
 In-situ Dep/Etch/Dep Process
Dep.
+ +
Ar Ar

Etch

Dep.

Metal
Sputtering Corner Chopping
47
 Dielectric CVD Precursors
• Silane (SiH4)
• TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4)

48
 CVD Precursor: Silane
• Dielectric CVD
– PECVD passivation dielectric depositions
– PMD barrier nitride layer
– Dielectric anti reflective coating (DARC)
– High density plasma CVD oxide processes
• LPCVD poly-Si and silicon nitride
• Metal CVD
– W CVD process for nucleation step
– Silicon source for WSix deposition
49
 Dielectric CVD Precursor: Silane
• Pyrophoric (ignite itself), explosive, and toxic
• Open silane line without thoroughly purging can
cause fire or minor explosion and dust line

50
Structure of Silane Molecule

H
H
H
H Si H
Si

H H

51
 CVD Precursor Adsorption: Silane
• Silane molecule is perfectly symmetrical
• Neither chemisorb nor physisorb
• Fragments of silane, SiH3, SiH2, or SiH, can easily
form chemical bonds with surface
• Low surface mobility, overhangs and poor step
coverage

52
 CVD Precursor Adsorption: TEOS
• TEOS (tetra-ethyl-oxy-silane, Si(OC2H5)4)
• Big organic molecule
• TEOS molecule is not perfectly symmetric
• Can form hydrogen bond and physisorb
• High surface mobility
• Good step coverage, conformality, and gap fill
• Widely used for oxide deposition
53
 H

H C H
TEOS Molecule
H C H

H H O H H

H C C O Si O C C H

H H O H H

H C H

H C H

H 54
 Applications of Dielectric Thin film

• Shallow trench isolation (STI, USG)

• Sidewall Spacer (USG)
• Pre-metal dielectric (PMD, PSG or BPSG)
• Inter-metal dielectric (IMD, USG or FSG)
• Anti-reflection coating (ARC, SiON)
• Passivation dielectric (PD, Oxide/Nitride)

55
 Shallow Trench Isolation (STI)
Grow pad oxide Etch nitride, Grow barrier CMP USG Strip nitride
Deposition nitride oxide and oxide Anneal USG and oxide
silicon
CVD USG
trench fill

USG USG USG

Si Si Si Si Si

56
Shallow Trench Isolation (STI)

57
 Sidewall Spacer Formation
Sidewall spacer
Oxide

Poly gate Poly gate

Substrate Substrate

•Lightly doped drain (LDD)

•Self aligned silicide (Salicide)

58
 PMD

• Doped oxide
• PSG or BPSG
• Phosphorus: gettering sodium and reduce flow
temperature.
• Boron: further reduces flow temperature without
excessive phosphorus

59
 Sodium Ion Turn-on the MOSFET

Sodium ions
VG = 0 VD VG = 0
Electron flow VD > 0

“Metal” Gate “Metal” Gate

SiO 2 Thin oxide -+ -+-+-+-+-+-+-+

+ + +
n n n n+
p-Si p-Si
Source Drain Source Drain

Electrons +
Normal off Turn on by Na

60
 PMD
• More phosphorus, lower reflow temperature
• >7wt% phosphorus, hygroscope
P2O5 + 3H2O  2H3PO4
• H3PO4 etches aluminum causes metal corrosion
• Too much boron will cause crystallization of boric
acid. H3BO3.
• Limit, P% + B% < 10%

61
 PSG Reflow at 1100 °C, N2, 20 min.

0% 2.2%

4.6% 7.2%

Source: VLSI Technology, by S.M. Sze

62
44 BPSG Reflow at 850 C, 30
Minutes in N2 Ambient

63
Development of PMD Processes

Dimension PMD Planarization Reflow temperature

> 2 mm PSG Reflow 1100C

2 - 0.35 mm BPSG Reflow 850 - 900C

0.25 mm BPSG Reflow + CMP 750C

0.18 mm PSG CMP -

64
 PMD Applications Roadmap
Feature Size 0.8 0.5 0.35 0.25 0.18
(mm)
Year 1989 1992 1995 1998 2000
Wafer Size 150 200 300
(mm)
O3-TEOS BPSG
Thermal Flow or RTP/CMP

O3-TEOS PSG + PE-PSG

APCVD Silane BPSG CMP
PE-TEOS BPSG
HDP PSG + PE-PSG
LPCVD BPSG
CMP
Thermal Flow Low-k Dielectric
CMP

65
 IMD

• Inter-metal dielectric
• Undoped silicate glass (USG) or FSG
• SOG
• Gap fill and planarization
• Temperature limited by metal melting
– Normally 400 °C
• PE-TEOS, O3-TEOS, and HDP
66
 TEOS
H

• Tetraethyloxysilane, H C H

Si(OC2H5)4 H C H

• Liquid silicon source H H O H H

H C C O Si O C C H
• Commonly used for
H H O H H
SiO2 deposition
H C H
• Good step coverage
H C H
and gap fill
H

67
 PE-TEOS
• Plasma-enhanced TEOS CVD processes
• TEOS and O2
• Most commonly used dielectric CVD process
• Deposit USG at ~400 °C
• Mainly for IMD

68
Spin-on Glass (SOG) Processes

METAL 4

IMD 3

METAL 3

IMD 2

69
 PE-TEOS

• PE-TEOS
Photo courtesy:
Applied Materials • Sputtering
etchback

• PE-TEOS

70
 O3-TEOS
• TEOS and Ozone

• O3  O2 + O (half-life time: 86 hours at 22 °C, <

1ms at 400 °C)
• O + TEOS  USG + other volatile byproducts

• Excellent step coverage and gap fill.

• Applied for IMD and PMD
71
 O3-TEOS vs PE-TEOS
PE-TEOS Ozone-TEOS

Step coverage: 50% Step coverage: 90%

Conformality: 87.5% Conformality: 100%
72
 Passivation

• Nitride and oxide

• Nitride is very good barrier layer, oxide help
nitride stick with metal
• Silane process
• NH3, N2 and nitrogen precursors, N2O as oxygen
precursor
• In-situ CVD process

73
 Thickness Measurement

• One of the most important measurements for

dielectric thin film processes.
• Determines
– Film deposition rate
– Wet etch rate
– Shrinkage

74
 Dielectric Thin Film Thickness
Measurement
Human eye or
Incident light photodetector
1
2

t Dielectric film, n( l )

Substrate

75
 Optical Measurements
Reflectometry Ellipsometry
Human eye or
photodetector Elliptically Polarized
Reflected Light
Incident light Linearly Polarized Incident Light
1
2
p
s
t Dielectric film n(l) n1, k1, t1
n2 ,k2
Substrate

• Spectrophotometers: light reflects and destructive interference will occur, the

index of refraction of the dielectric film must be known since it shows up
directly in above equation.
• Ellipsometry is a better method to measure both index of refraction and
thickness by polarized light. Commercially available ellipsometer can easily
measure films down to 1 nm in thickness.
• Simplest optical technique is using color charts. (10-20 nm to distinguishing).
76
 Uniformity
• Multi-point measurement
• Definition
x1  x2  x3      x N
• Average: x
N
• Standard deviation:

( x1 - x ) 2  ( x2 - x ) 2  ( x3 - x ) 2      ( x N - x ) 2
s
N -1

• Standard deviation non-uniformity: s/x

77
 Stress
• Mismatch between different materials
• Two kinds of stresses, intrinsic and extrinsic
• Intrinsic stress develops during the film
nucleation and growth process.
• The extrinsic stress results from differences in
the coefficients of thermal expansion
• Tensile stress: cracking film if too high
• Compressive stress: hillock if too strong
78
 Film Stress

Bare Wafer After Thin Film Deposition

Substrate Substrate
Substrate

Compressive Stress Tensile Stress

Negative curvature Positive curvature

79
 Illustration of Thermal Stress
At 400 °C
SiO2
L
Si

SiO2
Si At Room Temperature
L

L = a  T L
80
Coefficients of Thermal Expansion

a(SiO2) = 0.510-6 C-1

a(Si) = 2.510-6 C-1
a(Si3N4) = 2.810-6 C-1
a(W) = 4.510-6 C-1
a(Al) = 23.210-6 C-1

81
 Stress Measurement
2
E h 1 1
s ( - )
1 -  6t R2 R1

Wafer curvature change before and after thin film

deposition

Laser beam scans wafer surface, reflection light

indicates the wafer curvature
82
Stress Measurement
Detector
Mirror
Laser

83
 Dielectric CVD Processes
• Thermal Silane CVD Process
• Thermal TEOS CVD Process
• PECVD Silane Processes
• PECVD TEOS Processes
• Dielectric Etchback Processes
• O3-TEOS Processes
• Spin-on Glass
• High Density Plasma CVD
84
 Thermal Silane CVD Process
• Silane has been commonly used for silicon
dioxide deposition with both APCVD and
LPCVD process
heat

SiH4 + 2 O2  SiO2 + 2 H2O

• APCVD normally uses diluted silane (3% in
nitrogen) and LPCVD uses pure silane
• Not commonly used in the advanced fab
85
 Thermal TEOS CVD Process
• TEOS: physisorption, high surface mobility
• TEOS film has better step coverage
• LPCVD TEOS dissociates at high temp:
700 C
Si(OC2H5)4  SiO2 + volatile organics
• BPSG with TMB and TMP for PMD
• Temperature is too high for IMD
86
 PECVD Silane Processes
• Silane and N2O (laughing gas)
• Dissociation in plasma form SiH2 and O
• Radicals react rapidly to form silicon oxide
plasma
SiH4 + N2O  SiOxHy + H2O + N2 + NH3 + 
heat
• Overflow N2O, using SiH4 flow to control
deposition rate

87
 Passivation: Silicon Nitride
• Barrier layer for moisture and mobile ions
• The PECVD nitride
– Low deposition temperature (<450ºC)
– High deposition rate
– Silane, ammonia, and nitrogen
plasma
SiH4 + N2 + NH3  SiNxHy + H2 + N2 + NH3 + …
heat

• Requires good step coverage, high dep. rate, good

uniformity, and stress control

88
 Passivation Dielectric Deposition
• Stabilization 1 (stabilize pressure)
• Oxide deposition (stress buffer for nitride)
• Pump
• Stabilization 2 (stabilize pressure)
• Nitride deposition (passivation layer)
• Plasma purging (eliminate SiH4)
• Pump
89
 PMD Barrier Layer
• PSG or BPSG need a diffusion barrier layer
– USG (need 1000 Å )
– LPCVD nitride at ~700 ºC (~ 300 Å )
– PECVD nitride at <550 ºC (< 200 Å )
• At higher temperature, PECVD nitride film has
higher deposition rate, lower hydrogen
concentration, and better film quality
• Possible in future: remote plasma CVD

90
 Dielectric Anti-Reflective Coating
• High resolution for photolithography
• ARC layer is required to reduce the reflection
• Metallic ARC: TiN, 30% to 40% reflection
• No longer good enough for < 0.25 mm
• Dielectric ARC layer is used
– Spin-on before photoresist coating
– CVD

91
Dielectric Anti-Reflective Coating
UV light (l)  = 2nt = l/2
1
2
Photoresist

t Dielectric ARC, n, k

Aluminum alloy

92
 Dielectric ARC

• PECVD silane process

• N2O as oxygen and nitrogen source
plasma
SiH4 + N2O + He  SiOxNy + H2O + N2 + NH3 + He +
···
heat

93
 PE-TEOS
• Most widely used dielectric CVD process
• Fast
• Good uniformity
• Good step coverage

• Mainly used for IMD

94
 PE-TEOS

• USG process
Plasma
Si(OC2H5)4 + O2  SiO2 + other volatiles
400 ºC

• FGS process
plasma
FSi(OC2H5)3 + Si(OC2H5)4 + O2  SiOxFy + other volatile
(FTES) (TEOS) heat (FSG)

95
 FSG Process Trends

SiO2 SiOxFy (FSG) SiF4

solid solid gas

 = 3.9 3.8 <  < 3.2 ~ 1

higher k less F more F lower k, F outgassing

96
 Dielectric Etchback Processes

• Gap fill and planarization

• Performed in thin film bay with DCVD
• Cluster tool
• In-situ dep/etch/dep process

97
 Reactive Etch Back

• CF4 and O2
• Heavy bombardment with chemical reaction
• Applications
– Planarize dielectric surface
– SOG etch back

98
Reactive Etch Back Planarization

2 mm PE-TEOS oxide deposition

1 mm planarization etchback
99
 O3-TEOS Processes
• Ozone is a very unstable molecule,
O3  O2 + O
• At 400 C, half-lifetime of O3: < 1ms
• Used as carrier of free oxygen radicals
• Ozone reacts with TEOS form silicon oxide
• Excellent conformality and gap fill capability
• Sub-micron IC chip applications
• APCVD
100
 O3-TEOS USG Process
• TEOS + O3  SiO2 + volatile organics
heat

• Main applications
– STI (higher temperature, ~ 550 °C)
– IMD (~ 400 °C)

101
 O3-TEOS USG

Step coverage Gap fill

102
 O3-TEOS BPSG and PSG Process

O3  O2 + O

O + TEB + TEPO + TEOS  BPSG + volatile organics

heat

O + TEPO + TEOS  PSG + volatile organics

heat

• Main application
– PMD

103
 O3-TEOS BPSG
O 3 -TE O S
BPSG

B a rrier
N itride

S ilic ide

P oly S i

SACVD BPSG for 0.25 mm gap and 4:1 A/R.

104
 Spin-on Glass (SOG)

• Similar to PR coating and baking process

• People in fab like familiar technologies
• IMD gap fill and planarization
• Two kinds of spin-on glass:
– Silicate
– Siloxane

105
 Spin-on Glass: Silicate and Siloxane
H
R
O
H O Si O H
H O Si O H
R’
O
R = CH3, R’ = R or OH
H
Si(OH)4 RnSi(OH)4-n, n = 1, 2
Silicate Siloxane
106
Spin-on Glass Process Steps
PECVD USG
barrier layer

Spin-on glass

SOG cure

SOG
etchback

PECVD
USG cap
107
 HDP-CVD Processes
• For IMD Applications

• USG SiH4 + O2 + Ar  USG + H2O + Ar +…

• FSG SiH4 + SiF4 + O2 + Ar  FSG + volatiles

• For PMD Applications

• PSG SiH4 + PH3 + O2 + Ar  PSG + volatiles

108
 Silane PECVD Process Trends
• Increasing temperature increases deposition
rate
– Higher diffusion rate of precursors in boundary
layer
• Increasing temperature improves deposited step
coverage and film quality
• PMD uses a higher temperature
• IMD and PD, normally not exceed 400 ºC

109
Relationship of Deposition Rate and
RF Power

Ion bombardment
reduce adsorption

Free radicals
enhance reaction
RF power
110
Relationship of Deposition Rate and
Temperature

Dep. Rate
insensitive to
temperature
Dep. Rate
sensitive to
temperature

Temperature
111
 PE-TEOS Trends
• RF power: dep rate, compressive stress
– In process window, dep rate go down
• Temperature: dep rate
– In process window, dep rare go down
• TEOS flow: dep rate, compressive stress

112
PE-TEOS Trends: Temperature
Increasing Reducing
chemical adsorption rate
reaction rate

400 to 550 °C Temperature

113
 O3-TEOS Trends
• Temperature: dep rate
– In process window, dep rare go down
• TEOS flow: dep rate

114
 Typical W CVD Process
 Wafer transferred to chamber
 Temperature: 400 - 475 °C
 Step Coverage is 100 %
 Pressure and gas flows (H2, SiH4) established
 Nucleation takes place (silane reduction of WF6)
 Pressure and gas flows changed for bulk deposit
 Bulk deposit takes place (H2 reduction of WF6)
 Chamber pumped and purged
 Wafer transferred out of chamber

115
 W CVD Reactions
Nucleation on silicon
2 WF6 + 3 Si  2 W (s) + 3 SiF4
Nucleation on glue layer
2 WF6 + 3 SiH4  2 W (s) + 3 SiF4 + 6 H2
Bulk deposit
WF6 + 3 H2  W (s) + 6 HF
WF6 reaction with moisture
WF6 + 3 H2O  WO3 + 6 HF
116
 State of the Art

• HDP-CVD USG for STI

• Nitride or O3-TEOS oxide for sidewall spacer
• PECVD or RPCVD for PMD barrier nitride
• HDP-CVD PSG for PMD
• CMP for planarization
• Low- dielectric for IMD
• Silicon oxide/nitride as passivation dielectric

117
 State of the Art

• High- gate dielectric

• Possible candidates: TiO2, Ta2O5, and HfO2
• CVD and RTA

118
 State of the Art: Low- Dielectrics

• Need to reduce RC time delay

– low- reduces C and copper reduces R
• Require high thermal stability, high thermal conductivity,
and process integration capability
– CVD
• CSG (CxSiyO,  ~ 2.5 - 3.0) and a-CF (CxFy,  ~ 2.5 – 2.7)
– Spin-on dielectrics (SOD)
• Hydrogen silsequioxane (HSQ,  ~ 3.0),
• Porous SOD such as xerogels ( ~ 2.0 - 2.5)

119
 State of the Art: Low- Dielectrics

• Damascene process
• Copper metallization

• No gap fill, no planarization problem

• Main challenge: Integrate low- with copper
metallization

120
 Summary

• Applications of dielectric thin film are STI,

sidewall spacer, PMD, IMD and PD, in which
IMD application is the dominant one

• Silicon oxide and silicon nitride are the two most

commonly used dielectric materials

121
 Summary

• Basic CVD process sequence: introducing

precursor, precursor diffusion and adsorption,
chemical reaction, gaseous byproducts
desorption and diffusion
• Surface-reaction-limited regime
• Mass-transport-limited (MTL) regime
– Most dielectric CVD reactors operate in MTL
regime

122
 Summary

• PMD uses PSG or BPSG, temperature are

limited by thermal budget

• IMD mainly uses USG or FSG, temperature is

limited by aluminum melting point

• PD usually uses both oxide and nitride

123
 Summary

• Silane and TEOS are the two silicon sources for

dielectric CVD processes
• O2, N2O, and O3 are main oxygen precursors
• NH3 and N2 are the main nitrogen sources
• Fluorine chemistry is commonly used for
dielectric CVD chamber dry clean
– CF4, C2F6, C3F8 and NF3 are the most commonly
used fluorine source gases

124
 Summary

• Argon sputtering process is used for

dep/etch/dep gap fill application
• CF4/O2 etchback is used for planarization
• Compressive stress (~100 MPa) is favored for
the dielectric thin film

125
 Summary
• HDP CVD
– SiH4 and O2 to deposit oxide
– Ar for sputtering
– High aspect ratio gap fill
– ICP and ECR: most commonly used HDP sources
• Low- and copper for state-of-the-art
interconnections
• High- dielectric for gate insulator or DRAM
capacitor
126