CC1101

Low-Power Sub-1 GHz RF Transceiver

Applications
 Ultra low-power wireless applications  Wireless sensor networks
operating in the 315/433/868/915 MHz  AMR – Automatic Meter Reading
ISM/SRD bands  Home and building automation
 Wireless alarm and security systems  Wireless MBUS
 Industrial monitoring and control

Product Description
CC1101 is a low-cost sub-1 GHz transceiver microcontroller and a few additional passive
designed for very low-power wireless appli- components.
cations. The circuit is mainly intended for the
The CC1190 850-950 MHz range extender [21]
ISM (Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency bands can be used with CC1101 in long range
at 315, 433, 868, and 915 MHz, but can easily applications for improved sensitivity and higher
be programmed for operation at other output power.
frequencies in the 300-348 MHz, 387-464 MHz
and 779-928 MHz bands.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
20

19

18

17

16

supports various modulation formats and has

1 15

a configurable data rate up to 600 kbps.

CC1101
2 14

3 13

CC1101 provides extensive hardware support 4 12

for packet handling, data buffering, burst 5 11

transmissions, clear channel assessment, link

10
6

quality indication, and wake-on-radio.

The main operating parameters and the 64-
byte transmit/receive FIFOs of CC1101 can be
controlled via an SPI interface. In a typical
system, the CC1101 will be used together with a

SWRS061I Page 1 of 98
 CC1101

Key Features

RF Performance Low-Power Features

 200 nA sleep mode current consumption
 High sensitivity
 Fast startup time; 240 μs from sleep to RX
o -116 dBm at 0.6 kBaud, 433 MHz,
or TX mode (measured on EM reference
1% packet error rate
design [1] and [2])
o -112 dBm at 1.2 kBaud, 868 MHz,
1% packet error rate  Wake-on-radio functionality for automatic
low-power RX polling
 Low current consumption (14.7 mA in RX,
1.2 kBaud, 868 MHz)  Separate 64-byte RX and TX data FIFOs
(enables burst mode data transmission)
 Programmable output power up to +12
dBm for all supported frequencies
 Excellent receiver selectivity and blocking General
performance  Few external components; Completely on-
 Programmable data rate from 0.6 to 600 chip frequency synthesizer, no external
kbps filters or RF switch needed
 Frequency bands: 300-348 MHz, 387-464  Green package: RoHS compliant and no
MHz and 779-928 MHz antimony or bromine
 Small size (QLP 4x4 mm package, 20
Analog Features pins)
 Suited for systems targeting compliance
 2-FSK, 4-FSK, GFSK, and MSK supported
with EN 300 220 (Europe) and FCC CFR
as well as OOK and flexible ASK shaping
Part 15 (US)
 Suitable for frequency hopping systems
 Suited for systems targeting compliance
due to a fast settling frequency
with the Wireless MBUS standard
synthesizer; 75 μs settling time
EN 13757-4:2005
 Automatic Frequency Compensation
 Support for asynchronous and
(AFC) can be used to align the frequency
synchronous serial receive/transmit mode
synthesizer to the received signal centre
for backwards compatibility with existing
frequency
radio communication protocols
 Integrated analog temperature sensor
Improved Range using CC1190
Digital Features
 The CC1190 [21] is a range extender for
 Flexible support for packet oriented
850-950 MHz and is an ideal fit for CC1101
systems; On-chip support for sync word
to enhance RF performance
detection, address check, flexible packet
length, and automatic CRC handling  High sensitivity
o -118 dBm at 1.2 kBaud, 868 MHz,
 Efficient SPI interface; All registers can be
1% packet error rate
programmed with one “burst” transfer
o -120 dBm at 1.2 kBaud, 915 MHz,
 Digital RSSI output
1% packet error rate
 Programmable channel filter bandwidth
 +20 dBm output power at 868 MHz
 Programmable Carrier Sense (CS)
 +27 dBm output power at 915 MHz
indicator
 Refer to AN094 [22] and AN096 [23] for
 Programmable Preamble Quality Indicator
more performance figures of the CC1101 +
(PQI) for improved protection against false
sync word detection in random noise CC1190 combination
 Support for automatic Clear Channel
Assessment (CCA) before transmitting (for
listen-before-talk systems)
 Support for per-package Link Quality
Indication (LQI)
 Optional automatic whitening and de-
whitening of data

SWRS061I Page 2 of 98
 CC1101

Reduced Battery Current using battery is typically 22 mA when TPS62730

TPS62730 output voltage is 2.1 V. When connecting
CC1101 directly to a 3.6 V battery the
 The TPS62730 [26] is a step down current drawn is typically 34 mA (see
converter with bypass mode for ultra low Figure 2).
power wireless applications.  When CC1101 enters SLEEP mode, the
 In RX, the current drawn from a 3.6 V TPS62730 can be put in bypass mode for
battery is typically less than 11 mA when very low power down current
TPS62730 output voltage is 2.1 V. When  The typical TPS62730 current consumption
connecting CC1101 directly to a 3.6 V is 30 nA in bypass mode.
battery the current drawn is typically 17  The CC1101 is connected to the battery via
mA (see Figure 1) an integrated 2.1 Ω (typical) switch in
 In TX, at maximum output power (+12 bypass mode
dBm), the current drawn from a 3.6 V

Figure 1: Typical RX Battery Current vs Battery Voltage

Figure 2: Typical TX Battery Current vs Battery Voltage at Maximum CC1101 Output Power (+12
dBm)

SWRS061I Page 3 of 98
 CC1101

Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK Binary Frequency Shift Keying MSB Most Significant Bit
4-FSK Quaternary Frequency Shift Keying MSK Minimum Shift Keying
ACP Adjacent Channel Power N/A Not Applicable
ADC Analog to Digital Converter NRZ Non Return to Zero (Coding)
AFC Automatic Frequency Compensation OOK On-Off Keying
AGC Automatic Gain Control PA Power Amplifier
AMR Automatic Meter Reading PCB Printed Circuit Board
ASK Amplitude Shift Keying PD Power Down
BER Bit Error Rate PER Packet Error Rate
BT Bandwidth-Time product PLL Phase Locked Loop
CCA Clear Channel Assessment POR Power-On Reset
CFR Code of Federal Regulations PQI Preamble Quality Indicator
CRC Cyclic Redundancy Check PQT Preamble Quality Threshold
CS Carrier Sense PTAT Proportional To Absolute Temperature
CW Continuous Wave (Unmodulated Carrier) QLP Quad Leadless Package
DC Direct Current QPSK Quadrature Phase Shift Keying
DVGA Digital Variable Gain Amplifier RC Resistor-Capacitor
ESR Equivalent Series Resistance RF Radio Frequency
FCC Federal Communications Commission RSSI Received Signal Strength Indicator
FEC Forward Error Correction RX Receive, Receive Mode
FIFO First-In-First-Out SAW Surface Aqustic Wave
FHSS Frequency Hopping Spread Spectrum SMD Surface Mount Device
FS Frequency Synthesizer SNR Signal to Noise Ratio
GFSK Gaussian shaped Frequency Shift Keying SPI Serial Peripheral Interface
IF Intermediate Frequency SRD Short Range Devices
I/Q In-Phase/Quadrature TBD To Be Defined
ISM Industrial, Scientific, Medical T/R Transmit/Receive
LC Inductor-Capacitor TX Transmit, Transmit Mode
LNA Low Noise Amplifier UHF Ultra High frequency
LO Local Oscillator VCO Voltage Controlled Oscillator
LSB Least Significant Bit WOR Wake on Radio, Low power polling
LQI Link Quality Indicator XOSC Crystal Oscillator
MCU Microcontroller Unit XTAL Crystal

SWRS061I Page 4 of 98
 CC1101

Table Of Contents
APPLICATIONS .................................................................................................................................................. 1
PRODUCT DESCRIPTION ................................................................................................................................ 1
KEY FEATURES ................................................................................................................................................. 2
RF PERFORMANCE .......................................................................................................................................... 2
ANALOG FEATURES ........................................................................................................................................ 2
DIGITAL FEATURES......................................................................................................................................... 2
LOW-POWER FEATURES ................................................................................................................................ 2
GENERAL ............................................................................................................................................................ 2
IMPROVED RANGE USING CC1190 .............................................................................................................. 2
REDUCED BATTERY CURRENT USING TPS62730 .................................................................................... 3
ABBREVIATIONS ............................................................................................................................................... 4
TABLE OF CONTENTS ..................................................................................................................................... 5
1 ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 8
2 OPERATING CONDITIONS ................................................................................................................. 8
3 GENERAL CHARACTERISTICS ......................................................................................................... 8
4 ELECTRICAL SPECIFICATIONS ....................................................................................................... 9
4.1 CURRENT CONSUMPTION ............................................................................................................................ 9
4.2 RF RECEIVE SECTION ................................................................................................................................ 12
4.3 RF TRANSMIT SECTION ............................................................................................................................. 16
4.4 CRYSTAL OSCILLATOR .............................................................................................................................. 18
4.5 LOW POWER RC OSCILLATOR ................................................................................................................... 18
4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS .......................................................................................... 19
4.7 ANALOG TEMPERATURE SENSOR .............................................................................................................. 19
4.8 DC CHARACTERISTICS .............................................................................................................................. 20
4.9 POWER-ON RESET ..................................................................................................................................... 20
5 PIN CONFIGURATION ........................................................................................................................ 20
6 CIRCUIT DESCRIPTION .................................................................................................................... 22
7 APPLICATION CIRCUIT .................................................................................................................... 22
7.1 BIAS RESISTOR .......................................................................................................................................... 22
7.2 BALUN AND RF MATCHING ....................................................................................................................... 23
7.3 CRYSTAL ................................................................................................................................................... 23
7.4 REFERENCE SIGNAL .................................................................................................................................. 23
7.5 ADDITIONAL FILTERING ............................................................................................................................ 24
7.6 POWER SUPPLY DECOUPLING .................................................................................................................... 24
7.7 ANTENNA CONSIDERATIONS ..................................................................................................................... 24
7.8 PCB LAYOUT RECOMMENDATIONS ........................................................................................................... 26
8 CONFIGURATION OVERVIEW ........................................................................................................ 27
9 CONFIGURATION SOFTWARE ........................................................................................................ 29
10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE .................................................. 29
10.1 CHIP STATUS BYTE ................................................................................................................................... 31
10.2 REGISTER ACCESS ..................................................................................................................................... 31
10.3 SPI READ .................................................................................................................................................. 32
10.4 COMMAND STROBES ................................................................................................................................. 32
10.5 FIFO ACCESS ............................................................................................................................................ 32
10.6 PATABLE ACCESS ................................................................................................................................... 33
11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION .......................................... 34
11.1 CONFIGURATION INTERFACE ..................................................................................................................... 34
11.2 GENERAL CONTROL AND STATUS PINS ..................................................................................................... 34
11.3 OPTIONAL RADIO CONTROL FEATURE ...................................................................................................... 34
12 DATA RATE PROGRAMMING.......................................................................................................... 35

SWRS061I Page 5 of 98
 CC1101
13 RECEIVER CHANNEL FILTER BANDWIDTH .............................................................................. 35
14 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION .................................. 36
14.1 FREQUENCY OFFSET COMPENSATION........................................................................................................ 36
14.2 BIT SYNCHRONIZATION ............................................................................................................................. 36
14.3 BYTE SYNCHRONIZATION .......................................................................................................................... 36
15 PACKET HANDLING HARDWARE SUPPORT .............................................................................. 37
15.1 DATA WHITENING ..................................................................................................................................... 37
15.2 PACKET FORMAT ....................................................................................................................................... 38
15.3 PACKET FILTERING IN RECEIVE MODE ...................................................................................................... 40
15.4 PACKET HANDLING IN TRANSMIT MODE ................................................................................................... 40
15.5 PACKET HANDLING IN RECEIVE MODE ..................................................................................................... 41
15.6 PACKET HANDLING IN FIRMWARE ............................................................................................................. 41
16 MODULATION FORMATS ................................................................................................................. 42
16.1 FREQUENCY SHIFT KEYING ....................................................................................................................... 42
16.2 MINIMUM SHIFT KEYING........................................................................................................................... 43
16.3 AMPLITUDE MODULATION ........................................................................................................................ 43
17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ............................ 43
17.1 SYNC WORD QUALIFIER ............................................................................................................................ 43
17.2 PREAMBLE QUALITY THRESHOLD (PQT) .................................................................................................. 44
17.3 RSSI .......................................................................................................................................................... 44
17.4 CARRIER SENSE (CS)................................................................................................................................. 46
17.5 CLEAR CHANNEL ASSESSMENT (CCA) ..................................................................................................... 48
17.6 LINK QUALITY INDICATOR (LQI) .............................................................................................................. 48
18 FORWARD ERROR CORRECTION WITH INTERLEAVING ..................................................... 48
18.1 FORWARD ERROR CORRECTION (FEC)...................................................................................................... 48
18.2 INTERLEAVING .......................................................................................................................................... 49
19 RADIO CONTROL ................................................................................................................................ 50
19.1 POWER-ON START-UP SEQUENCE ............................................................................................................. 50
19.2 CRYSTAL CONTROL ................................................................................................................................... 51
19.3 VOLTAGE REGULATOR CONTROL.............................................................................................................. 52
19.4 ACTIVE MODES (RX AND TX)................................................................................................................... 52
19.5 WAKE ON RADIO (WOR) .......................................................................................................................... 53
19.6 TIMING ...................................................................................................................................................... 54
19.7 RX TERMINATION TIMER .......................................................................................................................... 55
20 DATA FIFO ............................................................................................................................................ 56
21 FREQUENCY PROGRAMMING ........................................................................................................ 57
22 VCO ......................................................................................................................................................... 58
22.1 VCO AND PLL SELF-CALIBRATION .......................................................................................................... 58
23 VOLTAGE REGULATORS ................................................................................................................. 58
24 OUTPUT POWER PROGRAMMING ................................................................................................ 59
25 SHAPING AND PA RAMPING ............................................................................................................ 60
26 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS ............................................................. 61
27 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION .............................................. 63
27.1 ASYNCHRONOUS SERIAL OPERATION ........................................................................................................ 63
27.2 SYNCHRONOUS SERIAL OPERATION .......................................................................................................... 63
28 SYSTEM CONSIDERATIONS AND GUIDELINES ......................................................................... 64
28.1 SRD REGULATIONS ................................................................................................................................... 64
28.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS ............................................................................ 64
28.3 WIDEBAND MODULATION WHEN NOT USING SPREAD SPECTRUM ............................................................. 65
28.4 WIRELESS MBUS ...................................................................................................................................... 65
28.5 DATA BURST TRANSMISSIONS................................................................................................................... 65
28.6 CONTINUOUS TRANSMISSIONS .................................................................................................................. 65
28.7 BATTERY OPERATED SYSTEMS ................................................................................................................. 66
28.8 INCREASING RANGE .................................................................................................................................. 66

SWRS061I Page 6 of 98
 CC1101
29 CONFIGURATION REGISTERS ........................................................................................................ 66
29.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ............... 71
29.2 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE ......... 91
29.3 STATUS REGISTER DETAILS....................................................................................................................... 92
30 SOLDERING INFORMATION ............................................................................................................ 95
31 DEVELOPMENT KIT ORDERING INFORMATION ..................................................................... 95
32 REFERENCES ....................................................................................................................................... 96
33 GENERAL INFORMATION ................................................................................................................ 97
33.1 DOCUMENT HISTORY ................................................................................................................................ 97

SWRS061I Page 7 of 98
 CC1101

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.
Parameter Min Max Units Condition
Supply voltage –0.3 3.9 V All supply pins must have the same voltage
Voltage on any digital pin –0.3 VDD + 0.3, V
max 3.9

Voltage on the pins RF_P, RF_N, –0.3 2.0 V

DCOUPL, RBIAS
Voltage ramp-up rate 120 kV/µs
Input RF level +10 dBm
Storage temperature range –50 150 C
Solder reflow temperature 260 C According to IPC/JEDEC J-STD-020

ESD 750 V According to JEDEC STD 22, method A114,

Human Body Model (HBM)
ESD 400 V According to JEDEC STD 22, C101C,
Charged Device Model (CDM)

Table 1: Absolute Maximum Ratings

Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.

2 Operating Conditions
The operating conditions for CC1101 are listed Table 2 in below.
Parameter Min Max Unit Condition
Operating temperature -40 85 C
Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

Table 2: Operating Conditions

3 General Characteristics
Parameter Min Typ Max Unit Condition/Note
Frequency 300 348 MHz
range
387 464 MHz If using a 27 MHz crystal, the lower frequency limit for
this band is 392 MHz
779 928 MHz
Data rate 0.6 500 kBaud 2-FSK
0.6 250 kBaud GFSK, OOK, and ASK
0.6 300 kBaud 4-FSK (the data rate in kbps will be twice the baud rate)
26 500 kBaud (Shaped) MSK (also known as differential offset QPSK).

Optional Manchester encoding (the data rate in kbps will

be half the baud rate)

Table 3: General Characteristics

SWRS061I Page 8 of 98
 CC1101

4 Electrical Specifications
4.1 Current Consumption
TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs
([1] and [2]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost
of a reduction in sensitivity. See Table 7 for additional details on current consumption and sensitivity.

Parameter Min Typ Max Unit Condition

Current consumption in power 0.2 1 A Voltage regulator to digital part off, register values retained
down modes (SLEEP state). All GDO pins programmed to 0x2F (HW to 0)
0.5 A Voltage regulator to digital part off, register values retained, low-
power RC oscillator running (SLEEP state with WOR enabled)
100 A Voltage regulator to digital part off, register values retained,
XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

165 A Voltage regulator to digital part on, all other modules in power
down (XOFF state)
Current consumption 8.8 A Automatic RX polling once each second, using low-power RC
oscillator, with 542 kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level (MCSM2.RX_TIME_RSSI=1)

35.3 A Same as above, but with signal in channel above carrier sense
level, 1.96 ms RX timeout, and no preamble/sync word found
1.4 A Automatic RX polling every 15th second, using low-power RC
oscillator, with 542 kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level (MCSM2.RX_TIME_RSSI=1)

39.3 A Same as above, but with signal in channel above carrier sense
level, 36.6 ms RX timeout, and no preamble/sync word found
1.7 mA Only voltage regulator to digital part and crystal oscillator running
(IDLE state)
8.4 mA Only the frequency synthesizer is running (FSTXON state). This
currents consumption is also representative for the other
intermediate states when going from IDLE to RX or TX, including
the calibration state
Current consumption, 15.4 mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity
315 MHz limit
14.4 mA Receive mode, 1.2 kBaud, register settings optimized for
reduced current, input well above sensitivity limit
15.2 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input at sensitivity limit
14.3 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input well above sensitivity limit
16.5 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input at sensitivity limit
15.1 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input well above sensitivity limit
27.4 mA Transmit mode, +10 dBm output power
15.0 mA Transmit mode, 0 dBm output power
12.3 mA Transmit mode, –6 dBm output power

SWRS061I Page 9 of 98
 CC1101

Parameter Min Typ Max Unit Condition

Current consumption, 16.0 mA Receive mode, 1.2 kBaud, register settings optimized for reduced
433 MHz current, input at sensitivity limit
15.0 mA Receive mode, 1.2 kBaud, register settings optimized for reduced
current, input well above sensitivity limit
15.7 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input at sensitivity limit
15.0 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input well above sensitivity limit
17.1 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input at sensitivity limit
15.7 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input well above sensitivity limit
29.2 mA Transmit mode, +10 dBm output power
16.0 mA Transmit mode, 0 dBm output power
13.1 mA Transmit mode, –6 dBm output power
Current consumption, 15.7 mA Receive mode, 1.2 kBaud, register settings optimized for
868/915 MHz reduced current, input at sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
14.7 mA Receive mode, 1.2 kBaud, register settings optimized for
reduced current, input well above sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
15.6 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input at sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
14.6 mA Receive mode, 38.4 kBaud, register settings optimized for
reduced current, input well above sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
16.9 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input at sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
15.6 mA Receive mode, 250 kBaud, register settings optimized for
reduced current, input well above sensitivity limit.
See Figure 3 for current consumption with register settings
optimized for sensitivity.
34.2 mA Transmit mode, +12 dBm output power, 868 MHz
30.0 mA Transmit mode, +10 dBm output power, 868 MHz
16.8 mA Transmit mode, 0 dBm output power, 868 MHz
16.4 mA Transmit mode, –6 dBm output power, 868 MHz.
33.4 mA Transmit mode, +11 dBm output power, 915 MHz
30.7 mA Transmit mode, +10 dBm output power, 915 MHz
17.2 mA Transmit mode, 0 dBm output power, 915 MHz
17.0 mA Transmit mode, –6 dBm output power, 915 MHz

Table 4: Current Consumption

SWRS061I Page 10 of 98
 CC1101
Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Current [mA], PATABLE=0xC0,
32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5
+12 dBm
Current [mA], PATABLE=0xC5,
30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6
+10 dBm
Current [mA], PATABLE=0x50,
16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.7
0 dBm

Table 5: Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz

Supply Voltage Supply Voltage Supply Voltage

VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Current [mA], PATABLE=0xC0,
31.9 30.7 29.8 34.6 33.4 32.5 34.8 33.6 32.7
+11 dBm
Current [mA], PATABLE=0xC3,
30.9 29.8 28.9 31.7 30.7 30.0 31.9 31.0 30.2
+10 dBm
Current [mA], PATABLE=0x8E,
17.2 16.8 16.4 17.6 17.2 16.9 17.8 17.4 17.1
0 dBm

Table 6: Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz

17,8 19,5
17,6
19
17,4
Current [mA]

Current [mA]

-40C 18,5 -40C

17,2
17 +25C 18 +25C
16,8 +85C +85C
17,5
16,6
16,4 17
16,2 16,5
-110 -90 -70 -50 -30 -10 -100 -80 -60 -40 -20
Input Power Level [dBm] Input Power Level [dBm]

1.2 kBaud GFSK 250 kBaud GFSK

17,8 19,5
17,6
19,0
17,4
Current [mA]

Current [mA]

17,2 -40C 18,5 -40C

17,0 +25C +25C
16,8 +85C 18,0 +85C
16,6
17,5
16,4
16,2 17,0
-100 -80 -60 -40 -20 -90 -70 -50 -30 -10
Input Power Level [dBm] Input Power Level [dBm]

38.4 kBaud GFSK 500 kBaud MSK

Figure 3: Typical RX Current Consumption over Temperature and Input Power Level,
868/915 MHz, Sensitivity Optimized Setting

SWRS061I Page 11 of 98
 CC1101
4.2 RF Receive Section
TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs
([1] and [2]).

Parameter Min Typ Max Unit Condition/Note

Digital channel filter 58 812 kHz User programmable. The bandwidth limits are proportional to
bandwidth crystal frequency (given values assume a 26.0 MHz crystal)
Spurious emissions -68 –57 dBm 25 MHz – 1 GHz
(Maximum figure is the ETSI EN 300 220 limit)
-66 –47 dBm Above 1 GHz
(Maximum figure is the ETSI EN 300 220 limit)
Typical radiated spurious emission is -49 dBm measured at the
VCO frequency
RX latency 9 bit Serial operation. Time from start of reception until data is
available on the receiver data output pin is equal to 9 bit

315 MHz
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity -111 dBm Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 17.2 mA to 15.4 mA at the
sensitivity limit. The sensitivity is typically reduced to -109 dBm
500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity -88 dBm MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates >
250 kBaud

433 MHz
0.6 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 14.3 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity -116 dBm
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity -112 dBm Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 18.0 mA to 16.0 mA at the
sensitivity limit. The sensitivity is typically reduced to -110 dBm
38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver sensitivity –104 dBm
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)
Receiver sensitivity -95 dBm

868/915 MHz
1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity –112 dBm Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 17.7 mA to 15.7 mA at
sensitivity limit. The sensitivity is typically reduced to -109 dBm
Saturation –14 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8]
Adjacent channel Desired channel 3 dB above the sensitivity limit.
rejection 100 kHz channel spacing
±100 kHz offset 37 dB See Figure 4 for selectivity performance at other offset
frequencies
Image channel 31 dB IF frequency 152 kHz
rejection Desired channel 3 dB above the sensitivity limit

SWRS061I Page 12 of 98
 CC1101
Parameter Min Typ Max Unit Condition/Note
Blocking Desired channel 3 dB above the sensitivity limit
±2 MHz offset -50 dBm See Figure 4 for blocking performance at other offset
±10 MHz offset -40 dBm frequencies
38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver sensitivity –104 dBm Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 17.7 mA to 15.6 mA at the
sensitivity limit. The sensitivity is typically reduced to -102
dBm
Saturation –16 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8]
Adjacent channel rejection Desired channel 3 dB above the sensitivity limit.
-200 kHz offset 12 dB 200 kHz channel spacing
+200 kHz offset 25 dB See Figure 5 for blocking performance at other offset
frequencies
Image channel rejection 23 dB IF frequency 152 kHz
Desired channel 3 dB above the sensitivity limit
Blocking Desired channel 3 dB above the sensitivity limit
±2 MHz offset -50 dBm See Figure 5 for blocking performance at other offset
±10 MHz offset -40 dBm frequencies
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)
Receiver sensitivity –95 dBm Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 18.9 mA to 16.9 mA at the
sensitivity limit. The sensitivity is typically reduced to -91 dBm
Saturation –17 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8]
Adjacent channel rejection 25 dB Desired channel 3 dB above the sensitivity limit.
750 kHz channel spacing
See Figure 6 for blocking performance at other offset
frequencies
Image channel rejection 14 dB IF frequency 304 kHz
Desired channel 3 dB above the sensitivity limit
Blocking Desired channel 3 dB above the sensitivity limit
±2 MHz offset -50 dBm See Figure 6 for blocking performance at other offset
±10 MHz offset -40 dBm frequencies
500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity –90 dBm MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data
rates > 250 kBaud
Image channel rejection 1 dB IF frequency 355 kHz
Desired channel 3 dB above the sensitivity limit
Blocking Desired channel 3 dB above the sensitivity limit
±2 MHz offset -50 dBm See Figure 7 for blocking performance at other offset
±10 MHz offset -40 dBm frequencies
4-FSK, 125 kBaud data rate (250 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(1% packet error rate, 20 bytes packet length, 127 kHz deviation, 406 kHz digital channel filter bandwidth)
Receiver sensitivity -96 dBm
4-FSK, 250 kBaud data rate (500 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(1% packet error rate, 20 bytes packet length, 254 kHz deviation, 812 kHz digital channel filter bandwidth)
Receiver sensitivity -91 dBm
4-FSK, 300 kBaud data rate (600 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(1% packet error rate, 20 bytes packet length, 228 kHz deviation, 812 kHz digital channel filter bandwidth)
Receiver sensitivity -89 dBm

Table 7: RF Receive Section

SWRS061I Page 13 of 98
 CC1101
Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Sensitivity [dBm]
-113 -112 -110 -113 -112 -110 -113 -112 -110
1.2 kBaud
Sensitivity [dBm]
-105 -104 -102 -105 -104 -102 -105 -104 -102
38.4 kBaud
Sensitivity [dBm]
-97 -96 -92 -97 -95 -92 -97 -94 -92
250 kBaud
Sensitivity [dBm]
-91 -90 -86 -91 -90 -86 -91 -90 -86
500 kBaud

Table 8: Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized
Setting

Supply Voltage Supply Voltage Supply Voltage

VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Sensitivity [dBm]
-113 -112 -110 -113 -112 -110 -113 -112 -110
1.2 kBaud
Sensitivity [dBm]
-105 -104 -102 -104 -104 -102 -105 -104 -102
38.4 kBaud
Sensitivity [dBm]
-97 -94 -92 -97 -95 -92 -97 -95 -92
250 kBaud
Sensitivity [dBm]
-91 -89 -86 -91 -90 -86 -91 -89 -86
500 kBaud

Table 9: Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized
Setting

80 60

70
50
60

50 40

40
Selectivity [dB]
Blocking [dB]

30

30

20
20

10 10

0
-40 -30 -20 -10 0 10 20 30 40 0
-10 -1 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

-20 -10
Offset [MHz] Offset [MHz]

Figure 4: Typical Selectivity at 1.2 kBaud Data Rate, 868.3 MHz, GFSK, 5.2 kHz Deviation. IF
Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz

SWRS061I Page 14 of 98
 CC1101

70 50

60
40

50

30
40

Selectivity [dB]
Blocking [dB]

20
30

20
10

10
0
-1 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
0
-40 -30 -20 -10 0 10 20 30 40
-10
-10

-20 -20
Offset [MHz] Offset [MHz]

Figure 5: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, GFSK, 20 kHz Deviation. IF
Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz

60 50

50
40

40
30

30
Selectivity [dB]
Blocking [dB]

20

20

10
10

0
0 -2 -1,5 -1 -0,5 0 0,5 1 1,5 2
-40 -30 -20 -10 0 10 20 30 40

-10 -10

-20 -20
Offset [MHz] Offset [MHz]

Figure 6: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 304 kHz and
the Digital Channel Filter Bandwidth is 540 kHz

60 40

50

30
40

30 20
Selectivity [dB]
Blocking [dB]

20

10
10

0 0
-40 -30 -20 -10 0 10 20 30 40 -2 -1,5 -1 -0,5 0 0,5 1 1,5 2
-10

-10
-20

-30 -20
Offset [MHz]
Offset [MHz]

Figure 7: Typical Selectivity at 500 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 355 kHz and
the Digital Channel Filter Bandwidth is 812 kHz

SWRS061I Page 15 of 98
 CC1101
4.3 RF Transmit Section
TA = 25C, VDD = 3.0 V, +10 dBm if nothing else stated. All measurement results are obtained using the CC1101EM reference
designs ([1] and [2]).

Parameter Min Typ Max Unit Condition/Note

Differential load Differential impedance as seen from the RF-port (RF_P and
impedance RF_N) towards the antenna. Follow the CC1101EM reference
designs ([1] and [2]) available from the TI website
315 MHz 122 + j31 
433 MHz 116 + j41 
868/915 MHz 86.5 + j43 
Output power, Output power is programmable, and full range is available in all
highest setting frequency bands. Output power may be restricted by
regulatory limits.
315 MHz +10 dBm
See Design Note DN013 [15] for output power and harmonics
433 MHz +10 dBm figures when using multi-layer inductors. The output power is
868 MHz +12 dBm then typically +10 dBm when operating at 868/915 MHz.

915 MHz +11 dBm Delivered to a 50  single-ended load via CC1101EM

reference designs ([1] and [2]) RF matching network
Output power, lowest -30 dBm Output power is programmable, and full range is available in all
setting frequency bands
Delivered to a 50 single-ended load via CC1101EM
reference designs ([1] and [2]) RF matching network
Harmonics, radiated Measured on CC1101EM reference designs ([1] and [2]) with
CW, maximum output power
2nd Harm, 433 MHz -49 dBm The antennas used during the radiated measurements
3rd Harm, 433 MHz -40 dBm (SMAFF-433 from R.W. Badland and Nearson S331 868/915)
play a part in attenuating the harmonics
2nd Harm, 868 MHz -47 dBm
3rd Harm, 868 MHz -55 dBm

2nd Harm, 915 MHz -50 dBm Note: All harmonics are below -41.2 dBm when operating in
3rd Harm, 915 MHz -54 dBm the 902 – 928 MHz band
Harmonics, conducted
Measured with +10 dBm CW at 315 MHz and 433 MHz
315 MHz < -35 dBm Frequencies below 960 MHz
< -53 dBm Frequencies above 960 MHz

433 MHz -43 dBm Frequencies below 1 GHz

< -45 dBm Frequencies above 1 GHz

868 MHz
2nd Harm -36 dBm Measured with +12 dBm CW at 868 MHz
other harmonics < -46 dBm

915 MHz
2nd Harm -34 dBm Measured with +11 dBm CW at 915 MHz (requirement is -20
dBc under FCC 15.247)
other harmonics < -50 dBm

SWRS061I Page 16 of 98
 CC1101

Parameter Min Typ Max Unit Condition/Note

Spurious emissions
conducted, harmonics
not included
Measured with +10 dBm CW at 315 MHz and 433 MHz
315 MHz < -58 dBm Frequencies below 960 MHz
< -53 dBm Frequencies above 960 MHz

433 MHz < -50 dBm Frequencies below 1 GHz

< -54 dBm Frequencies above 1 GHz
< -56 dBm Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz

Measured with +12 dBm CW at 868 MHz

868 MHz < -50 dBm Frequencies below 1 GHz
< -52 dBm Frequencies above 1 GHz
< -53 dBm Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz

All radiated spurious emissions are within the limits of ETSI.

The peak conducted spurious emission is -53 dBm at 699 MHz
(868 MHz – 169 MHz), which is in a frequency band limited to
-54 dBm by EN 300 220. An alternative filter can be used to
reduce the emission at 699 MHz below -54 dBm, for conducted
measurements, and is shown in Figure 11. See more
information in DN017 [9].
For compliance with modulation bandwidth requirements under
EN 300 220 in the 863 to 870 MHz frequency range it is
recommended to use a 26 MHz crystal for frequencies below
869 MHz and a 27 MHz crystal for frequencies above 869
MHz.

Measured with +11 dBm CW at 915 MHz

915 MHz < -51 dBm Frequencies below 960 MHz
< -54 dBm Frequencies above 960 MHz
TX latency 8 bit Serial operation. Time from sampling the data on the
transmitter data input pin until it is observed on the RF output
ports

Table 10: RF Transmit Section

Supply Voltage Supply Voltage Supply Voltage

VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Output Power [dBm],
12 11 10 12 12 11 12 12 11
PATABLE=0xC0, +12 dBm
Output Power [dBm],
11 10 9 11 10 10 11 10 10
PATABLE=0xC5, +10 dBm
Output Power [dBm],
1 0 -1 2 1 0 2 1 0
PATABLE=0x50, 0 dBm

Table 11: Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz

Supply Voltage Supply Voltage Supply Voltage

VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Output Power [dBm],
11 10 10 12 11 11 12 11 11
PATABLE=0xC0, +11 dBm
Output Power [dBm],
2 1 0 2 1 0 2 1 0
PATABLE=0x8E, +0 dBm

Table 12: Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz

SWRS061I Page 17 of 98
 CC1101
4.4 Crystal Oscillator
TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1]
and [2]).

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz For compliance with modulation bandwidth requirements under
EN 300 220 in the 863 to 870 MHz frequency range it is
recommended to use a 26 MHz crystal for frequencies below
869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal
loading, c) aging, and d) temperature dependence. The
acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.

Load capacitance 10 13 20 pF Simulated over operating conditions

ESR 100 
Start-up time 150 µs This parameter is to a large degree crystal dependent. Measured
on the CC1101EM reference designs ([1] and [2]) using crystal
AT-41CD2 from NDK

Table 13: Crystal Oscillator Parameters

4.5 Low Power RC Oscillator

TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1]
and [2]).

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency 34.7 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL
frequency divided by 750
Frequency accuracy after ±1 %
calibration
Temperature coefficient +0.5 % / C Frequency drift when temperature changes after
calibration
Supply voltage coefficient +3 %/V Frequency drift when supply voltage changes after
calibration
Initial calibration time 2 ms When the RC Oscillator is enabled, calibration is
continuously done in the background as long as
the crystal oscillator is running

Table 14: RC Oscillator Parameters

SWRS061I Page 18 of 98
 CC1101
4.6 Frequency Synthesizer Characteristics
TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference designs
([1] and [2]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency 397 FXOSC/ 412 Hz 26-27 MHz crystal. The resolution (in Hz) is equal
resolution 216 for all frequency bands
Synthesizer frequency ±40 ppm Given by crystal used. Required accuracy
tolerance (including temperature and aging) depends on
frequency band and channel bandwidth / spacing
RF carrier phase noise –92 dBc/Hz @ 50 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz @ 100 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz @ 200 kHz offset from carrier
RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier
RF carrier phase noise –107 dBc/Hz @ 1 MHz offset from carrier
RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier
RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier
RF carrier phase noise –129 dBc/Hz @ 10 MHz offset from carrier
PLL turn-on / hop time 72 75 75 s Time from leaving the IDLE state until arriving in
( See Table 34) the RX, FSTXON or TX state, when not
performing calibration. Crystal oscillator running.
PLL RX/TX settling time 29 30 30 s Settling time for the 1·IF frequency step from RX
( See Table 34) to TX
PLL TX/RX settling time 30 31 31 s Settling time for the 1·IF frequency step from TX
( See Table 34) to RX. 250 kbps data rate.
PLL calibration time 685 712 724 s Calibration can be initiated manually or
(See Table 35) automatically before entering or after leaving
RX/TX

Table 15: Frequency Synthesizer Parameters

4.7 Analog Temperature Sensor

TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1]
and [2]). Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40C 0.651 V

Output voltage at 0C 0.747 V

Output voltage at +40C 0.847 V

Output voltage at +80C 0.945 V

Temperature coefficient 2.47 mV/C Fitted from –20 C to +80 C

* *
Error in calculated -2 0 2 C From –20 C to +80 C when using 2.47 mV / C, after
temperature, calibrated 1-point calibration at room temperature
*
The indicated minimum and maximum error with 1-
point calibration is based on simulated values for
typical process parameters
Current consumption 0.3 mA
increase when enabled

Table 16: Analog Temperature Sensor Parameters

SWRS061I Page 19 of 98
 CC1101
4.8 DC Characteristics
TA = 25C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD-0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –50 nA Input equals 0V
Logic "1" input current N/A 50 nA Input equals VDD

Table 17: DC Characteristics

4.9 Power-On Reset

For proper Power-On-Reset functionality the power supply should comply with the requirements in
Table 18 below. Otherwise, the chip should be assumed to have unknown state until transmitting an
SRES strobe over the SPI interface. See Section 19.1 on page 50 for further details.
Parameter Min Typ Max Unit Condition/Note

Power-up ramp-up time 5 ms From 0V until reaching 1.8V

Power off time 1 ms Minimum time between power-on and power-off

Table 18: Power-On Reset Requirements

5 Pin Configuration
The CC1101 pin-out is shown in Figure 8 and Table 19. See Section 26 for details on the I/O
configuration.
DGUARD
RBIAS
GND

GND
SI

20 19 18 17 16

SCLK 1 15 AVDD
SO (GDO1) 2 14 AVDD
GDO2 3 13 RF_N
DVDD 4 12 RF_P
DCOUPL 5 11 AVDD

GND
6 7 8 9 10
Exposed die
GDO0 (ATEST)
CSn
XOSC_Q1
AVDD
XOSC_Q2

attach pad

Figure 8: Pinout Top View

.
Note: The exposed die attach pad must be connected to a solid ground plane as this is the main
ground connection for the chip

SWRS061I Page 20 of 98
 CC1101

Pin # Pin Name Pin type Description

1 SCLK Digital Input Serial configuration interface, clock input
2 SO (GDO1) Digital Output Serial configuration interface, data output
Optional general output pin when CSn is high
3 GDO2 Digital Output Digital output pin for general use:
 Test signals
 FIFO status signals
 Clear channel indicator
 Clock output, down-divided from XOSC
 Serial output RX data
4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling
NOTE: This pin is intended for use with the CC1101 only. It can not be used
to provide supply voltage to other devices
6 GDO0 Digital I/O Digital output pin for general use:
(ATEST)  Test signals
 FIFO status signals
 Clear channel indicator
 Clock output, down-divided from XOSC
 Serial output RX data
 Serial input TX data
Also used as analog test I/O for prototype/production testing
7 CSn Digital Input Serial configuration interface, chip select
8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input
9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
10 XOSC_Q2 Analog I/O Crystal oscillator pin 2
11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
12 RF_P RF I/O Positive RF input signal to LNA in receive mode
Positive RF output signal from PA in transmit mode
13 RF_N RF I/O Negative RF input signal to LNA in receive mode
Negative RF output signal from PA in transmit mode
14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
16 GND Ground (Analog) Analog ground connection
17 RBIAS Analog I/O External bias resistor for reference current
18 DGUARD Power (Digital) Power supply connection for digital noise isolation
19 GND Ground (Digital) Ground connection for digital noise isolation
20 SI Digital Input Serial configuration interface, data input

Table 19: Pinout Overview

SWRS061I Page 21 of 98
 CC1101

6 Circuit Description

RADIO CONTROL

DEMODULATOR
ADC

RXFIFO

DIGITAL INTERFACE TO MCU

LNA

FEC / INTERLEAVER
ADC

PACKET HANDLER
SCLK
SO (GDO1)
SI
RF_P FREQ
0 CSn
RF_N SYNTH
90
GDO0 (ATEST)
GDO2

MODULATOR
PA

TXFIFO
RC OSC BIAS XOSC

RBIAS XOSC_Q1 XOSC_Q2

Figure 9: CC1101 Simplified Block Diagram

A simplified block diagram of CC1101 is shown frequency synthesizer includes a completely
in Figure 9. on-chip LC VCO and a 90 degree phase
shifter for generating the I and Q LO signals to
CC1101 features a low-IF receiver. The received the down-conversion mixers in receive mode.
RF signal is amplified by the low-noise
amplifier (LNA) and down-converted in A crystal is to be connected to XOSC_Q1 and
quadrature (I and Q) to the intermediate XOSC_Q2. The crystal oscillator generates the
frequency (IF). At IF, the I/Q signals are reference frequency for the synthesizer, as
digitised by the ADCs. Automatic gain control well as clocks for the ADC and the digital part.
(AGC), fine channel filtering, demodulation, A 4-wire SPI serial interface is used for
and bit/packet synchronization are performed configuration and data buffer access.
digitally.
The digital baseband includes support for
The transmitter part of CC1101 is based on channel configuration, packet handling, and
direct synthesis of the RF frequency. The data buffering.

7 Application Circuit
Only a few external components are required wound inductors as this give better output
for using the CC1101. The recommended power, sensitivity, and attenuation of
application circuits for CC1101 are shown in harmonics compared to using multi-layer
Figure 10 and inductors. Refer to design note DN032 [24] for
information about performance when using
Figure 11. The external components are wire-wound inductors from different vendors.
described in Table 20, and typical values are See also Design Note DN013 [15], which gives
given in Table 21. the output power and harmonics when using
The 315 MHz and 433 MHz CC1101EM multi-layer inductors. The output power is then
reference design [1] use inexpensive multi- typically +10 dBm when operating at 868/915
layer inductors. The 868 MHz and 915 MHz MHz.
CC1101EM reference design [2] use wire-

7.1 Bias Resistor

The bias resistor R171 is used to set an accurate bias current.

SWRS061I Page 22 of 98
 CC1101
7.2 Balun and RF Matching
The balanced RF input and output of CC1101 DC blocking. Together with an appropriate LC
share two common pins and are designed for network, the balun components also transform
a simple, low-cost matching and balun network the impedance to match a 50  load. C125
on the printed circuit board. The receive- and provides DC blocking and is only needed if
transmit switching at the CC1101 front-end is there is a DC path in the antenna. For the
controlled by a dedicated on-chip function, 868/915 MHz reference design, this
eliminating the need for an external RX/TX- component may also be used for additional
switch. filtering, see Section 7.5 below.
A few external passive components combined Suggested values for 315 MHz, 433 MHz, and
with the internal RX/TX switch/termination 868/915 MHz are listed in Table 21.
circuitry ensures match in both RX and TX
The balun and LC filter component values and
mode. The components between the
their placement are important to keep the
RF_N/RF_P pins and the point where the two
performance optimized. It is highly
signals are joined together (C131, C121, L121
recommended to follow the CC1101EM
and L131 for the 315/433 MHz reference
reference design ([1] and [2]). Gerber files and
design [1], and L121, L131, C121, L122,
schematics for the reference designs are
C131, C122 and L132 for the 868/915 MHz
available for download from the TI website.
reference design [2]) form a balun that
converts the differential RF signal on CC1101 to
a single-ended RF signal. C124 is needed for

7.3 Crystal
A crystal in the frequency range 26-27 MHz swing. This ensures a fast start-up, and keeps
must be connected between the XOSC_Q1 the drive level to a minimum. The ESR of the
and XOSC_Q2 pins. The oscillator is designed crystal should be within the specification in
for parallel mode operation of the crystal. In order to ensure a reliable start-up (see Section
addition, loading capacitors (C81 and C101) 4.4).
for the crystal are required. The loading
The initial tolerance, temperature drift, aging
capacitor values depend on the total load
and load pulling should be carefully specified
capacitance, CL, specified for the crystal. The
in order to meet the required frequency
total load capacitance seen between the
accuracy in a certain application.
crystal terminals should equal CL for the
crystal to oscillate at the specified frequency. Avoid routing digital signals with sharp edges
close to XOSC_Q1 PCB track or underneath
1
CL   C parasitic the crystal Q1 pad as this may shift the crystal
1 1
 dc operating point and result in duty cycle
C81 C101 variation.
The parasitic capacitance is constituted by pin For compliance with modulation bandwidth
input capacitance and PCB stray capacitance. requirements under EN 300 220 in the 863 to
Total parasitic capacitance is typically 2.5 pF. 870 MHz frequency range it is recommended
to use a 26 MHz crystal for frequencies below
The crystal oscillator is amplitude regulated. 869 MHz and a 27 MHz crystal for frequencies
This means that a high current is used to start above 869 MHz.
up the oscillations. When the amplitude builds
up, the current is reduced to what is necessary
to maintain approximately 0.4 Vpp signal

7.4 Reference Signal

The chip can alternatively be operated with a XOSC_Q1 input. The sine wave must be
reference signal from 26 to 27 MHz instead of connected to XOSC_Q1 using a serial
a crystal. This input clock can either be a full- capacitor. When using a full-swing digital
swing digital signal (0 V to VDD) or a sine signal, this capacitor can be omitted. The
wave of maximum 1 V peak-peak amplitude. XOSC_Q2 line must be left un-connected. C81
The reference signal must be connected to the

SWRS061I Page 23 of 98
 CC1101
and C101 can be omitted when using a reference signal.

7.5 Additional Filtering

In the 868/915 MHz reference design, C126 If this filtering is not necessary, C125 will work
and L125 together with C125 build an optional as a DC block (only necessary if there is a DC
filter to reduce emission at carrier frequency – path in the antenna). C126 and L125 should in
169 MHz. This filter is necessary for that case be left unmounted.
applications with an external antenna
Additional external components (e.g. an RF
connector that seek compliance with ETSI EN
SAW filter) may be used in order to improve
300-220. For more information, see DN017 [9].
the performance in specific applications.

7.6 Power Supply Decoupling

The power supply must be properly decoupled decoupling capacitors are very important to
close to the supply pins. Note that decoupling achieve the optimum performance. The
capacitors are not shown in the application CC1101EM reference designs ([1] and [2])
circuit. The placement and the size of the should be followed closely.

7.7 Antenna Considerations

The reference design ([1] and [2]) contains a spectrum analyzer. The SMA connector can
SMA connector and is matched for a 50  also be replaced by an antenna suitable for
load. The SMA connector makes it easy to the desired application. Please refer to the
connect evaluation modules and prototypes to antenna selection guide [13] for further details
different test equipment for example a regarding antenna solutions provided by TI.

Component Description
C51 Decoupling capacitor for on-chip voltage regulator to digital part
C81/C101 Crystal loading capacitors
C121/C131 RF balun/matching capacitors
C122 RF LC filter/matching filter capacitor (315/433 MHz). RF balun/matching capacitor (868/915 MHz).
C123 RF LC filter/matching capacitor
C124 RF balun DC blocking capacitor
C125 RF LC filter DC blocking capacitor and part of optional RF LC filter (868/915 MHz)
C126 Part of optional RF LC filter and DC-block (868/915 MHz)
L121/L131 RF balun/matching inductors (inexpensive multi-layer type)
L122 RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz).
(inexpensive multi-layer type)
L123 RF LC filter/matching filter inductor (inexpensive multi-layer type)
L124 RF LC filter/matching filter inductor (inexpensive multi-layer type)
L125 Optional RF LC filter/matching filter inductor (inexpensive multi-layer type) (868/915 MHz)
L132 RF balun/matching inductor. (inexpensive multi-layer type)
R171 Resistor for internal bias current reference
XTAL 26 – 27 MHz crystal

Table 20: Overview of External Components (excluding supply decoupling capacitors)

SWRS061I Page 24 of 98
 CC1101

1.8V-3.6V power supply

R171

SI

SI 20

GND 19

DGUARD 18

RBIAS 17

GND 16
Antenna
SCLK (50 Ohm)
1 SCLK AVDD 15
C131
CC1101
Digital Inteface

SO 2 SO
AVDD 14
(GDO1) (GDO1)
L131 C125
GDO2
3 GDO2 RF_N 13
(optional)
DIE ATTACH PAD:
4 DVDD RF_P 12 L122 L123
C121
C122 C123
10 XOSC_Q2

5 DCOUPL AVDD 11
8 XOSC_Q1

L121
6 GDO0

9 AVDD
7 CSn

C51 C124
GDO0
(optional)
CSn

XTAL

C81 C101

Figure 10: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply
decoupling capacitors)

1.8V-3.6V power supply

R171

SI
SI 20

GND 19

DGUARD 18

RBIAS 17

GND 16

Antenna
SCLK C131 (50 Ohm)
1 SCLK AVDD 15
Digital Interface

SO 2 SO L131 L132
AVDD 14

CC1101
(GDO1) (GDO1)
GDO2
C125
3 GDO2 RF_N 13
(optional) L123 L124
4 DVDD DIE ATTACH PAD: RF_P 12 C121 C122
10 XOSC_Q2
8 XOSC_Q1

5 DCOUPL AVDD 11
L121 C123
6 GDO0

9 AVDD
7 CSn

C51 L122 C126 L125

C126 and L125
GDO0
(optional)
C124 may be added to
CSn build an optional
filter to reduce
XTAL emission at 699
MHz
C81 C101

Figure 11: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply
decoupling capacitors)

SWRS061I Page 25 of 98
 CC1101

Component Value at 315MHz Value at 433MHz Value at Manufacturer

868/915MHz
C51 100 nF ± 10%, 0402 X5R Murata GRM1555C series
C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C series
C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C series
C121 6.8 pF ± 0.5 pF, 3.9 pF ± 0.25 pF, 1.0 pF ± 0.25 pF, Murata GRM1555C series
0402 NP0 0402 NP0 0402 NP0
C122 12 pF ± 5%, 0402 8.2 pF ± 0.5 pF, 1.5 pF ± 0.25 pF, Murata GRM1555C series
NP0 0402 NP0 0402 NP0
C123 6.8 pF ± 0.5 pF, 5.6 pF ± 0.5 pF, 3.3 pF ± 0.25 pF, Murata GRM1555C series
0402 NP0 0402 NP0 0402 NP0
C124 220 pF ± 5%, 220 pF ± 5%, 0402 100 pF ± 5%, 0402 Murata GRM1555C series
0402 NP0 NP0 NP0
C125 220 pF ± 5%, 220 pF ± 5%, 0402 12 pF ± 5%, 0402 Murata GRM1555C series
0402 NP0 NP0 NP0
C126 47 pF ± 5%, 0402 Murata GRM1555C series
NP0
C131 6.8 pF ± 0.5 pF, 3.9 pF ± 0.25 pF, 1.5 pF ± 0.25 pF, Murata GRM1555C series
0402 NP0 0402 NP0 0402 NP0
L121 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)
monolithic monolithic monolithic Murata LQW15xx series (868/915 MHz)
L122 18 nH ± 5%, 0402 22 nH ± 5%, 0402 18 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)
monolithic monolithic monolithic Murata LQW15xx series (868/915 MHz)

L123 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)
monolithic monolithic monolithic Murata LQW15xx series (868/915 MHz)

L124 12 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)

monolithic Murata LQW15xx series (868/915 MHz)

L125 3.3 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)

monolithic Murata LQW15xx series (868/915 MHz)

L131 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)
monolithic monolithic monolithic Murata LQW15xx series (868/915 MHz)

L132 18 nH ± 5%, 0402 Murata LQG15HS series (315/433 MHz)

monolithic Murata LQW15xx series (868/915 MHz)

R171 56 kΩ ± 1%, 0402 Koa RK73 series

XTAL 26.0 MHz surface mount crystal NDK, NX3225GA or AT-41CD2
1
Table 21: Bill Of Materials for the Application Circuit

1
Refer to design note DN032 [24] for information about performance when using inductors from
other vendors than Murata.

7.8 PCB Layout Recommendations

The top layer should be used for signal In the CC1101EM reference designs ([1] and
routing, and the open areas should be filled [2]), 5 vias are placed inside the exposed die
with metallization connected to ground using attached pad. These vias should be “tented”
several vias. (covered with solder mask) on the component
side of the PCB to avoid migration of solder
The area under the chip is used for grounding
through the vias during the solder reflow
and shall be connected to the bottom ground
process.
plane with several vias for good thermal
performance and sufficiently low inductance to The solder paste coverage should not be
ground. 100%. If it is, out gassing may occur during the

SWRS061I Page 26 of 98
 CC1101
reflow process, which may cause defects ensures the shortest possible current return
(splattering, solder balling). Using “tented” vias path.
reduces the solder paste coverage below
Avoid routing digital signals with sharp edges
100%. See Figure 12 for top solder resist and
close to XOSC_Q1 PCB track or underneath
top paste masks.
the crystal Q1 pad as this may shift the crystal
Each decoupling capacitor should be placed dc operating point and result in duty cycle
as close as possible to the supply pin it is variation.
supposed to decouple. Each decoupling
The external components should ideally be as
capacitor should be connected to the power
small as possible (0402 is recommended) and
line (or power plane) by separate vias. The
surface mount devices are highly
best routing is from the power line (or power
recommended. Please note that components
plane) to the decoupling capacitor and then to
with different sizes than those specified may
the CC1101 supply pin. Supply power filtering is
have differing characteristics.
very important.
Precaution should be used when placing the
Each decoupling capacitor ground pad should
microcontroller in order to avoid noise
be connected to the ground plane by separate
interfering with the RF circuitry.
vias. Direct connections between neighboring
power pins will increase noise coupling and A CC1101DK Development Kit with a fully
should be avoided unless absolutely assembled CC1101EM Evaluation Module is
necessary. Routing in the ground plane available. It is strongly advised that this
underneath the chip or the balun/RF matching reference layout is followed very closely in
circuit, or between the chip’s ground vias and order to get the best performance. The
the decoupling capacitor’s ground vias should schematic, BOM and layout Gerber files are all
be avoided. This improves the grounding and available from the TI website ([1] and [2]).

Figure 12: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias

8 Configuration Overview
CC1101 can be configured to achieve optimum  Data buffering with separate 64-byte
performance for many different applications. receive and transmit FIFOs
Configuration is done using the SPI interface.  Packet radio hardware support
See Section 10 below for more description of  Forward Error Correction (FEC) with
the SPI interface. The following key interleaving
parameters can be programmed:  Data whitening
 Power-down / power up mode  Wake-On-Radio (WOR)
 Crystal oscillator power-up / power-down
 Receive / transmit mode Details of each configuration register can be
 RF channel selection found in Section 29, starting on page 66.
 Data rate
Figure 13 shows a simplified state diagram
 Modulation format
that explains the main CC1101 states together
 RX channel filter bandwidth with typical usage and current consumption.
 RF output power For detailed information on controlling the

SWRS061I Page 27 of 98
 CC1101

CC1101 state machine, and a complete state diagram, see Section 19, starting on page 50.

Sleep Lowest power mode. Most

SIDLE SPWD or wake-on-radio (WOR) register values are retained.
Current consumption typ
200 nA, or typ 500 nA when
Default state when the radio is not
wake-on-radio (WOR) is
receiving or transmitting. Typ. CSn = 0 enabled.
current consumption: 1.7 mA.
IDLE
SXOFF
Used for calibrating frequency SCAL
synthesizer upfront (entering CSn = 0
All register values are
receive or transmit mode can Manual freq. Crystal
retained. Typ. current
then be done quicker). synth. calibration SRX or STX or SFSTXON or wake-on-radio (WOR) oscillator off
consumption; 165 µA.
Transitional state. Typ. current
consumption: 8.4 mA.

Frequency
Frequency synthesizer is turned on, can optionally be
synthesizer startup,
calibrated, and then settles to the correct frequency.
SFSTXON optional calibration,
Frequency synthesizer is on, Transitional state. Typ. current consumption: 8.4 mA.
settling
ready to start transmitting.
Transmission starts very Frequency
quickly after receiving the STX synthesizer on
command strobe.Typ. current STX
consumption: 8.4 mA. SRX or wake-on-radio (WOR)

STX TXOFF_MODE = 01

SFSTXON or RXOFF_MODE = 01

Typ. current consumption: Typ. current

16.8 mA at 0 dBm output, STX or RXOFF_MODE=10
Transmit mode Receive mode consumption:
30.0 mA at +10 dBm output, from 14.7 mA (strong
34.2 mA at +12 dBm output. SRX or TXOFF_MODE = 11 input signal) to 15.7 mA
(weak input signal).

TXOFF_MODE = 00 RXOFF_MODE = 00
Optional transitional state. Typ.
In FIFO-based modes, current consumption: 8.4 mA.
In FIFO-based modes,
transmission is turned off and reception is turned off and this
this state entered if the TX TX FIFO Optional freq. RX FIFO
state entered if the RX FIFO
FIFO becomes empty in the underflow synth. calibration overflow
overflows. Typ. current
middle of a packet. Typ. consumption: 1.7 mA.
current consumption: 1.7 mA.

SFTX
SFRX

IDLE

Figure 13: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data
Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized). Frequency Band = 868 MHz

SWRS061I Page 28 of 98
 CC1101

9 Configuration Software
CC1101 can be configured using the SmartRFTM After chip reset, all the registers have default
Studio software [5]. The SmartRF Studio values as shown in the tables in Section 29.
software is highly recommended for obtaining The optimum register setting might differ from
optimum register settings, and for evaluating the default value. After a reset all registers that
performance and functionality. A screenshot of shall be different from the default value
the SmartRF Studio user interface for CC1101 is therefore needs to be programmed through
shown in Figure 14. the SPI interface.

TM
Figure 14: SmartRF Studio [5] User Interface

10 4-wire Serial Configuration and Data Interface

CC1101 is configured via a simple 4-wire SPI- transfer of a header byte or during read/write
compatible interface (SI, SO, SCLK and CSn) from/to a register, the transfer will be
where CC1101 is the slave. This interface is cancelled. The timing for the address and data
also used to read and write buffered data. All transfer on the SPI interface is shown in Figure
transfers on the SPI interface are done most 15 with reference to Table 22.
significant bit first. When CSn is pulled low, the MCU must wait
All transactions on the SPI interface start with until CC1101 SO pin goes low before starting to
a header byte containing a R/W̄ bit, a burst transfer the header byte. This indicates that
access bit (B), and a 6-bit address (A5 – A0). the crystal is running. Unless the chip was in
the SLEEP or XOFF states, the SO pin will
The CSn pin must be kept low during transfers always go low immediately after taking CSn
on the SPI bus. If CSn goes high during the low.

SWRS061I Page 29 of 98
 CC1101

tsp tch tcl tsd thd tns

SCLK:

CSn:

Write to register:
X 0 B A5 A4 A3 A2 A1 A0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X
SI
Hi-Z S7 B S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 Hi-Z
SO
Read from register:

X 1 B A5 A4 A3 A2 A1 A0 X
SI

SO Hi-Z S7 B S5 S4 S3 S2 S1 S0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Hi-Z

Figure 15: Configuration Registers Write and Read Operations

Parameter Description Min Max Units

fSCLK SCLK frequency - 10 MHz
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).

SCLK frequency, single access - 9

No delay between address and data byte

SCLK frequency, burst access - 6.5

No delay between address and data byte, or between data bytes

tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 - s

tsp CSn low to positive edge on SCLK, in active mode 20 - ns
tch Clock high 50 - ns
tcl Clock low 50 - ns
trise Clock rise time - 40 ns
tfall Clock fall time - 40 ns
tsd Setup data (negative SCLK edge) to Single access 55 - ns
positive edge on SCLK
(tsd applies between address and data bytes, and between Burst access 76 -
data bytes)

thd Hold data after positive edge on SCLK 20 - ns

tns Negative edge on SCLK to CSn high. 20 - ns

Table 22: SPI Interface Timing Requirements

Note: The minimum tsp,pd figure in Table 22 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-
down depends on the start-up time of the crystal being used. The 150 μs in Table 22 is the
crystal oscillator start-up time measured on CC1101EM reference designs ([1] and [2]) using
crystal AT-41CD2 from NDK.

SWRS061I Page 30 of 98
 CC1101
10.1 Chip Status Byte
When the header byte, data byte, or command when the chip is in receive mode. Likewise, TX
strobe is sent on the SPI interface, the chip is active when the chip is transmitting.
status byte is sent by the CC1101 on the SO pin.
The last four bits (3:0) in the status byte
The status byte contains key status signals,
contains FIFO_BYTES_AVAILABLE. For read
useful for the MCU. The first bit, s7, is the
operations (the R/W̄ bit in the header byte is
CHIP_RDYn signal and this signal must go low
set to 1), the FIFO_BYTES_AVAILABLE field
before the first positive edge of SCLK. The
contains the number of bytes available for
CHIP_RDYn signal indicates that the crystal is
reading from the RX FIFO. For write
running.
operations (the R/W̄ bit in the header byte is
Bits 6, 5, and 4 comprise the STATE value. set to 0), the FIFO_BYTES_AVAILABLE field
This value reflects the state of the chip. The contains the number of bytes that can be
XOSC and power to the digital core are on in written to the TX FIFO. When
the IDLE state, but all other modules are in FIFO_BYTES_AVAILABLE=15, 15 or more
power down. The frequency and channel bytes are available/free.
configuration should only be updated when the
Table 23 gives a status byte summary.
chip is in this state. The RX state will be active

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4 STATE[2:0] Indicates the current main state machine mode
Value State Description
000 IDLE IDLE state
(Also reported for some transitional states instead
of SETTLING or CALIBRATE)

001 RX Receive mode

010 TX Transmit mode
011 FSTXON Fast TX ready
100 CALIBRATE Frequency synthesizer calibration is running
101 SETTLING PLL is settling
110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

Table 23: Status Byte Summary

10.2 Register Access

The configuration registers on the CC1101 are the status byte is sent on the SO pin each time
located on SPI addresses from 0x00 to 0x2E. a header byte or data byte is transmitted on
Table 43 on page 68 lists all configuration the SI pin. When reading from registers, the
registers. It is highly recommended to use status byte is sent on the SO pin each time a
SmartRF Studio [5] to generate optimum header byte is transmitted on the SI pin.
register settings. The detailed description of
Registers with consecutive addresses can be
each register is found in Section 29.1 and
accessed in an efficient way by setting the
29.2, starting on page 71. All configuration
burst bit (B) in the header byte. The address
registers can be both written to and read. The
bits (A5 – A0) set the start address in an
R/W̄ bit controls if the register should be
internal address counter. This counter is
written to or read. When writing to registers,
incremented by one each new byte (every 8

SWRS061I Page 31 of 98
 CC1101
clock pulses). The burst access is either a zero. See more in Section 10.3 below.
read or a write access and must be terminated Because of this, burst access is not available
by setting CSn high. for status registers and they must be accessed
one at a time. The status registers can only be
For register addresses in the range 0x30-
read.
0x3D, the burst bit is used to select between
status registers when burst bit is one, and
between command strobes when burst bit is

10.3 SPI Read

When reading register fields over the SPI is being corrupt. As an example, the
interface while the register fields are updated probability of any single read from TXBYTES
by the radio hardware (e.g. MARCSTATE or being corrupt, assuming the maximum data
TXBYTES), there is a small, but finite, rate is used, is approximately 80 ppm. Refer to
probability that a single read from the register the CC1101 Errata Notes [3] for more details.

10.4 Command Strobes

Command Strobes may be viewed as single address bits (in the range 0x30 through 0x3D)
byte instructions to CC1101. By addressing a are written. The R/W̄ bit can be either one or
command strobe register, internal sequences zero and will determine how the
will be started. These commands are used to FIFO_BYTES_AVAILABLE field in the status
disable the crystal oscillator, enable receive byte should be interpreted.
mode, enable wake-on-radio etc. The 13
When writing command strobes, the status
command strobes are listed in Table 42 on
byte is sent on the SO pin.
page 67.
A command strobe may be followed by any
Note: An SIDLE strobe will clear all other SPI access without pulling CSn high.
pending command strobes until IDLE However, if an SRES strobe is being issued,
state is reached. This means that if for one will have to wait for SO to go low again
example an SIDLE strobe is issued before the next header byte can be issued as
while the radio is in RX state, any other shown in Figure 16. The command strobes are
command strobes issued before the executed immediately, with the exception of
radio reaches IDLE state will be the SPWD, SWOR, and the SXOFF strobes,
ignored. which are executed when CSn goes high.
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W̄ bit,
the burst access bit (set to 0), and the six

CSn

SO

SI HeaderSRES HeaderAddr Data

Figure 16: SRES Command Strobe

10.5 FIFO Access

The 64-byte TX FIFO and the 64-byte RX The TX FIFO is write-only, while the RX FIFO
FIFO are accessed through the 0x3F address. is read-only.
When the R/W̄ bit is zero, the TX FIFO is
The burst bit is used to determine if the FIFO
accessed, and the RX FIFO is accessed when
access is a single byte access or a burst
the R/W̄ bit is one.
access. The single byte access method

SWRS061I Page 32 of 98
 CC1101
expects a header byte with the burst bit set to underflow while writing data to the TX FIFO.
zero and one data byte. After the data byte, a Note that the status byte contains the number
new header byte is expected; hence, CSn can of bytes free before writing the byte in
remain low. The burst access method expects progress to the TX FIFO. When the last byte
one header byte and then consecutive data that fits in the TX FIFO is transmitted on SI,
bytes until terminating the access by setting the status byte received concurrently on SO
CSn high. will indicate that one byte is free in the TX
FIFO.
The following header bytes access the FIFOs:
The TX FIFO may be flushed by issuing a
 0x3F: Single byte access to TX FIFO
SFTX command strobe. Similarly, a SFRX
 0x7F: Burst access to TX FIFO command strobe will flush the RX FIFO. A
SFTX or SFRX command strobe can only be
 0xBF: Single byte access to RX FIFO issued in the IDLE, TXFIFO_UNDERFLOW, or
 0xFF: Burst access to RX FIFO RXFIFO_OVERFLOW states. Both FIFOs are
flushed when going to the SLEEP state.
When writing to the TX FIFO, the status byte
(see Section 10.1) is output on SO for each Figure 17 gives a brief overview of different
new data byte as shown in Figure 15. This register access types possible.
status byte can be used to detect TX FIFO

10.6 PATABLE Access

The 0x3E address is used to access the highest value is reached the counter restarts
PATABLE, which is used for selecting PA at zero.
power control settings. The SPI expects up to
The access to the PATABLE is either single
eight data bytes after receiving the address.
byte or burst access depending on the burst
By programming the PATABLE, controlled PA
bit. When using burst access the index counter
power ramp-up and ramp-down can be
will count up; when reaching 7 the counter will
achieved, as well as ASK modulation shaping
restart at 0. The R/W̄ bit controls whether the
for reduced bandwidth. See SmartRF Studio
access is a read or a write access.
[5] for recommended shaping / PA ramping
sequences. See also Section 24 for details on If one byte is written to the PATABLE and this
output power programming. value is to be read out, CSn must be set high
before the read access in order to set the
The PATABLE is an 8-byte table that defines
index counter back to zero.
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit Note that the content of the PATABLE is lost
value FREND0.PA_POWER). The table is when entering the SLEEP state, except for the
written and read from the lowest setting (0) to first byte (index 0).
the highest (7), one byte at a time. An index
For more information, see Design Note DN501
counter is used to control the access to the
[18].
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the

CSn:

Command strobe(s):
HeaderStrobe HeaderStrobe HeaderStrobe

Read or write register(s):

HeaderReg Data HeaderReg Data HeaderReg Data

Read or write consecutive

registers (burst): HeaderReg n Datan Datan + 1 Datan + 2

Read or write n + 1 bytes

from/to the RX/TX FIFO: HeaderFIFO DataByte 0 DataByte 1 DataByte 2 DataByte n - 1 DataByte n

Combinations:
HeaderReg Data HeaderStrobe HeaderReg Data HeaderStrobe HeaderFIFO DataByte 0 DataByte 1

Figure 17: Register Access Types

SWRS061I Page 33 of 98
 CC1101

11 Microcontroller Interface and Pin Configuration

In a typical system, CC1101 will interface to a  Read and write buffered data
microcontroller. This microcontroller must be
able to:  Read back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
 Program CC1101 into different modes SCLK and CSn)

11.1 Configuration Interface

The microcontroller uses four I/O pins for the CSn). The SPI is described in Section 10 on
SPI configuration interface (SI, SO, SCLK and page 29.

11.2 General Control and Status Pins

The CC1101 has two dedicated configurable The GDO0 pin can also be used for an on-chip
pins (GDO0 and GDO2) and one shared pin analog temperature sensor. By measuring the
(GDO1) that can output internal status voltage on the GDO0 pin with an external
information useful for control software. These ADC, the temperature can be calculated.
pins can be used to generate interrupts on the Specifications for the temperature sensor are
MCU. See Section 26 on page 61 for more found in Section 4.7. With default PTEST
details on the signals that can be register setting (0x7F), the temperature sensor
programmed. output is only available if the frequency
synthesizer is enabled (e.g. the MANCAL,
GDO1 is shared with the SO pin in the SPI
FSTXON, RX, and TX states). It is necessary
interface. The default setting for GDO1/SO is
to write 0xBF to the PTEST register to use the
3-state output. By selecting any other of the
analog temperature sensor in the IDLE state.
programming options, the GDO1/SO pin will
Before leaving the IDLE state, the PTEST
become a generic pin. When CSn is low, the
register should be restored to its default value
pin will always function as a normal SO pin.
(0x7F).
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX
data input pin while in transmit mode.

11.3 Optional Radio Control Feature

The CC1101 has an optional way of controlling SCLK are set to RX and CSn toggles. When
the radio by reusing SI, SCLK, and CSn from CSn is low the SI and SCLK has normal SPI
the SPI interface. This feature allows for a functionality.
simple three-pin control of the major states of
All pin control command strobes are executed
the radio: SLEEP, IDLE, RX, and TX. This
immediately except the SPWD strobe. The
optional functionality is enabled with the
SPWD strobe is delayed until CSn goes high.
MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows: CSn SCLK SI Function

1 X X Chip unaffected by SCLK/SI

 If CSn is high, the SI and SCLK are set to
the desired state according to Table 24.  0 0 Generates SPWD strobe

 If CSn goes low, the state of SI and SCLK  0 1 Generates STX strobe
is latched and a command strobe is  1 0 Generates SIDLE strobe
generated internally according to the pin
configuration.  1 1 Generates SRX strobe
SPI SPI SPI mode (wakes up into
It is only possible to change state with the 0
mode mode IDLE if in SLEEP/XOFF)
latter functionality. That means that for
instance RX will not be restarted if SI and Table 24: Optional Pin Control Coding

SWRS061I Page 34 of 98
 CC1101

12 Data Rate Programming

The data rate used when transmitting, or the The data rate can be set from 0.6 kBaud to
data rate expected in receive is programmed 500 kBaud with the minimum step size
by the MDMCFG3.DRATE_M and the according to Table 25 below. See Table 3 for
MDMCFG4.DRATE_E configuration registers. the minimum and maximum data rates for the
The data rate is given by the formula below. different modulation formats.
As the formula shows, the programmed data
Min Data Typical Data Max Data Data rate
rate depends on the crystal frequency. Rate Rate Rate Step Size
[kBaud] [kBaud] [kBaud] [kBaud]
0.6 1.0 0.79 0.0015

RDATA 
256  DRATE _ M   2DRATE _ E  f 0.79 1.2 1.58 0.0031
XOSC
228
1.59 2.4 3.17 0.0062
3.17 4.8 6.33 0.0124
The following approach can be used to find 6.35 9.6 12.7 0.0248
suitable values for a given data rate:
12.7 19.6 25.3 0.0496
 R 2 20
 25.4 38.4 50.7 0.0992
DRATE _ E  log 2  DATA 
  f XOSC  50.8 76.8 101.4 0.1984
101.6 153.6 202.8 0.3967
R DATA  2 28
DRATE _ M   256 203.1 250 405.5 0.7935
f XOSC  2 DRATE _ E 406.3 500 500 1.5869

Table 25: Data Rate Step Size (assuming a

If DRATE_M is rounded to the nearest integer 26 MHz crystal)
and becomes 256, increment DRATE_E and
use DRATE_M = 0.

13 Receiver Channel Filter Bandwidth

In order to meet different channel width
requirements, the receiver channel filter is
MDMCFG4. MDMCFG4.CHANBW_E
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers CHANBW_M 00 01 10 11
control the receiver channel filter bandwidth, 00 812 406 203 102
which scales with the crystal oscillator
frequency. 01 650 325 162 81
10 541 270 135 68
The following formula gives the relation
between the register settings and the channel 11 464 232 116 58
filter bandwidth:
Table 26: Channel Filter Bandwidths [kHz]
f XOSC (assuming a 26 MHz crystal)
BWchannel 
8  (4  CHANBW _ M )·2CHANBW _ E
Table 26 lists the channel filter bandwidths By compensating for a frequency offset
supported by the CC1101. between the transmitter and the receiver, the
filter bandwidth can be reduced and the
sensitivity improved, see more in DN005 [17]
and in Section 14.1.

SWRS061I Page 35 of 98
 CC1101

14 Demodulator, Symbol Synchronizer, and Data Decision

CC1101 contains an advanced and highly (see Section 17.3 for more information), the
configurable demodulator. Channel filtering signal level in the channel is estimated. Data
and frequency offset compensation is filtering is also included for enhanced
performed digitally. To generate the RSSI level performance.

14.1 Frequency Offset Compensation

The CC1101 has a very fine frequency since the algorithm may drift to the boundaries
resolution (see Table 15). This feature can be when trying to track noise.
used to compensate for frequency offset and The tracking loop has two gain factors, which
drift. affects the settling time and noise sensitivity of
When using 2-FSK, GFSK, 4-FSK, or MSK the algorithm. FOCCFG.FOC_PRE_K sets the
modulation, the demodulator will compensate gain before the sync word is detected, and
for the offset between the transmitter and FOCCFG.FOC_POST_K selects the gain after
receiver frequency within certain limits, by the sync word has been found.
estimating the centre of the received data. The
frequency offset compensation configuration is Note: Frequency offset compensation is
controlled from the FOCCFG register. By not supported for ASK or OOK modulation.
compensating for a large frequency offset
between the transmitter and the receiver, the The estimated frequency offset value is
sensitivity can be improved, see DN005 [17]. available in the FREQEST status register. This
The tracking range of the algorithm is can be used for permanent frequency offset
selectable as fractions of the channel compensation. By writing the value from
bandwidth with the FOCCFG.FOC_LIMIT FREQEST into FSCTRL0.FREQOFF, the
configuration register. frequency synthesizer will automatically be
adjusted according to the estimated frequency
If the FOCCFG.FOC_BS_CS_GATE bit is set, offset. More details regarding this permanent
the offset compensator will freeze until carrier frequency compensation algorithm can be
sense asserts. This may be useful when the found in DN015 [10].
radio is in RX for long periods with no traffic,

14.2 Bit Synchronization

The bit synchronization algorithm extracts the is programmed as described in Section 12.
clock from the incoming symbols. The Re-synchronization is performed continuously
algorithm requires that the expected data rate to adjust for error in the incoming symbol rate.

14.3 Byte Synchronization

Byte synchronization is achieved by a correlation threshold can be set to 15/16,
continuous sync word search. The sync word 16/16, or 30/32 bits match. The sync word can
is a 16 bit configurable field (can be repeated be further qualified using the preamble quality
to get a 32 bit) that is automatically inserted at indicator mechanism described below and/or a
the start of the packet by the modulator in carrier sense condition. The sync word is
transmit mode. The MSB in the sync word is configured through the SYNC1 and SYNC0
sent first. The demodulator uses this field to registers.
find the byte boundaries in the stream of bits.
The sync word will also function as a system In order to make false detections of sync
identifier, since only packets with the correct words less likely, a mechanism called
predefined sync word will be received if the preamble quality indication (PQI) can be used
sync word detection in RX is enabled in to qualify the sync word. A threshold value for
register MDMCFG2 (see Section 17.1). The the preamble quality must be exceeded in
order for a detected sync word to be accepted.
sync word detector correlates against the
See Section 17.2 for more details.
user-configured 16 or 32 bit sync word. The

SWRS061I Page 36 of 98
 CC1101

15 Packet Handling Hardware Support

The CC1101 has built-in hardware support for  Preamble detection
packet oriented radio protocols.  Sync word detection
In transmit mode, the packet handler can be  CRC computation and CRC check
configured to add the following elements to the  One byte address check
packet stored in the TX FIFO:  Packet length check (length byte checked
against a programmable maximum length)
 A programmable number of preamble  De-whitening
bytes  De-interleaving and decoding
 A two byte synchronization (sync) word.
Can be duplicated to give a 4-byte sync Optionally, two status bytes (see Table 27 and
word (recommended). It is not possible to Table 28) with RSSI value, Link Quality
only insert preamble or only insert a sync Indication, and CRC status can be appended
word in the RX FIFO.
 A CRC checksum computed over the data
field. Bit Field Name Description
7:0 RSSI RSSI value
The recommended setting is 4-byte preamble
and 4-byte sync word, except for 500 kBaud Table 27: Received Packet Status Byte 1
data rate where the recommended preamble (first byte appended after the data)
length is 8 bytes. In addition, the following can
Bit Field Name Description
be implemented on the data field and the
optional 2-byte CRC checksum: 7 CRC_OK 1: CRC for received data OK
(or CRC disabled)
 Whitening of the data with a PN9 0: CRC error in received data
sequence 6:0 LQI Indicating the link quality
 Forward Error Correction (FEC) by the use
of interleaving and coding of the data Table 28: Received Packet Status Byte 2
(convolutional coding) (second byte appended after the data)

Note: Register fields that control the

In receive mode, the packet handling support
packet handling features should only be
will de-construct the data packet by
implementing the following (if enabled): altered when CC1101 is in the IDLE state.

15.1 Data Whitening

From a radio perspective, the ideal over the air With CC1101, this can be done automatically.
data are random and DC free. This results in By setting PKTCTRL0.WHITE_DATA=1, all
the smoothest power distribution over the data, except the preamble and the sync word
occupied bandwidth. This also gives the will be XOR-ed with a 9-bit pseudo-random
regulation loops in the receiver uniform (PN9) sequence before being transmitted. This
operation conditions (no data dependencies). is shown in Figure 18. At the receiver end, the
Real data often contain long sequences of data are XOR-ed with the same pseudo-
zeros and ones. In these cases, performance random sequence. In this way, the whitening is
can be improved by whitening the data before reversed, and the original data appear in the
transmitting, and de-whitening the data in the receiver. The PN9 sequence is initialized to all
receiver. 1’s.

SWRS061I Page 37 of 98
 CC1101

8 7 6 5 4 3 2 1 0

TX_DATA 7 6 5 4 3 2 1 0

The first TX_DATA byte is shifted in before doing the XOR-operation providing the first TX_OUT[7:0] byte. The
second TX_DATA byte is then shifted in before doing the XOR-operation providing the second TX_OUT[7:0] byte.

TX_OUT[7:0]

Figure 18: Data Whitening in TX Mode

15.2 Packet Format

The format of the data packet can be  Optional length byte
configured and consists of the following items  Optional address byte
(see Figure 19):  Payload
 Preamble  Optional 2 byte CRC
 Synchronization word

Optional data whitening

Optionally FEC encoded/decoded Legend:
Optional CRC-16 calculation Inserted automatically in TX,
processed and removed in RX.
Address field
Length field
Sync word

CRC-16

Preamble bits Optional user-provided fields processed in TX,

Data field processed but not removed in RX.
(1010...1010)
Unprocessed user data (apart from FEC
and/or whitening)
8 8
8 x n bits 16/32 bits 8 x n bits 16 bits
bits bits
Figure 19: Packet Format
The preamble pattern is an alternating The synchronization word is a two-byte value
sequence of ones and zeros (10101010…). set in the SYNC1 and SYNC0 registers. The
The minimum length of the preamble is sync word provides byte synchronization of the
programmable through the value of incoming packet. A one-byte sync word can be
MDMCFG1.NUM_PREAMBLE. When enabling emulated by setting the SYNC1 value to the
TX, the modulator will start transmitting the preamble pattern. It is also possible to emulate
preamble. When the programmed number of a 32 bit sync word by setting
preamble bytes has been transmitted, the MDMCFG2.SYNC_MODE to 3 or 7. The sync
modulator will send the sync word and then word will then be repeated twice.
data from the TX FIFO if data is available. If
the TX FIFO is empty, the modulator will CC1101 supports both constant packet length
continue to send preamble bytes until the first protocols and variable length protocols.
byte is written to the TX FIFO. The modulator Variable or fixed packet length mode can be
will then send the sync word and then the data used for packets up to 255 bytes. For longer
bytes.

SWRS061I Page 38 of 98
 CC1101
packets, infinite packet length mode must be the packet. Then the PKTLEN value is set
used. according to this value. The end of packet will
occur when the byte counter in the packet
Fixed packet length mode is selected by
handler is equal to the PKTLEN register. Thus,
setting PKTCTRL0.LENGTH_CONFIG=0. The
the MCU must be able to program the correct
desired packet length is set by the PKTLEN
length, before the internal counter reaches the
register. This value must be different from 0.
packet length.
In variable packet length mode,
PKTCTRL0.LENGTH_CONFIG=1, the packet 15.2.2 Packet Length > 255
length is configured by the first byte after the
The packet automation control register,
sync word. The packet length is defined as the
PKTCTRL0, can be reprogrammed during TX
payload data, excluding the length byte and
and RX. This opens the possibility to transmit
the optional CRC. The PKTLEN register is
and receive packets that are longer than 256
used to set the maximum packet length
bytes and still be able to use the packet
allowed in RX. Any packet received with a
handling hardware support. At the start of the
length byte with a value greater than PKTLEN packet, the infinite packet length mode
will be discarded. The PKTLEN value must be (PKTCTRL0.LENGTH_CONFIG=2) must be
different from 0.The first byte written to the active. On the TX side, the PKTLEN register is
TXFIFO must be different from 0.
set to mod(length, 256). On the RX side the
With PKTCTRL0.LENGTH_CONFIG=2, the MCU reads out enough bytes to interpret the
packet length is set to infinite and transmission length field in the packet and sets the PKTLEN
and reception will continue until turned off register to mod(length, 256). When less than
manually. As described in the next section, 256 bytes remains of the packet, the MCU
this can be used to support packet formats disables infinite packet length mode and
with different length configuration than natively activates fixed packet length mode. When the
supported by CC1101. One should make sure internal byte counter reaches the PKTLEN
that TX mode is not turned off during the value, the transmission or reception ends (the
transmission of the first half of any byte. Refer radio enters the state determined by
to the CC1101 Errata Notes [3] for more details. TXOFF_MODE or RXOFF_MODE). Automatic
CRC appending/checking can also be used
Note: The minimum packet length (by setting PKTCTRL0.CRC_EN=1).
supported (excluding the optional length When for example a 600-byte packet is to be
byte and CRC) is one byte of payload transmitted, the MCU should do the following
data. (see also Figure 20)
 Set PKTCTRL0.LENGTH_CONFIG=2.
15.2.1 Arbitrary Length Field Configuration
 Pre-program the PKTLEN register to
The packet length register, PKTLEN, can be mod(600, 256) = 88.
reprogrammed during receive and transmit. In
combination with fixed packet length mode  Transmit at least 345 bytes (600 - 255), for
(PKTCTRL0.LENGTH_CONFIG=0), this opens example by filling the 64-byte TX FIFO six
the possibility to have a different length field times (384 bytes transmitted).
configuration than supported for variable
 Set PKTCTRL0.LENGTH_CONFIG=0.
length packets (in variable packet length mode
the length byte is the first byte after the sync  The transmission ends when the packet
word). At the start of reception, the packet counter reaches 88. A total of 600 bytes
length is set to a large value. The MCU reads are transmitted.
out enough bytes to interpret the length field in

SWRS061I Page 39 of 98
 CC1101
Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again

0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................

Infinite packet length enabled Fixed packet length 600 bytes transmitted and
enabled when less than received
256 bytes remains of
packet
Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88

Figure 20: Packet Length > 255

15.3 Packet Filtering in Receive Mode

CC1101 supports three different types of used to set the maximum allowed packet
packet-filtering; address filtering, maximum length. If the received length byte has a larger
length filtering, and CRC filtering. value than this, the packet is discarded and
receive mode restarted (regardless of the
15.3.1 Address Filtering MCSM1.RXOFF_MODE setting).
Setting PKTCTRL1.ADR_CHK to any other
15.3.3 CRC Filtering
value than zero enables the packet address
filter. The packet handler engine will compare The filtering of a packet when CRC check fails
the destination address byte in the packet with is enabled by setting
the programmed node address in the ADDR PKTCTRL1.CRC_AUTOFLUSH=1. The CRC
register and the 0x00 broadcast address when auto flush function will flush the entire RX
PKTCTRL1.ADR_CHK=10 or both the 0x00 FIFO if the CRC check fails. After auto flushing
and 0xFF broadcast addresses when the RX FIFO, the next state depends on the
PKTCTRL1.ADR_CHK=11. If the received MCSM1.RXOFF_MODE setting.
address matches a valid address, the packet When using the auto flush function, the
is received and written into the RX FIFO. If the maximum packet length is 63 bytes in variable
address match fails, the packet is discarded packet length mode and 64 bytes in fixed
and receive mode restarted (regardless of the packet length mode. Note that when
MCSM1.RXOFF_MODE setting). PKTCTRL1.APPEND_STATUS is enabled, the
If the received address matches a valid maximum allowed packet length is reduced by
address when using infinite packet length two bytes in order to make room in the RX
mode and address filtering is enabled, 0xFF FIFO for the two status bytes appended at the
will be written into the RX FIFO followed by the end of the packet. Since the entire RX FIFO is
address byte and then the payload data. flushed when the CRC check fails, the
previously received packet must be read out of
15.3.2 Maximum Length Filtering the FIFO before receiving the current packet.
The MCU must not read from the current
In variable packet length mode, packet until the CRC has been checked as
PKTCTRL0.LENGTH_CONFIG=1, the OK.
PKTLEN.PACKET_LENGTH register value is

15.4 Packet Handling in Transmit Mode

The payload that is to be transmitted must be second byte written to the TX FIFO must be
written into the TX FIFO. The first byte written the address byte.
must be the length byte when variable packet
If fixed packet length is enabled, the first byte
length is enabled. The length byte has a value
written to the TX FIFO should be the address
equal to the payload of the packet (including
(assuming the receiver uses address
the optional address byte). If address
recognition).
recognition is enabled on the receiver, the

SWRS061I Page 40 of 98
 CC1101
The modulator will first send the programmed Writing to the TX FIFO after it has underflowed
number of preamble bytes. If data is available will not restart TX mode.
in the TX FIFO, the modulator will send the
If whitening is enabled, everything following
two-byte (optionally 4-byte) sync word followed
the sync words will be whitened. This is done
by the payload in the TX FIFO. If CRC is
before the optional FEC/Interleaver stage.
enabled, the checksum is calculated over all
Whitening is enabled by setting
the data pulled from the TX FIFO, and the
PKTCTRL0.WHITE_DATA=1.
result is sent as two extra bytes following the
payload data. If the TX FIFO runs empty If FEC/Interleaving is enabled, everything
before the complete packet has been following the sync words will be scrambled by
transmitted, the radio will enter the interleaver and FEC encoded before being
TXFIFO_UNDERFLOW state. The only way to modulated. FEC is enabled by setting
exit this state is by issuing an SFTX strobe. MDMCFG1.FEC_EN=1.

15.5 Packet Handling in Receive Mode

In receive mode, the demodulator and packet the length byte. If fixed packet length mode is
handler will search for a valid preamble and used, the packet handler will accept the
the sync word. When found, the demodulator programmed number of bytes.
has obtained both bit and byte synchronization
Next, the packet handler optionally checks the
and will receive the first payload byte.
address and only continues the reception if the
If FEC/Interleaving is enabled, the FEC address matches. If automatic CRC check is
decoder will start to decode the first payload enabled, the packet handler computes CRC
byte. The interleaver will de-scramble the bits and matches it with the appended CRC
before any other processing is done to the checksum.
data.
At the end of the payload, the packet handler
If whitening is enabled, the data will be de- will optionally write two extra packet status
whitened at this stage. bytes (see Table 27 and Table 28) that contain
CRC status, link quality indication, and RSSI
When variable packet length mode is enabled,
value.
the first byte is the length byte. The packet
handler stores this value as the packet length
and receives the number of bytes indicated by

15.6 Packet Handling in Firmware

When implementing a packet oriented radio on how many bytes that are in the RX FIFO
protocol in firmware, the MCU needs to know and TX FIFO respectively. The
when a packet has been received/transmitted. IOCFGx.GDOx_CFG=0x00 and the
Additionally, for packets longer than 64 bytes, IOCFGx.GDOx_CFG=0x01 configurations are
the RX FIFO needs to be read while in RX and associated with the RX FIFO while the
the TX FIFO needs to be refilled while in TX. IOCFGx.GDOx_CFG=0x02 and the
This means that the MCU needs to know the IOCFGx.GDOx_CFG=0x03 configurations
number of bytes that can be read from or are associated with the TX FIFO. See Table
written to the RX FIFO and TX FIFO 41 for more information.
respectively. There are two possible solutions
to get the necessary status information: b) SPI Polling
a) Interrupt Driven Solution The PKTSTATUS register can be polled at a
given rate to get information about the current
The GDO pins can be used in both RX and TX GDO2 and GDO0 values respectively. The
to give an interrupt when a sync word has RXBYTES and TXBYTES registers can be
been received/transmitted or when a complete
polled at a given rate to get information about
packet has been received/transmitted by
the number of bytes in the RX FIFO and TX
setting IOCFGx.GDOx_CFG=0x06. In addition, FIFO respectively. Alternatively, the number of
there are two configurations for the bytes in the RX FIFO and TX FIFO can be
IOCFGx.GDOx_CFG register that can be used read from the chip status byte returned on the
as an interrupt source to provide information

SWRS061I Page 41 of 98
 CC1101
MISO line each time a header byte, data byte, is a small, but finite, probability that a single
or command strobe is sent on the SPI bus. read from registers PKTSTATUS , RXBYTES
It is recommended to employ an interrupt and TXBYTES is being corrupt. The same is
driven solution since high rate SPI polling the case when reading the chip status byte.
reduces the RX sensitivity. Furthermore, as Refer to the TI website for SW examples ([6]
explained in Section 10.3 and the CC1101 and [7]).
Errata Notes [3], when using SPI polling, there

16 Modulation Formats
CC1101 supports amplitude, frequency, and MDMCFG2.MANCHESTER_EN=1.
phase shift modulation formats. The desired
modulation format is set in the Note: Manchester encoding is not
MDMCFG2.MOD_FORMAT register. supported at the same time as using the
FEC/Interleaver option or when using MSK
Optionally, the data stream can be Manchester
and 4-FSK modulation.
coded by the modulator and decoded by the
demodulator. This option is enabled by setting

16.1 Frequency Shift Keying

CC1101 supports both 2-FSK and 4-FSK The frequency deviation is programmed with
modulation. 2-FSK can optionally be shaped the DEVIATION_M and DEVIATION_E values
by a Gaussian filter with BT = 0.5, producing a in the DEVIATN register. The value has an
GFSK modulated signal. This spectrum- exponent/mantissa form, and the resultant
shaping feature improves adjacent channel deviation is given by:
power (ACP) and occupied bandwidth. When
f xosc
selecting 4-FSK, the preamble and sync word f dev   (8  DEVIATION _ M )  2 DEVIATION _ E
is sent using 2-FSK (see Figure 21). 217
In ‘true’ 2-FSK systems with abrupt frequency
The symbol encoding is shown in Table 29.
shifting, the spectrum is inherently broad. By
making the frequency shift ‘softer’, the Format Symbol Coding
spectrum can be made significantly narrower.
‘0’ – Deviation
Thus, higher data rates can be transmitted in 2-FSK/GFSK
the same bandwidth using GFSK. ‘1’ + Deviation

When 2-FSK/GFSK/4-FSK modulation is used, ‘01’ – Deviation

the DEVIATN register specifies the expected ‘00’ – 1/3∙ Deviation
frequency deviation of incoming signals in RX 4-FSK
‘10’ +1/3∙ Deviation
and should be the same as the TX deviation
for demodulation to be performed reliably and ‘11’ + Deviation
robustly.
Table 29: Symbol Encoding for 2-FSK/GFSK
and 4-FSK Modulation

1/Baud Rate 1/Baud Rate 1/Baud Rate

+1
+1/3
-1/3
-1
1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 00 01 01 11 10 00 11 01

Preamble Sync Data

0xAA 0xD3 0x17 0x8D

Figure 21: Data Sent Over the Air (MDMCFG2.MOD_FORMAT=100)

SWRS061I Page 42 of 98
 CC1101
16.2 Minimum Shift Keying
2
When using MSK , the complete transmission This is equivalent to changing the shaping of
(preamble, sync word, and payload) will be the symbol. The DEVIATN register setting has
MSK modulated. no effect in RX when using MSK.
Phase shifts are performed with a constant When using MSK, Manchester
transition time. The fraction of a symbol period encoding/decoding should be disabled by
used to change the phase can be modified setting MDMCFG2.MANCHESTER_EN=0.
with the DEVIATN.DEVIATION_M setting.
The MSK modulation format implemented in
2
CC1101 inverts the sync word and data
Identical to offset QPSK with half-sine compared to e.g. signal generators.
shaping (data coding may differ).

16.3 Amplitude Modulation

CC1101 supports two different forms of produces a more bandwidth constrained
amplitude modulation: On-Off Keying (OOK) output spectrum.
and Amplitude Shift Keying (ASK).
When using OOK/ASK, the AGC settings from
OOK modulation simply turns the PA on or off the SmartRF Studio [5] preferred FSK/MSK
to modulate ones and zeros respectively. settings are not optimum. DN022 [16] give
guidelines on how to find optimum OOK/ASK
The ASK variant supported by the CC1101 settings from the preferred settings in
allows programming of the modulation depth SmartRF Studio [5]. The DEVIATN register
(the difference between 1 and 0), and shaping setting has no effect in either TX or RX when
of the pulse amplitude. Pulse shaping using OOK/ASK.

17 Received Signal Qualifiers and Link Quality Information

CC1101 has several qualifiers that can be used  RSSI
to increase the likelihood that a valid sync
word is detected:  Carrier Sense

 Sync Word Qualifier  Clear Channel Assessment

 Preamble Quality Threshold  Link Quality Indicator

17.1 Sync Word Qualifier

If sync word detection in RX is enabled in the word qualifier mode is set by
MDMCFG2 register, the CC1101 will not start MDMCFG2.SYNC_MODE and is summarized in
filling the RX FIFO and perform the packet Table 30. Carrier sense in Table 30 is
filtering described in Section 15.3 before a described in Section 17.4.
valid sync word has been detected. The sync

SWRS061I Page 43 of 98
 CC1101

MDMCFG2.SYNC_MODE Sync Word Qualifier Mode

000 No preamble/sync
001 15/16 sync word bits detected
010 16/16 sync word bits detected
011 30/32 sync word bits detected
100 No preamble/sync + carrier sense
above threshold
101 15/16 + carrier sense above threshold
110 16/16 + carrier sense above threshold
111 30/32 + carrier sense above threshold

Table 30: Sync Word Qualifier Mode

17.2 Preamble Quality Threshold (PQT)

The Preamble Quality Threshold (PQT) sync The threshold is configured with the register
word qualifier adds the requirement that the field PKTCTRL1.PQT. A threshold of 4∙PQT for
received sync word must be preceded with a this counter is used to gate sync word
preamble with a quality above the detection. By setting the value to zero, the
programmed threshold. preamble quality qualifier of the sync word is
disabled.
Another use of the preamble quality threshold
is as a qualifier for the optional RX termination A “Preamble Quality Reached” signal can be
timer. See Section 19.7 for details. observed on one of the GDO pins by setting
The preamble quality estimator increases an IOCFGx.GDOx_CFG=8. It is also possible to
internal counter by one each time a bit is determine if preamble quality is reached by
received that is different from the previous bit, checking the PQT_REACHED bit in the
and decreases the counter by eight each time PKTSTATUS register. This signal / bit asserts
a bit is received that is the same as the last bit. when the received signal exceeds the PQT.

17.3 RSSI
The RSSI value is an estimate of the signal (BW channel is defined in Section 13) and
power level in the chosen channel. This value AGCCTRL0.FILTER_LENGTH.
is based on the current gain setting in the RX
2  BWchannel
chain and the measured signal level in the f RSSI 
channel. 8  2FILTER _ LENGTH
In RX mode, the RSSI value can be read If PKTCTRL1.APPEND_STATUS is enabled,
continuously from the RSSI status register the last RSSI value of the packet is
until the demodulator detects a sync word automatically added to the first byte appended
(when sync word detection is enabled). At that after the payload.
point the RSSI readout value is frozen until the
next time the chip enters the RX state. The RSSI value read from the RSSI status
register is a 2’s complement number. The
Note: It takes some time from the radio following procedure can be used to convert the
enters RX mode until a valid RSSI value is RSSI reading to an absolute power level
present in the RSSI register. Please see (RSSI_dBm)
DN505 [12] for details on how the RSSI 1) Read the RSSI status register
response time can be estimated.
2) Convert the reading from a hexadecimal
number to a decimal number (RSSI_dec)
The RSSI value is given in dBm with a ½ dB 3) If RSSI_dec ≥ 128 then RSSI_dBm =
resolution. The RSSI update rate, fRSSI, (RSSI_dec - 256)/2 – RSSI_offset
depends on the receiver filter bandwidth

SWRS061I Page 44 of 98
 CC1101
4) Else if RSSI_dec < 128 then RSSI_dBm = typical plots of RSSI readings as a function of
(RSSI_dec)/2 – RSSI_offset input power level for different data rates.
Table 31 gives typical values for the
RSSI_offset. Figure 22 and Figure 23 show

Data rate [kBaud] RSSI_offset [dB], 433 MHz RSSI_offset [dB], 868 MHz
1.2 74 74
38.4 74 74
250 74 74
500 74 74

Table 31: Typical RSSI_offset Values

-10

-20

-30

-40
RSSI Readout [dBm]

-50

-60

-70

-80

-90

-100

-110

-120
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

Input Power [dBm]

1.2 kBaud 38.4 kBaud 250 kBaud 500 kBaud

Figure 22: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz

SWRS061I Page 45 of 98
 CC1101

-10

-20

-30

-40
RSSI Readout [dBm]

-50

-60

-70

-80

-90

-100

-110

-120
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Power [dBm]

1.2 kBaud 38.4 kBaud 250 kBaud 500 kBaud

Figure 23: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz

17.4 Carrier Sense (CS)

Carrier sense (CS) is used as a sync word optional fast RX termination (see Section
qualifier and for Clear Channel Assessment 19.7).
(see Section 17.5). CS can be asserted based
CS can be used to avoid interference from
on two conditions which can be individually
other RF sources in the ISM bands.
adjusted:
 CS is asserted when the RSSI is above a 17.4.1 CS Absolute Threshold
programmable absolute threshold, and de-
The absolute threshold related to the RSSI
asserted when RSSI is below the same
value depends on the following register fields:
threshold (with hysteresis). See more in
Section 17.4.1.  AGCCTRL2.MAX_LNA_GAIN
 CS is asserted when the RSSI has  AGCCTRL2.MAX_DVGA_GAIN
increased with a programmable number of
dB from one RSSI sample to the next, and  AGCCTRL1.CARRIER_SENSE_ABS_THR
de-asserted when RSSI has decreased
 AGCCTRL2.MAGN_TARGET
with the same number of dB. This setting
is not dependent on the absolute signal For given AGCCTRL2.MAX_LNA_GAIN and
level and is thus useful to detect signals in AGCCTRL2.MAX_DVGA_GAIN settings, the
environments with time varying noise floor. absolute threshold can be adjusted ±7 dB in
See more in Section 17.4.2. steps of 1 dB using
Carrier sense can be used as a sync word CARRIER_SENSE_ABS_THR.
qualifier that requires the signal level to be The MAGN_TARGET setting is a compromise
higher than the threshold for a sync word between blocker tolerance/selectivity and
search to be performed and is set by setting sensitivity. The value sets the desired signal
MDMCFG2 The carrier sense signal can be level in the channel into the demodulator.
observed on one of the GDO pins by setting Increasing this value reduces the headroom
IOCFGx.GDOx_CFG=14 and in the status for blockers, and therefore close-in selectivity.
register bit PKTSTATUS.CS. It is strongly recommended to use SmartRF
Other uses of Carrier sense include the TX-if- Studio [5] to generate the correct
CCA function (see Section 17.5) and the MAGN_TARGET setting. Table 32 and Table

SWRS061I Page 46 of 98
 CC1101
33 show the typical RSSI readout values at the MAX_DVGA_GAIN[1:0]
CS threshold at 2.4 kBaud and 250 kBaud
00 01 10 11
data rate respectively. The default reset value
for CARRIER_SENSE_ABS_THR = 0 (0 dB) has 000 -90.5 -84.5 -78.5 -72.5
been used. MAGN_TARGET = 3 (33 dB) and 7 001 -88 -82 -76 -70

MAX_LNA_GAIN[2:0]
(42 dB) have been used for 2.4 kBaud and
010 -84.5 -78.5 -72 -66
250 kBaud data rate respectively. For other
data rates, the user must generate similar 011 -82.5 -76.5 -70 -64
tables to find the CS absolute threshold. 100 -80.5 -74.5 -68 -62
If the threshold is set high, i.e. only strong 101 -78 -72 -66 -60
signals are wanted, the threshold should be
110 -76.5 -70 -64 -58
adjusted upwards by first reducing the
MAX_LNA_GAIN value and then the 111 -74.5 -68 -62 -56
MAX_DVGA_GAIN value. This will reduce
power consumption in the receiver front end, Table 33: Typical RSSI Value in dBm at CS
since the highest gain settings are avoided. Threshold with MAGN_TARGET = 7 (42 dB) at
250 kBaud, 868 MHz
MAX_DVGA_GAIN[1:0]

00 01 10 11
17.4.2 CS Relative Threshold
000 -97.5 -91.5 -85.5 -79.5
The relative threshold detects sudden changes
001 -94 -88 -82.5 -76
MAX_LNA_GAIN[2:0]

in the measured signal level. This setting does

010 -90.5 -84.5 -78.5 -72.5 not depend on the absolute signal level and is
011 -88 -82.5 -76.5 -70.5 thus useful to detect signals in environments
with a time varying noise floor. The register
100 -85.5 -80 -73.5 -68 field AGCCTRL1.CARRIER_SENSE_REL_THR
101 -84 -78 -72 -66 is used to enable/disable relative CS, and to
110 -82 -76 -70 -64
select threshold of 6 dB, 10 dB, or 14 dB RSSI
change.
111 -79 -73.5 -67 -61

Table 32: Typical RSSI Value in dBm at CS

Threshold with MAGN_TARGET = 3 (33 dB) at
2.4 kBaud, 868 MHz

SWRS061I Page 47 of 98
 CC1101
17.5 Clear Channel Assessment (CCA)
The Clear Channel Assessment (CCA) is used becomes available, the radio will not enter TX
to indicate if the current channel is free or or FSTXON state before a new strobe
busy. The current CCA state is viewable on command is sent on the SPI interface. This
any of the GDO pins by setting feature is called TX-if-CCA. Four CCA
IOCFGx.GDOx_CFG=0x09. requirements can be programmed:
MCSM1.CCA_MODE selects the mode to use  Always (CCA disabled, always goes to TX)
when determining CCA.
 If RSSI is below threshold
When the STX or SFSTXON command strobe is
 Unless currently receiving a packet
given while CC1101 is in the RX state, the TX or
FSTXON state is only entered if the clear  Both the above (RSSI below threshold and
channel requirements are fulfilled. Otherwise, not currently receiving a packet)
the chip will remain in RX. If the channel then

17.6 Link Quality Indicator (LQI)

The Link Quality Indicator is a metric of the the magnitude of the error between ideal
current quality of the received signal. If constellations and the received signal over the
PKTCTRL1.APPEND_STATUS is enabled, the 64 symbols immediately following the sync
value is automatically added to the last byte word. LQI is best used as a relative
appended after the payload. The value can measurement of the link quality (a low value
also be read from the LQI status register. The indicates a better link than what a high value
LQI gives an estimate of how easily a received does), since the value is dependent on the
signal can be demodulated by accumulating modulation format.

18 Forward Error Correction with Interleaving

18.1 Forward Error Correction (FEC)
CC1101 has built in support for Forward Error phenomena will produce occasional errors
Correction (FEC). To enable this option, set even in otherwise good reception conditions.
MDMCFG1.FEC_EN to 1. FEC is only supported FEC will mask such errors and, combined with
in fixed packet length mode, i.e. when interleaving of the coded data, even correct
PKTCTRL0.LENGTH_CONFIG=0. FEC is relatively long periods of faulty reception (burst
employed on the data field and CRC word in errors).
order to reduce the gross bit error rate when The FEC scheme adopted for CC1101 is
operating near the sensitivity limit. convolutional coding, in which n bits are
Redundancy is added to the transmitted data generated based on k input bits and the m
in such a way that the receiver can restore the most recent input bits, forming a code stream
original data in the presence of some bit able to withstand a certain number of bit errors
errors. between each coding state (the m-bit window).
The use of FEC allows correct reception at a The convolutional coder is a rate ½ code with
lower Signal-to-Noise Ratio (SNR), thus a constraint length of m = 4. The coder codes
extending communication range if the receiver one input bit and produces two output bits;
bandwidth remains constant. Alternatively, for hence, the effective data rate is halved. This
a given SNR, using FEC decreases the bit means that in order to transmit at the same
error rate (BER). The packet error rate (PER) effective data rate when using FEC, it is
is related to BER by necessary to use twice as high over-the-air
data rate. This will require a higher receiver
PER  1  (1  BER ) packet _ length
bandwidth, and thus reduce sensitivity. In
A lower BER can therefore be used to allow other words the improved reception by using
longer packets, or a higher percentage of FEC and the degraded sensitivity from a
packets of a given length, to be transmitted higher receiver bandwidth will be
successfully. Finally, in realistic ISM radio counteracting factors. See Design Note
environments, transient and time-varying DN504 for more details [19].

SWRS061I Page 48 of 98
 CC1101

18.2 Interleaving
Data received through radio channels will passed onto the convolutional decoder is read
often experience burst errors due to from the columns of the matrix.
interference and time-varying signal strengths.
In order to increase the robustness to errors CC1101 employs a 4x4 matrix interleaver with 2
spanning multiple bits, interleaving is used bits (one encoder output symbol) per cell and
when FEC is enabled. After de-interleaving, a the amount of data transmitted over the air will
continuous span of errors in the received thus always be a multiple of four bytes (see
stream will become single errors spread apart. DN507 [20] for more details). When FEC and
interleaving is used, at least one extra byte is
CC1101 employs matrix interleaving, which is required for trellis termination and the packet
illustrated in Figure 24. The on-chip control hardware therefore automatically
interleaving and de-interleaving buffers are 4 x inserts one or two extra bytes at the end of the
4 matrices. In the transmitter, the data bits packet. These bytes will be invisible to the
from the rate ½ convolutional coder are written user, as they are removed before the received
into the rows of the matrix, whereas the bit packet enters the RXFIFO.
sequence to be transmitted is read from the
When FEC and interleaving is used the
columns of the matrix. Conversely, in the
minimum data payload is 2 bytes.
receiver, the received symbols are written into
the rows of the matrix, whereas the data

Interleaver Interleaver
Write buffer Read buffer

Packet FEC
Modulator
Engine Encoder

Interleaver Interleaver
Write buffer Read buffer

FEC Packet
Demodulator
Decoder Engine

Figure 24: General Principle of Matrix Interleaving

SWRS061I Page 49 of 98
 CC1101

19 Radio Control

SIDLE

SPWD | SWOR
SLEEP
CAL_COMPLETE 0

MANCAL IDLE CSn = 0 | WOR

3,4,5 1
SXOFF
SCAL
CSn = 0
XOFF
SRX | STX | SFSTXON | WOR 2

FS_WAKEUP
6,7
FS_AUTOCAL = 01
&
SRX | STX | SFSTXON | WOR

FS_AUTOCAL = 00 | 10 | 11
& CALIBRATE
SRX | STX | SFSTXON | WOR 8

CAL_COMPLETE
SETTLING
SFSTXON 9,10,11

FSTXON
18
STX SRX | WOR

SRX
STX
SFSTXON | RXOFF_MODE = 01
TXOFF_MODE=01

STX | RXOFF_MODE = 10 RXTX_SETTLING ( STX | SFSTXON ) & CCA

21 |
TX RXOFF_MODE = 01 | 10 RX
TXOFF_MODE = 10 RXOFF_MODE = 11
19,20 13,14,15

SRX | TXOFF_MODE = 11 TXRX_SETTLING

16

TXOFF_MODE = 00 RXOFF_MODE = 00
TXFIFO_UNDERFLOW RXFIFO_OVERFLOW
& &
FS_AUTOCAL = 10 | 11 FS_AUTOCAL = 10 | 11

CALIBRATE
TXOFF_MODE = 00 12 RXOFF_MODE = 00
&
&
FS_AUTOCAL = 00 | 01
TX_UNDERFLOW FS_AUTOCAL = 00 | 01 RX_OVERFLOW
22 17

SFTX SFRX

IDLE
1

Figure 25: Complete Radio Control State Diagram

CC1101 has a built-in state machine that is used shown in Figure 13 on page 28. The complete
to switch between different operational states radio control state diagram is shown in Figure
(modes). The change of state is done either by 25. The numbers refer to the state number
using command strobes or by internal events readable in the MARCSTATE status register.
such as TX FIFO underflow. This register is primarily for test purposes.
A simplified state diagram, together with
typical usage and current consumption, is

19.1 Power-On Start-Up Sequence

When the power supply is turned on, the automatic power-on reset (POR) or manual
system must be reset. This is achieved by one reset. After the automatic power-on reset or
of the two sequences described below, i.e. manual reset, it is also recommended to

SWRS061I Page 50 of 98
 CC1101
change the signal that is output on the GDO0 this strobe, all internal registers and states are
pin. The default setting is to output a clock set to the default, IDLE state. The manual
signal with a frequency of CLK_XOSC/192. power-up sequence is as follows (see Figure
However, to optimize performance in TX and 27):
RX, an alternative GDO setting from the
settings found in Table 41 on page 62 should  Set SCLK = 1 and SI = 0, to avoid
be selected. potential problems with pin control mode
(see Section 11.3).
19.1.1 Automatic POR  Strobe CSn low / high.
A power-on reset circuit is included in the  Hold CSn low and then high for at least 40
CC1101. The minimum requirements stated in µs relative to pulling CSn low
Table 18 must be followed for the power-on
reset to function properly. The internal power-  Pull CSn low and wait for SO to go low
up sequence is completed when CHIP_RDYn (CHIP_RDYn).
goes low. CHIP_RDYn is observed on the SO  Issue the SRES strobe on the SI line.
pin after CSn is pulled low. See Section 10.1
for more details on CHIP_RDYn.  When SO goes low again, reset is
complete and the chip is in the IDLE state.
When the CC1101 reset is completed, the chip
will be in the IDLE state and the crystal
oscillator will be running. If the chip has had XOSC and voltage regulator switched on
sufficient time for the crystal oscillator to
stabilize after the power-on-reset, the SO pin 40 us
will go low immediately after taking CSn low. If
CSn is taken low before reset is completed, CSn
the SO pin will first go high, indicating that the
crystal oscillator is not stabilized, before going SO
low as shown in Figure 26.
XOSC Stable
CSn
SI SRES

SO
Figure 27: Power-On Reset with SRES
XOSC Stable
Note that the above reset procedure is
only required just after the power supply is
Figure 26: Power-On Reset first turned on. If the user wants to reset
the CC1101 after this, it is only necessary to
19.1.2 Manual Reset issue an SRES command strobe.
The other global reset possibility on CC1101
uses the SRES command strobe. By issuing

19.2 Crystal Control

The crystal oscillator (XOSC) is either state machine will then go to the IDLE state.
automatically controlled or always on, if The SO pin on the SPI interface must be
MCSM0.XOSC_FORCE_ON is set. pulled low before the SPI interface is ready to
be used as described in Section 10.1.
In the automatic mode, the XOSC will be
turned off if the SXOFF or SPWD command If the XOSC is forced on, the crystal will
strobes are issued; the state machine then always stay on even in the SLEEP state.
goes to XOFF or SLEEP respectively. This Crystal oscillator start-up time depends on
can only be done from the IDLE state. The crystal ESR and load capacitances. The
XOSC will be turned off when CSn is released electrical specification for the crystal oscillator
(goes high). The XOSC will be automatically can be found in Section 4.4.
turned on again when CSn goes low. The

SWRS061I Page 51 of 98
 CC1101

19.3 Voltage Regulator Control

The voltage regulator to the digital core is chip is then in the SLEEP state. Setting CSn
controlled by the radio controller. When the low again will turn on the regulator and crystal
chip enters the SLEEP state which is the state oscillator and make the chip enter the IDLE
with the lowest current consumption, the state.
voltage regulator is disabled. This occurs after
When Wake on Radio is enabled, the WOR
CSn is released when a SPWD command
module will control the voltage regulator as
strobe has been sent on the SPI interface. The
described in Section19.5.

19.4 Active Modes (RX and TX)

CC1101 has two active modes: receive and  IDLE
transmit. These modes are activated directly
 FSTXON: Frequency synthesizer on and
by the MCU by using the SRX and STX
ready at the TX frequency. Activate TX
command strobes, or automatically by Wake
with STX
on Radio.
The frequency synthesizer must be calibrated  TX: Start sending preamble
regularly. CC1101 has one manual calibration  RX: Start search for a new packet
option (using the SCAL strobe), and three
automatic calibration options that are Note: When MCSM1.RXOFF_MODE=11
controlled by the MCSM0.FS_AUTOCAL setting: and a packet has been received, it will
take some time before a valid RSSI value
 Calibrate when going from IDLE to either
is present in the RSSI register again even
RX or TX (or FSTXON)
if the radio has never exited RX mode.
 Calibrate when going from either RX or TX This time is the same as the RSSI
3
to IDLE automatically response time discussed in DN505 [12].
 Calibrate every fourth time when going Similarly, when TX is active the chip will
from either RX or TX to IDLE remain in the TX state until the current packet
3
automatically has been successfully transmitted. Then the
If the radio goes from TX or RX to IDLE by state will change as indicated by the
issuing an SIDLE strobe, calibration will not be MCSM1.TXOFF_MODE setting. The possible
performed. The calibration takes a constant destinations are the same as for RX.
number of XOSC cycles; see Table 34 for The MCU can manually change the state from
timing details regarding calibration. RX to TX and vice versa by using the
When RX is activated, the chip will remain in command strobes. If the radio controller is
receive mode until a packet is successfully currently in transmit and the SRX strobe is
received or the RX termination timer expires used, the current transmission will be ended
(see Section 19.7). The probability that a false and the transition to RX will be done.
sync word is detected can be reduced by
If the radio controller is in RX when the STX or
using PQT, CS, maximum sync word length,
and sync word qualifier mode as described in SFSTXON command strobes are used, the TX-
Section 17. After a packet is successfully if-CCA function will be used. If the channel is
received, the radio controller goes to the state not clear, the chip will remain in RX. The
indicated by the MCSM1.RXOFF_MODE setting. MCSM1.CCA_MODE setting controls the
The possible destinations are: conditions for clear channel assessment. See
Section 17.5 for details.
The SIDLE command strobe can always be
3
Not forced in IDLE by issuing an SIDLE used to force the radio controller to go to the
strobe IDLE state.

SWRS061I Page 52 of 98
 CC1101
19.5 Wake On Radio (WOR)
The optional Wake on Radio (WOR) Rx timeout
functionality enables CC1101 to periodically
State: SLEEP IDLE RX SLEEP IDLE RX
wake up from SLEEP and listen for incoming
packets without MCU interaction. Event0 Event1 Event0 Event1
t
When the SWOR strobe command is sent on tEvent0
the SPI interface, the CC1101 will go to the tEvent0
SLEEP state when CSn is released. The RC tEvent1 tEvent1
oscillator must be enabled before the SWOR
tSLEEP
strobe can be used, as it is the clock source
for the WOR timer. The on-chip timer will set
CC1101 into IDLE state and then RX state. After
Figure 28: Event 0 and Event 1 Relationship
a programmable time in RX, the chip will go
back to the SLEEP state, unless a packet is The time from the CC1101 enters SLEEP state
received. See Figure 28 and Section 19.7 for until the next Event0 is programmed to
details on how the timeout works. appear, tSLEEP in Figure 28, should be larger
than 11.08 ms when using a 26 MHz crystal
To exit WOR mode, set the CC1101 into the
and 10.67 ms when a 27 MHz crystal is used.
IDLE state
If tSLEEP is less than 11.08 (10.67) ms, there is
CC1101 can be set up to signal the MCU that a a chance that the consecutive Event 0 will
packet has been received by using the GDO occur
pins. If a packet is received, the
750
MCSM1.RXOFF_MODE will determine the 128 seconds
behaviour at the end of the received packet. f XOSC
When the MCU has read the packet, it can put too early. Application Note AN047 [4] explains
the chip back into SLEEP with the SWOR strobe in detail the theory of operation and the
from the IDLE state. different registers involved when using WOR,
as well as highlighting important aspects when
Note: The FIFO looses its content in the using WOR mode.
SLEEP state.
19.5.1 RC Oscillator and Timing
The WOR timer has two events, Event 0 and
Event 1. In the SLEEP state with WOR The frequency of the low-power RC oscillator
activated, reaching Event 0 will turn on the used for the WOR functionality varies with
temperature and supply voltage. In order to
digital regulator and start the crystal oscillator.
keep the frequency as accurate as possible,
Event 1 follows Event 0 after a programmed
the RC oscillator will be calibrated whenever
timeout.
possible, which is when the XOSC is running
The time between two consecutive Event 0 is and the chip is not in the SLEEP state. When
programmed with a mantissa value given by the power and XOSC are enabled, the clock
WOREVT1.EVENT0 and WOREVT0.EVENT0, used by the WOR timer is a divided XOSC
and an exponent value set by clock. When the chip goes to the sleep state,
WORCTRL.WOR_RES. The equation is: the RC oscillator will use the last valid
calibration result. The frequency of the RC
750
t Event 0   EVENT 0  2 5WOR _ RES oscillator is locked to the main crystal
f XOSC frequency divided by 750.

The Event 1 timeout is programmed with In applications where the radio wakes up very
WORCTRL.EVENT1. Figure 28 shows the often, typically several times every second, it
timing relationship between Event 0 timeout is possible to do the RC oscillator calibration
and Event 1 timeout. once and then turn off calibration to reduce the
current consumption. This is done by setting
WORCTRL.RC_CAL=0 and requires that RC
oscillator calibration values are read from
registers RCCTRL0_STATUS and
RCCTRL1_STATUS and written back to

SWRS061I Page 53 of 98
 CC1101
RCCTRL0 and RCCTRL1 respectively. If the temperature and supply voltage changes.
RC oscillator calibration is turned off, it will Refer to Application Note AN047 [4] for further
have to be manually turned on again if details.

19.6 Timing
19.6.1 Overall State Transition Times Table 34 shows timing in crystal clock cycles
for key state transitions.
The main radio controller needs to wait in
certain states in order to make sure that the Power on time and XOSC start-up times are
internal analog/digital parts have settled down variable, but within the limits stated in Table
and are ready to operate in the new states. A 13.
number of factors are important for the state
transition times: Note that TX to IDLE and TX to RX transition
times are functions of data rate (fbaudrate). When
 The crystal oscillator frequency, fxosc PA ramping is enabled (i.e.
FREND0.PA_POWER≠000b), TX to IDLE and
 PA ramping enabled or not TX to RX will require
 The data rate in cases where PA ramping (FREND0.PA_POWER)/8∙fbaudrate longer times
is enabled than the times stated in Table 34.
 The value of the TEST0, TEST1, and
FSCAL3 registers

Description Transition Time Transition Time [µs]

(no PA ramping)
IDLE to RX, no calibration 1953/fxosc 75.1
IDLE to RX, with calibration 1953/fxosc + FS calibration Time 799
IDLE to TX/FSTXON, no calibration 1954/fxosc 75.2
IDLE to TX/FSTXON, with calibration 1953/fxosc + FS calibration Time 799
TX to RX switch 782/fxosc + 0.25/fbaudrate 31.1
RX to TX switch 782/fxosc 30.1
TX to IDLE, no calibration ~0.25/fbaudrate ~1
TX to IDLE, with calibration ~0.25/fbaudrate + FS calibration Time 725
RX to IDLE, no calibration 2/fxosc ~0.1
RX to IDLE, with calibration 2/fxosc + FS calibration Time 724
Manual calibration 283/fxosc + FS calibration Time 735

Table 34: Overall State Transition Times (Example for 26 MHz crystal oscillator, 250 kBaud data
rate, and TEST0 = 0x0B (maximum calibration time)).

19.6.2 Frequency Synthesizer Calibration TEST0 when operating with different frequency
Time bands are 0x09 and 0x0B. SmartRF Studio
software [5] always sets
Table 35 summarizes the frequency FSCAL3.CHP_CURR_CAL_EN to 10b.
synthesizer (FS) calibration times for possible
settings of TEST0 and Note that in a frequency hopping spread
FSCAL3.CHP_CURR_CAL_EN. Setting spectrum or a multi-channel protocol the
FSCAL3.CHP_CURR_CAL_EN to 00b disables calibration time can be reduced from 712/724
the charge pump calibration stage. TEST0 is µs to 145/157 µs. This is explained in Section
set to the values recommended by SmartRF 28.2.
Studio software [5]. The possible values for

SWRS061I Page 54 of 98
 CC1101

TEST0 FSCAL3.CHP_CURR_CAL_EN FS Calibration Time FS Calibration Time

fxosc = 26 MHz fxosc = 27 MHz
0x09 00b 3764/fxosc = 145 us 3764/fxosc = 139 us
0x09 10b 18506/fxosc = 712 us 18506/fxosc = 685 us
0x0B 00b 4073/fxosc = 157 us 4073/fxosc = 151 us
0x0B 10b 18815/fxosc = 724 us 18815/fxosc = 697 us

Table 35: Frequency Synthesizer Calibration Times (26/27 MHz crystal)

19.7 RX Termination Timer

CC1101 has optional functions for automatic For ASK/OOK modulation, lack of carrier
termination of RX after a programmable time. sense is only considered valid after eight
The main use for this functionality is Wake on symbol periods. Thus, the
Radio, but it may also be useful for other MCSM2.RX_TIME_RSSI function can be used
applications. The termination timer starts when in ASK/OOK mode when the distance between
in RX state. The timeout is programmable with “1” symbols is eight or less.
the MCSM2.RX_TIME setting. When the timer
If RX terminates due to no carrier sense when
expires, the radio controller will check the
the MCSM2.RX_TIME_RSSI function is used,
condition for staying in RX; if the condition is
or if no sync word was found when using the
not met, RX will terminate.
MCSM2.RX_TIME timeout function, the chip
The programmable conditions are: will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
 MCSM2.RX_TIME_QUAL=0: Continue
Otherwise, the MCSM1.RXOFF_MODE setting
receive if sync word has been found
determines the state to go to when RX ends.
 MCSM2.RX_TIME_QUAL=1: Continue This means that the chip will not automatically
receive if sync word has been found, or if go back to SLEEP once a sync word has been
the preamble quality is above threshold received. It is therefore recommended to
(PQT) always wake up the microcontroller on sync
word detection when using WOR mode. This
If the system expects the transmission to have can be done by selecting output signal 6 (see
started when enabling the receiver, the Table 41 on page 62) on one of the
MCSM2.RX_TIME_RSSI function can be used. programmable GDO output pins, and
The radio controller will then terminate RX if programming the microcontroller to wake up
the first valid carrier sense sample indicates on an edge-triggered interrupt from this GDO
no carrier (RSSI below threshold). See Section pin.
17.4 for details on Carrier Sense.

SWRS061I Page 55 of 98
 CC1101

20 Data FIFO
The CC1101 contains two 64 byte FIFOs, one 3. Repeat steps 1 and 2 until n = # of bytes
for received data and one for data to be remaining in packet.
transmitted. The SPI interface is used to read
4. Read the remaining bytes from the RX
from the RX FIFO and write to the TX FIFO.
FIFO.
Section 10.5 contains details on the SPI FIFO
access. The FIFO controller will detect The 4-bit FIFOTHR.FIFO_THR setting is used
overflow in the RX FIFO and underflow in the to program threshold points in the FIFOs.
TX FIFO.
Table 36 lists the 16 FIFO_THR settings and
When writing to the TX FIFO it is the the corresponding thresholds for the RX and
responsibility of the MCU to avoid TX FIFO TX FIFOs. The threshold value is coded in
overflow. A TX FIFO overflow will result in an opposite directions for the RX FIFO and TX
error in the TX FIFO content. FIFO. This gives equal margin to the overflow
Likewise, when reading the RX FIFO the MCU and underflow conditions when the threshold
must avoid reading the RX FIFO past its empty is reached.
value since a RX FIFO underflow will result in FIFO_THR Bytes in TX FIFO Bytes in RX FIFO
an error in the data read out of the RX FIFO. 0 (0000) 61 4
The chip status byte that is available on the 1 (0001) 57 8
SO pin while transferring the SPI header and 2 (0010) 53 12
contains the fill grade of the RX FIFO if the 3 (0011) 49 16
access is a read operation and the fill grade of 4 (0100) 45 20
the TX FIFO if the access is a write operation. 5 (0101) 41 24
Section 10.1 contains more details on this. 6 (0110) 37 28
7 (0111) 33 32
The number of bytes in the RX FIFO and TX
FIFO can be read from the status registers 8 (1000) 29 36
RXBYTES.NUM_RXBYTES and 9 (1001) 25 40
TXBYTES.NUM_TXBYTES respectively. If a 10 (1010) 21 44
received data byte is written to the RX FIFO at 11 (1011) 17 48
the exact same time as the last byte in the RX 12 (1100) 13 52
FIFO is read over the SPI interface, the RX 13 (1101) 9 56
FIFO pointer is not properly updated and the 14 (1110) 5 60
last read byte will be duplicated. To avoid this 15 (1111) 1 64
problem, the RX FIFO should never be
emptied before the last byte of the packet is Table 36: FIFO_THR Settings and the
received. Corresponding FIFO Thresholds

For packet lengths less than 64 bytes it is A signal will assert when the number of bytes
recommended to wait until the complete in the FIFO is equal to or higher than the
packet has been received before reading it out programmed threshold. This signal can be
of the RX FIFO. viewed on the GDO pins (see Table 41 on
page 62).
If the packet length is larger than 64 bytes, the
MCU must determine how many bytes can be Figure 29 shows the number of bytes in both
read from the RX FIFO the RX FIFO and TX FIFO when the threshold
(RXBYTES.NUM_RXBYTES-1). The following signal toggles in the case of FIFO_THR=13.
software routine can be used: Figure 30 shows the signal on the GDO pin as
the respective FIFO is filled above the
1. Read RXBYTES.NUM_RXBYTES threshold, and then drained below in the case
repeatedly at a rate specified to be at least of FIFO_THR=13.
twice that of which RF bytes are received
until the same value is returned twice;
store value in n.
2. If n < # of bytes remaining in packet, read
n-1 bytes from the RX FIFO.

SWRS061I Page 56 of 98
 CC1101

Overflow NUM_RXBYTES 53 54 55 56 57 56 55 54 53
margin
GDO
FIFO_THR=13

NUM_TXBYTES 6 7 8 9 10 9 8 7 6

GDO

56 bytes
Figure 30: Number of Bytes in FIFO vs. the
GDO Signal (GDOx_CFG=0x00 in RX and
GDOx_CFG=0x02 in TX, FIFO_THR=13)

FIFO_THR=13

Underflow
margin 8 bytes

RXFIFO TXFIFO

Figure 29: Example of FIFOs at Threshold

21 Frequency Programming
The frequency programming in CC1101 is by the 24 bit frequency word located in the
designed to minimize the programming FREQ2, FREQ1, and FREQ0 registers. This
needed in a channel-oriented system. word will typically be set to the centre of the
lowest channel frequency that is to be used.
To set up a system with channel numbers, the
desired channel spacing is programmed with The desired channel number is programmed
the MDMCFG0.CHANSPC_M and with the 8-bit channel number register,
MDMCFG1.CHANSPC_E registers. The channel CHANNR.CHAN, which is multiplied by the
spacing registers are mantissa and exponent channel offset. The resultant carrier frequency
respectively. The base or start frequency is set is given by:

f carrier 
f XOSC
216
 
 FREQ  CHAN  256  CHANSPC _ M   2CHANSPC _ E 2 
With a 26 MHz crystal the maximum channel f XOSC
spacing is 405 kHz. To get e.g. 1 MHz channel f IF   FREQ _ IF
210
spacing, one solution is to use 333 kHz
channel spacing and select each third channel If any frequency programming register is
in CHANNR.CHAN. altered when the frequency synthesizer is
running, the synthesizer may give an
The preferred IF frequency is programmed undesired response. Hence, the frequency
with the FSCTRL1.FREQ_IF register. The IF programming should only be updated when
frequency is given by: the radio is in the IDLE state.

SWRS061I Page 57 of 98
 CC1101

22 VCO
The VCO is completely integrated on-chip.

22.1 VCO and PLL Self-Calibration

The VCO characteristics vary with temperature If calibration is performed each time before
and supply voltage changes as well as the entering active mode (RX or TX) the user can
desired operating frequency. In order to program register IOCFGx.GDOx_CFG to 0x0A
ensure reliable operation, CC1101 includes to check that the PLL is in lock. The lock
frequency synthesizer self-calibration circuitry. detector output available on the GDOx pin
This calibration should be done regularly, and should then be an interrupt for the MCU (x =
must be performed after turning on power and 0,1, or 2). A positive transition on the GDOx
before using a new frequency (or channel). pin means that the PLL is in lock. As an
The number of XOSC cycles for completing alternative the user can read register FSCAL1.
the PLL calibration is given in Table 34 on The PLL is in lock if the register content is
page 54. different from 0x3F. Refer also to the CC1101
Errata Notes [3]. The PLL must be re-
The calibration can be initiated automatically
calibrated until PLL lock is achieved if the PLL
or manually. The synthesizer can be
does not lock the first time.
automatically calibrated each time the
synthesizer is turned on, or each time the If the calibration is not performed each time
synthesizer is turned off automatically. This is before entering active mode (RX or TX) the
configured with the MCSM0.FS_AUTOCAL user should program register
register setting. In manual mode, the IOCFGx.GDOx_CFG to 0x0A to check that the
calibration is initiated when the SCAL PLL is in lock before receiving/transmitting
command strobe is activated in the IDLE data. The lock detector output available on the
mode. GDOx pin should then be an interrupt for the
MCU (x = 0,1, or 2). A positive transition on
Note: The calibration values are the GDOx pin means that the PLL is in lock.
maintained in SLEEP mode, so the Since the current calibration values are only
calibration is still valid after waking up from valid for a finite temperature range (typically
SLEEP mode unless supply voltage or ±40C) the PLL must be re-calibrated if the lock
temperature has changed significantly. indicator does not indicate PLL lock.

23 Voltage Regulators
CC1101 contains several on-chip linear voltage edge of SCLK (setup time is given in Table
regulators that generate the supply voltages 22).
needed by low-voltage modules. These
If the chip is programmed to enter power-down
voltage regulators are invisible to the user, and
mode (SPWD strobe issued), the power will be
can be viewed as integral parts of the various
turned off after CSn goes high. The power and
modules. The user must however make sure
crystal oscillator will be turned on again when
that the absolute maximum ratings and
CSn goes low.
required pin voltages in Table 1 and Table 19
are not exceeded. The voltage regulator for the digital core
requires one external decoupling capacitor.
By setting the CSn pin low, the voltage
regulator to the digital core turns on and the The voltage regulator output should only be
crystal oscillator starts. The SO pin on the SPI used for driving the CC1101.
interface must go low before the first positive

SWRS061I Page 58 of 98
 CC1101

24 Output Power Programming

The RF output power level from the device has If OOK modulation is used, the logic 0 and
two levels of programmability as illustrated in logic 1 power levels shall be programmed to
Figure 31. The special PATABLE register can index 0 and 1 respectively.
hold up to eight user selected output power
Table 39 contains recommended PATABLE
settings. The 3-bit FREND0.PA_POWER value
settings for various output levels and
selects the PATABLE entry to use. This two- frequency bands. DN013 [15] gives the
level functionality provides flexible PA power complete tables for the different frequency
ramp up and ramp down at the start and end bands using multi-layer inductors. Using PA
of transmission when using 2-FSK, GFSK, settings from 0x61 to 0x6F is not allowed.
4-FSK, and MSK modulation as well as ASK Table 40 contains output power and current
modulation shaping. All the PA power settings consumption for default PATABLE setting
in the PATABLE from index 0 up to the (0xC6).
FREND0.PA_POWER value are used.
See Section 10.6 for PATABLE programming
The power ramping at the start and at the end details. PATABLE must be programmed in
of a packet can be turned off by setting
burst mode if you want to write to other entries
FREND0.PA_POWER=0 and then program the
than PATABLE[0].
desired output power to index 0 in the
PATABLE. Note: All content of the PATABLE except
for the first byte (index 0) is lost when
entering the SLEEP state.

868 MHz 915 MHz

Output Current Current
Power Setting Consumption, Setting Consumption,
[dBm] Typ. [mA] Typ. [mA]
-30 0x03 12.0 0x03 11.9
-20 0x17 12.6 0x0E 12.5
-15 0x1D 13.3 0x1E 13.3
-10 0x26 14.5 0x27 14.8
-6 0x37 16.4 0x38 17.0
0 0x50 16.8 0x8E 17.2
5 0x86 19.9 0x84 20.2
7 0xCD 25.8 0xCC 25.7
10 0xC5 30.0 0xC3 30.7
12/11 0xC0 34.2 0xC0 33.4

Table 37: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
Using Wire-Wound Inductors in 868/915 MHz Frequency Bands

SWRS061I Page 59 of 98
 CC1101

868 MHz 915 MHz

Default Output Current Output Current
Power Power Consumption, Power Consumption,
Setting [dBm] Typ. [mA] [dBm] Typ. [mA]
0xC6 9.6 29.4 8.9 28.7

Table 38: Output Power and Current Consumption for Default PATABLE Setting Using Wire-
Wound Inductors in 868/915 MHz Frequency Bands

315 MHz 433 MHz 868 MHz 915 MHz

Output Current Current Current Current
Power Setting Consumption, Setting Consumption, Setting Consumption, Setting Consumption,
[dBm] Typ. [mA] Typ. [mA] Typ. [mA] Typ. [mA]
-30 0x12 10.9 0x12 11.9 0x03 12.1 0x03 12.0
-20 0x0D 11.4 0x0E 12.4 0x0F 12.7 0x0E 12.6
-15 0x1C 12.0 0x1D 13.1 0x1E 13.4 0x1E 13.4
-10 0x34 13.5 0x34 14.4 0x27 15.0 0x27 14.9
0 0x51 15.0 0x60 15.9 0x50 16.9 0x8E 16.7
5 0x85 18.3 0x84 19.4 0x81 21.0 0xCD 24.3
7 0xCB 22.1 0xC8 24.2 0xCB 26.8 0xC7 26.9
10 0xC2 26.9 0xC0 29.1 0xC2 32.4 0xC0 31.8

Table 39: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
Using Multi-layer Inductors

315 MHz 433 MHz 868 MHz 915 MHz

Default Output Current Output Current Output Current Output Current
Power Power Consumption, Power Consumption, Power Consumption, Power Consumption,
Setting [dBm] Typ. [mA] [dBm] Typ. [mA] [dBm] Typ. [mA] [dBm] Typ. [mA]
0xC6 8.5 24.4 7.8 25.2 8.5 29.5 7.2 27.4

Table 40: Output Power and Current Consumption for Default PATABLE Setting Using Multi-layer
Inductors

25 Shaping and PA Ramping

With ASK modulation, up to eight power This counter value is used as an index for a
settings are used for shaping. The modulator lookup in the power table. Thus, in order to
contains a counter that counts up when utilize the whole table, FREND0.PA_POWER
transmitting a one and down when transmitting should be 7 when ASK is active. The shaping
a zero. The counter counts at a rate equal to 8 of the ASK signal is dependent on the
times the symbol rate. The counter saturates configuration of the PATABLE. Figure 32
at FREND0.PA_POWER and 0 respectively. shows some examples of ASK shaping.

SWRS061I Page 60 of 98
 CC1101

PATABLE(7)[7:0]
The PA uses this
PATABLE(6)[7:0]
setting.
PATABLE(5)[7:0]
PATABLE(4)[7:0]
Settings 0 to PA_POWER are
PATABLE(3)[7:0] used during ramp-up at start of
transmission and ramp-down at
PATABLE(2)[7:0] end of transmission, and for
PATABLE(1)[7:0] ASK/OOK modulation.

PATABLE(0)[7:0]

Index into PATABLE(7:0)

The SmartRF® Studio software
e.g 6 should be used to obtain optimum
PATABLE settings for various
PA_POWER[2:0] output powers.
in FREND0 register

Figure 31: PA_POWER and PATABLE

Output Power

PATABLE[7]
PATABLE[6]
PATABLE[5]
PATABLE[4]
PATABLE[3]
PATABLE[2]
PATABLE[1]
PATABLE[0]
Time
1 0 0 1 0 1 1 0 Bit Sequence

FREND0.PA_POWER = 3

FREND0.PA_POWER = 7

Figure 32: Shaping of ASK Signal

26 General Purpose / Test Output Control Pins

The three digital output pins GDO0, GDO1, An on-chip analog temperature sensor is
and GDO2 are general control pins configured enabled by writing the value 128 (0x80) to the
with IOCFG0.GDO0_CFG, IOCFG0 register. The voltage on the GDO0
IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG pin is then proportional to temperature. See
respectively. Table 41 shows the different Section 4.7 for temperature sensor
signals that can be monitored on the GDO specifications.
pins. These signals can be used as inputs to
If the IOCFGx.GDOx_CFG setting is less than
the MCU.
0x20 and IOCFGx_GDOx_INV is 0 (1), the
GDO1 is the same pin as the SO pin on the GDO0 and GDO2 pins will be hardwired to 0
SPI interface, thus the output programmed on (1), and the GDO1 pin will be hardwired to 1
this pin will only be valid when CSn is high. (0) in the SLEEP state. These signals will be
The default value for GDO1 is 3-stated which hardwired until the CHIP_RDYn signal goes
is useful when the SPI interface is shared with low.
other devices.
If the IOCFGx.GDOx_CFG setting is 0x20 or
The default value for GDO0 is a 135-141 kHz higher, the GDO pins will work as programmed
clock output (XOSC frequency divided by also in SLEEP state. As an example, GDO1 is
192). Since the XOSC is turned on at power- high impedance in all states if
on-reset, this can be used to clock the MCU in IOCFG1.GDO1_CFG=0x2E.
systems with only one crystal. When the MCU
is up and running, it can change the clock
frequency by writing to IOCFG0.GDO0_CFG.

SWRS061I Page 61 of 98
 CC1101
GDOx_CFG[5:0] Description
0 (0x00) Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO
is drained below the same threshold.
1 (0x01) Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is
reached. De-asserts when the RX FIFO is empty.
2 (0x02) Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX
FIFO is below the same threshold.
3 (0x03) Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below the TX FIFO
threshold.
4 (0x04) Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will also de-
6 (0x06) assert when a packet is discarded due to address or maximum length filtering or when the radio enters
RXFIFO_OVERFLOW state. In TX the pin will de-assert if the TX FIFO underflows.
7 (0x07) Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO.
8 (0x08) Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. De-asserted when the chip re-
enters RX state (MARCSTATE=0x0D) or the PQI gets below the programmed PQT value.
9 (0x09) Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting).
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To
10 (0x0A) check for PLL lock the lock detector output should be used as an interrupt for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.
11 (0x0B) In RX mode, data is set up on the falling edge by CC1101 when GDOx_INV=0.
In TX mode, data is sampled by CC1101 on the rising edge of the serial clock when GDOx_INV=0.
12 (0x0C) Serial Synchronous Data Output. Used for synchronous serial mode.
13 (0x0D) Serial Data Output. Used for asynchronous serial mode.
14 (0x0E) Carrier sense. High if RSSI level is above threshold. Cleared when entering IDLE mode.
15 (0x0F) CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.
16 (0x10)
to Reserved – used for test
21 (0x15)
22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
24 (0x18)
to Reserved – used for test
26 (0x1A)
PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch
27 (0x1B) in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX
28 (0x1C) switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead.
29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.
30 (0x1E)
to Reserved – used for test
35 (0x23)
36 (0x24) WOR_EVNT0
37 (0x25) WOR_EVNT1
38 (0x26) CLK_256
39 (0x27) CLK_32k
40 (0x28) Reserved – used for test
41 (0x29) CHIP_RDYn
42 (0x2A) Reserved – used for test
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test
45 (0x2D) Reserved – used for test
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch.
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4 Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any
53 (0x35) CLK_XOSC/6 time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must
54 (0x36) CLK_XOSC/8 be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
55 (0x37) CLK_XOSC/12
56 (0x38) CLK_XOSC/16 To optimize RF performance, these signals should not be used while the radio is in RX or TX
57 (0x39) CLK_XOSC/24 mode.
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192

Table 41: GDOx Signal Selection (x = 0, 1, or 2)

SWRS061I Page 62 of 98
 CC1101

27 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have to use the built-in packet handling features, as
been included in the CC1101 to provide they can give more robust communication,
backward compatibility with previous Chipcon significantly offload the microcontroller, and
products and other existing RF communication simplify software development.
systems. For new systems, it is recommended

27.1 Asynchronous Serial Operation

Asynchronous transfer is included in the for the asynchronous stream is that the error in
CC1101 for backward compatibility with systems the bit period must be less than one eighth of
that are already using the asynchronous data the programmed data rate.
transfer.
In asynchronous serial mode no data decision
When asynchronous transfer is enabled, is done on-chip and the raw data is put on the
several of the support mechanisms for the data output line in RX. When using
MCU that are included in CC1101 will be asynchronous serial mode make sure the
disabled, such as packet handling hardware, interfacing MCU does proper oversampling
buffering in the FIFO, and so on. The and that it can handle the jitter on the data
asynchronous transfer mode does not allow output line. The MCU should tolerate a jitter of
for the use of the data whitener, interleaver, ±1/8 of a bit period as the data stream is time-
and FEC, and it is not possible to use discrete using 8 samples per bit.
Manchester encoding. MSK is not supported In asynchronous serial mode there will be
for asynchronous transfer. glitches of 37 - 38.5 ns duration (1/XOSC)
Setting PKTCTRL0.PKT_FORMAT to 3 occurring infrequently and with random
enables asynchronous serial mode. In TX, the periods. A simple RC filter can be added to the
GDO0 pin is used for data input (TX data). data output line between CC1101 and the MCU
Data output can be on GDO0, GDO1, or to get rid of the 37 - 38.5 ns ns glitches if
GDO2. This is set by the considered a problem. The filter 3 dB cut-off
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG frequency needs to be high enough so that the
and IOCFG2.GDO2_CFG fields. data is not filtered and at the same time low
enough to remove the glitch. As an example,
The CC1101 modulator samples the level of the for 2.4 kBaud data rate a 1 kohm resistor and
asynchronous input 8 times faster than the 2.7 nF capacitor can be used. This gives a 3
programmed data rate. The timing requirement dB cut-off frequency of 59 kHz.

27.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 If preamble and sync word is disabled, all
enables synchronous serial mode. In the other packet handler features and FEC should
synchronous serial mode, data is transferred also be disabled. The MCU must then handle
on a two-wire serial interface. The CC1101 preamble and sync word insertion and
provides a clock that is used to set up new detection in software.
data on the data input line or sample data on If preamble and sync word insertion/detection
the data output line. Data input (TX data) is on are left on, all packet handling features and
the GDO0 pin. This pin will automatically be FEC can be used. One exception is that the
configured as an input when TX is active. The address filtering feature is unavailable in
TX latency is 8 bits. The data output pin can synchronous serial mode.
be any of the GDO pins. This is set by the
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, When using the packet handling features in
and IOCFG2.GDO2_CFG fields. Time from synchronous serial mode, the CC1101 will insert
start of reception until data is available on the and detect the preamble and sync word and
receiver data output pin is equal to 9 bit. the MCU will only provide/get the data
payload. This is equivalent to the
Preamble and sync word insertion/detection recommended FIFO operation mode.
may or may not be active, dependent on the
sync mode set by the MDMCFG2.SYNC_MODE. An alternative serial RX output option is to
configure any of the GD0 pins for

SWRS061I Page 63 of 98
 CC1101
RX_SYMBOL_TICK and RX_HARD_DATA, see RX_SYMBOL_TICK signal is the symbol clock
Table 41. RX_HARD_DATA[1:0] is the hard and is high for one half symbol period
decision symbol. RX_HARD_DATA[1:0] whenever a new symbol is presented on the
contain data for 4-ary modulation formats hard and soft data outputs. This option may be
while RX_HARD_DATA[1] contain data for 2- used for both synchronous and asynchronous
ary modulation formats. The interfaces.

28 System Considerations and Guidelines

28.1 SRD Regulations
International regulations and national laws For compliance with modulation bandwidth
regulate the use of radio receivers and requirements under EN 300 220 in the 863 to
transmitters. Short Range Devices (SRDs) for 870 MHz frequency range it is recommended
license free operation below 1 GHz are usually to use a 26 MHz crystal for frequencies below
operated in the 315 MHz, 433 MHz, 868 MHz 869 MHz and a 27 MHz crystal for frequencies
or 915 MHz frequency bands. The CC1101 is above 869 MHz.
specifically designed for such use with its 300
Please note that compliance with regulations
- 348 MHz, 387 - 464 MHz, and 779 - 928
is dependent on the complete system
MHz operating ranges. The most important
performance. It is the customer’s responsibility
regulations when using the CC1101 in the 315 to ensure that the system complies with
MHz, 433 MHz, 868 MHz, or 915 MHz regulations.
frequency bands are EN 300 220 (Europe)
and FCC CFR47 Part 15 (USA).

28.2 Frequency Hopping and Multi-Channel Systems

The 315 MHz, 433 MHz, 868 MHz, or 915 2) Fast frequency hopping without calibration
MHz bands are shared by many systems both for each hop can be done by performing the
in industrial, office, and home environments. It necessary calibrating at startup and saving the
is therefore recommended to use frequency resulting FSCAL3, FSCAL2, and FSCAL1
hopping spread spectrum (FHSS) or a multi- register values in MCU memory. The VCO
channel protocol because the frequency capacitance calibration FSCAL1 register value
diversity makes the system more robust with must be found for each RF frequency to be
respect to interference from other systems used. The VCO current calibration value and
operating in the same frequency band. FHSS the charge pump current calibration value
also combats multipath fading. available in FSCAL2 and FSCAL3 respectively
CC1101 is highly suited for FHSS or multi- are not dependent on the RF frequency, so the
channel systems due to its agile frequency same value can therefore be used for all RF
synthesizer and effective communication frequencies for these two registers. Between
interface. Using the packet handling support each frequency hop, the calibration process
and data buffering is also beneficial in such can then be replaced by writing the FSCAL3,
systems as these features will significantly FSCAL2 and FSCAL1 register values that
offload the host controller. corresponds to the next RF frequency. The
PLL turn on time is approximately 75 µs (Table
Charge pump current, VCO current, and VCO 34). The blanking interval between each
capacitance array calibration data is required frequency hop is then approximately 75 µs.
for each frequency when implementing
frequency hopping for CC1101. There are 3 3) Run calibration on a single frequency at
ways of obtaining the calibration data from the startup. Next write 0 to FSCAL3[5:4] to
chip: disable the charge pump calibration. After
writing to FSCAL3[5:4], strobe SRX (or STX)
1) Frequency hopping with calibration for each with MCSM0.FS_AUTOCAL=1 for each new
hop. The PLL calibration time is 712/724 µs
frequency hop. That is, VCO current and VCO
(26 MHz crystal and TEST0 = 0x09/0B, see capacitance calibration is done, but not charge
Table 35). The blanking interval between each pump current calibration. When charge pump
frequency hop is then 787/799 µs. current calibration is disabled the calibration

SWRS061I Page 64 of 98
 CC1101
time is reduced from 712/724 µs to 145/157 µs The recommended settings for
(26 MHz crystal and TEST0 = 0x09/0B, see TEST0.VCO_SEL_CAL_EN change with
Table 35). The blanking interval between each frequency. This means that one should always
frequency hop is then 220/232 µs. use SmartRF Studio [5] to get the correct
settings for a specific frequency before doing a
There is a trade off between blanking time and
calibration, regardless of which calibration
memory space needed for storing calibration
method is being used.
data in non-volatile memory. Solution 2) above
gives the shortest blanking interval, but
requires more memory space to store Note: The content in the TEST0 register is
calibration values. This solution also requires not retained in SLEEP state, thus it is
that the supply voltage and temperature do not necessary to re-write this register when
vary much in order to have a robust solution. returning from the SLEEP state.
Solution 3) gives 567 µs smaller blanking
interval than solution 1).

28.3 Wideband Modulation when not Using Spread Spectrum

Digital modulation systems under FCC Section targeting compliance with digital modulation
15.247 include 2-FSK, GFSK, and 4-FSK system as defined by FCC Section 15.247. An
modulation. A maximum peak output power of external power amplifier such as CC1190 [21] is
1 W (+30 dBm) is allowed if the 6 dB needed to increase the output above +11
bandwidth of the modulated signal exceeds dBm. Please refer to DN006 [11] for further
500 kHz. In addition, the peak power spectral details concerning wideband modulation using
density conducted to the antenna shall not be CC1101 and DN036 for wideband modulation at
greater than +8 dBm in any 3 kHz band. 600 kbps data rate, +19 dBm output power
Operating at high data rates and frequency when using CC1101 +CC1101 [25].
separation, the CC1101 is suited for systems

28.4 Wireless MBUS

The wireless MBUS standard is a cost, low power and flexible transceiver, and
communication standard for meters and MSP430 a high performance and low power
wireless readout of meters, and specifies the MCU. For more informati on regarding using
physical and the data link layer. Power CC1101 for Wireless MBUS applications, see
consumption is a critical parameter for the AN067 [14].
meter side, since the communication link shall
be operative for the full lifetime of the meter, Since the Wireless MBUS standard operates
without changing the battery. CC1101 combined in the 868-870 ISM band, the radio
requirements must also comply with the ETSI
with MSP430 is an excellent choice for the
EN 300 220 and CEPT/ERC/REC 70-03 E
Wireless MBUS standard, CC1101 is a truly low
standards.

28.5 Data Burst Transmissions

The high maximum data rate of CC1101 opens Reducing the time in active mode will reduce
up for burst transmissions. A low average data the likelihood of collisions with other systems
rate link (e.g. 10 kBaud) can be realized by in the same frequency range.
using a higher over-the-air data rate. Buffering
the data and transmitting in bursts at high data Note: The sensitivity and thus transmission
rate (e.g. 500 kBaud) will reduce the time in range is reduced for high data rate bursts
active mode, and hence also reduce the compared to lower data rates.
average current consumption significantly.

28.6 Continuous Transmissions

In data streaming applications, the CC1101 done with a closed loop PLL, there is no
opens up for continuous transmissions at 500 limitation in the length of a transmission (open
kBaud effective data rate. As the modulation is loop modulation used in some transceivers

SWRS061I Page 65 of 98
 CC1101
often prevents this kind of continuous data streaming and reduces the effective data rate).

28.7 Battery Operated Systems

In low power applications, the SLEEP state running in the SLEEP state if start-up time is
with the crystal oscillator core switched off critical. The WOR functionality should be used
should be used when the CC1101 is not active. in low power applications.
It is possible to leave the crystal oscillator core

28.8 Increasing Range

In some applications it may be necessary to improved receiver sensitivity in addition to
extend the range. The CC1190 [21] is a range switches and RF matching for simple design of
extender for 850-950 MHz RF transceivers, high performance wireless systems. Refer to
transmitters, and System-on-Chip devices AN094 [22] and AN096 [23] for performance
from Texas Instruments. It increases the link figures of the CC1101 + CC1190 combination.
budget by providing a power amplifier (PA) for
Figure 33 shows a simplified application
increased output power, and a low-noise
circuit.
amplifier (LNA) with low noise figure for

VDD
VDD
1 2 A
A A N
P P L
_ _ _
D D D PA_IN RF_P
D D D SAW
V V V LNA_OUT
PA_OUT RF_N

CC1101
CC1190
TR_SW
PA_EN GDOx
LNA_EN
LNA_IN
S HGM
A
IB

Connected to MCU

Connected to
VDD/GND/MCU

Figure 33: Simplified CC1101-CC1190 Application Circuit

29 Configuration Registers
The configuration of CC1101 is done by registers listed in Table 43. Many of these
programming 8-bit registers. The optimum registers are for test purposes only, and need
configuration data based on selected system not be written for normal operation of CC1101.
parameters are most easily found by using the
There are also 12 status registers that are
SmartRF Studio software [5]. Complete
listed in Table 44. These registers, which are
descriptions of the registers are given in the
read-only, contain information about the status
following tables. After chip reset, all the
registers have default values as shown in the of CC1101.
tables. The optimum register setting might The two FIFOs are accessed through one 8-bit
differ from the default value. After a reset, all register. Write operations write to the TX FIFO,
registers that shall be different from the default while read operations read from the RX FIFO.
value therefore needs to be programmed
through the SPI interface. During the header byte transfer and while
writing data to a register or the TX FIFO, a
There are 13 command strobe registers, listed status byte is returned on the SO line. This
in Table 42. Accessing these registers will status byte is described in Table 23 on page
initiate the change of an internal state or 31.
mode. There are 47 normal 8-bit configuration

SWRS061I Page 66 of 98
 CC1101
Table 45 summarizes the SPI address space. read/write bits on the top. Note that the burst
The address to use is given by adding the bit has different meaning for base addresses
base address to the left and the burst and above and below 0x2F.

Address Strobe Description

Name
0x30 SRES Reset chip.
0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
0x32 SXOFF Turn off crystal oscillator.
0x33 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
setting manual calibration mode (MCSM0.FS_AUTOCAL=0)

0x34 SRX Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.

0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
0x38 SWOR Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if
WORCTRL.RC_PD=0.
0x39 SPWD Enter power down mode when CSn goes high.
0x3A SFRX Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states.
0x3B SFTX Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
0x3C SWORRST Reset real time clock to Event1 value.
0x3D SNOP No operation. May be used to get access to the chip status byte.

Table 42: Command Strobes

SWRS061I Page 67 of 98
 CC1101
Preserved in Details on
Address Register Description
SLEEP State Page Number
0x00 IOCFG2 GDO2 output pin configuration Yes 71

0x01 IOCFG1 GDO1 output pin configuration Yes 71

0x02 IOCFG0 GDO0 output pin configuration Yes 71

0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 72
0x04 SYNC1 Sync word, high byte Yes 73
0x05 SYNC0 Sync word, low byte Yes 73
0x06 PKTLEN Packet length Yes 73
0x07 PKTCTRL1 Packet automation control Yes 73
0x08 PKTCTRL0 Packet automation control Yes 74
0x09 ADDR Device address Yes 74
0x0A CHANNR Channel number Yes 74
0x0B FSCTRL1 Frequency synthesizer control Yes 75
0x0C FSCTRL0 Frequency synthesizer control Yes 75
0x0D FREQ2 Frequency control word, high byte Yes 75
0x0E FREQ1 Frequency control word, middle byte Yes 75
0x0F FREQ0 Frequency control word, low byte Yes 75
0x10 MDMCFG4 Modem configuration Yes 76
0x11 MDMCFG3 Modem configuration Yes 76
0x12 MDMCFG2 Modem configuration Yes 77
0x13 MDMCFG1 Modem configuration Yes 78
0x14 MDMCFG0 Modem configuration Yes 78
0x15 DEVIATN Modem deviation setting Yes 79
0x16 MCSM2 Main Radio Control State Machine configuration Yes 80
0x17 MCSM1 Main Radio Control State Machine configuration Yes 81
0x18 MCSM0 Main Radio Control State Machine configuration Yes 82
0x19 FOCCFG Frequency Offset Compensation configuration Yes 83
0x1A BSCFG Bit Synchronization configuration Yes 84
0x1B AGCTRL2 AGC control Yes 85
0x1C AGCTRL1 AGC control Yes 86
0x1D AGCTRL0 AGC control Yes 87
0x1E WOREVT1 High byte Event 0 timeout Yes 87
0x1F WOREVT0 Low byte Event 0 timeout Yes 88
0x20 WORCTRL Wake On Radio control Yes 88
0x21 FREND1 Front end RX configuration Yes 89
0x22 FREND0 Front end TX configuration Yes 89
0x23 FSCAL3 Frequency synthesizer calibration Yes 89
0x24 FSCAL2 Frequency synthesizer calibration Yes 90
0x25 FSCAL1 Frequency synthesizer calibration Yes 90
0x26 FSCAL0 Frequency synthesizer calibration Yes 90
0x27 RCCTRL1 RC oscillator configuration Yes 90
0x28 RCCTRL0 RC oscillator configuration Yes 90
0x29 FSTEST Frequency synthesizer calibration control No 91
0x2A PTEST Production test No 91
0x2B AGCTEST AGC test No 91
0x2C TEST2 Various test settings No 91
0x2D TEST1 Various test settings No 91
0x2E TEST0 Various test settings No 92

Table 43: Configuration Registers Overview

SWRS061I Page 68 of 98
 CC1101

Address Register Description Details on page number

0x30 (0xF0) PARTNUM Part number for CC1101 92

0x31 (0xF1) VERSION Current version number 92

0x32 (0xF2) FREQEST Frequency Offset Estimate 92
0x33 (0xF3) LQI Demodulator estimate for Link Quality 92
0x34 (0xF4) RSSI Received signal strength indication 92
0x35 (0xF5) MARCSTATE Control state machine state 93
0x36 (0xF6) WORTIME1 High byte of WOR timer 93
0x37 (0xF7) WORTIME0 Low byte of WOR timer 93
0x38 (0xF8) PKTSTATUS Current GDOx status and packet status 94
Current setting from PLL calibration 94
0x39 (0xF9) VCO_VC_DAC module
Underflow and number of bytes in the TX 94
0x3A (0xFA) TXBYTES FIFO
Overflow and number of bytes in the RX 94
0x3B (0xFB) RXBYTES FIFO
0x3C (0xFC) RCCTRL1_STATUS Last RC oscillator calibration result 94
0x3D (0xFD) RCCTRL0_STATUS Last RC oscillator calibration result 95

Table 44: Status Registers Overview

Table 45: SPI Address Space (see next page)

SWRS061I Page 69 of 98
 CC1101
Write Read
Single Byte Burst Single Byte Burst
+0x00 +0x40 +0x80 +0xC0
0x00 IOCFG2
0x01 IOCFG1
0x02 IOCFG0
0x03 FIFOTHR
0x04 SYNC1
0x05 SYNC0
0x06 PKTLEN
0x07 PKTCTRL1
0x08 PKTCTRL0
0x09 ADDR
0x0A CHANNR
0x0B FSCTRL1
0x0C FSCTRL0
0x0D FREQ2
0x0E FREQ1

R/W configuration registers, burst access possible

0x0F FREQ0
0x10 MDMCFG4
0x11 MDMCFG3
0x12 MDMCFG2
0x13 MDMCFG1
0x14 MDMCFG0
0x15 DEVIATN
0x16 MCSM2
0x17 MCSM1
0x18 MCSM0
0x19 FOCCFG
0x1A BSCFG
0x1B AGCCTRL2
0x1C AGCCTRL1
0x1D AGCCTRL0
0x1E WOREVT1
0x1F WOREVT0
0x20 WORCTRL
0x21 FREND1
0x22 FREND0
0x23 FSCAL3
0x24 FSCAL2
0x25 FSCAL1
0x26 FSCAL0
0x27 RCCTRL1
0x28 RCCTRL0
0x29 FSTEST
0x2A PTEST
0x2B AGCTEST
0x2C TEST2
0x2D TEST1
0x2E TEST0
0x2F
0x30 SRES SRES PARTNUM
0x31 SFSTXON SFSTXON VERSION
0x32 SXOFF SXOFF FREQEST
Command Strobes, Status registers
(read only) and multi byte registers

0x33 SCAL SCAL LQI

0x34 SRX SRX RSSI
0x35 STX STX MARCSTATE
0x36 SIDLE SIDLE WORTIME1
0x37 WORTIME0
0x38 SWOR SWOR PKTSTATUS
0x39 SPWD SPWD VCO_VC_DAC
0x3A SFRX SFRX TXBYTES
0x3B SFTX SFTX RXBYTES
0x3C SWORRST SWORRST RCCTRL1_STATUS
0x3D SNOP SNOP RCCTRL0_STATUS
0x3E PATABLE PATABLE PATABLE PATABLE
0x3F TX FIFO TX FIFO RX FIFO RX FIFO

SWRS061I Page 70 of 98
 CC1101
29.1 Configuration Register Details – Registers with preserved values in SLEEP state

0x00: IOCFG2 – GDO2 Output Pin Configuration

Bit Field Name Reset R/W Description

7 R0 Not used
6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHP_RDYn (See Table 41 on page 62).

0x01: IOCFG1 – GDO1 Output Pin Configuration

Bit Field Name Reset R/W Description

7 GDO_DS 0 R/W Set high (1) or low (0) output drive strength on the GDO pins.
6 GDO1_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO1_CFG[5:0] 46 (0x2E) R/W Default is 3-state (See Table 41 on page 62).

0x02: IOCFG0 – GDO0 Output Pin Configuration

Bit Field Name Reset R/W Description

7 TEMP_SENSOR_ENABLE 0 R/W Enable analog temperature sensor. Write 0 in all other register
bits when using temperature sensor.
6 GDO0_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO0_CFG[5:0] 63 (0x3F) R/W Default is CLK_XOSC/192 (See Table 41 on page 62).
It is recommended to disable the clock output in initialization, in
order to optimize RF performance.

SWRS061I Page 71 of 98
 CC1101
0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds
Bit Field Name Reset R/W Description

7 0 R/W Reserved , write 0 for compatibility with possible future extensions

6 ADC_RETENTION 0 R/W 0: TEST1 = 0x31 and TEST2= 0x88 when waking up from SLEEP
1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP
Note that the changes in the TEST registers due to the
ADC_RETENTION bit setting are only seen INTERNALLY in the analog
part. The values read from the TEST registers when waking up from
SLEEP mode will always be the reset value.
The ADC_RETENTION bit should be set to 1before going into SLEEP
mode if settings with an RX filter bandwidth below 325 kHz are wanted at
time of wake-up.
5:4 CLOSE_IN_RX [1:0] 0 (00) R/W For more details, please see DN010 [8]
Setting RX Attenuation, Typical Values
0 (00) 0 dB
1 (01) 6 dB
2 (10) 12 dB
3 (11) 18 dB

3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO and RX FIFO. The threshold is
exceeded when the number of bytes in the FIFO is equal to or higher than
the threshold value.
Setting Bytes in TX FIFO Bytes in RX FIFO
0 (0000) 61 4
1 (0001) 57 8
2 (0010) 53 12
3 (0011) 49 16
4 (0100) 45 20
5 (0101) 41 24
6 (0110) 37 28
7 (0111) 33 32
8 (1000) 29 36
9 (1001) 25 40
10 (1010) 21 44
11 (1011) 17 48
12 (1100) 13 52
13 (1101) 9 56
14 (1110) 5 60
15 (1111) 1 64

SWRS061I Page 72 of 98
 CC1101
0x04: SYNC1 – Sync Word, High Byte
Bit Field Name Reset R/W Description

7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word

0x05: SYNC0 – Sync Word, Low Byte

Bit Field Name Reset R/W Description

7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word

0x06: PKTLEN – Packet Length

Bit Field Name Reset R/W Description

7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed packet length mode is enabled. If
variable packet length mode is used, this value indicates the maximum
packet length allowed. This value must be different from 0.

0x07: PKTCTRL1 – Packet Automation Control

Bit Field Name Reset R/W Description

7:5 PQT[2:0] 0 (0x00) R/W Preamble quality estimator threshold. The preamble quality estimator
increases an internal counter by one each time a bit is received that is
different from the previous bit, and decreases the counter by 8 each time a
bit is received that is the same as the last bit.
A threshold of 4∙PQT for this counter is used to gate sync word detection.
When PQT=0 a sync word is always accepted.
4 0 R0 Not Used.
3 CRC_AUTOFLUSH 0 R/W Enable automatic flush of RX FIFO when CRC is not OK. This requires that
only one packet is in the RXIFIFO and that packet length is limited to the
RX FIFO size.
2 APPEND_STATUS 1 R/W When enabled, two status bytes will be appended to the payload of the
packet. The status bytes contain RSSI and LQI values, as well as CRC OK.
1:0 ADR_CHK[1:0] 0 (00) R/W Controls address check configuration of received packages.
Setting Address check configuration
0 (00) No address check
1 (01) Address check, no broadcast
2 (10) Address check and 0 (0x00) broadcast
3 (11) Address check and 0 (0x00) and 255 (0xFF)
broadcast

SWRS061I Page 73 of 98
 CC1101
0x08: PKTCTRL0 – Packet Automation Control
Bit Field Name Reset R/W Description

7 R0 Not used
6 WHITE_DATA 1 R/W Turn data whitening on / off
0: Whitening off
1: Whitening on
5:4 PKT_FORMAT[1:0] 0 (00) R/W Format of RX and TX data
Setting Packet format
0 (00) Normal mode, use FIFOs for RX and TX
Synchronous serial mode, Data in on GDO0 and
1 (01)
data out on either of the GDOx pins
Random TX mode; sends random data using PN9
2 (10) generator. Used for test.
Works as normal mode, setting 0 (00), in RX
Asynchronous serial mode, Data in on GDO0 and
3 (11)
data out on either of the GDOx pins

3 0 R0 Not used
2 CRC_EN 1 R/W 1: CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
1:0 LENGTH_CONFIG[1:0] 1 (01) R/W Configure the packet length
Setting Packet length configuration
0 (00) Fixed packet length mode. Length configured in
PKTLEN register
1 (01) Variable packet length mode. Packet length
configured by the first byte after sync word
2 (10) Infinite packet length mode
3 (11) Reserved

0x09: ADDR – Device Address

Bit Field Name Reset R/W Description

7:0 DEVICE_ADDR[7:0] 0 (0x00) R/W Address used for packet filtration. Optional broadcast addresses are 0
(0x00) and 255 (0xFF).

0x0A: CHANNR – Channel Number

Bit Field Name Reset R/W Description

7:0 CHAN[7:0] 0 (0x00) R/W The 8-bit unsigned channel number, which is multiplied by the channel
spacing setting and added to the base frequency.

SWRS061I Page 74 of 98
 CC1101
0x0B: FSCTRL1 – Frequency Synthesizer Control
Bit Field Name Reset R/W Description

7:6 R0 Not used

5 0 R/W Reserved
4:0 FREQ_IF[4:0] 15 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency
in RX and controls the digital complex mixer in the demodulator.

f XOSC
f IF   FREQ _ IF
210
The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz
crystal.

0x0C: FSCTRL0 – Frequency Synthesizer Control

Bit Field Name Reset R/W Description

7:0 FREQOFF[7:0] 0 (0x00) R/W Frequency offset added to the base frequency before being used by the
frequency synthesizer. (2s-complement).
Resolution is FXTAL/214 (1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz,
dependent of XTAL frequency.

0x0D: FREQ2 – Frequency Control Word, High Byte

Bit Field Name Reset R/W Description

7:6 FREQ[23:22] 0 (00) R FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26-27 MHz
crystal)
5:0 FREQ[21:16] 30 (0x1E) R/W FREQ[23:0] is the base frequency for the frequency synthesiser in
increments of fXOSC/216.

 FREQ 23 : 0
f XOSC
f carrier 
216

0x0E: FREQ1 – Frequency Control Word, Middle Byte

Bit Field Name Reset R/W Description

7:0 FREQ[15:8] 196 (0xC4) R/W Ref. FREQ2 register

0x0F: FREQ0 – Frequency Control Word, Low Byte

Bit Field Name Reset R/W Description

7:0 FREQ[7:0] 236 (0xEC) R/W Ref. FREQ2 register

SWRS061I Page 75 of 98
 CC1101
0x10: MDMCFG4 – Modem Configuration
Bit Field Name Reset R/W Description

7:6 CHANBW_E[1:0] 2 (0x02) R/W

5:4 CHANBW_M[1:0] 0 (0x00) R/W Sets the decimation ratio for the delta-sigma ADC input stream and thus the
channel bandwidth.

f XOSC
BWchannel 
8  (4  CHANBW _ M )·2CHANBW _ E
The default values give 203 kHz channel filter bandwidth, assuming a 26.0
MHz crystal.
3:0 DRATE_E[3:0] 12 (0x0C) R/W The exponent of the user specified symbol rate

0x11: MDMCFG3 – Modem Configuration

Bit Field Name Reset R/W Description

7:0 DRATE_M[7:0] 34 (0x22) R/W The mantissa of the user specified symbol rate. The symbol rate is configured
using an unsigned, floating-point number with 9-bit mantissa and 4-bit
exponent. The 9th bit is a hidden ‘1’. The resulting data rate is:

RDATA 
256  DRATE _ M   2 DRATE _ E  f
XOSC
228
The default values give a data rate of 115.051 kBaud (closest setting to 115.2
kBaud), assuming a 26.0 MHz crystal.

SWRS061I Page 76 of 98
 CC1101
0x12: MDMCFG2 – Modem Configuration
Bit Field Name Reset R/W Description

7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator.

0 = Enable (better sensitivity)
1 = Disable (current optimized). Only for data rates
≤ 250 kBaud
The recommended IF frequency changes when the DC blocking is disabled.
Please use SmartRF Studio [5] to calculate correct register setting.
6:4 MOD_FORMAT[2:0] 0 (000) R/W The modulation format of the radio signal
Setting Modulation format
0 (000) 2-FSK
1 (001) GFSK
2 (010) -
3 (011) ASK/OOK
4 (100) 4-FSK
5 (101) -
6 (110) -
7 (111) MSK
MSK is only supported for data rates above 26 kBaud
3 MANCHESTER_EN 0 R/W Enables Manchester encoding/decoding.
0 = Disable
1 = Enable
2:0 SYNC_MODE[2:0] 2 (010) R/W Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables preamble and sync word
transmission in TX and preamble and sync word detection in RX.
The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word
transmission in TX and 16-bits sync word detection in RX. Only 15 of 16 bits
need to match in RX when using setting 1 (001) or 5 (101). The values 3 (011)
and 7 (111) enables repeated sync word transmission in TX and 32-bits sync
word detection in RX (only 30 of 32 bits need to match).
Setting Sync-word qualifier mode
0 (000) No preamble/sync
1 (001) 15/16 sync word bits detected
2 (010) 16/16 sync word bits detected
3 (011) 30/32 sync word bits detected
4 (100) No preamble/sync, carrier-sense
above threshold
5 (101) 15/16 + carrier-sense above threshold
6 (110) 16/16 + carrier-sense above threshold
7 (111) 30/32 + carrier-sense above threshold

SWRS061I Page 77 of 98
 CC1101
0x13: MDMCFG1– Modem Configuration
Bit Field Name Reset R/W Description

7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet
payload
0 = Disable
1 = Enable (Only supported for fixed packet length mode, i.e.
PKTCTRL0.LENGTH_CONFIG=0)
6:4 NUM_PREAMBLE[2:0] 2 (010) R/W Sets the minimum number of preamble bytes to be transmitted
Setting Number of preamble bytes
0 (000) 2
1 (001) 3
2 (010) 4
3 (011) 6
4 (100) 8
5 (101) 12
6 (110) 16
7 (111) 24

3:2 R0 Not used

1:0 CHANSPC_E[1:0] 2 (10) R/W 2 bit exponent of channel spacing

0x14: MDMCFG0– Modem Configuration

Bit Field Name Reset R/W Description

7:0 CHANSPC_M[7:0] 248 (0xF8) R/W 8-bit mantissa of channel spacing. The channel spacing is
multiplied by the channel number CHAN and added to the base
frequency. It is unsigned and has the format:
f XOSC
f CHANNEL   256  CHANSPC _ M   2CHANSPC _ E
218
The default values give 199.951 kHz channel spacing (the closest
setting to 200 kHz), assuming 26.0 MHz crystal frequency.

SWRS061I Page 78 of 98
 CC1101
0x15: DEVIATN – Modem Deviation Setting
Bit Field Name Reset R/W Description

7 R0 Not used.
6:4 DEVIATION_E[2:0] 4 (100) R/W Deviation exponent.
3 R0 Not used.
2:0 DEVIATION_M[2:0] 7 (111) R/W TX
Specifies the nominal frequency deviation from the carrier for a
‘0’ (-DEVIATN) and ‘1’ (+DEVIATN) in a mantissa-exponent
format, interpreted as a 4-bit value with MSB implicit 1. The
2-FSK/ resulting frequency deviation is given by:
GFSK/ f xosc
f dev   (8  DEVIATION _ M )  2 DEVIATION _ E
4-FSK 217
The default values give ±47.607 kHz deviation assuming 26.0
MHz crystal frequency.
MSK Specifies the fraction of symbol period (1/8-8/8) during which a
phase change occurs (‘0’: +90deg, ‘1’:-90deg). Refer to the
SmartRF Studio software [5] for correct DEVIATN setting when
using MSK.
ASK/OOK This setting has no effect.
RX
2-FSK/
Specifies the expected frequency deviation of incoming signal,
GFSK/ must be approximately right for demodulation to be performed
reliably and robustly.
4-FSK
MSK/
This setting has no effect.
ASK/OOK

SWRS061I Page 79 of 98
 CC1101
0x16: MCSM2 – Main Radio Control State Machine Configuration
Bit Field Name Reset R/W Description

7:5 R0 Not used

4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For
ASK/OOK modulation, RX times out if there is no carrier sense in the first 8
symbol periods.
3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires, the chip checks if sync word is found when
RX_TIME_QUAL=0, or either sync word is found or PQI is set when
RX_TIME_QUAL=1.
2:0 RX_TIME[2:0] 7 (111) R/W Timeout for sync word search in RX for both WOR mode and normal RX
operation. The timeout is relative to the programmed EVENT0 timeout.

The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is the
crystal oscillator frequency in MHz:
Setting WOR_RES = 0 WOR_RES = 1 WOR_RES = 2 WOR_RES = 3
0 (000) 3.6058 18.0288 32.4519 46.8750
1 (001) 1.8029 9.0144 16.2260 23.4375
2 (010) 0.9014 4.5072 8.1130 11.7188
3 (011) 0.4507 2.2536 4.0565 5.8594
4 (100) 0.2254 1.1268 2.0282 2.9297
5 (101) 0.1127 0.5634 1.0141 1.4648
6 (110) 0.0563 0.2817 0.5071 0.7324
7 (111) Until end of packet
As an example, EVENT0=34666, WOR_RES=0 and RX_TIME=6 corresponds to 1.96 ms RX timeout, 1 s polling interval and
0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR because using WOR_RES > 1 will give a very low
duty cycle. In applications where WOR is not used all settings of WOR_RES can be used.
The duty cycle using WOR is approximated by:
Setting WOR_RES=0 WOR_RES=1

0 (000) 12.50% 1.95%

1 (001) 6.250% 9765ppm
2 (010) 3.125% 4883ppm
3 (011) 1.563% 2441ppm
4 (100) 0.781% NA
5 (101) 0.391% NA
6 (110) 0.195% NA
7 (111) NA
Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator periods.
WOR mode does not need to be enabled.
The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0,
decreasing to the 7MSBs of EVENT0 with RX_TIME=6.

SWRS061I Page 80 of 98
 CC1101
0x17: MCSM1– Main Radio Control State Machine Configuration
Bit Field Name Reset R/W Description

7:6 R0 Not used

5:4 CCA_MODE[1:0] 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal
Setting Clear channel indication
0 (00) Always
1 (01) If RSSI below threshold
2 (10) Unless currently receiving a packet
3 (11) If RSSI below threshold unless currently
receiving a packet

3:2 RXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been received
Setting Next state after finishing packet reception
0 (00) IDLE
1 (01) FSTXON
2 (10) TX
3 (11) Stay in RX

It is not possible to set RXOFF_MODE to be TX or FSTXON and at the same

time use CCA.
1:0 TXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been sent (TX)
Setting Next state after finishing packet transmission
0 (00) IDLE
1 (01) FSTXON
2 (10) Stay in TX (start sending preamble)
3 (11) RX

SWRS061I Page 81 of 98
 CC1101
0x18: MCSM0– Main Radio Control State Machine Configuration
Bit Field Name Reset R/W Description

7:6 R0 Not used

5:4 FS_AUTOCAL[1:0] 0 (00) R/W Automatically calibrate when going to RX or TX, or back to IDLE
Setting When to perform automatic calibration

0 (00) Never (manually calibrate using SCAL strobe)

1 (01) When going from IDLE to RX or TX (or FSTXON)
When going from RX or TX back to IDLE
2 (10)
automatically
Every 4th time when going from RX or TX to IDLE
3 (11)
automatically
In some automatic wake-on-radio (WOR) applications, using setting 3 (11)
can significantly reduce current consumption.
3:2 PO_TIMEOUT 1 (01) R/W Programs the number of times the six-bit ripple counter must expire after
[1]
XOSC has stabilized before CHP_RDYn goes low .
If XOSC is on (stable) during power-down, PO_TIMEOUT should be set so that
the regulated digital supply voltage has time to stabilize before CHP_RDYn
goes low (PO_TIMEOUT=2 recommended). Typical start-up time for the
voltage regulator is 50 μs.
For robust operation it is recommended to use PO_TIMEOUT = 2 or 3 when
XOSC is off during power-down.
[1]
Note that the XOSC_STABLE signal will be asserted at the same time as
the CHP_RDYn signal; i.e. the PO_TIMEOUT delays both signals and does not
insert a delay between the signals
Setting Expire count Timeout after XOSC start
0 (00) 1 Approx. 2.3 – 2.4 μs
1 (01) 16 Approx. 37 – 39 μs
2 (10) 64 Approx. 149 – 155 μs
3 (11) 256 Approx. 597 – 620 μs
Exact timeout depends on crystal frequency.
1 PIN_CTRL_EN 0 R/W Enables the pin radio control option
0 XOSC_FORCE_ON 0 R/W Force the XOSC to stay on in the SLEEP state.

SWRS061I Page 82 of 98
 CC1101
0x19: FOCCFG – Frequency Offset Compensation Configuration
Bit Field Name Reset R/W Description

7:6 R0 Not used

5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock
recovery feedback loops until the CS signal goes high.
4:3 FOC_PRE_K[1:0] 2 (10) R/W The frequency compensation loop gain to be used before a sync word is
detected.
Setting Freq. compensation loop gain before sync word
0 (00) K
1 (01) 2K
2 (10) 3K
3 (11) 4K

2 FOC_POST_K 1 R/W The frequency compensation loop gain to be used after a sync word is detected.
Setting Freq. compensation loop gain after sync word
0 Same as FOC_PRE_K
1 K/2

1:0 FOC_LIMIT[1:0] 2 (10) R/W The saturation point for the frequency offset compensation algorithm:
Setting Saturation point (max compensated offset)
0 (00) ±0 (no frequency offset compensation)
1 (01) ±BWCHAN/8
2 (10) ±BWCHAN/4
3 (11) ±BWCHAN/2
Frequency offset compensation is not supported for ASK/OOK. Always use
FOC_LIMIT=0 with these modulation formats.

SWRS061I Page 83 of 98
 CC1101
0x1A: BSCFG – Bit Synchronization Configuration
Bit Field Name Reset R/W Description

7:6 BS_PRE_KI[1:0] 1 (01) R/W The clock recovery feedback loop integral gain to be used before a sync word is
detected (used to correct offsets in data rate):
Setting Clock recovery loop integral gain before sync word
0 (00) KI
1 (01) 2KI
2 (10) 3KI
3 (11) 4KI

5:4 BS_PRE_KP[1:0] 2 (10) R/W The clock recovery feedback loop proportional gain to be used before a sync word
is detected.
Setting Clock recovery loop proportional gain before sync word
0 (00) KP
1 (01) 2KP
2 (10) 3KP
3 (11) 4KP

3 BS_POST_KI 1 R/W The clock recovery feedback loop integral gain to be used after a sync word is
detected.
Setting Clock recovery loop integral gain after sync word
0 Same as BS_PRE_KI
1 KI /2

2 BS_POST_KP 1 R/W The clock recovery feedback loop proportional gain to be used after a sync word
is detected.
Setting Clock recovery loop proportional gain after sync word
0 Same as BS_PRE_KP
1 KP

1:0 BS_LIMIT[1:0] 0 (00) R/W The saturation point for the data rate offset compensation algorithm:
Setting Data rate offset saturation (max data rate difference)
0 (00) ±0 (No data rate offset compensation performed)
1 (01) ±3.125 % data rate offset
2 (10) ±6.25 % data rate offset
3 (11) ±12.5 % data rate offset

SWRS061I Page 84 of 98
 CC1101
0x1B: AGCCTRL2 – AGC Control
Bit Field Name Reset R/W Description

7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain.
Setting Allowable DVGA settings
0 (00) All gain settings can be used
1 (01) The highest gain setting can not be used
2 (10) The 2 highest gain settings can not be used
3 (11) The 3 highest gain settings can not be used

5:3 MAX_LNA_GAIN[2:0] 0 (000) R/W Sets the maximum allowable LNA + LNA 2 gain relative to the maximum
possible gain.
Setting Maximum allowable LNA + LNA 2 gain
0 (000) Maximum possible LNA + LNA 2 gain
1 (001) Approx. 2.6 dB below maximum possible gain
2 (010) Approx. 6.1 dB below maximum possible gain
3 (011) Approx. 7.4 dB below maximum possible gain
4 (100) Approx. 9.2 dB below maximum possible gain
5 (101) Approx. 11.5 dB below maximum possible gain
6 (110) Approx. 14.6 dB below maximum possible gain
7 (111) Approx. 17.1 dB below maximum possible gain

2:0 MAGN_TARGET[2:0] 3 (011) R/W These bits set the target value for the averaged amplitude from the
digital channel filter (1 LSB = 0 dB).
Setting Target amplitude from channel filter
0 (000) 24 dB
1 (001) 27 dB
2 (010) 30 dB
3 (011) 33 dB
4 (100) 36 dB
5 (101) 38 dB
6 (110) 40 dB
7 (111) 42 dB

SWRS061I Page 85 of 98
 CC1101
0x1C: AGCCTRL1 – AGC Control
Bit Field Name Reset R/W Description

7 R0 Not used
6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2 gain
adjustment. When 1, the LNA gain is decreased first. When 0, the
LNA 2 gain is decreased to minimum before decreasing LNA gain.
5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00) R/W Sets the relative change threshold for asserting carrier sense
Setting Carrier sense relative threshold
0 (00) Relative carrier sense threshold disabled
1 (01) 6 dB increase in RSSI value
2 (10) 10 dB increase in RSSI value
3 (11) 14 dB increase in RSSI value

3:0 CARRIER_SENSE_ABS_THR[3:0] 0 R/W Sets the absolute RSSI threshold for asserting carrier sense. The
(0000) 2-complement signed threshold is programmed in steps of 1 dB
and is relative to the MAGN_TARGET setting.
Setting Carrier sense absolute threshold
(Equal to channel filter amplitude when AGC
has not decreased gain)
-8 (1000) Absolute carrier sense threshold disabled
-7 (1001) 7 dB below MAGN_TARGET setting
… …
-1 (1111) 1 dB below MAGN_TARGET setting
0 (0000) At MAGN_TARGET setting
1 (0001) 1 dB above MAGN_TARGET setting
… …
7 (0111) 7 dB above MAGN_TARGET setting

SWRS061I Page 86 of 98
 CC1101
0x1D: AGCCTRL0 – AGC Control
Bit Field Name Reset R/W Description

7:6 HYST_LEVEL[1:0] 2 (10) R/W Sets the level of hysteresis on the magnitude deviation (internal AGC
signal that determine gain changes).
Setting Description
0 (00) No hysteresis, small symmetric dead zone, high gain
Low hysteresis, small asymmetric dead zone, medium
1 (01)
gain
Medium hysteresis, medium asymmetric dead zone,
2 (10)
medium gain
Large hysteresis, large asymmetric dead zone, low
3 (11)
gain

5:4 WAIT_TIME[1:0] 1 (01) R/W Sets the number of channel filter samples from a gain adjustment has
been made until the AGC algorithm starts accumulating new samples.
Setting Channel filter samples
0 (00) 8
1 (01) 16
2 (10) 24
3 (11) 32

3:2 AGC_FREEZE[1:0] 0 (00) R/W Control when the AGC gain should be frozen.
Setting Function
0 (00) Normal operation. Always adjust gain when required.
The gain setting is frozen when a sync word has been
1 (01)
found.
Manually freeze the analogue gain setting and
2 (10)
continue to adjust the digital gain.
Manually freezes both the analogue and the digital
3 (11)
gain setting. Used for manually overriding the gain.

1:0 FILTER_LENGTH[1:0] 1 (01) R/W 2-FSK, 4-FSK, MSK: Sets the averaging length for the amplitude from
the channel filter.
ASK, OOK: Sets the OOK/ASK decision boundary for OOK/ASK
reception.
Setting Channel filter OOK/ASK decision boundary
samples
0 (00) 8 4 dB
1 (01) 16 8 dB
2 (10) 32 12 dB
3 (11) 64 16 dB

0x1E: WOREVT1 – High Byte Event0 Timeout

Bit Field Name Reset R/W Description

7:0 EVENT0[15:8] 135 (0x87) R/W High byte of EVENT0 timeout register

750
t Event 0   EVENT 0  2 5WOR _ RES
f XOSC

SWRS061I Page 87 of 98
 CC1101
0x1F: WOREVT0 –Low Byte Event0 Timeout
Bit Field Name Reset R/W Description

7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register.
The default EVENT0 value gives 1.0s timeout, assuming a 26.0 MHz crystal.

0x20: WORCTRL – Wake On Radio Control

Bit Field Name Reset R/W Description

7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic initial
calibration will be performed
6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block. Decoded to Event 1 timeout. RC oscillator
clock frequency equals FXOSC/750, which is 34.7 – 36 kHz, depending on
crystal frequency. The table below lists the number of clock periods after
Event 0 before Event 1 times out.
Setting tEvent1
0 (000) 4 (0.111 – 0.115 ms)
1 (001) 6 (0.167 – 0.173 ms)
2 (010) 8 (0.222 – 0.230 ms)
3 (011) 12 (0.333 – 0.346 ms)
4 (100) 16 (0.444 – 0.462 ms)
5 (101) 24 (0.667 – 0.692 ms)
6 (110) 32 (0.889 – 0.923 ms)
7 (111) 48 (1.333 – 1.385 ms)

3 RC_CAL 1 R/W Enables (1) or disables (0) the RC oscillator calibration.

2 R0 Not used
1:0 WOR_RES 0 (00) R/W Controls the Event 0 resolution as well as maximum timeout of the WOR
module and maximum timeout under normal RX operation:
Setting Resolution (1 LSB) Max timeout
0 (00) 1 period (28 – 29 μs) 1.8 – 1.9 seconds
1 (01) 25 periods (0.89 – 0.92 ms) 58 – 61 seconds
10
2 (10) 2 periods (28 – 30 ms) 31 – 32 minutes
15
3 (11) 2 periods (0.91 – 0.94 s) 16.5 – 17.2 hours
Note that WOR_RES should be 0 or 1 when using WOR because WOR_RES >
1 will give a very low duty cycle.
In normal RX operation all settings of WOR_RES can be used.

SWRS061I Page 88 of 98
 CC1101
0x21: FREND1 – Front End RX Configuration
Bit Field Name Reset R/W Description

7:6 LNA_CURRENT[1:0] 1 (01) R/W Adjusts front-end LNA PTAT current output
5:4 LNA2MIX_CURRENT[1:0] 1 (01) R/W Adjusts front-end PTAT outputs
3:2 LODIV_BUF_CURRENT_RX[1:0] 1 (01) R/W Adjusts current in RX LO buffer (LO input to mixer)
1:0 MIX_CURRENT[1:0] 2 (10) R/W Adjusts current in mixer

0x22: FREND0 – Front End TX Configuration

Bit Field Name Reset R/W Description

7:6 R0 Not used

5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (0x01) R/W Adjusts current TX LO buffer (input to PA). The value to use
in this field is given by the SmartRF Studio software [5].
3 R0 Not used
2:0 PA_POWER[2:0] 0 (0x00) R/W Selects PA power setting. This value is an index to the
PATABLE, which can be programmed with up to 8 different
PA settings. In OOK/ASK mode, this selects the PATABLE
index to use when transmitting a ‘1’. PATABLE index zero is
used in OOK/ASK when transmitting a ‘0’. The PATABLE
settings from index ‘0’ to the PA_POWER value are used for
ASK TX shaping, and for power ramp-up/ramp-down at the
start/end of transmission in all TX modulation formats.

0x23: FSCAL3 – Frequency Synthesizer Calibration

Bit Field Name Reset R/W Description

7:6 FSCAL3[7:6] 2 (0x02) R/W Frequency synthesizer calibration configuration. The value to
write in this field before calibration is given by the SmartRF
Studio software.
5:4 CHP_CURR_CAL_EN[1:0] 2 (0x02) R/W Disable charge pump calibration stage when 0.
3:0 FSCAL3[3:0] 9 (1001) R/W Frequency synthesizer calibration result register. Digital bit
vector defining the charge pump output current, on an
FSCAL3[3:0]/4
exponential scale: I_OUT = I0·2
Fast frequency hopping without calibration for each hop can
be done by calibrating upfront for each frequency and saving
the resulting FSCAL3, FSCAL2 and FSCAL1 register values.
Between each frequency hop, calibration can be replaced by
writing the FSCAL3, FSCAL2 and FSCAL1 register values
corresponding to the next RF frequency.

SWRS061I Page 89 of 98
 CC1101
0x24: FSCAL2 – Frequency Synthesizer Calibration
Bit Field Name Reset R/W Description

7:6 R0 Not used

5 VCO_CORE_H_EN 0 R/W Choose high (1) / low (0) VCO
4:0 FSCAL2[4:0] 10 (0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration
result and override value.
Fast frequency hopping without calibration for each hop can be done by
calibrating upfront for each frequency and saving the resulting FSCAL3,
FSCAL2 and FSCAL1 register values. Between each frequency hop,
calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1
register values corresponding to the next RF frequency.

0x25: FSCAL1 – Frequency Synthesizer Calibration

Bit Field Name Reset R/W Description

7:6 R0 Not used

5:0 FSCAL1[5:0] 32 (0x20) R/W Frequency synthesizer calibration result register. Capacitor array setting for
VCO coarse tuning.
Fast frequency hopping without calibration for each hop can be done by
calibrating upfront for each frequency and saving the resulting FSCAL3,
FSCAL2 and FSCAL1 register values. Between each frequency hop,
calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1
register values corresponding to the next RF frequency.

0x26: FSCAL0 – Frequency Synthesizer Calibration

Bit Field Name Reset R/W Description

7 R0 Not used
6:0 FSCAL0[6:0] 13 (0x0D) R/W Frequency synthesizer calibration control. The value to use in this register is
given by the SmartRF Studio software [5].

0x27: RCCTRL1 – RC Oscillator Configuration

Bit Field Name Reset R/W Description

7 0 R0 Not used
6:0 RCCTRL1[6:0] 65 (0x41) R/W RC oscillator configuration.

0x28: RCCTRL0 – RC Oscillator Configuration

Bit Field Name Reset R/W Description

7 0 R0 Not used
6:0 RCCTRL0[6:0] 0 (0x00) R/W RC oscillator configuration.

SWRS061I Page 90 of 98
 CC1101
29.2 Configuration Register Details – Registers that Loose Programming in SLEEP State

0x29: FSTEST – Frequency Synthesizer Calibration Control

Bit Field Name Reset R/W Description

7:0 FSTEST[7:0] 89 (0x59) R/W For test only. Do not write to this register.

0x2A: PTEST – Production Test

Bit Field Name Reset R/W Description

7:0 PTEST[7:0] 127 (0x7F) R/W Writing 0xBF to this register makes the on-chip temperature sensor
available in the IDLE state. The default 0x7F value should then be written
back before leaving the IDLE state. Other use of this register is for test only.

0x2B: AGCTEST – AGC Test

Bit Field Name Reset R/W Description

7:0 AGCTEST[7:0] 63 (0x3F) R/W For test only. Do not write to this register.

0x2C: TEST2 – Various Test Settings

Bit Field Name Reset R/W Description

7:0 TEST2[7:0] 136 (0x88) R/W The value to use in this register is given by the SmartRF Studio software
[5]. This register will be forced to 0x88 or 0x81 when it wakes up from
SLEEP mode, depending on the configuration of FIFOTHR.
ADC_RETENTION.
Note that the value read from this register when waking up from SLEEP
always is the reset value (0x88) regardless of the ADC_RETENTION
setting. The inverting of some of the bits due to the ADC_RETENTION
setting is only seen INTERNALLY in the analog part.

0x2D: TEST1 – Various Test Settings

Bit Field Name Reset R/W Description

7:0 TEST1[7:0] 49 (0x31) R/W The value to use in this register is given by the SmartRF Studio software
[5]. This register will be forced to 0x31 or 0x35 when it wakes up from
SLEEP mode, depending on the configuration of FIFOTHR.
ADC_RETENTION.
Note that the value read from this register when waking up from SLEEP
always is the reset value (0x31) regardless of the ADC_RETENTION
setting. The inverting of some of the bits due to the ADC_RETENTION
setting is only seen INTERNALLY in the analog part.

SWRS061I Page 91 of 98
 CC1101
0x2E: TEST0 – Various Test Settings
Bit Field Name Reset R/W Description

7:2 TEST0[7:2] 2 (0x02) R/W The value to use in this register is given by the SmartRF Studio software
[5].
1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1
0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF Studio software
[5].

29.3 Status Register Details

0x30 (0xF0): PARTNUM – Chip ID

Bit Field Name Reset R/W Description

7:0 PARTNUM[7:0] 0 (0x00) R Chip part number

0x31 (0xF1): VERSION – Chip ID

Bit Field Name Reset R/W Description

7:0 VERSION[7:0] 20 R Chip version number. Subject to change without notice.

(0x14)

0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator

Bit Field Name Reset R/W Description

7:0 FREQOFF_EST R The estimated frequency offset (2’s complement) of the carrier. Resolution is
FXTAL/214 (1.59 - 1.65 kHz); range is ±202 kHz to ±210 kHz, depending on XTAL
frequency.
Frequency offset compensation is only supported for 2-FSK, GFSK, 4-FSK, and
MSK modulation. This register will read 0 when using ASK or OOK modulation.

0x33 (0xF3): LQI – Demodulator Estimate for Link Quality

Bit Field Name Reset R/W Description

7 CRC OK R The last CRC comparison matched. Cleared when entering/restarting RX mode.
6:0 LQI_EST[6:0] R The Link Quality Indicator estimates how easily a received signal can be
demodulated. Calculated over the 64 symbols following the sync word

0x34 (0xF4): RSSI – Received Signal Strength Indication

Bit Field Name Reset R/W Description

7:0 RSSI R Received signal strength indicator

SWRS061I Page 92 of 98
 CC1101
0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State
Bit Field Name Reset R/W Description

7:5 R0 Not used

4:0 MARC_STATE[4:0] R Main Radio Control FSM State
Value State name State (Figure 25, page 50)
0 (0x00) SLEEP SLEEP
1 (0x01) IDLE IDLE
2 (0x02) XOFF XOFF
3 (0x03) VCOON_MC MANCAL
4 (0x04) REGON_MC MANCAL
5 (0x05) MANCAL MANCAL
6 (0x06) VCOON FS_WAKEUP
7 (0x07) REGON FS_WAKEUP
8 (0x08) STARTCAL CALIBRATE
9 (0x09) BWBOOST SETTLING
10 (0x0A) FS_LOCK SETTLING
11 (0x0B) IFADCON SETTLING
12 (0x0C) ENDCAL CALIBRATE
13 (0x0D) RX RX
14 (0x0E) RX_END RX
15 (0x0F) RX_RST RX
16 (0x10) TXRX_SWITCH TXRX_SETTLING
17 (0x11) RXFIFO_OVERFLOW RXFIFO_OVERFLOW
18 (0x12) FSTXON FSTXON
19 (0x13) TX TX
20 (0x14) TX_END TX
21 (0x15) RXTX_SWITCH RXTX_SETTLING
22 (0x16) TXFIFO_UNDERFLOW TXFIFO_UNDERFLOW
Note: it is not possible to read back the SLEEP or XOFF state numbers
because setting CSn low will make the chip enter the IDLE mode from the
SLEEP or XOFF states.

0x36 (0xF6): WORTIME1 – High Byte of WOR Time

Bit Field Name Reset R/W Description

7:0 TIME[15:8] R High byte of timer value in WOR module

0x37 (0xF7): WORTIME0 – Low Byte of WOR Time

Bit Field Name Reset R/W Description

7:0 TIME[7:0] R Low byte of timer value in WOR module

SWRS061I Page 93 of 98
 CC1101
0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status
Bit Field Name Reset R/W Description

7 CRC_OK R The last CRC comparison matched. Cleared when entering/restarting RX

mode.
6 CS R Carrier sense. Cleared when entering IDLE mode.
5 PQT_REACHED R Preamble Quality reached. If leaving RX state when this bit is set it will
remain asserted until the chip re-enters RX state (MARCSTATE=0x0D). The
bit will also be cleared if PQI goes below the programmed PQT value.
4 CCA R Channel is clear
3 SFD R Start of Frame Delimiter. In RX, this bit is asserted when sync word has
been received and de-asserted at the end of the packet. It will also de-
assert when a packet is discarded due to address or maximum length
filtering or the radio enters RXFIFO_OVERFLOW state. In TX this bit will
always read as 0.
2 GDO2 R Current GDO2 value. Note: the reading gives the non-inverted value
irrespective of what IOCFG2.GDO2_INV is programmed to.
It is not recommended to check for PLL lock by reading PKTSTATUS[2]
with GDO2_CFG=0x0A.

1 R0 Not used
0 GDO0 R Current GDO0 value. Note: the reading gives the non-inverted value
irrespective of what IOCFG0.GDO0_INV is programmed to.
It is not recommended to check for PLL lock by reading PKTSTATUS[0]
with GDO0_CFG=0x0A.

0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module

Bit Field Name Reset R/W Description

7:0 VCO_VC_DAC[7:0] R Status register for test only.

0x3A (0xFA): TXBYTES – Underflow and Number of Bytes

Bit Field Name Reset R/W Description

7 TXFIFO_UNDERFLOW R
6:0 NUM_TXBYTES R Number of bytes in TX FIFO

0x3B (0xFB): RXBYTES – Overflow and Number of Bytes

Bit Field Name Reset R/W Description

7 RXFIFO_OVERFLOW R
6:0 NUM_RXBYTES R Number of bytes in RX FIFO

0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result

Bit Field Name Reset R/W Description

7 R0 Not used
6:0 RCCTRL1_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine.
For usage description refer to Application Note AN047 [4]

SWRS061I Page 94 of 98
 CC1101
0x3D (0xFD): RCCTRL0_STATUS – Last RC Oscillator Calibration Result
Bit Field Name Reset R/W Description

7 R0 Not used
6:0 RCCTRL0_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine.
For usage description refer to Application Note AN047 [4].

30 Soldering Information
The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed.

31 Development Kit Ordering Information

Orderable Evaluation Module Description Minimum Order Quantity

CC1101DK433 CC1101 Development Kit, 433 MHz 1
CC1101DK868-915 CC1101 Development Kit, 868/915 MHz 1
CC1101EMK433 CC1101 Evaluation Module Kit, 433 MHz 1
CC1101EMK868-915 CC1101 Evaluation Module Kit, 868/915 MHz 1

Figure 34: Development Kit Ordering Information

SWRS061I Page 95 of 98
 CC1101

32 References
[1] CC1101EM 315 - 433 MHz Reference Design (swrr046.zip)

[2] CC1101EM 868 – 915 MHz Reference Design (swrr045.zip)

[3] CC1101 Errata Notes (swrz020.pdf)

[4] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf)

TM
[5] SmartRF Studio (swrc046.zip)

[6] CC1100 CC2500 Examples Libraries (swrc021.zip)

[7] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User

Manual (swru109.pdf)

[8] DN010 Close-in Reception with CC1101 (swra147.pdf)

[9] DN017 CC11xx 868/915 MHz RF Matching (swra168.pdf)

[10] DN015 Permanent Frequency Offset Compensation (swra159.pdf)

[11] DN006 CC11xx Settings for FCC 15.247 Solutions (swra123.pdf)

[12] DN505 RSSI Interpretation and Timing (swra114.pdf)

[13] AN058 Antenna Selection Guide (swra161.pdf)

[14] AN067 Wireless MBUS Implementation with CC1101 and MSP430 (swra234.pdf)

[15] DN013 Programming Output Power on CC1101 (swra168.pdf)

[16] DN022 CC11xx OOK/ASK register settings (swra215.pdf)

[17] DN005 CC11xx Sensitivity versus Frequency Offset and Crystal Accuracy (swra122.pdf)

[18] DN501 PATABLE Access (swra110.pdf)

[19] DN504 FEC Implementation (swra113.pdf)

[20] DN507 FEC Decoding (swra313.pdf)

[21] CC1190 Data Sheet (swrs089.pdf)

[22] AN094 Using the CC1190 Front End with CC1101 under EN 300 220 (swra356.pdf)

[23] AN096 Using the CC1190 Front End with CC1101 under FCC 15.247 (swra361.pdf)

[24] DN032 Options for Cost Optimized CC11xx Matching (swra346.pdf)

[25] DN036 CC1101+CC1190 600 kbps Data Rate, +19 dBm transmit power without FHSS in
902-928 MHz frequency Band (swrr078.pdf)

[26] TPS62730 Data Sheet (slvsac3.pdf)

SWRS061I Page 96 of 98
 CC1101

33 General Information

33.1 Document History

Revision Date Description/Changes
SWRS061I 2013.11.05 Updated the package designator from RTK to RGP
Changed description of VERSION. Reset value changed from 0x04 to 0x14
SWRS061H 2012.10.09 Added 256 Hz clock to Table 41: GDOx Signal Selection
SWRS061G 2011.07.26 Crystal NX3225GA added to application circuit BOM
Added reference to CC1190 range extender
Added reference to AN094 and AN096
Corrected settling times and PLL turn-on/hop time in Table 15
Added reference to design notes DN032 and DN036
Removed references to AN001 and AN050
Changed description of MCSM0.PO_TIMEOUT
Removed link to DN009
Added more detailed information about how to check for PLL lock in Section 22.1
SWRS061F 2010.01.10 Changed from multi-layer to wire-wound inductors in Table 38.
Included PA_PD and LNA_PD GDO signals Table 41 as they were erroneously
removed in SWRS061E.
Updated WOR current consumption figures in Table 4.
The Gaussian filter BT is changed from 1.0 to 0.5.
Changed minimum data rate to 0.6 kBaud.
Updated Table 25 with 0.6 kBaud data rate.
Added information that digital signals with sharp edges should not be routed close to
XOSC_Q1 PCB track.
Added information about 1/XOSC glitch in received data output when using
asynchronous serial mode
Added information that a 27 MHz crystal is recommended for systems targeting
compliance with modulation bandwidth requirements in the 869 to 870 MHz frequency
range under EN 300 220.
Updated overall state transition times in Table 34 and added table with frequency
synthesizer calibration times (Table 35).
Added -116 dBm 1% PER at 0.6 kBaud, 434 MHz
Included information about 4-FSK modulation
Added sensitivity figures for 4-FSK
Added link to DN507
Updated PKTSTATUS.SFD. In TX this bit reads as 0.
Updated PKTSTATUS.PQT_REACHED.
Removed chapter on Packet Description
Changed chapter on Ordering Information since this was duplicate information.
SWRS061E 2009.04.21 Maximum output power increased to +12/+11 dBm at 868/915MHz with the use of
wire-wound inductors (Murata LQW15xx series).
Changes to optimum PATABLE settings.
Added typical output power over temperature and supply voltage.
Changes to current consumption in TX mode.
Added typical TX current consumption over temperature and supply voltage.
Improved sensitivity figures at 868/915 MHz.
Added typical sensitivity figures over temperature and supply voltage.
Added typical RX current consumption over temperature and input power level.
Changes to adjacent channel rejection at 38.4 kBaud.
Changes to image rejection at 250 kBaud.
Updates to selectivity/blocking plots.
Changed bill of materials for 868/915 MHz application circuits to Murata LQW15xx
series inductors.
Changed analog temperature sensor temperature coefficient.
Added links to DN501 and DN504
Changes to section 17.6. A low LQI value indicates a good link
Changes to Package Description section
Changes to Ordering Information section

SWRS061I Page 97 of 98
 CC1101

Revision Date Description/Changes

SWRS061D 2008.05.22 Edited title and removed CC logo.
Formatted and edited text. Put important notes in boxes.
Corrected the 250 kBaud settings information from MSK to GFSK.
Added plot over RX current variation versus input power level and temperature.
Added tables for sensitivity, output power and TX current consumption variation
versus temperature and supply voltage.
Moved the selectivity plots to the electrical specification section and updated the 1.2
kBaud setting plot.
Added load capacitance spec for the crystal oscillator.
Updated links from AN039 to AN050.
Updated information regarding optional filtering of 699 MHz emission, updated the
868/915 MHz application figure and bills of material, and added link to DN017.
Updated and moved information regarding the crystal, a reference signal, the balun,
and PCB layout recommendations to the section regarding the application circuit.
Added information regarding antennas and link to the antenna selection guide AN058.
Added link to DN005.
Restructured Section 14.1 and added link to DN015.
Moved improved spectrum information (GFSK info) to Section 16.1.
Added information regarding the DEVIATN register in Chapter 16 and in the register
description.
Added information on ASK/OOK settings and added a link to DN022.
Updated RSSI information and added link to DN505.
Updated Section 18.2 information.
Clarified the text describing Figure 27.
Added link to DN013.
Updated Figure 33.
Updated Section 28.2.
Updated information regarding serial synchronous mode.
Added information regarding Wireless MBUS and added link to AN067.
Updated info regarding the FIFOTHR register and TEST1 and TEST2.
Updated info regarding the PKTSTAUS.SFD bit.
Updated address for reading content from 0x3D.
Updated registers information on bits that are not used.
Updated Command Strobes section.
Added link to DN009.
Updated links in the reference chapter.
Added link to the Community.
SWRS061C 2008.05.22 Added product information on the front page
SWRS061B 2007.06.05 Changed name on DN009 Close-in Reception with CC1101 to DN010 Close-in
Reception with CC1101.
Added info regarding how to reduce spurious emission at 699 MHz. Changes
regarding this was done the following places: Table: RF Transmit Section,
Figure 11: Typical Application and Evaluation Circuit 868/915 MHz, Table 20:
Overview of External Components, and Table 21: Bill Of Materials for the Application
Circuit.
Changes made to Figure 27: Power-On Reset with SRES
SWRS061A 2007.06.30 Initial release.
SWRS061 2007.04.16 First preliminary data sheet release

Table 46: Document History

SWRS061I Page 98 of 98
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Mar-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CC1101RGP ACTIVE QFN RGP 20 92 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC1101
& no Sb/Br) CU NIPDAUAG
CC1101RGPR ACTIVE QFN RGP 20 3000 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC1101
& no Sb/Br) CU NIPDAUAG
CC1101RGPT ACTIVE QFN RGP 20 250 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC1101
& no Sb/Br) CU NIPDAUAG

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Mar-2018

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CC1101 :

• Automotive: CC1101-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated