ADSD Question Bank Final
ADSD Question Bank Final
ADSD Question Bank Final
UNIT – 1
UNIT - 2
11. Explain different data objects in VHDL with suitable examples (7)
12. Create a physical data type, Capacitance ranging from µF (Microfarad) to MF (Megafarad) (7)
13. Write short notes on: (i) Entity (ii) Architecture (iii) Package (iv) Configuration (12)
14. Explain various data types in VHDL. / How are scalar data types classified? Explain real and integer data
type in brief (8)
15. Differentiate between conditional and selected signal assignment statements / Explain the
difference between selected signal assignment and conditional signal assignment statement with
example of 4 to 1 MUX (7)
16. All codes pertaining to simple, conditional (when-else) and selected (with-select) signal assignment
statement (Dataflow), case statement, if-then-else statement (Behavioral) from ADSD CODE BANK
UNIT - 3
17. What is subprogram? Explain 'Function' and 'Procedure' with their syntax. (7)
18. What do you mean by Port mapping? What are the types? Explain each with syntax (6)
19. Explain Predefined Attributes with examples (7)
20. All the codes pertaining to Test-Bench from ADSD CODE BANK (8)
21. All the codes pertaining to Generate statement from ADSD CODE BANK (8)
22. All the codes pertaining to Component Declaration & Component Instantiation (Structural) from
ADSD CODE BANK (8)
UNIT – 5
32. Define synthesis in VHDL? What are the steps of synthesis / What is Synthesis in VHDL? Explain synthesis
design flow in VHDL (7)
33. Write short note on pipelining in VHDL (7)
34. Write a short note on "Partitioning for synthesis" (6)
35. Explain power analysis of FPGA based system (8)
36. Explain efficient coding style used for HDL synthesis (6)
37. Write short note on Optimizing Arithmetic Expression (7)
38. Explain timing analysis of logic circuits (4)
39. Explain the term Resource Sharing (5)
UNIT – 6
40. A combinational circuit is defined by the function.
F1 (A, B, C) = (3, 5, 6, 7)
F2 (A, B, C) = (0, 2, 4, 7)
Implement the circuit with a PLA having three inputs, four product terms and two outputs (8)
41. Implement the following function using PLA :
F1 (A, B, C, D) = ∑m (0, 1, 4, 5, 9, 10, 11)
F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 5, 8, 9, 10, 11)
F3 (A, B, C, D) = ∑m (4, 5, 6, 7, 8, 9) (8)
42. Design and Write VHDL code for 4-bit Barrel shifter (7)
43. Write a short note on XC4000 series FPGA / Explain with suitable block diagram Xilinx 4000 series FPGA
(7)
44. Explain place, map and route process in FPGA based system (6)
45. Write a VHDL code for 3x3 binary multiplier using structural style (7)
46. Write a VHDL code for 4-bit ALU (7)
47. Explain the architecture of FPGA with neat diagram (6)
48. Design a 4 x 4 Keyboard Scanner and write a VHDL code for the same (7)
NOTE: All Codes given in ADSD CODE BANK must be thoroughly practiced.