Computer Architecture LAB 2

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Computer Architecture LAB 2

Name: Abdul Hayee Atta Roll No.8015 7th – Semester Bsc(Hons) Computer Science

Experiment 1: To study the basics of data hazards and Forwarding.


1. DATA Hazard
1.1 Example 1
1. Run MIPS 5 Stage Integer Pipeline and load program Lab2 Example 1.
2. NITIALIZE registers and write the values of register used in the program before
execution.

R1:100, R2:220, R3:300, R4:444, R5:500, R6:668, R7:700.

3. Now execute this program and write the values again circling those which you think
are wrong due to data hazard in pipelining.

R1:520, R2:220, R3:300, R4:334, R5, 344, R6:668, R7:1188.

Note: Wrong values in above blanks are in bold.

4. Now press RESET to reset the processor. Go to options menu and select Stall Detection. This will
bring the stall detection hardware in circuit. How many clock cycle it takes to run this program 12 (before
the last non-NOP instruction leaves the WB stage)?
5. Does this program run properly? Yes . Complete the following pipeline diagram by simulation.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12

ADD R1, R2, R3 IF ID EX ME WB

ADDI R4,R1,234 IF ID ID ID EX ME WB

SUB R5,R4,R1 IF IF IF ID ID ID EX ME WB

ADD R7,R1,R6 IF IF IF ID EX ME EX

6. Reset the processor again. Go to options menu and Turn OFF Stall Detection and select Forwarding
option to bring Forwarding circuit in action. Complete the following table again.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12

ADD R1, R2, R3 IF ID EX ME WB

ADDI R4,R1,234 IF ID EX ME WB

SUB R5,R4,R1 IF ID EX ME WB

ADD R7,R1,R6 IF ID EX ME WB

7. Does this program run properly? Yes. How many clock cycle it takes before the last non-NOP
instruction leaves the WB stage 8.
8. How many times data was forwarded during this program 2?
9. Number instruction 1 onwards and you can list forwarding instances (circle A or B)
i. Between instruction no.1 and 2, on (A / B) input of ALU, Cause Register R1, Data520
ii. Between instruction no.1 and 3, on (A / B) input of ALU, Cause Register R1, Data520
iii. Between instruction no._____ and _____, on (A / B) input of ALU, Cause Register ____, Data______
iv. Between instruction no._____ and _____, on (A / B) input of ALU, Cause Register ____, Data______
Also sown these forwardings in the above table by arrows.

Note: A/B shown in bold in Q. No. 9

1.2 Difference kind of forwarding.


1. Exit the simulator and run again, this time load Example 2 Lab2. INITIALIZE registers.
2. Before running this program, find the Effective Address from where data is loaded 444 and where it is
stored 1100. Now make sure Forwarding Circuit is OFF and run this program. When asked for initial value
for LW instruction, type 102030.
3. Does this program run properly? If not what went wrong? You can use Memory menu to answer this
question. No, we loaded 102030 from (444) and when stored it at (1100) we got 220 instead of 102030
4. Now RESET the processor and rerun this program with Forwarding option enabled. Does this
program run properly (again use memory menu option and again give same value for initial memory data)?
Yes, this time the value loaded from (444) and stored at (1100) is same according to our requirement i.e.
102030.

1.2 LOAD USE DELAYS.


Now let us see another special kind of data hazard, very problematic in all processors.
1. Exit simulator, restart and load Example 3 Lab2. Is there a data hazard? Yes, What cause register R2.
2. INITIALIZE registers and no need to simulate without forwarding this time! Switch ON the forwarding
circuit and run this program again. Again enter 6000 as initial value for the memory location. Does this
program run properly? No How would you say what is forwarded 220 , instead of what?6000
3. RESET the processor again and make both Stall Detection and Forwarding options enabled. Run this
program again. In what stage the second instruction was STALLed EXE? How is this different from step 4
in example 1. It is different from step 4 in example 1 in a way that we are facing a LUD instead of any
other king of STALL which could be removed in an easier way, whereas in case of LUD we have to face at
least a single STALL even if the forwarding is on. You can fill the following pipeline diagram.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12

LW R2, 100(R1) IF ID EX ME WB

ADD R1,R2,R4 IF ID EX EX ME WB

Bonus question: Suggest any solution of LUD from top of your head We may change the order of
instructions in case we have such situation in which we can do that in order to avoid the stall.

EXPERIMENT 2: BRANCH HAZARDS

2.1 EXAMPLE 1. Implementation and Study of branches and pipeline hazards.


1. Restart simulator and load Example 4 Lab2.
2. Initialize registers and make Forwarding and Stall Detection Enabled.
3. As you can see this program initializes two registers to two values 5 and 6. In the third instruction,
program branches to some other area of the program using instruction Branch if Not Equal (in this case it
is not as 5 <> 6). What is the address of target instruction. Show this without simulation: 2020. Now run
this program when BNEQ is EXE stage, notice that the top ALU has calculated some target address. Is it
same as you have just mentioned? Yes
4. Advance to next clock, and click on the red-colored AND gate and read bottom info bar. Notice there is
a multiplexer in the IF stage, what is its select input?1. What output is being selected? 2020.
5. Now let us come to the branch penalty. Branches have three basic operations,
i. Instruction is decoded and it found to be a branch instruction. (ID)
ii. Target address is calculated (TA)
ii. Branch Condition is Evaluated (BC)
TA and BC are evaluated in same clock cycle and program branches in the MEM stage. Notice what
happens to instruction in the pipelines when branch is TAKEN (means branch condition is TRUE).
RESET the program again and fill the following table. The instructions in the pipeline should not continue
so they are converted to NOPs and pipeline is FLUSHed. The instruction from TARGET address enters
the pipeline. How many instructions are FLUSHED 3. WHY? Because they were the instructions which
have been fetched and were at different stages but as soon as the branch instruction got executed they
became useless because branch was taken and now the instruction at target address should be fetched,
therefore these 3 instructions are simply flushed.

Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13

ADDI R3,R0,5 IF ID EX ME WB

ADDI R4,R0,6 IF ID EX ME

BNEQ R3,R4,2 IF ID EX ME WB

OR R2,R2,R2 IF ID FL

NOR R3,R3,R0 IF FL

AND R4,R2,R3 FL IF ID EX ME WB

ADD R4,R4,R4 IF ID EX ME WB

ADDI R4,R4,-1 IF ID EX ME WB

2.2: EXAMPLE 2. Quit and restart the simulator. Initialize the registers and set stall detection and forwarding
options. Load Example 5 LAB 2. Write the equivalent C code of the given program.

NOTE: Sorry! but there is some error in this file.

How many times the loop runs? ____________ What is the final value of all the registers. _______________

How many total USEFUL instructions are executed in the program that you have loaded.________________
To see that fill the pipeline diagram on the next page by simulating.

How many clock cycles it takes to execute this program ______________________. Count until first NOP is
in the WB stage and last useful instruction has left WB stage.

What is the CPI of this program? _____________________________

Bonus Question: How can we reduce branch penalty and decrease the CPI (do not ask)?

_________________________________________________________________________________
_______
3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Instr
No.

IF =F, ID = D, EXE = X, MEM = M, WB = W, Flushed = Fl

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