Computer Architecture LAB 2
Computer Architecture LAB 2
Computer Architecture LAB 2
Name: Abdul Hayee Atta Roll No.8015 7th – Semester Bsc(Hons) Computer Science
3. Now execute this program and write the values again circling those which you think
are wrong due to data hazard in pipelining.
4. Now press RESET to reset the processor. Go to options menu and select Stall Detection. This will
bring the stall detection hardware in circuit. How many clock cycle it takes to run this program 12 (before
the last non-NOP instruction leaves the WB stage)?
5. Does this program run properly? Yes . Complete the following pipeline diagram by simulation.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12
ADDI R4,R1,234 IF ID ID ID EX ME WB
SUB R5,R4,R1 IF IF IF ID ID ID EX ME WB
ADD R7,R1,R6 IF IF IF ID EX ME EX
6. Reset the processor again. Go to options menu and Turn OFF Stall Detection and select Forwarding
option to bring Forwarding circuit in action. Complete the following table again.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12
ADDI R4,R1,234 IF ID EX ME WB
SUB R5,R4,R1 IF ID EX ME WB
ADD R7,R1,R6 IF ID EX ME WB
7. Does this program run properly? Yes. How many clock cycle it takes before the last non-NOP
instruction leaves the WB stage 8.
8. How many times data was forwarded during this program 2?
9. Number instruction 1 onwards and you can list forwarding instances (circle A or B)
i. Between instruction no.1 and 2, on (A / B) input of ALU, Cause Register R1, Data520
ii. Between instruction no.1 and 3, on (A / B) input of ALU, Cause Register R1, Data520
iii. Between instruction no._____ and _____, on (A / B) input of ALU, Cause Register ____, Data______
iv. Between instruction no._____ and _____, on (A / B) input of ALU, Cause Register ____, Data______
Also sown these forwardings in the above table by arrows.
LW R2, 100(R1) IF ID EX ME WB
ADD R1,R2,R4 IF ID EX EX ME WB
Bonus question: Suggest any solution of LUD from top of your head We may change the order of
instructions in case we have such situation in which we can do that in order to avoid the stall.
Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13
ADDI R3,R0,5 IF ID EX ME WB
ADDI R4,R0,6 IF ID EX ME
BNEQ R3,R4,2 IF ID EX ME WB
OR R2,R2,R2 IF ID FL
NOR R3,R3,R0 IF FL
AND R4,R2,R3 FL IF ID EX ME WB
ADD R4,R4,R4 IF ID EX ME WB
ADDI R4,R4,-1 IF ID EX ME WB
2.2: EXAMPLE 2. Quit and restart the simulator. Initialize the registers and set stall detection and forwarding
options. Load Example 5 LAB 2. Write the equivalent C code of the given program.
How many times the loop runs? ____________ What is the final value of all the registers. _______________
How many total USEFUL instructions are executed in the program that you have loaded.________________
To see that fill the pipeline diagram on the next page by simulating.
How many clock cycles it takes to execute this program ______________________. Count until first NOP is
in the WB stage and last useful instruction has left WB stage.
Bonus Question: How can we reduce branch penalty and decrease the CPI (do not ask)?
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3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Instr
No.