Introduction to the software

development for nanosatellite

microcontrollers

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 Main problems

• What tasks has our computer to execute?

• What kind of processor is the most
suitable for us?
• Do we need operating system?
• What language shall we use for
programming?

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ARM ARCHITECTURES

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NXP CPUs for laboratories

• LPC2148 ARM7TDMI
• LPC2388
• LPC1768 CORTEX-M3

• LPC1114 CORTEX-M0

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 LPC2142/44/46/48 Block Diagram 64-pin LQFP

RST
Vdd
TRST

Vss
16-32KB 64-512 KB

TMS

TDO
TCK

X1
X2
TDI
SRAM FLASH
System Clock PLL1 System
Test/Debug ETM
PLL2 Functions
USB Clock
SRAM Memory
ARM 7TDMI-S BrownOutDetect
Controller Accelerator VIC PowerOnReset
Local Bus AMBA AHB Bus

D+
AHB to 8 KB SRAM USB 2.0 Full D-
32 kHz shared w/ DMA
Real Time Watchdog VPB Speed Device Up_LED OR
(LPC2148 only) Connect
Vbat
Clock Timer Bridge w/ DMA Vbus

VLSI Peripheral Bus (VPB)

I2C 0/1 SPI Port SSP Port UART0/1 ADC 0/1 DAC Fast I/O Timer0/1 PWM

PWM1 - 6
Tx/RX 0,1

CAP x 8

MAT x 8
6+8 pins

1-10-bit
pins (6)
Modem

46 max
GPIO
SDA

SSEL

SSEL
SCK

MOSI

MOSI
SCL

MISO

MISO
SCK

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6
7
ARM7TDMI CORE

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9
ARM/Thumb interaction

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 ARM7TDMI Processor Modes
ARM has seven operating modes
– User unprivileged mode under which most applications run
– FIQ entered, when a high priority (fast) interrupt is raised
– IRQ general purpose interrupt handling
– Supervisor protected mode for the operating system
entered on reset or software interrupt
instruction
– System privileged mode using the same registers as user
mode
– Abort used to handle memory access violations
– Undefined used to handle undefined instructions

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 Exception Vectors
• Vector Table
.
.
.
0x1C FIQ
0x18 IRQ
Valid user program key:
0x14 (Reserved) Must contain a value that
Data Abort ensures that the checksum of
0x10
all vectors is zero
0x0C Prefetch Abort
0x08 Software Interrupt
0x04 Undefined Instruction
0x00 Reset

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CORTEX MCU Modes

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CORTEX Operation modes

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15
User and System

r0 Register Banking
r1
r2
r3
r4
Banked registers
r5
r6 FIQ IRQ Supervisor Abort Undefined
r7
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12 r12_fiq
r13 (SP) r13_fiq (SP) r13_irq (SP) r13_svc (SP) r13_abt (SP) r13_und (SP)
r14 (LR) r14_fiq (LR) r14_irq (LR) r14_svc (LR) r14_abt (LR) r14_und (LR)
r15 (PC)

CPSR
SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und

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17
Load-And-Store Architecture

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19
 ARM7TDMI Memory Map
4.0 GB
AHB Peripherals 0xFFFF FFFF
3.75 GB 0xF000 0000
VPB Peripherals 0xEFFF FFFF
3.5 GB 0xE000 0000

3.0 GB Reserved for External Memory

0xC000 0000

2.0 GB 0x8000 0000

Boot Block (re-mapped from On-Chip Flash)
0x7FFF E000

Reserved for On-Chip Memory

16 / 32 / 64 KB On-Chip Static RAM 0x4000 nnnn*

1.0 GB 0x4000 0000
0x3FFF FFFF

Reserved for On-Chip Memory

128 ... 512 KB On-Chip Non-Volatile Memory 0x000m FFF**

0.0 GB 0x0000 0000

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21
Memory Accelerator Module
Address Bus

ARM7

Bus Interface
Core
Flash Memory Flash Memory
Bank 1 Bank 2

128 bit 128 bit

Prefetch Buffer 1 Prefetch Buffer 2

Local Bus
Branch Trail Buffer 1 Branch Trail Buffer 2

128 bit (2x) 128 bit (2x)

Data Buffer
Selection

Data Bus (32 / 16 bit)

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 Phase Locked Loop (LPC21xx/22xx)

156 to 320 MHz 10 to 60 MHz

Fosc * 2 * M * P Fosc * M

FOSC
XTAL1 FCCO
Current cclk
Phase
Oscillator Controlled ÷P
Detector
Oscillator
XTAL2 Divider
Value Default: 4
10 to 25 MHz
VPB pclk
1 to 30 MHz ÷M Divider
without PLL ÷ 1/2/4
Multiplier Value

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Handling of the exceptions

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 Exception / Interrupt Handling
• Entering an exception the ARM core
– saves the address of the next instruction in the appropriate LR
PC + 4 or PC + 8
r15 (PC) r14_<mode> (LR)

– copies the CPSR into the appropriate SPSR

CPSR SPSR_<mode>

– sets appropriate CPSR bits

• interrupt disable bits 8 7 6 5 4 0

CPSR: mode
• mode field bits I F T

• if running in Thumb mode, enter ARM mode* Control bits

– forces PC to fetch next instruction from relevant exception vector

*: all exceptions are handled in ARM mode!

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 Leaving Exception
• To leave an exception, the exception handler must
– copy SPSR back into CPSR
SPSR_<mode> CPSR

(automatically restoring also I, F and T)

8 7 6 5 4 0

CPSR: I F T mode

Control bits

– move contents of current LR minus offset* to PC

PC - offset
r14_<mode> (LR) r15 (PC)

*: varies according to type of exception: 2, 4 or 8

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 Multiple Exceptions
• Exception priorities
– When multiple exceptions arise at the same time, a fixed priority
system determines the order in which they are handled

1. Reset highest priority

2. Data Abort (data memory access cannot be completed)
3. FIQ
4. IRQ
5. Prefetch Abort (instruction memory access cannot be
completed)
6. Undefined Instruction
7. SWI - Software Interrupt (to enter supervisor mode) lowest priority

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 Vectored Interrupt Controller

FIQStatus
Interrupt Source FIQ
FIQ
IntEnableClear
RawInterrupt

32
IntEnable

High Priority
OR VectorCntl
SoftIntClear

En Channel VICVectorAddr 0
SoftInt

IRQStatus 5 0:4
IRQ

...
16 Prioritized
32

IntSelect En Channel VICVectorAddr 15

5 0:4
VICDefVectAddr

Low Priority

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CORTEX’s NVIC

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30
Peripherals

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 Pin Connect Block
• Many on-chip functions can use I/O pins
• Number of I/O-pins is limited

 I/Os can be configured to adapt various functions

• Pin function selection is done by Pin Connect Block
PINSEL0/1/2
GPIO
UART
PIN
Timer/Counter
reserved

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 General Purpose I/O
Register
IOxPIN The current state of the port pins is read from this register

IOxSET Writing "1" sets pins high, writing "0" has no effect

IOxCLR Writing "1" sets pins low and clears corresponding bits in IOSET

IOxDIR Port pin direction: 0 = INPUT 1 = OUTPUT

PINSEL Selects function of pins (Pin Connect Block)

8/27/2018

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TIMERS

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 PWM
InitPWM ():
PWMMR0 = 0x000FFFFF;→PWMMR0 = 0x00000FFF;.

A and B values should be

reduced to make a ‘soft’
light.

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 Real Time Clock
• Full Clock/Calendar function with alarms
– Generates its own 32.768 kHz reference clock from any crystal
frequency
– Counts seconds, minutes, hours, day of month, month, year, day of
week and day of year
– Can generate an interrupt or set an alarm flag for any combination
of the counters

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 Real Time Clock
PCLK

Clock Divider
(prescaler)
Time Alarm
Comparators
Counters Registers
Clock

The Counter Interrupt Generator

Increment can
cause an
interrupt

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 Watchdog Timer
Watchdog Timer
WDFEED Constant

PCLK /4 32-bit Down Counter

UNDERFLOW
Current Timer Count
(WDTC)

WDMOD Register WDEN WDTOF WDINT WDRESET

Sticky bits! RESET

(cleared by WDT underflow or
ext. reset) INTERRUPT
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 Power Control
• Power Control Register [PCON – 0xE01FC0C0] R/W
PCON 0 IDL Idle mode - processor clock
stopped, on-chip peripherals remain
active, interrupts cause wakeup
PCON 1 PD Power Down mode - oscillator and
on-chip clocks stopped, wakeup by
external interrupt

20 uA at room For example 5 mA with most

temperature, peripherals powered down
50 uA with single
voltage supply
Biggest factors:
temperature, clock rates
Peripheral Clock Divider: 20%
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LPC21XX ADC

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41
 Interfaces
• SPI
• I2C
• I2S
• RS-232/RS-485
• Ethernet
• USB
• CAN

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Programming tips

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44
45
 C/C++ basics
• C file usually has .c extension
• C++ file usually has .cpp extension
• Any program should have main function
int main(void)
{
Code here;
}

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 C/C++ basics
• All used functions has to be preliminary
declared – int main(void);
• Program can include header file with .h
extension, containing declarations
• All used variables should be anywhere
declared
• Variables, declared inside the function, are
available only within that function

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 C/C++ basics
• C++ can use structures, that include sets
of data - variables and functions
• C/C++ can operate with the pointers =
addresses of the data/functions
• Symbol * denotes, that it is a pointer
• Symbol & before the name denotes the
link (address will be used instead of the
value)

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 C/C++ notations
• X++ equals to X=X+1
• X-- equals to X=X-1
• X op=N equals to X=X op N
• !X equals NOT X (logical)
• (A==B) is TRUE, then operands are equal
• X&Y Bitwise operation X AND Y
• X^Y Bitwise operation X XOR Y
• X|Y Bitwise operation X OR Y
• ~X Bitwise operation NOT X

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 C/C++ notations
• Static means, that variable keeps its value always,
till the program is being executed
• Extern means, that the function is defined outside
the current file
• 0xNNN represents hexadecimal value
• 123…45 represents decimal value
• __fiq FIQ handler
• __irq IRQ handler
• __arm to be compiled in ARM instruction set

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Thank you for your attention !
Good luck in your trainings !

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