04 - Comparators and Offset Cancellation Techniques
04 - Comparators and Offset Cancellation Techniques
04 - Comparators and Offset Cancellation Techniques
Jieh-Tsorng Wu
September 7, 2016
ES
National Chiao-Tung University
A
1896
Department of Electronics Engineering
Comparators
Vi1
Vo
Typical Architecture
Vi2
Vi1
Vo A Latch Vo
Vi2
CLK
Vi1 Vi2
0
• Resolution (gain).
• Accuracy (offset).
• Common-mode rejection.
• Power dissipation.
• Area
Vo
Vo Vi
Ao
Vi
R C U
g t
m Vi
t
a
Vo h
−ta /(RC)
i C
U= = Ao 1 − e Ao = gmR τm =
Vi gm
ta 1 ta
= Ao × ln ⇒ ≈U if U Ao
τm 1− U
Ao
τm
Vo1 Vo2 Vo
Vi
R C R C R C
g g g
m Vi m V o1 m V o(N−1)
ta 1
≈ (U × N!) N for ta Aoτm
τm
t
C R g g R C
m m t
a
d Vo1 Vo1
C + + gmVo2 = 0
dt R d Vo Vo
⇒ C + − gm Vo = 0 Vo = Vo1 − Vo2
d Vo2 Vo2 dt R
C + + gmVo1 = 0
dt R
Vo(ta) C RC τm C
U= =e t/τr
τr = = = Ao = gmR τm =
Vo(0) gm − 1/R Ao − 1 1 − 1/Ao gm
ta 1
= × ln(U) ≈ ln(U)
τm 1 − 1
A o
• It is faster than the multi-stage cascaded amplifier, and dissipates less power.
VA VD /U VD 1 VD T
− τc
PM = = × = ×e r
VA VA U VA
VD
U Tc t
VD
0 The mean time to failure (MTF) is
U
1
VA
MTF =
PM × fs
VD
fs = Number of comparisons per second
• A metastable state occurs when the input is too small that the output cannot exceed
±VD after Tc duration of regeneration.
VOSA VOSL
Vi2 Vo2 2 2
vna vnl
2 2
VOSL σ (VOSL) vnl
VOS = VOSA + σ 2(VOS ) = σ 2(VOSA) + vn2 = vna
2
+
A A2 A2
T
− τc
• The probability of metastability is PM = (1/A) × (VD /VA) × e r .
• The preamplifier also provides: (1) input common mode rejection; (2) kick-back noise
reduction; (3) analog signal processing (offset cancellation, averaging).
Vi1 M1 M2 Vi1 M1 M2
Vi2 Vi2
VOS
M1 M2 M1 M2
2 2 2
!
Vov σ (∆β) 1 Vov
σ 2(VOS ) = σ 2(∆Vt ) + × = A2V + · A2β
2 β2 W ·L t 4
2 2 2
W AVt σ (∆β) Aβ
β = µCox σ 2(∆Vt ) = =
L W ·L β2 W ·L
I1 I1 = Gm1(Vo1 − VS1)
M3 M1
Gm1
Vo1 Vo2
I2 = Gm2(Vo2 − VS2)
Vo1 Vo2
C1C2 1/2
τr =
C1 Gm2 C2 Gm1Gm2
M4 M2 I2 Gm2 C2 1/2
α=
VSS Gm1 C1
1
Vo1(t) ∼ + [(Vo1(0) − VS1) − α(Vo2(0) − VS2)] × et/τr + VS1
2
1
Vo2(t) ∼ − [(Vo1(0) − VS1) − α(Vo2(0) − VS2)] × et/τr + VS2
2
where
• Consider only capacitor mismatch. Gm1 = Gm2. VS1 = VS2. C1 = C and C2 = C + ∆C.
s
C2 1 ∆C
VOS = (α − 1) · [Vo2(0) − VS2] = − 1 · [Vo2(0) − VS2] ≈
· [Vo2(0) − VS2]
C1 2 C
2 2 2 2
!
AVt0 σ (∆β) Aβ 1 Vov
σ 2(∆Vt ) = = ⇒ σ 2(VOS ) = A2V + · A2β
W ·L β2 W ·L W ·L t 4
For a comparator
2
A2Vt · A2β
2 Vov
gm 2I/Vov 1 σ (VOS ) + 4
Speed ∝ ≈ ∝ ≈
2 2 2
C (2/3) · W L · Cox Accuracy VDD W L · VDD
2
Speed × Accuracy 1 VDD
Power ∝ I · VDD ⇒ ∝ ×
Power
2
Vov Vov
Cox · AV + 4 · A2β
2
t
2 2 2
vn1 vn2 vn
2
vn1 1 Kf 1 2
= 4kT γ + · γ≈
∆f gm W LCox f 3
2 2
vna = 2 × vn1
Vo1 Vo2
M4 M2 2 g 2
id1 C R m g R C id2
m
VSS
id2 2
q q
= 4kT (γgm) γ≈ id 1(t) = 4kT γgm × n1(t) id 2(t) = 4kT γgm × n2(t)
∆f 3
n1(t) and n2(t) are random variables. n1 = n2 = 0 n21 = n21 = 1 n1 × n2 = 0
d Vo1 Vo1 d Vo2 Vo2
KCL ⇒ C + + gmVo2 + id 1 = 0 C + + gmVo1 + id 2 = 0
dt R dt R
4kT γgm
p
d Vo Vo d Vo gm − G
C + − gmVo + (id 1 − id 2) = 0 ⇒ = × Vo − × n(t) = 0
dt R dt C C
If n(t) = 0, we have the canonical regeneration function:
C
V (t) = V (0)e t/τr
Regeneration Time Constant = τr =
gm − G
vn
Do
σ 0 σ vn Vi 0 vn
Vi
P(Do=1)
1
CLK 0.5
Vi
σ 0 σ
1 2 2
vn2 =σ 2
Probability Density Function = PDF(vn) = √ e −vn /(2σ )
2πσ
Z∞
Vi
P (Do = 1) = PDF(vn + Vi )d vn = 0.5 + 0.5 × erf √
0 2σ
M3 M5
M4 M6
Vo
V i1 M1 M2
V i2 M7 M8 M9 M10
• During the track mode (φ = 1), want gm7,m8 < gm9,m10 so that the combination of
M7-M8 and M9-M10 pair become the resistive loads for M5 and M6. The small-signal
voltage gain is
vo gm1 (W/L)6
≈ ·
vi gm9 − gm7 (W/L)4
• During the latch mode (φ = 0), M7, M8, and M11 must be large enough to prevent
the change of latched state by the Vi variation.
CLK M13
M3 M5
M4 M6 M11 M12
IVT1
A
Vo
V i1 M1 M2
B
IVT2
V i2
M8 M7
CLK M9 M10
I1
• During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9-
M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 and
IVT2.
• During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration.
They must be large enough to to prevent the change of latched state by the Vi
variation.
The input threshold level of IVT1 and IVT2 must be high enough to avoid false
triggering.
VSS VSS
Triode Input Stage Saturated Input Stage
• By moving input pair to the top of the latch, input pair can be biased into saturation
for lower offset.
VDD
CLK M11
• Reference: B. Razavi, 1999
ISSCC Short Course.
VSS
Vip M1 M2 Vin
φ φ
φ M5 M17 M15 M16 M18
VSS VSS
Let C1 = C2 = C. When φ = 1, let gm1 = gm2 = gm, gm/Id = 2/Vov ∼ 1/nUT , Id = Id 5/2.
gm Vi gm Vi Id 1 Id 2
= Id +
Id 1 Id 2 = Id − Van = VDD − ×t Vap = VDD − ×t
2 2 C C
Van + Vap Id gm Vi
Va,cm = = VDD − × t Va,d m = Vap − Van = ×t
2 C C
∆Va,d m gmVi Vi ∆Va,d m ∆Va,cm
= = ⇒ Ad m ≡ = ∆Va,cm ∼ |Vtp|
∆Va,cm Id Vov /2 Vi Vov /2
Id C
∆Va,cm = × Ta ⇒ Ta = ∆Va,cm ×
C Id
Consider only thermal noise. The equivalent input noise power is estimated as
2 1
vn2 ≈ 4kT × × Bn Bn =
gm 2Ta
kT Id 1 kT Vov /2 kT 4
⇒ vn2 = 4 × × =4× × = ×
C gm ∆Va,cm C ∆Va,cm C Ad m
φa φa φa φa
b
φb
φb
M3 M4 M3 M4
b
Static Latch Dynamic Latch
M1 M2 M1 M2
Vi Vi
φa M11 φa M11
VSS VSS
φa
φb
Io Io
Vi = Vi + − Vi −
Vi Gm1 Vi VR Gm2 VR VR = VR+ − VR−
Io = Io+ − Io−
IB IB
Io = Gm1Vi − Gm2VR
= Gm(Vi − VR ) if Gm1 = Gm2
• The SCP’s input voltage range must cover the full Vi range.
Io Io
Vi + = +∆Vi + VCMI
Vi − = −∆Vi + VCMI
Vi Gm1 VR VR Gm2 Vi VR+ = +∆VR + VCMR
VR− = −∆VR + VCMR
IB IB Io = Io+ − Io−
Io = Gm1 (+∆Vi + VCMI ) − (+∆VR + VCMR ) − Gm2 (−∆Vi + VCMI ) − (−∆VR + VCMR )
• The SCP’s input voltage range must cover the common-mode difference between Vi
and VR , i.e., VCMI − VCMR .
Vop Von
Van Vap
M13 M14
M1 M3 M4 M2
Vip Vin Vap M11 M12 Van
VRP VRN
VB1
M5 M6 φ M19
VSS VSS
Vi VCMI
1 Ca
1d S3 Ci
S1
2
VR
S5 Vo
2
VR
S6 Ci A1
1d 1 Ca
S4 S2
Vi VCMI
Ci
During φ2 = 1 Vo = −(Vi − VR ) × × A1
Ci + Ca
• The A1’s input common-mode range must tolerate the switching errors from S1 and
S2, and the common-mode difference between Vi and VR .
M3 M4
M5 M6
φ2 φ2
φ1d
a
Vi
Ci1 Ci2
M3 M4
VR M1 M2 φ2
φ2d
M1 M2
IB
φ1 φ1
VCMI VCMI a
VSS
φ2 M11
φ1 VSS
φ2
Vo = 0 Vc = A × VOS
• During the reset-to-amplification transition, let S3 open before S2, so that ∆Q can be
a constant.
S1 V V V
c1 X c2 Y c3
V V
i o
A1 C A2 C A3 C
1 2 3
V OS1 V OS2 V OS3
S2 S3 S4 S5
S1
S2
S3
S4
S5
I II III IV V
Vo = A1 · A2 · A3 · Vi + 4
4
VOS,i n =
A1 · A2 · A3
A
Vo = Vc = VOS ×
A+1
During the amplification mode (φ2 = 1)
0
Vo VOS ∆Q VOSL
A ∆Q
= −Vi × A + VOS − A − VOSL = −A Vi − + +
UL A + 1 Ci A + 1 Ci A
VOS∆Q VOSL
Input-Referred Offset = VOS,i n = − −
A + 1 Ci A
• The IOS allows rail-to-rail input common-mode level and quick overdrive recovery.
V S3 V S4
S1 c1 c2
V V
i o
C C X
1 A1 2 A2
V OS1 V OS2
S2
S1
S2
S3
S4
I II III IV
A1 A2 A2 A1
Vc1 = VOS1 Vc2 = VOS2 − Vc1 = VOS2 − VOS1
A1 + 1 A2 + 1 A2 + 1 A1 + 1
A1 A2 A1
Vc1 = VOS1 + 1 Vc2 = VOS2 − VOS1 + A11
A1 + 1 A2 + 1 A1 + 1
A2 A1 A2
Vc2 = V − V + A11 + 2 Vo = V − A 2 2
A2 + 1 OS2 A1 + 1 OS1 A2 + 1 OS2
A2 VOS2 2
Vo = A 1 A 2 Vi + VOS2 − A22 = A1A2 Vi + −
A2 + 1 A1(A2 + 1) A1
VOS2 2
Input-Referred Offset = VOS,i n = −
A1(A2 + 1) A1
VDD
Vo
2 Vo = Vx
Vi1 MA
S1 Vx 1
Vo
1 C S3
Vi2 I Bias Point
MB
S2
Vx
VSS
VDD VDD
V M1 M3
i1
S1
Latch Vo
C S3 C S4
V 1 2
i2 M2 M4
S2
VSS VSS CK
S1
S2
S3
S4
CK
1 1
Vip M3 M4 Vin
S1 1a 1a S2
Vop Von
2 C S5 S6 C 2
VRp I1 I2 VRn
M1 M2
S3 S4
IB
VSS
CK M5 M6 CK
M10 M8 M9 M11
Vo2 Vo1
M3 I1 M4
C1
I1 Vi1 M1 M2 Vi2 I2
C2
VSS CK VSS
M7
VSS
V CM
V OS
CK
CAL
CAL
V i1
Dc 0 t
V i2
CAL V OS
CAL
V CM Up/Down
Counter
• During Calibration, Vi = Vi 1 − Vi 2 = 0.
q[k] CK q[k]
V i1 Dr
Dc
V i2
CHP1 V OS CHP2
Up/Down
Counter
• CHP1 and CHP2 are random choppers controlled by a binary random sequence, q[k].
φ1 φ1a φc
V1 Vcm
S1 C1 S3 Va
φ2 Dc
VRC [n] Vc
S2
Vcm Vos Latch
Ip
up φ1a
1
Dc
φ1
dn
0 φ2
C2
In φc
• Reference: Y-H Chung and J-T Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE JSSC,
2010/11, pp. 2217–2226.
VDD
φc M9 M10 φc
Dc,p Dc,n
M11 M12
VDD M3 VDD M7
φc M4 φc M8
VSS VSS
R1 R2
Q7
Q8
Q1 Q2 Q3 Q4
Vi Vo
Q5 Q6
φ
I1 I2 I3
VEE
• During the track mode (φ = 1), the variation of input capacitance with Vi causes
input-dependent delay and hence harmonic distortion.
• During latch-to-track transition, Q1 and Q2 are initially off, the I1 current then flows
through Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickback
noise.
V o2
C C
2 6
C
4
• During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain and
a2 is high gain.
• The OOS and IOS perform correlated double sampling (CDS) so that the effect of 1/f
noise is also reduced.
• Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loop
settling behavior.
VDD
M9
M10 VBP1
M3
M4 VBP2
S3 Vo1
1
2
Vi1 M1 M2 Vo2
S1 1 1
M11
2 M6 VBN2
Vi2 M5 S5 M12 S6
S2
C1 C2
S4
1 I1 VBN1 I2
M8
M7
VSS
S3
S1 1
Vi 2 Vo
S2 G m1 R
S4
1 S5
G m2 S6
C1 C2
• The Gm2 compensation circuit is not in the signal path. The original frequency/speed
performance can be maintained.
• VOS1 and VOS2 are the input-referred offset of the Gm1-R and Gm2-R pairs.
• ∆V is due to the mismatch between the switching errors of S5 and S6. Its effect on Vo
can be reduced by making Gm2/Gm1 small.
Vi A Vo
1 LPF
VOS
f
f f f f f
0 0 0 fc 0 fc 0
φ
R1 R2 I3 I4 I5
M5 M6
C1
M3 M4 1
φ C2 Vo
RL
Vi M1 M2
Vi
I1 I2 M7 M8 M9
VSS
φ a
b φa
b
φb
a
• The M3–M4 is a high-gain stage with low Gm. A common-mode feedback circuit is
required to stabilize the drain voltages of M3 and M4.
• The M5–M8 is a high-gain Miller stage for frequency compensation and low-pass
filter.
• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effects
of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization,” Proc. IEEE, 1996/11, pp. 1584–1614.
Vi A Vo
1 LPF
VOS
f
t Modulation Signal
t Spikes at Input
t Demodulation Signal
Residual Offset
t Demodulated Spikes
Vi A Vo
1 LPF
VOS
f
t Modulation Signal
t Spikes at Input
t Demodulation Signal
Residual Offset
t Demodulated Spikes
• The spikes at the input is due to the switching error mismatch of the chopper.
√
Achieve 1.3 µV input offset, 95 nV/ Hz input noise density, 130 dB open-loop dc gain,
and 100 kHz unity-gain frequency, at 13 µA supply current.