Verilog

Introduction to Verilog HDL
Jorge Ramírez
Corp Application Engineer
Synopsys University Courseware

Copyright © 2011 Synopsys, Inc. All rights reserved.
Developed by: Jorge Ramirez
Outline
Lexical elements
• HDL Verilog Data type representation
• Synthesis Verilog tutorial Structures and Hierarchy
Operators
• Synthesis coding guidelines Assignments
Control statements
• Verilog - Test bench Task and functions
Generate blocks
• Fine State Machines
• References

HDL VERILOG

What is HDL?
• Hard & Difficult Language?
– No, means Hardware Description Language
• High Level Language
– To describe the circuits by syntax and sentences
– As oppose to circuit described by schematics
• Widely used HDLs
– Verilog – Similar to C
– SystemVerilog – Similar to C++
– VHDL – Similar to PASCAL
Verilog
• Verilog was developed by Gateway Design
Automation as a proprietary language for logic
simulation in 1984.
• Gateway was acquired by Cadence in 1989
• Verilog was made an open standard in 1990
under the control of Open Verilog International.
• The language became an IEEE standard in 1995
(IEEE STD 1364) and was updated in 2001 and
2005.
SystemVerilog
• SystemVerilog is the industry's first unified
hardware description and verification language
• Started with Superlog language to Accellera in
2002
• Verification functionality (base on OpenVera
language) came from Synopsys
• In 2005 SystemVerilog was adopted as IEEE
Standard (1800-2005). The current version is
1800-2009
IEEE-1364 / IEEE-1800
Verilog 2005 (IEEE Standard
1364-2005) consists of minor
corrections, spec clarifications,
and a few new language
features
SystemVerilog is a superset of
Verilog-2005, with many new
features and capabilities to aid
design-verification and design-
modeling
Types of modeling
• Behavioral
– Models describe what a module rst Counter
cnt [0:3]
does. clk
If (rst)
cnt = 0;
else
– Use of assignment statements,

cnt = cnt+1;
loops, if, else kind of statements

• Structural
– Describes the structure of the
hardware components
– Interconnections of primitive gates
(AND, OR, NAND, NOR, etc.) and
other modules

Behavioral - Structural
Behavioral Structural
module cter ( module cter ( rst, clock, count );
input rst, clock, output [1:0] count;
output reg [1:0] count input rst, clock;
); wire N5, n1, n4, n5, n6;
always@(posedge clock) FFD U0 (.D(N5), .CP(clock),
begin .Q(count[0]), .QN(n6));
if (rst) count = 0; FFD U1 (.D(n1), .CP(clock),
else count = count +1; .Q(count[1]), .QN(n5));
end MUX21 U2 (.A(N5), .B(n4),
.S(n5), .Z(n1) );
endmodule
NR U3 (.A(n6), .B(rst), .Z(n4));
NR U4 (.A(count[0]), .B(rst),
.Z(N5));
endmodule
Simulation and Synthesis
• The two major purposes of HDLs are logic
simulation and synthesis
– During simulation, inputs are applied to a module, and
the outputs are checked to verify that the module
operates correctly
– During synthesis, the textual description of a module
is transformed into logic gates
• Circuit descriptions in HDL resemble code in a
programming language. But the code is intended
to represent hardware
Simulation and Synthesis
• Not all of the Verilog commands can be
synthesized into hardware
• Our primary interest is to build hardware, we will
emphasize a synthesizable subset of the language
• Will divide HDL code into synthesizable modules
and a test bench (simulation).
– The synthesizable modules describe the hardware.
– The test bench checks whether the output results are
correct (only for simulation and cannot be
synthesized)
SYNTHESIS VERILOG TUTORIAL

Outline
• Lexical elements
• Data type representation
• Structures and Hierarchy
• Operators
• Assignments
• Control statements
• Task and functions
• Generate blocks
Lexical elements
• Case sensitive - keywords are lower case
• Semicolons(;) are line terminators
• Comments:
– One line comments start with // ...
– Multi-line comments start with /*and end
with*/
• System tasks and functions start with a dollar
sign, ex $display, $signed
Lexical elements
• Variable names have to start with an alphabetic
character or underscore (_) followed by
alphanumeric or underscore characters
• Escaped identifiers (\)
– Permit non alphanumeric characters in Verilog name
– The escaped name includes all the characters
following the backslash until the first white space
character
wire \fo+o=a ; // Declare the varaible fo+o=a=a
wire \fo+o =a ; // Assign a to wire fo+o
Compiler directives
• The directives start with
ìnclude “file1.v”
a grave accent ( ` ) // Used as `WORD_SIZE in code
followed by some `define WORD_SIZE 32
keyword
`define module test ();
Text-macro substitution ìfdef TEST
// A implementation
ìfdef, ìfndef, èlse, èlse
èndif // B implementation
Conditional compilation èndif
ìnclude assign out = `WORD_SIZE{1’b1};
File inclusion endmodule

Reserved keywords
and always assign attribute begin buf bufif0 bufif1
case cmos deassign default defparam disable else endattribute
end endcase endfunction endprimitive endmodule endtable endtask event
for force forever fork function highz0 highz1 if
initial inout input integer join large medium module
nand negedge nor not notif0 notif1 nmos or
output parameter pmos posedge primitive pulldown pullup pull0
pull1 rcmos reg release repeat rnmos rpmos rtran
rtranif0 rtranif1 scalared small specify specparam strong0 strong1
supply0 supply1 table task tran tranif0 tranif1 time
tri triand trior trireg tri0 tri1 vectored wait
wand weak0 weak1 while wire wor

Outline
• Operators
• Assignments
• Generate blocks
Logical values
• A bit can have any of these values
– 0 representing logic low (false)
– 1 representing logic high (true)
– X representing either 0, 1, or Z
– Z representing high impedance for tri-state
(unconnected inputs are set to Z)

Logical values
• Logic with multilevel (0,1,X,Z) logic values
– Nand anything with 0 is 1
– Nand two get an X
• True tables define the how outputs are
compute
& 0 1 X Z | 0 1 X Z
0 0 0 0 0 0 0 1 X X
1 0 1 X X 1 1 1 1 1
X 0 X X X X X 1 X X
Z 0 X X X Z X 1 X X

Number representation
<size>'<base format><number>
• <size>:
– number of bits (optional)
• <base format>:
– It is a single character ' followed by one of the following
characters b, d, o and h, which stand for binary, decimal,
octal and hex, respectively.
• <number>
– Contains digits which are legal for the <base format>
– ‘_’ underscore can be use for readability
• Negative numbers are store as 2’s
complement
• Extended number
– If MSB is 0, X or Z number is extended to fill MSBs
with 0, X, Z respectively
3’b01=3’b001 3’bx1=3’bxx1 3’bz=3’bzz
– If MSB is 1 number is extend to fill MSBs with 0/1,

depending on the sign
3’b1=3’b001 -3’b1=-3’b01=3’b111
Unsized numbers (at least 32 bit)
549 // decimal number
'h8F_F // hex number
'o765 // octal number
Size numbers
4'b11 // 4-bit binary number 0011
3'b10x // 3-bit binary number with LSM bit unknown
8'hz // 8-bit binary high-impedance number
4'hz1 // 4’bzzz1
5'd3 // 5-bit decimal number
Signed numbers
-8'd6 // 8-bit two's complement of 6 (-6)
4'shF // 4-bit number ‘1111’ to be interpreted as
// 2’s complement number
Data types (reg)
• A reg (reg) stores its value from one
assignment to the next (model data storage
elements)
– Don’t confuse reg with register
– Default value is X
– Default range is one bit
– By default are unsigned, but can be declare
signed, using keyword signed

Data types (Nets)
• Nets (wire) correspond to physical wires that
connect instances
– Nets do not store values
– Have to be continuously driven
– The default range is one bit
– By default are unsigned
• The wire declaration is used most frequently,
other net types are wand, wor, tri, triand,
trior, etc.
Other data types
• Integer (integer)
– Convenient to counting purposes
– At least 32-bit wide
– Useful for loop
• Real (real) simulation only
– Can be specified in decimal and scientific notation

Verilog vectors
Know as BUS in hardware
• Declare by a range following the type
<data type> [left range : right range] <Variable name>
• Single element that is n-bits wide
reg [0:7] A, B; //Two 8-bit reg with MSB as the 0th bit
wire [3:0] Data; //4-bit wide wire MSB as the 4th bit
• Vector part select (access)
A[5] // bit # 5 of vector A
Data[2:0] // Three LSB of vector Data

Verilog arrays
• Array: range follows the name
<datatype> <array name> [<array indices>]
reg B [15:0]; // array of 16 reg elements
• Array of vectors
<data type> [<vector indices>]<array
name>[<array indices>]
reg [15:0] C [1023:0]; // array of vectors
• Memory access
<var name>[<array indices>] [<vector indices>]

Data storage and Verilog arrays
Simple RAM Model
module RAM (output [7:0] Obus,
input [7:0] Ibus,
input [3:0] Adr,
input Clk, Read
);
reg [7:0] Storage[15:0];
reg [7:0] ObusReg;
assign Obus = ObusReg;
always @(posedge Clk)

if (Read==1’b0) Storage[Adr] = Ibus;
else ObusReg = Storage[Adr];
endmodule
Data storage and Verilog arrays
Counter
module cter (input rst, clock, jmp,
input [7:0] jump,
output reg [7:0] count
);
always@(posedge clock)
begin
if (rst) count = 8’h00;
else if (jmp) count = jump + count;
else count = count + 8’h1;
end
endmodule

Outline
• Operators
• Assignments
• Generate blocks
Structures and Hierarchy
• Hierarchical HDL structures are achieved by
defining modules and instantiating modules
top.v TOP
comp.v COMP
mux.v
MUX
Module declaration
module <module name> #(<param list>) (<port list>);

<Declarations>
<Instantiations>
<Data flow statements>
<Behavioral blocks>
<task and functions>
endmodule

Module header
• Start with module keyword, contains the I/O ports
• Port declarations begins with output, input or
inout follow by bus indices
• Each directions are followed by one or more I/O
names
• Each declaration is separated by comma (,)
module ALU (output [31:0] z,
input [15:0] A, B,
input clock, ena);
Port declaration
• input and inout are declared as wires
• outputs port can be declared as reg (holds a
value)
• 2 flavors for port declaration:
module S1 (a, b, c, d, e); module S2 (input [1:0] a, b,
input [1:0] a, b; input c,
input c; output reg [1:0] d,
output reg [1:0] d; output e);
output e;
//Verilog 1995 Style //ANSI C Style
endmodule endmodule
Parameters
• Parameters are means of giving names to
constant values
• The values can be overridden when the design
is compiled
• Parameters cannot be used as variables
• Syntax:
parameter <name> = <constant expression>;

Parameter declaration
• Default value need to be set at declaration time
• 32 bit wide by default, but may be declared of
any width
parameter [2:0] IDLE = 3’d0;
• 2 declaration flavors:
Inside a module In module header
module test (... I/O’s ...) module test
parameter ASIZE = 32, BSIZE =16; #(parameter ASIZE = 32, BSIZE =16)
//… (... I/O’s ...);
reg [ASIZE -1:0] Abus, Zbus; //…
wire [BSIZE-1:0] Bwire; reg [ASIZE -1:0] Abus, Zbus;
//… wire [BSIZE-1:0] Bwire;
endmodule //…
endmodule
Example
module Adder (A, B, Cin, S,
A[N-1:0]
Cout, Clk); Adder S[N-1:0]
parameter N=8; B[N-1:0]
N-bits
input [N-1:0]A, B;
(8 by default) Cout
input Cin; Cin
reg-ouputs
input Clk;
output [N-1:0] S;
output Cout;
reg [N-1:0] S; Clk
reg Cout;
//module internals module Adder #(parameter N=8)
endmodule (input [N-1:0]A, B,
input Cin,
input Clk,
output reg [N-1:0] S,
output reg Cout
ANSI C style );
//module internals
endmodule
Structures and Hierarchy
• Instance of a module
– Instantiation is the process of “calling” a module
– Create objects from a module template
<module name> #(<param list>)
<instance name> (<port list>);
Where:
<module name> Module to be instantiated
<param list> Parameters values passed to the instance
<instance name> Identifies the instance of the module
<port list> Port list connection
Port list connections
• Ports
– Provide the interface by which a module can
communicate with the environment
– Port declarations (input, output, inout)
reg o net net reg o net net
input output
net inout
net

Port connections/Parameter overwrite
• Named connection
– Explicitly linking the 2 names for each side of the
connection
my_mod #(.W(1), .N(4)) U1 (.in1(a), .in2(b),
.out(c));
• Order connection
– Expression shall be listed in the same order as the
port declaration
my_mod #(1,4) U2 (a, b, c);
Hierarchy example
TOP module TOP (…port_list…);

U1 ALU U1 (…port connection…);
ALU S1 MEM U2 (…port connection…);
FIFO endmodule
module ALU (…port_list…);
U2 FIFO S1 (…port connection…);
endmodule
MEM
module FIFO (…port_list…);
//...
endmodule

Outline
• Operators
• Assignments
• Generate blocks
Relational operators
• Mainly use in expression (e.g. if sentences)
• Returns a logical value (1/true 0/false)
• If there are any X or Z bit returns X (false on a
expression)
< a < b // is a less than b?
> a > b // is a greater than b?
>= a >= b // is a greater than or equal to b
<= a <= b // is a less than or equal to b

Arithmetic operators
• Binary operators
– Takes 2 operators
• Unary operators (+/-)
– Specify the sign of the operand
– Negative numbers are represented as 2’s
complement
* c = a * b ; // multiply a with b
/ c = a / b ; // int divide a by b
+ sum = a + b ; // add a and b
- diff = a - b ; // subtract b from a
% amodb = a % b ; // a mod(b)
Logical operators
• Logical operators evaluate to a 1-bit value
&& a && b ; // is a and b true? returns 1-bit true/false
|| a || b ; // is a or b true? returns 1-bit true/false
! if (!a) c = b; // if a is not true assign b to c
• If an operant is not zero is treat as logical 1

A=3; B=0;
A&&B //Evaluates to 0 Equivalent to (logical-1 && logical-0)
!B //Evaluates to 1 Equivalent to (!logical-0)
• If an operant is Z o X is treat as X (false)
A=2’b0x; B=2’b10;
A&&B //Evaluates to x Equivalent to (x && logical-0)
Equality and Identity operators
== c == a ; /* is c equal to a returns 1-bit true/false

applies for 1 or 0, logic equality, using X or
Z operands returns always false ('hx == 'h5
returns 0) */
!= c != a ; // is c not equal to a, returns 1-bit true
=== a === b ; // is a identical to b (includes 0, 1, x, z)
/* is a not identical to b returns 1-bit
!== a !== b ;
true/false*/

Bitwise and Reduction operations
/* AND all bits of a

& b = &a ;
(reduction) */
| b = |a ; /*OR all bits (reduction)*/
/*Exclusive or all bits of
^ b = â ;
a (reduction)*/
/* NAND, NOR, EX-NOR all
~&, ~|,~^ c = ~& b ;
bits together */
/*bit-wise NOT, AND, OR,
~,&, |, ^ b = ~a ; e = b | a
EX-OR*/
/*bit-wise NAND, NOR, EX-
~&, ~|, ~^ e = a ~^ b ;
NOR*/

Shift and other operator
<< a << 1 ; // shift left a by 1-bit
>> a >> 1 ; // shift right a by 1
<<< b <<< 1 ; // arithmetic shift by 1
>>> b >>> 1 ; // arithmetic shift by 1
/* if sel is true c = a, else c
?: c = sel ? a : b ;
= b , ?: ternary operator */
/* add a, b, ci assign the

overflow to co and the result to
{} {co, sum} = a + b + ci;
sum: operator is called
concatenation */
/* replicate a 3 times,
{{}} b = {3{a}}
equivalent to {a,a,a} */
Operators precedence
Operator precedence
Unary, Multiply, Divide, +,-,!,~ Highest
Modulus *, / %
+, -
Add, subtract, shift
<<. >>
<, < =, >, >=
Relational
=, ==. !=
Equality
===, !==
&, ~&
^, ^~
Reduction
|, ~|
Logical
&&
||
Conditional ?: Lowest
Outline
• Operators
• Assignments
• Generate blocks
Concurrent blocks
• Blocks of code with no well-defined order
relative to one another
– Module instance is the most important concurrent
block
– Continuous assignments, and procedural blocks
are concurrent within a module
module AND (input A, B, output C);
wire w;
NAND U1 (A, B, w);
NAND U2 (w, w, C);
endmodule
Continuous assignments
• Continuous assignments imply that whenever
any change on the RHS of the assignment
occurs, it is evaluated and assigned to the LHS
• Continuous assignments always implement
combinational logic
• Continuous assignments drive wire variables
wire A;
assign A = (B|C)&D;
Continuous assignments
• Implicit continuous assignment
– Continuous assignment can be placed when the
net is declared
wire A = i1 & i2;
• Implicit net declaration (not recommended)
– If a signal name is used to the left of a continuous
assignment, a implicit net declaration will be
inferred
wire i1, i2;
assign A = i1 & i2;
Example
A module NAND (A, B, C);
C input A, B;
output C;
B // Continuous assignments
assign C = ~(A&B);
endmodule
module AND (A, B, C);

input A, B;
output C;
A
C wire w;
// 2 NAND instantiations
B
NAND U1 (A, B, w);
NAND U2 (w, w, C);
endmodule
Procedural blocks
• Each procedural block represent a separate
activity flow in Verilog
• Procedural blocks
– always blocks
• To model a block of activity that is repeated continuously
– initial blocks simulation only
• To model a block of activity that is executed at the beginning
• Multiple behavioral statements can be grouped
using keywords begin and end
Procedural assignments
• Procedural assignment changes the state of a reg
• Used for both combinational and sequential
logic inference
• All procedural statements must be within always
(or inital) block
reg A;
always @ (B or C)
begin
A = ~(B & C);
end
Always block – Event control (@)
• Always blocks model an activity that is
repeated continuously
• @ can control the execution
– posdege or negedge make sensitive to edge
– @* / @(*), are sensitive to any signal that may be
read in the statement group
– Use “,”/or for multiple signals

Always block – Event control (@)
module M1 (input B, C, clk, rst, output reg X, Y,Z);
// controlled by any value change in B or C
always @ (B or C)
X = B & C;
// Controlled by positive edge of clk

always @(posedge clk)
Y = B & C;
// Controlled by negative edge of clk or rst

always @(negedge clk, negedge rst)
if (!rst) Z = B & C;
else Z = B & C;
endmodule

Example
D Q D Q
R G
module FFD (input Clk, R, D, module LD (G, D, Q);

output reg Q); input G, D;
always @ (posedge Clk) output Q;
begin reg Q;
if (R) always @(G or D)
Q = 1'b0; if (G)
else Q = D;
Q = D; endmodule
end
endmodule

Blocking / Non-Blocking assignment
Blocking assignment always @(posedge Clk)
begin
• (= operator) acts much like in //blocking procedural assignment
traditional programming C = C + 1;
languages A = C + 1;
end
• The whole statement is done
before control passes on to the always @(posedge Clk)
next statement. begin
//non-blocking procedural assignment
Non-blocking assignment D <= D + 1;
• (<= operator) Evaluates all the B <= D + 1;
end
right-hand sides for the current
time unit and assigns the left- Example: During every clock cycle
hand sides at the end of the time A is ahead of C by 1
unit. B is same as D

Procedural blocks (summary)
• Blocks of code within a concurrent block
which are read (simulated, executed) in order
• Procedural blocks may contain:
– Blocking assignments
– Nonblocking assignments
– Procedural control statements (if, for, case)
– function, or task calls
– Event control (‘@’)
– Nested procedural blocks enclosed in begin … end
Outline
• Operators
• Assignments
• Generate blocks
Conditional statements (if … else)
• The statement occurs if the expressions controlling
the if statement evaluates to true
– True: 1 or non-zero value
always @ (WRITE or STATUS)
– False: 0 or ambiguous (X) begin
• Explicit priority if (!WRITE)

begin
out = oldvalue;
if (<expression>) end
// statement1 else if (!STATUS)
else if (<expression>) begin
// statement2 q = newstatus;
else end
// statement3 end
Conditional statements (case)
• case, casex, casez: case statements are used for
switching between multiple selections
– If there are multiple matches only the first is evaluated
– Breaks automatically
• casez treats Z as don’t care
• casex treats Z and X as don’t care
case (<expression>)
<alternative 1> : <statement 1>;
<alternative 2> : <statement 2>;
default : <default statement>;
endcase

Conditional statements (case)
always @(s, a, b, c, d)
case (s) always @*
2'b00: out = a; casex (state)
2'b01: out = b; /*
2'b10: out = c; during comparison : 3'b01z,
2'b11: out = d; 3'b01x, 3b'011 ... match case
endcase 3'b01x
always @* */
casez (state) 3'b01x: fsm = 0 ;
// 3'b11z, 3'b1zz,... match 3'b0xx: fsm = 1 ;
3'b1?? default: fsm = 1 ;
3'b1??: fsm = 0; endcase
3'b01?: fsm = 1;
endcase
Example
module mux(a, b, c, d, s, out);
input [7:0] a, b, c, d;
a input [1:0] s;
b output [7:0] out;
8-bit out reg [7:0] out;
c 4-to-1 // used in procedural statement
multiplexer always @ (s or a or b or c or d)
d case (s)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
s[0] s[1] 2'b11: out = d;
endcase
endmodule

Latches / Muxes (Comb logic)
• Assuming only level sensitivity on a always block:
– A variable or signal when is fully specified (it is
assigned under all possible conditions) a mux or
combinational logic.
– If a variable or signal is not fully specified a latch will
be inferred
always @ (a,b,sel) always @ (DATA, GATE) always @ (DATA, GATE)

if (sel==1’b1) if (GATE) begin
z=a; Q = DATA; Q = 0;
else if (GATE) Q = DATA;
z=b; end
MUX LATCH COMB LOGIC

Loop statements (for)
• Works the same ways as C
• Unary increment/decrement is not allowed
for (<loop var init>; <loop var reentry expr>; <loop var update>)
<statement>;
// General purpose loop

interger i;
always @*
for (i = 0 ; i < 7 ; i=i+1)
memory[i] = 0;
Loop statements (while)
• Loop execute until the expression is not true
always @*
while(delay)
// multiple statement groups with begin-end
begin
ldlang = oldldlang;
delay = delay – 1;
end

Loop statements (repeat)
• Repeat statement a specified number of times
• The number is evaluated only at the beginning
always @*
repeat(`BIT-WIDTH)
begin
if (a[0]) out = b + out;
a = a << 1;
end

Outline
• Operators
• Assignments
• Generate blocks
Tasks and Functions
Task and function serve the same purpose on Verilog as
subroutines do in C
Task: Functions:
• Declare with task and • Declare with function and
endtask endfunction
• May have zero arguments • Must have at lease one
or more arguments of type input
input, output, inout
• Do not return with a value, • Always return a single value
can pass values through (cannot have output or
output and inout inout arguments)
arguments
Tasks and Functions - example
module top (input a1, a2, output reg [1:0] b1, b2);
always @ (a1, a2)
begin
b1 = out (a1, a2); // function calling
out_task (a1, a2, b2); // task calling
end
function [1:0] out (input in1, in2); // Function Declaration
begin
if (in1) out = {in2,in1}; else out = {in1,in2};
end
endfunction
task out_task (input in1, in2, output [1:0] out); // Task Declaration
begin
if (in1) out = {in2,in1}; else out = {in1,in2};
end
endtask
endmodule

Task and Functions
• Functions are simpler
Function Task
Can call another function Can call another function or task
Can modify only one value Can modify multiple values
• Data Sharing
– Functions and task could be declare as automatic
– A static function retains the value of all it's
internal variables between calls. An automatic
function re-initializes them each call
Outline
• Operators
• Assignments
• Generate blocks
Generate blocks
• Allow to generate Verilog code dynamically at
elaboration time
– Facilitated the parameterized model generation
– Required the keywords generate – endgenerate
– Generate instantiations can be
• Module instantiations
• Continuous assignments
• initial / always blocks
– Typically used are generate loop and conditional
generate
Generate loop
module top( input [0:3] in1,

output [0:3] out1);
// genvar control the loop
genvar I;
generate
for( I = 0; I <= 3; I = I+1 )
begin
sub U1(in1[I], out1[I]);
end
endgenerate
endmodule

Conditional generate
module top #(parameter POS=0)
(input in, clk, output reg out);
generate
if(POS==1)
always @ (posedge clk)
out = in;
else
always @ (negedge clk)
out = in;
endgenerate
endmodule

SYNTHESIS CODING GUIDELINES

Synthesis coding guidelines
• Inferring Three-State Drivers
– Never use high-impedance values in a conditional
expression (Evaluates expressions compared to
high-impedance values as false)
• Sensitivity Lists
– You should completely specify the sensitivity list
for each always block. Incomplete sensitivity lists
can result in simulation mismatches
always @ (A)
C <= A | B;
• Value Assignments
– The hardware generated by blocking assignments
(=) is dependent on the ordering of the
assignments
– The hardware generated by nonblocking
assignments (<=) is independent of the ordering of
the assignments
– For correct simulation results, Use nonblocking
assignments within sequential Verilog always
blocks
• Value Assignments
– Do not mix blocking and nonblocking assignments
in the same always block
– Do not make assignments to the same variable
from more than one always block. It is a Verilog
race condition, even when using nonblocking
assignments
– Place one module per file
• If Statements
– When an if statement used in a Verilog always block as
part of a continuous assignment does not include an
else clause, synthesis tool may creates a latch.
• Case Statements
– If your if statement contains more than three
conditions, consider using the case statement to
improve the parallelism of your design and the clarity
of your code
– An incomplete case statement results in the creation
of a latch
• Constant Definitions
– Use the Verilog `define statement to define global
constants
– Keep global constant definitions in a separate file.
• Using Verilog Macro Definitions
– In Verilog, macros are implemented using the `define
statement
– Keep `define statements in a separate file.
– Do not use nested `define statements (difficult to
read)
• Guidelines for Identifiers
– Ensure that the signal name conveys the meaning of
the signal or the value of a variable without being
verbose
– Use a consistent naming style for capitalization and to
distinguish separate words in the name.
– Examples:
• C style uses lowercase names and separates words with an
underscore, for example, packet_addr, data_in, and
first_grant_enable
• Pascal style capitalizes the first letter of the name and first
letter of each word, for example, PacketAddr, DataIn, and
FirstGrantEnable
JUST FOR FUN

Question 1
input [7:0] data;
output [7:0] data_reversed;
Can the bit reversal be done by applying the next assignment?
data_reversed = data[0:7];
data_reversed = {data_8[0], data_8[1], data_8[2], data_8[3],

data_8[4], data_8[5], data_8[6], data_8[7]};
input [127:0] data;

output [127:0] data_reversed;
for (i = 127; i >= 0; i = i - 1)
data_deversed[i] = data[127 - i];

Question 2
parameter WIDTH = 4;
output [WIDTH - 1 : 0] data;
How we can assign to each bit a 1'b1?
assign data= {WIDTH{1'b1}};
assign data= (1 << WIDTH) – 1;

Question 3
Which is the correct macro usage?
`define TEST `define TEST `define TEST
`define SIZE 32 `define SIZE 32 `define SIZE 32
module test (); module test (); module test ();

ìfdef TEST ìfdef TEST ìfdef `TEST
assign out = SIZE{1’b1}; assign out = `SIZE{1’b1}; assign out = `SIZE{1’b1};
èlse èlse èlse
assign out = SIZE{1’b0}; assign out = `SIZE{1’b0}; assign out = `SIZE{1’b0};
èndif èndif èndif
endmodule endmodule endmodule

Question 4
• Which code infer a asynchronous reset FF?
module FFD (input Clk, R, D, module FFD (input Clk, R, D,
output reg Q); output reg Q);
always @ (posedge Clk, negedge R) always @ (posedge Clk, negedge R)
begin begin
if (!R) if (R)
Q = 1'b0; Q = 1'b0;
else else
Q = D; Q = D;
end end
endmodule endmodule

Question 5
Is the next module header correct?
module Adder(input [N-1:0]A, B,
input Cin, NO!
input Clk,
output reg [N-1:0] S, Parameter is used
output reg Cout); before it is declared !
parameter N=8;
//module internals
endmodule module Adder #(parameter N=8)
(input [N-1:0]A, B,
input Cin,
input Clk,
output reg [N-1:0] S,
output reg Cout
);
//module internals
endmodule
Question 6
What does X means in synthesis and simulation?
Synthesis Simulation
Unknown value
Don’t care
Assigning “X” to a wire or reg is Be aware, when
highly encouraged for synthesis: assigning X’s they may
it specifies a don’t care propagate throughout
condition, letting the synthesis your design under
tool do further optimization
simulation

VERILOG TEST BENCH

Writing Test Bench
• A test bench specifies a sequence of inputs to be
applied by the simulator to an Verilog-based
design.
• The test bench uses an initial block and delay
statements and procedural statement.
• Verilog has advanced “behavioral” commands to
facilitate this:
– Delay for n units of time
– Full high-level constructs: if, while, sequential
assignment.
– Input/output: file I/O, output to display, etc.
Test Bench
`timescale 10ns/1ps
module test_bench; module DUT (in1, in2, clk, out1);
// Interface to communicate with the DUT input in1, in2;
reg a, b, clk; input clk;
wire c; output reg out1;
// Device under test instantiation always @(posedge clk)
DUT U1 (.in1(a), .in2(b), .clk(clk), .out1(c)); out1 = in1în2;
initial endmodule
begin // Test program
test1 ();
$finish;
end task test1 ();
initial begin
begin a = 0; b = 0;
clk = 0; #10 a = 0; b = 1;
forever #5 clk = ~clk; #10 a = 1; b = 1;
end #10 a = 1; b = 0;
initial end
begin // Monitor the simulation endtask
$dumpvars;
$display ("clk | in1| in2 | out1 |");
$monitor (" %b| %b | %b | %b |",clk, a, b, c);
end
endmodule
Simulation results
Chronologic VCS simulator copyright 1991-2008
clk | in1| in2 | out1 |

0| 0 | 0 | x |
1| 0 | 0 | 0 |
0| 0 | 1 | 0 |
1| 0 | 1 | 1 |
0| 1 | 1 | 1 |
1| 1 | 1 | 0 |
V C S S i m u l a t i o n R e p o r t
Time: 300000 ps
CPU Time: 0.010 seconds; Data structure size: 0.0Mb

Precision macro
• `timescale
– Defines the time units and simulation precision
(smallest increment)
`timescale Time_Unit/Precision_Unit
– Time : 1 10 100
– Units: ms us ns ps fs
– The precision unit must be less than or equal to
the time unit
– Example:
`timescale 10ns/1ps
Initial block
• initial block
– Contains a statement or block of statement which
is executed only once, stating at the beginning of
the simulation
– Each block is executed concurrently before
simulation time 0 (ignore by synthesis)
– No sensitivity list initial
begin
X = 1’b0;
end
Forever block
• forever block
– Cause one or more statements to be executed in
an infinite loop.
– Example: clock signal generation
initial
begin
clk = 0;
forever #5 clk = ~clk;
end

Delay
• Delay (#)
– Specifies the delay time units before a statement is
executed during simulation
– Regular delay control
#<num> y = 1;
• Regular delay control is used when a non-zero value is
specified
– Zero delay control
#0;
• Ensure that statements are executed
at the end of time 0
– Intra-assignment delay control
y = #<num> x+z;
Delay example
parameter sim_cycle = 6;
initial
begin
x=0;
#10 y=1; //assignment is delayed 10 time units
#(sim_cycle/3) x=2; //delay number can came from a parameter
end
initial
begin
p = 0; q = 0;
r = #5 p+q; //Take the value of p and q at time 0, evaluate
// p+q and wait 5 time units to assign value to r
end
initial
begin
#0 x =1; //x=0,p=0;q=0,x=1 are executed a time 0 but x=1 is
//executed at the end
end
Task
• Task helps to simplify the test bench
• Can include timing control
– Inputs
– Delays (#) and regular event control (@)
task load (input [7:0] data, task reset;
input enable); begin
begin rst_n = 1'b0;
#2 rst_n = 1’b0; repeat(3)
#10 data_in=data; @(negedge clk);
#2 read_ena=enab; rst_n = 1'b1;
end end
endtask endtask
Hierarchical names
• Hierarchical name references allows us to denote
every identifier in the design with a unique name
• Hierarchical name is a list of identifier separated
by dots (“.”)
TB (U1)
SUB1 (U1)
SUB2.1 module TB ();
reg mem; //...
$monitor (“%b”, TB.U1.U1.mem);
(U2) $monitor (“%b”, TB.U1.U2.data);
SUB2.2 endmodule
wire data;

System tasks and functions
• System task are tool specific tasks and functions.
$display, $write // utility to display information
$monitor // monitor, display
$time, $realtime // current simulation time
$finish // exit the simulator
$stop // stop the simulator
$timeformat // format for printing simulation
$random // random number generation
$dumpvars // dump signals to file

$display - $strobe - $monitor
• Print message to a simulator (similar to C printf)
• $display (format, args)
– Display information before RHS evaluation (before
nonblocking assignments)
• $strobe (format, args)
– Display information after RHS evaluation (after
nonblocking assignments)
• $monitor (format, args)
– Print-on-change after RHS and nonblocking
assignments whenever one argument change
Verilog string and messages
initial
begin
$display (“Results\n”);
$monitor (“\n Time=%t X=%b”, $time , X);
end
Useful format specifiers:

%h hex integer %t simulation time
%d decimal integer %u 2-value data
%b binary %z 4-value data
%c single ASCII character %m module instance name
%s character string
$random
• Random number generation
• Returns as 32-bit signed integer
reg [31:0] rand1, rand2, rand3;

rand1 = $random; // generates random numbers
rand2 = $random % 60; // random numbers between -59 and 59
rand3 = {$random} % 60;// random positive values
// between 0 and 59

$dumpvars
• The Verilog $dumpvars command is used to
generate a value change dump (VCD)
• VCD is an ASCII file that contains information
about simulation, time, scope and signal
definition, and signal value changes
• VCD files can be read on graphical wave from
displays
initial
begin // Monitor the simulation
$dumpfile ("myfile.dump");
$dumpvars;
end

Test Bench
`timescale 10ns/1ps
module test_bench;
// Interface to communicate with the DUT
reg a, b, clk; module DUT (in1, in2, clk, out1);
wire c; input in1, in2;
// Device under test instantiation input clk;
DUT U1 (.in1(a), .in2(b), .clk(clk), .out1(c)); output reg out1;
initial always @(posedge clk)
begin // Test program out1 = in1în2;
test1 (); endmodule
$finish;
end
initial task test1 ();
begin begin
clk = 0; a = 0; b = 0;
forever #5 clk = ~clk; #10 a = 0; b = 1;
end #10 a = 1; b = 1;
initial #10 a = 1; b = 0;
begin // Monitor the simulation end
$dumpvars; endtask
$display ("clk | in1| in2 | out1 |");
$monitor (" %b| %b | %b | %b |",clk, a, b, c);
end
endmodule
FINITE STATE MACHINE

Finite-State machine
Abstraction
Inputs (X) Outputs (Y)
Combinational
Logic
Y=Y(X, Sn)
Clocked Storage
Elements
Present State: Sn Next State Sn+1

Clock Sn+1 = f (Sn, X)
Abstraction
• Clocked Storage Elements: Flip-Flops and
Latches should be viewed as synchronization
elements, not merely as storage elements !
• Their main purpose is to synchronize fast and
slow paths:
– Prevent the fast path from corrupting the state
• Function of clock signals is to provide a
reference point in time when the FSM changes
states Synopsys University Courseware
Finite State machine
Mealy and More
• Mealy and More FSM
– A Moore FSM is a state machine where the outputs
are only a function of the present state.
– A Mealy FSM is a state machine where one or more of
the outputs is a function of the present state and one
or more of the inputs.

Jorge Ramírez
Developed by: Jorge Ramirez 114
State Changes
Xt Combinational Yt Xt+1 Combinational Yt+1

Logic Logic
Sn Sn+1
Clock
DCQ DCQ
U U
Y= Sn-1 Sn Sn+1
Time

Critical Path
Critical path is Inputs (X)

Combinational
Outputs (Y)
defined as the Logic

Y=Y(X, Sn)
chain of gates in
Clocked Storage
the longest Elements
(slowed) path
thought the logic Present State: Sn
Clock
Next State Sn+1
Sn+1 = f (Sn, X)

FSM Implementation
Design example
• A level-to-pulse converter produces a single-
cycle pulse each time its input goes high.
• In other words, it’s a synchronous rising-edge
detector.
• Sample uses:
– Buttons and switches pressed by humans for
arbitrary periods of time
– Single-cycle enable signals for counters
Level to Pulse
L P
Converter
Whenever input L goes from low to high... ...output P produces a single pulse, one clock period wide.
CLK
FSM Implementation
State Diagram (Moore implementation)
Current State In Next State Out

S1 S0 L S1 + S0 + P
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 1
1 1 0 0 0 0
1 1 1 1 1 0

FSM Implementation
Logic implementation
P S+ L
Comb Comb
Flip-Flops
Logic Logic
For S1+: S For P:

L\S1S0 00 01 11 10 S0\S1 0 1
0 0 0 0 X 0 0 X
1 0 1 1 X 1 1 0
For S0+:
L\S1S0 00 01 11 10
0 0 0 0 X
1 1 1 1 X

FSM Implementation
Mealy implementation
• Since outputs are
determined by state and
inputs, Mealy FSMs may
need fewer states than
Moore FSM Pres In Next Out
implementations State State
S L S+ P
0 0 0 0
0 1 1 1
1 0 0 0
1 1 1 0
FSM Implementation
Moore/Mealy trade-off
• Remember that the difference is in the output:
– Moore outputs are based on state only
– Mealy outputs are based on state and input
– Therefore, Mealy outputs generally occur one cycle earlier than a
Moore:
Moore Mealy
• Compared to a Moore FSM, a Mealy FSM might...

– Be more difficult to conceptualize and design
– Have fewer states
HDL FSM Implementation
FSM Coding goals
• The FSM coding style should be easily
modified to change state encodings and FSM
styles
• The coding style should be compact
• The coding style should be easy to code and
understand
• The coding style should facilitate debugging
• The coding style should yield efficient
synthesis results
Binary Encoding
• Straight encoding of states
S0=“00” S1=“01” S2=“10” S3=“11”
• For n states, there are [log2(n)] flip-flops needed
• This gives the least numbers of flip-flops
• Good for “Area” constrained designs
• Number of possible illegal states = 2[log2(n)]–n
• Drawbacks:
– Multiple bits switch at the same time = Increased noise
and power
– Next state logic is multi-level = Increased power and
reduced speed

Gray-Code Encoding
• Encoding using a gray code where only one bits
switches at a time
S0=“00” S1=“01” S2=“11” S3=“10”
• For n states, there are [log2(n)]flip-flops needed
• This gives low power and noise due to only one bit
switching
• Good for “power/noise” constrained designs
• Number of possible illegal states = 2[log2(n)]–n
• Drawbacks:
– The next state logic is multi-level = Increased power and
reduced speed

One-Hot Encoding
• Encoding one flip-flop for each state
S0=“0001” S1=“0010” S2=“0100” S3=“1000”
• For n states, there are n flip-flops needed
• The combination logic is one level (i.e., a decoder)
• Good for speed
• Especially good for FPGA due to “Programmable Logic
Block”
• Number of possible illegal states = 2n–n
• Drawbacks:
– Takes more area
State Encoding Trade-Offs
• Typically trade off Speed, Area, and Power
One-Hot
Speed
Area Power
Binary Gray
The Fundamentals of Efficient Synthesizable
Finite State Machine.
Clifford E. Cummings
http://www.sunburst-
design.com/papers/CummingsICU2
002_FSMFundamentals.pdf

Two Always Block FSM Style (Good Style)
• One of the best Verilog parameter [1:0]
IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;
coding styles reg [1:0] state, next;
• Code the FSM design using
always @(posedge clk or negedge rst_n)
two always blocks, if (!rst_n) state <= IDLE;
– One for the sequential state else state <= next;
register
– One for the combinational always @(state or in1 or in2) begin
next-state and next = 2'bx; out1 = 1'b0;
case (state)
combinational output logic.
IDLE : if (in1) next = BBUSY;
else next = IDLE;
BBUSY: begin
out1 = 1'b1;
if (in2) next = BBUSY;
else next = BFREE;
end
//...
endcase
end
parameter [1:0]
1. The sequential always block reg [1:0] state, next;
is coded using nonblocking
assignments. if (!rst_n) state <= IDLE;
1
else state <= next;
2. The combinational always
block sensitivity list is always @(state or in1 or in2) begin 2
sensitive to changes on the next = 2'bx; out1 = 1'b0;
case (state)
state variable and all of the IDLE : if (in1) next = BBUSY;
inputs referenced in the else next = IDLE;
BBUSY: begin
combinational always block. out1 = 1'b1; 3
if (in2) next = BBUSY;
3. Assignments within the else next = BFREE;
combinational always block end
//...
are made using Verilog endcase
blocking assignments. end
parameter [1:0]
4. Default output reg [1:0] state, next;
assignments are made
before coding the case always @(posedge clk or negedge rst_n)
if (!rst_n) state <= IDLE;
statement (this else state <= next;
eliminates latches and
reduces the amount of always @(state or in1 or in2) begin
code required to code 5 next = 2'bx; out1 = 1'b0;
case (state)
4
the rest of the) IDLE : if (in1) next = BBUSY;
5. Placing a default next else
BBUSY: begin
next = IDLE;
state assignment on the out1 = 1'b1;
line immediately if (in2) next = BBUSY;
following the always else next = BFREE;
end
block sensitivity list is a //...
very efficient coding style endcase
end
One Always Block FSM Style (Avoid This Style!)
parameter [1:0]
• One of the most common IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;
reg [1:0] state;
FSM coding styles in use always @(posedge clk or negedge rst_n)
today if (!rst_n) begin
state <= IDLE;
– It is more verbose out1 <= 1'b0;
end
– It is more confusing else begin
state <= 2'bx; out1 <= 1'b0;
– It is more error prone case (state)
(comparable two always block IDLE : if (in1) begin
state <= BBUSY;
coding style) out1 <= 1'b1;
end
else state <= IDLE;
BBUSY: if (in2) begin
state <= BBUSY;
out1 <= 1'b1;
end
else state <= BFREE;
endcase
end
parameter [1:0]
1. A declaration is made reg [1:0] state; 1
for state. Not for next. if (!rst_n) begin
state <= IDLE;
2. The state assignments out1 <= 1'b0;
end
do not correspond to else begin
the current state of the state <= 2'bx; out1 <= 1'b0;
case (state)
case statement, but IDLE : if (in1) begin
state <= BBUSY; 2
the state that case out1 <= 1'b1;
statement is end
else state <= IDLE;
transitioning to. BBUSY: if (in2) begin
state <= BBUSY;
This is error prone (but out1 <= 1'b1;
it does work if coded end
correctly). endcase
end
parameter [1:0]
3. There is just one sequential reg [1:0] state;
always block, coded using always @(posedge clk or negedge rst_n) 3
nonblocking assignments. if (!rst_n) begin
state <= IDLE;
4. All outputs will be out1 <= 1'b0;
registered (unless the end
else begin
outputs are placed into a state <= 2'bx; out1 <= 1'b0;
separate combinational case (state)
always block or assigned IDLE : if (in1) begin
using continuous state <= BBUSY;
out1 <= 1'b1; 4
assignments). end
No asynchronous Mealy else state <= IDLE;
outputs can be generated BBUSY: if (in2) begin
from a single synchronous state <= BBUSY;
out1 <= 1'b1;
always block. end
endcase
end
Onehot FSM Coding Style (Good Style)
parameter [1:0] IDLE=0, BBUSY=1,BFREE=2;
reg [2:0] state, next; Efficient (small and
fast) Onehot state
if (!rst_n) state <= 3’b001; machines can be coded
else state <= next;
using an inverse case
always @(state or in1 or in2) begin
next = 3’b000; out1 = 1'b0; statement
case (1’b1) //ambit synthesis case full, parallel
state[IDLE] : if (in1) next[BBUSY] = 1’b1;
else next[IDLE] = 1’b1;
state[BBUSY]: begin
out1 = 1'b1;
if (in2) next[BBUSY] = 1’b1;
else next[BFREE] = 1’b1;
end
//...
endcase
end

parameter [1:0] IDLE=0, BBUSY=1, BFREE=2; 1
1. Index into the reg [2:0] state, next; 2
state register, not always @(posedge clk or negedge rst_n)
state encodings if (!rst_n) state <= 3’b001;

else state <= next;
3
2. Onehot requires always @(state or in1 or in2) begin

4 next = 3’b000; out1 = 1'b0;
larger declarations case (1’b1) //ambit synthesis case full, parallel
3. State reset, set to else
state[BBUSY]: begin
next[IDLE] = 1’b1;
1 the IDLE bit out1 = 1'b1;

4. Next state else
end
next[BFREE] = 1’b1;
assignment must //...

endcase
make all-0's end

parameter [1:0] IDLE=0, BBUSY=1, BFREE=2;
1. Inverse case reg [2:0] state, next;
statement usage always @(posedge clk or negedge rst_n)

if (!rst_n) state <= 3’b001;
2. Case branch check else state <= next;
state values always @(state or in1 or in2) begin

next = 3’b000; out1 = 1'b0;
3. Added “full” and 1 case (1’b1) //ambit synthesis case full, parallel
3
parallel case else next[IDLE] = 1’b1;

2 state[BBUSY]: begin
pragmas out1 = 1'b1;
4
4. Only the next else
end
next[BFREE] = 1’b1;
state bit //...

endcase
end

Full-Parallel Case
From:
Verilog: Frequently Asked
Questions: Language,
Applications and Extensions
Shivakumar S. Chonnad,
Needamangalam B.
Balachander
ISBN: 1441919864

Registered FSM Outputs (Good Style) output reg out1;
• Registering the outputs of an parameter [1:0] IDLE=2'b00, BBUSY=2'b01,BFREE=2'b10;
reg [1:0] state, next;
FSM design always @(posedge clk or negedge rst_n)
if (!rst_n) state <= IDLE;
– Insures that the outputs are else state <= next;
glitch-free and frequently always @(state or in1 or in2) begin
next = 2'bx;
– Improves synthesis results by case (state)
standardizing the output and IDLE : if (in1) next = BBUSY;
input delay constraints of else next = IDLE;
BBUSY: if (in2) next = BBUSY;
synthesized modules else next = BFREE;
endcase
end
if (!rst_n) out1 <= 1'b0;
else begin
out1 <= 1'b0;
case (next)
IDLE, BFREE: ; // default outputs
BBUSY, BWAIT: out1 <= 1'b1;
endcase
end
REFERENCES

References
• Verilog HDL – Samir Palnitkar
• The Fundamentals of Efficient Synthesizable
Finite State Machine Design using NC-Verilog
and Build Gates – Clifford E. Cummings
• Verilog: Frequently Asked Questions, Springer
Science

References
• Verilog: Frequently Asked Questions: Language,
Applications and Extensions - Shivakumar S.
Chonnad, Needamangalam B. Balachander
• ECE 369 - Fundamentals of Computer
Architecture.
http://www2.engr.arizona.edu/~ece372_spr04/e
ce369_spr05
• Madhavan, R., Quick Reference for Verilog HDL
http://www.stanford.edu/class/ee183/handouts.
shtml

Verilog

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Verilog

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Introduction to Verilog HDL

Synopsys University Courseware

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– Use of assignment statements,

loops, if, else kind of statements

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– If MSB is 1 number is extend to fill MSBs with 0/1,

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assign Obus = ObusReg;

always @(posedge Clk)

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module <module name> #(<param list>) (<port list>);

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reg o net net reg o net net

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TOP module TOP (…port_list…);

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Synopsys University Courseware

• If an operant is not zero is treat as logical 1

== c == a ; /* is c equal to a returns 1-bit true/false

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/* AND all bits of a

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/* add a, b, ci assign the

module AND (A, B, C);

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// Controlled by positive edge of clk

// Controlled by negative edge of clk or rst

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module FFD (input Clk, R, D, module LD (G, D, Q);

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• Explicit priority if (!WRITE)

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always @ (a,b,sel) always @ (DATA, GATE) always @ (DATA, GATE)

MUX LATCH COMB LOGIC

// General purpose loop

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module top( input [0:3] in1,

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data_reversed = {data_8[0], data_8[1], data_8[2], data_8[3],

input [127:0] data;

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How we can assign to each bit a 1'b1?

assign data= {WIDTH{1'b1}};

assign data= (1 << WIDTH) – 1;

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module test (); module test (); module test ();

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Chronologic VCS simulator copyright 1991-2008

clk | in1| in2 | out1 |

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Useful format specifiers:

reg [31:0] rand1, rand2, rand3;