F If o Depth Calculation Made Easy 2
F If o Depth Calculation Made Easy 2
F If o Depth Calculation Made Easy 2
Volume 7: Display
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No Derivative Works. You may not alter, transform, or build upon this work.
Table of Contents
Display Audio Codec Verbs ........................................................................................................... 1
Programming ............................................................................................................................................................. 1
Node ID 00h Root Node Verbs ...................................................................................................................... 1
F00h - Get Parameters .................................................................................................................................. 1
Parameter 00h: VID - Vendor ID ............................................................................................................... 1
Parameter 02h: RID - Revision ID ............................................................................................................. 1
Parameter 04h: PARAM_SNC - Subordinate Node Count .............................................................. 2
North Display Engine Registers .................................................................................................... 2
MIPI ................................................................................................................................................................................ 2
MIPI Configurations ............................................................................................................................................ 2
MIPI DSI Registers ............................................................................................................................................... 2
DSC ..............................................................................................................................................................................10
Broxton Display Connections ............................................................................................................................13
Display Pipes .......................................................................................................................................................14
Display Transcoders ..........................................................................................................................................15
Audio ......................................................................................................................................................................15
DDIs.........................................................................................................................................................................15
Pipe to Transcoder to DDI Mappings ........................................................................................................16
Mode Set ...................................................................................................................................................................17
Broxton Sequences to Initialize Display ....................................................................................................17
Initialize Sequence ........................................................................................................................................17
Un-initialize Sequence ................................................................................................................................18
Sequences for MIPI ...........................................................................................................................................18
Enable Sequence ...........................................................................................................................................18
Interrupt Usage ..............................................................................................................................................20
Command Sequence for DBI Writes/Reads........................................................................................21
Command Sequence for Generic/Manufacturer Writes/Reads ..................................................21
DBI Frame Sequence....................................................................................................................................21
Disable Sequence..........................................................................................................................................21
Enter Low Power Mode ..............................................................................................................................23
Exit Low Power Mode ..................................................................................................................................23
Overall Flow.....................................................................................................................................................23
Sequences for DisplayPort .............................................................................................................................24
Enable Sequence ...........................................................................................................................................24
Notes..................................................................................................................................................................25
Enabling DisplayPort Sync Mode ...........................................................................................................25
Disable Sequence..........................................................................................................................................26
Disabling DisplayPort Sync Mode ..........................................................................................................27
Sequences for HDMI and DVI .......................................................................................................................27
Enable Sequence ...........................................................................................................................................27
Notes..................................................................................................................................................................28
Disable Sequence..........................................................................................................................................28
Sequences for Display C5 and C6 ...............................................................................................................29
Sequence to Allow DC5 or DC6 ...................................................................................................................30
Sequence to Disallow DC5 and DC6 ..........................................................................................................30
DMC Firmware Package ..................................................................................................................................31
Major version 1 ..............................................................................................................................................31
Package Layout ..............................................................................................................................................31
CSS Header ......................................................................................................................................................32
Package Header .............................................................................................................................................32
DMC firmware binary ..................................................................................................................................33
Sequences for Display C9 ...............................................................................................................................34
Sequence to Allow DC9 ..................................................................................................................................34
Sequence to Disallow DC9 .............................................................................................................................35
Hotplug Detection During DC9 ...................................................................................................................35
Gen9 Display Resolution Support ...............................................................................................................36
Maximum Pipe Pixel Rate ...............................................................................................................................36
Maximum Port Link Rate ................................................................................................................................37
Maximum Memory Read Bandwidth .........................................................................................................37
Maximum Watermark ......................................................................................................................................37
Display Resolution Capabilities ....................................................................................................................38
Examples ...............................................................................................................................................................39
Clocks .....................................................................................................................................................................40
Broxton Clocks ...............................................................................................................................................40
Registers ...........................................................................................................................................................40
Overview of Display Clock Paths.............................................................................................................41
Display Engine Clock Reference ..................................................................................................................42
Display Engine PLLs ..........................................................................................................................................42
DDI Clocks ............................................................................................................................................................43
Transcoder Clocks .............................................................................................................................................43
CD Clock ................................................................................................................................................................44
Recommended CD Clock Frequency Selection .....................................................................................45
Port PLL Formula for Divider Values ..........................................................................................................45
Port PLL Algorithm to Find Divider Values ..............................................................................................46
Port PLL Example Divider Values .................................................................................................................47
PORT_PLL_6, PORT_PLL_8, and PORT_PLL_10 Values ..........................................................................47
Lane Stagger Values .........................................................................................................................................48
Port PLL Enabling Sequence..........................................................................................................................48
Port PLL Disabling Sequence ........................................................................................................................49
MIPI DSI PLL.........................................................................................................................................................49
MIPI DSI PLL Enabling Sequence.................................................................................................................50
MIPI DSI PLL Disabling Sequence ...............................................................................................................50
MIPI Additional Clock Dividers .....................................................................................................................51
DE PLL ....................................................................................................................................................................52
DE PLL Sequences .............................................................................................................................................52
Broxton Sequences for Changing CD Clock Frequency .....................................................................53
Sequence for Changing CD Clock Frequency ....................................................................................53
Resets .....................................................................................................................................................................55
DGunit Registers (DGR) ...................................................................................................................................56
Fuses and Straps ................................................................................................................................................58
Hot Plug Detection ...........................................................................................................................................58
Broxton Hot Plug Detection ..........................................................................................................................58
Broxton 0 and Broxton 1 Board Mapping for A Stepping .................................................................59
Broxton 0 and Broxton 1 Board Mapping for E Stepping and Later .............................................59
Broxton P Board Mapping .............................................................................................................................59
Backlight ................................................................................................................................................................59
Backlight Enabling Sequence ...................................................................................................................60
Address Name
6B000h MIPIA_DEVICE_READY_REG
6B004h MIPIA_INTR_STAT_REG
6B008h MIPIA_INTR_EN_REG
Address Name
6B00Ch MIPIA_DSI_FUNC_PRG_REG
6B010h MIPIA_HS_TX_TIMEOUT_REG
6B014h MIPIA_LP_RX_TIMEOUT_REG
6B018h MIPIA_TURN_AROUND_TIMEOUT_REG
6B01Ch MIPIA_DEVICE_RESET_TIMER
6B020h MIPIA_DPI_RESOLUTION_REG
6B024h MIPIA_DBI_FIFO_THRTL_REG
6B028h MIPIA_HORIZ_SYNC_PADDING_COUNT
6B02Ch MIPIA_HORIZ_BACK_PORCH_COUNT
6B030h MIPIA_HORIZ_FRONT_PORCH_COUNT
6B034h MIPIA_HORIZ_ACTIVE_AREA_COUNT
6B038h MIPIA_VERT_SYNC_PADDING_COUNT
6B03Ch MIPIA_VERT_BACK_PORCH_COUNT
6B040h MIPIA_VERT_FRONT_PORCH_COUNT
6B044h MIPIA_HIGH_LOW_SWITCH_COUNT
6B048h MIPIA_DPI_CTRL_REG
6B04Ch MIPIA_DPI_DATA_REGISTER
6B050h MIPIA_INIT_COUNT_REGISTER
6B054h MIPIA_MAX_RETURN_PKT_SIZE_REGISTER
6B058h MIPIA_VIDEO_MODE_FORMAT_REGISTER
6B05Ch MIPIA_EOT_DISABLE_REGISTER
6B060h MIPIA_LP_BYTECLK_REGISTER
Address Name
6B064h MIPIA_LP_GEN_DATA_REGISTER
6B068h MIPIA_HS_GEN_DATA_REGISTER
6B06Ch MIPIA_LP_GEN_CTRL_REGISTER
6B070h MIPIA_HS_GEN_CTRL_REGISTER
6B074h MIPIA_GEN_FIFO_STAT_REGISTER
6B078h MIPIA_HS_LS_DBI_ENABLE_REG
6B07Ch MIPI_HS_READ_TRANSFER_COUNT
6B080h MIPIA_DPHY_PARAM_REG
6B084h MIPIA_DBI_BW_CTRL_REG
6B088h MIPIA_CLK_LANE_SWITCHING_TIME_CNT
6B08Ch MIPIA_STOP_STATE_STALL
6B090h MIPIA_INTR_STAT_REG_1
6B094h MIPIA_INTR_EN_REG_1
6B098h MIPIA_CLK_LANE_TIMING
6B09Ch MIPIA_PLL_LOCK_COUNT
6B0A0h MIPIA_DATA_LANE_POLARITY
6B0A4h MIPIA_TLPX_TIME_COUNT
6B0C0h MIPIA_PORT_CTRL
6B0C4h MIPIA_STATUS
6B0C8h MIPIA_AUTOPWG
6B0CCh MIPIA_WR_DATA 0
6B0D0h MIPIA_WR_DATA 1
Address Name
6B0D4h MIPIA_WR_DATA 2
6B0D8h MIPIA_WR_DATA 3
6B0DCh MIPIA_WR_DATA 4
6B0E0h MIPIA_WR_DATA 5
6B0E4h MIPIA_WR_DATA 6
6B0E8h MIPIA_WR_DATA 7
6B0ECh MIPIA_WR_COMMAND
6B0F0h MIPIA_WR_DATA_CTRL
6B0F4h MIPIA_EN_DLY_CNTR
6B0F8h MIPIA_TRANS_HACTIVE
6B0FCh MIPIA_TRANS_VACTIVE
6B100h MIPIA_TRANS_VTOTAL
6B104h MIPIA_CTRL
6B108h MIPIA_TE_CTR
6B118h MIPIA_RD_DATA_RETURN 0
6B11Ch MIPIA_RD_DATA_RETURN 1
6B120h MIPIA_RD_DATA_RETURN 2
6B124h MIPIA_RD_DATA_RETURN 3
6B128h MIPIA_RD_DATA_RETURN 4
6B12Ch MIPIA_RD_DATA_RETURN 5
6B130h MIPIA_RD_DATA_RETURN 6
6B134h MIPIA_RD_DATA_RETURN 7
Address Name
6B138h MIPIA_RD_DATA_VALID
6B13Ch MIPIA_CRC_CTL
6B140h MIPIA_CRC_RESULT
6B800h MIPIC_DEVICE_READY_REG
6B804h MIPIC_INTR_STAT_REG
6B808h MIPIC_INTR_EN_REG
6B80Ch MIPIC_DSI_FUNC_PRG_REG
6B810h MIPIC_HS_TX_TIMEOUT_REG
6B814h MIPIC_LP_RX_TIMEOUT_REG
6B818h MIPIC_TURN_AROUND_TIMEOUT_REG
6B81Ch MIPIC_DEVICE_RESET_TIMER
6B820h MIPIC_DPI_RESOLUTION_REG
6B824h MIPIC_DBI_FIFO_THRTL_REG
6B828h MIPIC_HORIZ_SYNC_PADDING_COUNT
6B82Ch MIPIC_HORIZ_BACK_PORCH_COUNT
6B830h MIPIC_HORIZ_FRONT_PORCH_COUNT
6B834h MIPIC_HORIZ_ACTIVE_AREA_COUNT
6B838h MIPIC_VERT_SYNC_PADDING_COUNT
6B83Ch MIPIC_VERT_BACK_PORCH_COUNT
6B840h MIPIC_VERT_FRONT_PORCH_COUNT
6B844h MIPIC_HIGH_LOW_SWITCH_COUNT
Address Name
6B848h MIPIC_DPI_CTRL_REG
6B84Ch MIPIC_DPI_DATA_REGISTER
6B850h MIPIC_INIT_COUNT_REGISTER
6B854h MIPIC_MAX_RETURN_PKT_SIZE_REGISTER
6B858h MIPIC_VIDEO_MODE_FORMAT_REGISTER
6B85Ch MIPIC_EOT_DISABLE_REGISTER
6B860h MIPIC_LP_BYTECLK_REGISTER
6B864h MIPIC_LP_GEN_DATA_REGISTER
6B868h MIPIC_HS_GEN_DATA_REGISTER
6B86Ch MIPIC_LP_GEN_CTRL_REGISTER
6B870h MIPIC_HS_GEN_CTRL_REGISTER
6B874h MIPIC_GEN_FIFO_STAT_REGISTER
6B878h MIPIC_HS_LS_DBI_ENABLE_REG
6B87Ch MIPI_HS_READ_TRANSFER_COUNT
6B880h MIPIC_DPHY_PARAM_REG
6B884h MIPIC_DBI_BW_CTRL_REG
6B888h MIPIC_CLK_LANE_SWITCHING_TIME_CNT
6B88Ch MIPIC_STOP_STATE_STALL
6B890h MIPIC_INTR_STAT_REG_1
6B894h MIPIC_INTR_EN_REG_1
6B898h MIPIC_CLK_LANE_TIMING
6B89Ch MIPIC_PLL_LOCK_COUNT
Address Name
6B8A0h MIPIC_DATA_LANE_POLARITY
6B8A4h MIPIC_TLPX_TIME_COUNT
6B8C0h MIPIC_PORT_CTRL
6B8C4h MIPIC_STATUS
6B8C8h MIPIC_AUTOPWG
6B8CCh MIPIC_WR_DATA 0
6B8D0h MIPIC_WR_DATA 1
6B8D4h MIPIC_WR_DATA 2
6B8D8h MIPIC_WR_DATA 3
6B8DCh MIPIC_WR_DATA 4
6B8E0h MIPIC_WR_DATA 5
6B8E4h MIPIC_WR_DATA 6
6B8E8h MIPIC_WR_DATA 7
6B8ECh MIPIC_WR_COMMAND
6B8F0h MIPIC_WR_DATA_CTRL
6B8F4h MIPIC_EN_DLY_CNTR
6B8F8h MIPIC_TRANS_HACTIVE
6B8FCh MIPIC_TRANS_VACTIVE
6B900h MIPIC_TRANS_VTOTAL
6B904h MIPIC_CTRL
6B908h MIPIC_TE_CTR
6B918h MIPIC_RD_DATA_RETURN 0
Address Name
6B91Ch MIPIC_RD_DATA_RETURN 1
6B920h MIPIC_RD_DATA_RETURN 2
6B924h MIPIC_RD_DATA_RETURN 3
6B928h MIPIC_RD_DATA_RETURN 4
6B92Ch MIPIC_RD_DATA_RETURN 5
6B930h MIPIC_RD_DATA_RETURN 6
6B934h MIPIC_RD_DATA_RETURN 7
6B938h MIPIC_RD_DATA_VALID
6B93Ch MIPIC_CRC_CTL
6B940h MIPIC_CRC_RESULT
DSC
Note
These registers must all be written only as full 32 bit Dwords. Byte or word writes are not supported.
Address Name
6B200h DSCA_PICTURE_PARAMETER_SET_0
6B204h DSCA_PICTURE_PARAMETER_SET_1
6B208h DSCA_PICTURE_PARAMETER_SET_2
6B20Ch DSCA_PICTURE_PARAMETER_SET_3
6B210h DSCA_PICTURE_PARAMETER_SET_4
6B214h DSCA_PICTURE_PARAMETER_SET_5
6B218h DSCA_PICTURE_PARAMETER_SET_6
6B21Ch DSCA_PICTURE_PARAMETER_SET_7
6B220h DSCA_PICTURE_PARAMETER_SET_8
6B224h DSCA_PICTURE_PARAMETER_SET_9
6B228h DSCA_PICTURE_PARAMETER_SET_10
6B22Ch DSCA_PICTURE_PARAMETER_SET_11
6B230h DSCA_RC_BUF_THRESH_0
6B238h DSCA_RC_BUF_THRESH_1
6B240h DSCA_RC_RANGE_PARAMETERS_0
6B248h DSCA_RC_RANGE_PARAMETERS_1
6B250h DSCA_RC_RANGE_PARAMETERS_2
6B258h DSCA_RC_RANGE_PARAMETERS_3
6B260h DSCA_PICTURE_PARAMETER_SET_12
Address Name
6B264h DSCA_PICTURE_PARAMETER_SET_13
6B268h DSCA_PICTURE_PARAMETER_SET_14
6B26Ch DSCA_PICTURE_PARAMETER_SET_15
6B270h DSCA_PICTURE_PARAMETER_SET_16
6B280h Reserved
6B284h DSC_CRC_CTL_A
6B288h DSC_CRC_RES_A
6B28Ch Reserved
6B290h Reserved
6B294h Reserved
6B298h Reserved
6B29Ch Reserved
6B2A0h Reserved
6B2A4h Reserved
6B2A8h Reserved
6BA00h DSCC_PICTURE_PARAMETER_SET_0
6BA04h DSCC_PICTURE_PARAMETER_SET_1
6BA08h DSCC_PICTURE_PARAMETER_SET_2
6BA0Ch DSCC_PICTURE_PARAMETER_SET_3
6BA10h DSCC_PICTURE_PARAMETER_SET_4
6BA14h DSCC_PICTURE_PARAMETER_SET_5
6BA18h DSCC_PICTURE_PARAMETER_SET_6
6BA1Ch DSCC_PICTURE_PARAMETER_SET_7
6BA20h DSCC_PICTURE_PARAMETER_SET_8
6BA24h DSCC_PICTURE_PARAMETER_SET_9
Address Name
6BA28h DSCC_PICTURE_PARAMETER_SET_10
6BA2Ch DSCC_PICTURE_PARAMETER_SET_11
6BA30h DSCC_RC_BUF_THRESH_0
6BA38h DSCC_RC_BUF_THRESH_1
6BA40h DSCC_RC_RANGE_PARAMETERS_0
6BA48h DSCC_RC_RANGE_PARAMETERS_1
6BA50h DSCC_RC_RANGE_PARAMETERS_2
6BA58h DSCC_RC_RANGE_PARAMETERS_3
6BA60h DSCC_PICTURE_PARAMETER_SET_12
6BA64h DSCC_PICTURE_PARAMETER_SET_13
6BA68h DSCC_PICTURE_PARAMETER_SET_14
6BA6Ch DSCC_PICTURE_PARAMETER_SET_15
6BA70h DSCC_PICTURE_PARAMETER_SET_16
6BA80h Reserved
6BA84h DSC_CRC_CTL_C
6BA88h DSC_CRC_RES_C
6BA8Ch Reserved
6BA90h Reserved
6BA94h Reserved
6BA98h Reserved
6BA9Ch Reserved
6BAA0h Reserved
6BAA4h Reserved
6BAA8h Reserved
The front end of the display contains the pipes. There are three instances which are referred to as Pipe A,
Pipe B, and Pipe C.
The pipes connect to the transcoders. There are seven instances which are referred to as Transcoder A,
Transcoder B, Transcoder C, Transcoder EDP, Transcoder WD0, Transcoder MIPIA, and Transcoder MIPIC.
The transcoders connect to the DDIs. There are three instances which are referred to as DDI A, DDI B, and
DDI C.
Display Pipes
The display pipes contain the planes, blending, color correction, DPST, scaling, dithering, and clipping.
Pipe A and Pipe B have four planes and a cursor. Each plane can be used as a sprite, primary, or overlay.
Pipe C has three planes and a cursor. Each plane can be used as a sprite, primary, or overlay.
The background color that is seen under the bottom most plane is programmable.
The plane blending follows a fixed Z-order. Plane 1 is the bottom most plane and higher numbered
planes stack on top of it.
The cursor and top most plane are mutually exclusive and cannot be both enabled at the same time.
Pipe A and Pipe B each have two pipe scalers. Pipe C has one pipe scaler.
Each pipe scaler can be assigned to scale an individual plane or scale the blended output.
Display Transcoders
The display transcoders contain the timing generators and port encoders.
Transcoders A, B, and C also contain Audio/Video mixers, Video Data Island Packet mixers, and Panel Self
Refresh controllers.
Transcoder EDP also contains a Video Data Island Packet mixer and Panel Self Refresh controllers. It does
not support HDMI, DVI, or Audio.
Transcoder WD0 only supports display capture and write back to memory.
Transcoders MIPIA and MIPIC only supports MIPI DSI.
Audio
The Azalia interface provides data to the audio codec.
The audio codec connects to the Audio/Video mixers in the transcoders.
The audio codec connects to memory write back for wireless audio.
DDIs
The DDIs contain the DisplayPort transport control and other port logic to interface to the DDI physical
pins.
DDI A, DDI B, and DDI C support lane reversal where the internal lane to package lane mapping is
swapped.
DDI A does not support DisplayPort multistream.
Transcoders MIPIA and MIPIC does not connect to any DDI. Transcoders MIPIA and MIPIC output only
goes to MIPI.
DDI A can connect only to Transcoder EDP. DDI A does not support DisplayPort multistream.
DDI B can connect to Transcoder A, B, or C, individually or simultaneously if DisplayPort multistream is
used.
DDI C can connect to Transcoder A, B, or C, individually or simultaneously if DisplayPort multistream is
used.
Mode Set
Broxton Sequences to Initialize Display
These sequences are used to initialize the display engine before any display engine functions can be
enabled.
Most display engine functions will not operate while display is not initialized. Only basic PCI, I/O, and
MMIO register read/write operations are supported when display is not initialized.
Initialize Sequence
1. Disable PCH Reset Handshake
a. Clear NDE_RSTWRN_OPT RST PCH Handshake En to 0b.
2. Enable Power Well 1 (PG1)
a. Poll for FUSE_STATUS Fuse PG0 Distribution Status == 1b.
Timeout and fail after 5 μs.
b. Set PWR_WELL_CTL Power Well 1 Request to 1b.
c. Poll for PWR_WELL_CTL Power Well 1 State == 1b.
Timeout and fail after 10 μs.
d. Poll for FUSE_STATUS Fuse PG1 Distribution Status == 1b.
Timeout and fail after 5 μs.
3. Enable CD clock following the Sequences for Changing CD Clock Frequency
4. Enable DBUF
a. Set DBUF_CTL DBUF Power Request to 1b.
b. Poll for DBUF_CTL DBUF Power State == 1b.
Timeout and fail after 10 μs.
5. If DDIA/EDP, DDIB, or DDIC will be used, follow DDI Buffer DDI PHY Initialization Sequence to
initialize DDI PHY
6. If MIPI will be used, follow Mode Set Sequences for MIPI to initialize MIPI PHY
7.
Workaround
If MIPI will not be used, power down DSI regulator to save power.
a. Set P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR MIPIO_RST_CTRL to 0x1 to bring MIPI IO out of
reset
b. Write 0x160020 = 0x00000001 (DSI_CFG: STAP_SELECT 0x1)
c. Write 0x160054 = 0x00000001 (DSI_TXCNTRL: HS_IO_CONTROL_SELECT 0x1)
d. Set P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR MIPIO_RST_CTRL to 0x0 to put MIPI IO back into
reset
Un-initialize Sequence
1. Disable all display engine functions using the full mode set disable sequence on all pipes,
transcoders, ports, planes, and power well 2 (PG2).
2. Clear both PHY_CTL_FAMILY_EDP and PHY_CTL_FAMILY_DDI Common Reset to 0b (Disable)
3. Clear P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR to 0x0
4. Disable DBUF
a. Clear DBUF_CTL DBUF Power Request to 0b.
b. Poll for DBUF_CTL DBUF Power State == 0b.
Timeout and fail after 10 μs.
5. Disable CD clock following the Sequences for Changing CD Clock Frequency
6. Disable Power Well 1 (PG1)
a. Clear PWR_WELL_CTL Power Well 1 Request to 0b.
b. Wait for 10us. Do not poll for the power well to disable. Other clients may be keeping it
enabled.
(BXT:*:A) In DBI mode there must always be at least one plane enabled on the pipe attached to MIPI.
Enable Sequence
Display must already be initialized.
d. If currently in Low Power mode, follow the Exit Low Power Mode sequence
e. Enable transparent latch - Set MIPI_PORT_CTRL LPOUTPUT_HOLD to 0x1
5. If needed - Send Manufacturer DCS Commands to Initialize DSI Controller
a. Set MIPI_DEVICE_READY_REG DEVICE_READY to 0x1
b. Follow Command Sequence for Generic/Manufacturer Writes/Reads
6. Enable Planes and Pipe Scaler
a. Configure and enable planes (VGA or hires). This can be done later if desired.
b. If VGA, clear VGA I/O register SR01 bit 5
c. Enable pipe scaler if needed (must be enabled for VGA)
d. Configure pipe settings
7. Prepare Port
a. Clear MIPI_DEVICE_READY_REG DEVICE_READY to 0x0
b. Configure MIPIA_DPHY_PARAM_REG and MIPIC_DPHY_PARAM_REG (both must be
configured regardless of single or dual link mode in order to allow ULPS to be entered later)
c. Configure MIPI_TRANS_HACTIVE and MIPI_TRANS_VACTIVE
d. If DPI, configure MIPI_TRANS_VTOTAL, MIPI_DPI_RESOLUTION_REG, back porch, front porch,
and sync padding registers
e. Configure other timing parameters, timeouts, switch count, byteclk
Interrupt Usage
MIPI interrupt events are enabled by setting bits in MIPI_INTR_EN_REG and MIPI_INTR_EN_REG_1. When
an enabled interrupt event occurs, it sets a sticky bit in MIPI_INTR_STAT_REG or MIPI_INTR_STAT_REG_1.
The sticky bits are ORd together to create the consolidated interrupts for MIPI A and MIPI C in the DE
Port Interrupt, which propagates to the internal graphics interrupt. To detect a MIPI event, software can
either poll on the MIPI status bit or use the internal graphics interrupt. The sticky bit should be cleared by
writing a 1 to it.
Disable Sequence
1. Disable Backlight
a. Disable panel backlight
Workaround
Overall Flow
1. Initialization Sequence (ULPS exited by default, latch out disabled)
2. Enable PLL with dividers setup for any future use for both MIPI ports (can't change dividers after
PLL is enabled)
3. Exit Low Power Mode if not already exited from boot
4. Enable and disable MIPI ports as needed (enable sequence and disable sequence, while keeping
PLL enabled and not entering Low Power Mode)
5. If all MIPI ports disabled and low power requested, Enter Low Power Mode and Disable PLL
6. If MIPI needs to be enabled again, go to step 2. Else, display can be un-initialized or configured for
DC9.
Enable Sequence
Display must already be initialized
DDIA Lane Capability Control must be configured prior to enabling any ports or port clocks
a. If DisplayPort multi-stream - use AUX to program receiver VC Payload ID table to add stream
b. Configure Transcoder Clock Select to direct the Port clock to the Transcoder
c. Configure and enable planes (VGA or hires). This can be done later if desired.
d. If VGA - Clear VGA I/O register SR01 bit 5
e. Enable panel fitter if needed (must be enabled for VGA)
f. Configure transcoder timings, M/N/TU/VC payload size, and other pipe and transcoder
settings
g. Configure and enable TRANS_DDI_FUNC_CTL
h. If DisplayPort multistream - Enable pipe VC payload allocation in TRANS_DDI_FUNC_CTL
i. If DisplayPort multistream - Wait for ACT sent status in DP_TP_STATUS and receiver DPCD
(timeout after >410us)
j. Configure and enable TRANS_CONF
k. If panel power sequencing is required - Enable panel backlight
SRD and/or Audio can be enabled after everything is complete. Follow the audio enable sequence in the
audio registers section.
Notes
Changing voltage swing during link training:
Change the swing setting following the DDI Buffer section. The port does not need to be disabled.
If the mode set fails, follow the disable sequence to disable everything that had been enabled up to the
failing point.
1. Follow the enable sequence for the DisplayPort slave, but skip the step that sets DP_TP_CTL link
training to Normal (stay in Idle Pattern).
Set TRANS_DDI_FUNC_CTL Port Sync Mode Master Select and Port Sync Mode Enable when
configuring and enabling TRANS_DDI_FUNC_CTL.
2. Follow the enable sequence for the DisplayPort master, but skip the step that sets DP_TP_CTL link
training to Normal (stay in Idle Pattern).
3. Set DisplayPort slave DP_TP_CTL link training to Normal.
4. Wait 200 uS.
5. Set DisplayPort master DP_TP_CTL link training to Normal.
Software may need to use DOUBLE_BUFFER_CTL to ensure updates to plane and pipe registers will take
place in the same frame.
For example: If pipe A and pipe B are synchronized together and software needs the surface addresses
for two planes to update at the same time, software should use DOUBLE_BUFFER_CTL when writing the
surface address registers for both planes, otherwise there is a possibility that the updates could be split
across a vertical blank such that one plane would update on the current vertical blank and the other
plane would update on the next vertical blank.
Disable Sequence
SRD and Audio must be disabled first. Follow the audio disable sequence in the audio registers section.
Enable Sequence
Display must already be initialized
Audio can be enabled after everything is complete. Follow the audio enable sequence in the audio
registers section.
Notes
If the mode set fails, follow the disable sequence to disable everything that had been enabled up to the
failing point.
Disable Sequence
Audio must be disabled first. Follow the audio disable sequence in the audio registers section.
a. If no required resource is in the power well - Disable PWR_WELL_CTL Power Well 2 Request
Atom CPUs support DC5 and not DC6. They also support DC9, which has a separate sequence.
The context save and restore program is reset on DC9, cold boot, warm reset, PCI function level reset, and
hibernate/suspend.
The MIPI DSI related registers are not saved and restored by hardware.
Programming Note
Context: Display C5 and C6
Do not switch between "Enable up to DC5" and "Enable up to DC6" without moving to "Disable" and reloading the
CSR program in between.
Disable DC5/DC6 during mode set and re-enable after the mode set programming is completed.
MMIO accesses have more latency when DC5/DC6 is enabled. For optimal performance, disable DC5/DC6 when
programming a set of registers and re-enable them after the programming is completed.
Programming Note
Context: Display C5 and C6
For atom CPUs, in step 3 also set 0x45520 bit 0 to 1b. It does not need to be cleared at any time.
Major version 1
Package Layout
CSS Header
typedef struct _CssHeader {
uint32_t moduleType; // 0x09 for DMC
uint32_t headerLen; // CSS header length in dwords
uint32_t headerVer; // 0x10000
uint32_t moduleID; // Not used
uint32_t moduleVendor; // Not used
uint32_t date; // YYYYMMDD(YYYY « 16 + MM « 8
+ DD)
uint32_t size; // Total dmc fw binary size in
dwords - (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4
uint32_t keySize; // Not used
uint32_t modulusSize; // Not used
uint32_t exponentSize; // Not used
uint32_t reserved1[12]; // Not used
uint32_t version; // Major Minor
uint32_t reserved2[8]; // Not used
uint32_t uKernelHeaderInfo; // Not used
} CssHeader;
Package Header
Package header contains the firmware/stepping mapping table and the corresponding firmware offsets
to the individual binaries, within the package. Mapping table will list the exceptions first, followed by the
default entries. An Offset value of "0xFFFFFFFF" in the mapping table indicates that there is no firmware
available/supported for that stepping. The offsets to the individual binary are DWord aligned. The first
individual binary starts at an offset value of "0x00000000" after the CSS Header and the Package Header.
Stepping/Version mapping example
Stepping FW Version
A1 1.1
B* 1.6
** 2.3
typedef struct _PackageHeader {
uint8_t headerLen; // DMC package header length
in dwords
uint8_t headerVer; // 0x01
for i = 1 to <mmioCount>
Perform MMIO write to address <mmioaddr[i]> with data <mmiodata[i]>
typedef struct _DMCHeader {
uint32_t reserved; // 0x40403E3E
uint8_t headerLen; // DMC binary header length in bytes
uint8_t headerVer; // 0x01
uint16_t dmccVer; // Reserved
uint32_t project; // Major, Minor
1. Display driver follows the Sequence to Allow DC9 with display engine hotplug detection logic
enabled and the hotplug and DDI DC9 HPD interrupts enabled and unmasked.
2. When display is powered down, PMC wakes the system if it detects the selected edge type on the
hotplug line.
3. The power controller unit forwards a DDI DC9 HPD interrupt to the display engine PCU Interrupt.
4. If the DDI DC9 HPD interrupt is enabled and unmasked, it triggers a graphics device interrupt. If it
is disabled or masked, no interrupt happens and the system can re-enter DC9.
5. Display driver services the interrupt and determines it it was a connect, disconnect, or HPD_IRQ.
6. The display driver and operating system interpret the result and decide whether to disallow DC9
and enable a display output or do nothing.
Pipe maximum pixel rate = CDCLK frequency * Pipe Ratio // See the display clocks section for the
supported CDCLK frequencies.
Do not use more than 60% of raw system memory bandwidth for display.
Maximum Watermark
The display resolution must not exceed the level 0 maximum watermark value. See the volume on
Watermark Programming.
Attribute CD 624 MHz CD 576 MHz CD 384 MHz CD 288 MHz CD 144 MHz
eDP/DP x4 single 4096x2304 60Hz 4096x2160 60Hz 2880x1620 60Hz 4096x2160 30Hz 1920x1080 60Hz
stream 24Bpp4 30Bpp4 30Bpp2 30Bpp2 30Bpp1
2560x1600 60Hz
30Bpp1
HDMI Same as entry to Same as entry to 4Kx2K 24-30Hz 1080p 59.94- 720p 59.94-60Hz
the right the right 24Bpp2 60Hz 24Bpp1 24Bpp1
DVI Same as entry to Same as entry to Same as entry to 1920x1200 60Hz 1920x1080 60Hz
the right the right the right 24Bpp1 24Bpp1
MIPI DSI single Same as entry to Same as entry to Same as entry to 1920x1200 60Hz 1920x1080 60Hz
link the right the right the right 24Bpp1 24Bpp1
1:1 compression
MIPI DSI single Same as entry to Same as entry to 2880x1620 60Hz 2560x1600 60Hz Same as entry
link the right the right 24Bpp2 24Bpp1 above
2:1 compression
MIPI DSI single Same as entry to 3200x2000 60Hz Same as entry Same as entry Same as entry
link the right 24Bpp3 above above above
3:1 compression
MIPI DSI dual link Same as entry to Same as entry to 2880x1620 60Hz 2560x1600 60Hz 1920x1080 60Hz
1:1 compression the right the right 24Bpp2 24Bpp1 24Bpp1
MIPI DSI dual link 4096x2304 60Hz 4096x2160 60Hz Same as entry Same as entry Same as entry
2:1 compression 24Bpp4 24Bpp4 above above above
MIPI DSI dual link Same as entry Same as entry Same as entry Same as entry Same as entry
3:1 compression above above above above above
Each entry is showing the highest common resolutions at that CD clock frequency step. Lower resolutions
are also supported. Higher, less common, resolutions can also work, but need to be calculated
individually.
eDP, DP, DVI, and MIPI DSI are calculated using CVT 1.2 RB1 blanking and pixel rate.
HDMI is calculated using HDMI specification blanking and pixel rate.
Bpp is referring to the port output bits per pixel.
1 Requires at least single channel DDR3 1333 for 3 simultaneous displays
2 Requires at least single channel DDR3 1600 for 3 simultaneous displays
3 Requires at least dual channel DDR3 1333 for 3 simultaneous displays
4 Requires at least dual channel DDR3 1600 for 3 simultaneous displays
Examples
Example pipe pixel rate:
Plane 1 enabled at 32bpp, plane 2 enabled at 16bpp, pipe scaling enabled and down scale amount 1.12,
and CDCLK 450 MHz:
Plane 1 ratio = 1
Plane 2 ratio = 1
Pipe ratio = Minimum[1, 1] = 1
Pipe ratio = 1/1.12 = 0.89
Pipe maximum pixel rate = 450 MHz * 0.89 = 400.5 MHz
Example pipe pixel rate:
Plane 1 enabled at 64bpp and plane down scale amount 1.25, plane 2 enabled at 32bpp, no panel fitting
enabled, and CDCLK 540 MHz:
Plane 1 ratio = 1/1.25 * 8/9 = 0.71
Plane 2 ratio = 1
Pipe ratio = Minimum[1, 0.71] = 0.71
Pipe maximum pixel rate = 540 MHz * 0.71 = 383.4 MHz
Example memory bandwidth:
System memory bandwidth available for display = 4000 MB/s
Pipe A - Plane 1 enabled at 32bpp, plane 2 enabled at 16bpp, scaling disabled, pixel rate 148.5 MHz
Pipe B - Plane 1 enabled at 32bpp, scaling disabled, pixel rate 148.5 MHz
Pipe C - Plane 1 enabled at 32bpp, scaling disabled, pixel rate 148.5 MHz
Pipe A - Plane 1 bandwidth = 148.5 * 4 bytes = 594 MB/s
Pipe A - Plane 2 bandwidth = 148.5 * 2 bytes = 297 MB/s
Pipe B - Plane 1 bandwidth = 148.5 * 4 bytes = 594 MB/s
Pipe C - Plane 1 bandwidth = 148.5 * 4 bytes = 594 MB/s
Total display bandwidth = 594 + 297 + 594 + 594 = 2079 MB/s
System memory bandwidth available for display not exceeded
Example memory bandwidth:
System memory bandwidth available for display = 4000 MB/s
Pipe A - Plane 1 enabled at 32bpp, plane 2 plane enabled at 32bpp, pipe scaling enabled and down scale
amount 1.12, pixel rate 414.5 MHz
Pipe B - Plane 1 enabled at 32bpp, scaling disabled, pixel rate 414.5 MHz
Pipe C - Plane 1 enabled at 32bpp, scaling disabled, pixel rate 414.5 MHz
Pipe A - Plane 1 bandwidth = 414.5 * 4 bytes * 1.12 = 1863 MB/s
Pipe A - Plane 2 bandwidth = 414.5 * 4 bytes * 1.12 = 1863 MB/s
Pipe B - Plane 1 bandwidth = 414.5 * 4 bytes = 1658 MB/s
Pipe C - Plane 1 bandwidth = 414.5 * 4 bytes = 1658 MB/s
Total display bandwidth = 1863 + 1863 + 1658 + 1658 = 7042 MB/s
System memory bandwidth available for display exceeded
Clocks
Broxton Clocks
Registers
CDCLK_CTL
DE_PLL_CTL
DE_PLL_ENABLE
MIPI_CLOCK_CTL
DSI_PLL_CTL
DSI_PLL_ENABLE
PORT_PLL_PCS_0
PORT_PCS_DW12
PORT_PLL_EBB_0
PORT_PLL_EBB_4
PORT_PLL_0
PORT_PLL_1
PORT_PLL_2
PORT_PLL_3
PORT_PLL_6
PORT_PLL_8
PORT_PLL_9
PORT_PLL_10
PORT_PLL_ENABLE
TRANS_CLK_SEL
TIMESTAMP_CTR
DDI Clocks
There is one DDI clock tied to each DDI port.
A single DDI clock output may be used by multiple transcoders simultaneously for DisplayPort Multi-
streaming.
DDI clocks A, B, C
Usage DDI ports I/O bit clock and symbol/TMDS clock, source for transcoder clocks
Input The associated Port PLL
Frequency Port PLL frequency
Default after reset Disabled
Programming Not programmable
Transcoder Clocks
There is one Transcoder clock tied to each display transcoder, except Transcoder WD which uses only CD
clock.
Transcoder clock Transcoder clocks MIPI1 (MIPI A),
EDP Transcoder clocks A, B, C MIPI2 (MIPI C)
Transcoder EDP Transcoders A, B, and C Transcoder MIPI clocks
Usage
symbol clock symbol/TMDS clocks
Always uses DDI A Programmable selection between Always uses associated MIPI DSI
Input
clock DDI clocks B, and C. output clock
PLL output PLL output frequency divided by 5 Multiple options from additional
Frequency frequency divided dividers in display engine
by 5
Default after Connected to DDI Disabled Connected to DSI Clock
reset A Clock
Not programmable. Mapping of DDI to Transcoder must Dividers must be programmed by
be programmed by software when software when enabling and disabling
enabling and disabling a display. a display.
Programming
Programming is done through the Programming is done through the
TRANS_CLK_SEL registers. MIPI_CLOCK_CTLregisters.
CD Clock
CD clock refers to the Core Display clock which includes the Core Display 1X Clock (CD clock, CDclk,
cdclk, CDCLK) and the Core Display 2X Clock (CD2X clock, cd2xclk, CD2XCLK).
CD clock
Usage Clocking for most display engine functions
DE PLL output (with two frequency options) or iCLKPLL 19.2 MHz reference.
Input iCLKPLL 19.2 MHz is automatically selected by hardware when Power Well #1 is disabled
or DE PLL is not locked.
iCLKPLL (DE PLL disabled) - 19.2 MHz CD, 19.2 MHz CD2X
DE PLL with output 1152 MHz
144 MHz CD, 288 MHz CD2X
288 MHz CD, 576 MHz CD2X
Frequency 384 MHz CD, 768 MHz CD2X
576 MHz CD, 1152 MHz CD2X
eDP link rates: 1.62, 2.16, 2.43, 2.7, 3.24, 4.32, 5.4 GHz SSC and Non-SSC
DP link rates: 1.62, 2.7, 5.4 GHz SSC and Non-SSC
HDMI/DVI link rates: 0.2 to 3.0 GHz Non-SSC
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2
P1 must be 2, 3, or 4
P2 must be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, or 20 (1 to 20, even numbers when greater
than 10)
VCO must be in the range 4800 to 6700
M2 = VCO / (M1 * Reference Clock / N)
M1 must be 2
N must be 1
Reference Clock must be 100 MHz
With the fixed values for M1, N, and reference clock, the formulas reduce to the following:
M2 = Desired Output * P1 * P2 / 400
VCO = M2 * 200
Actual Output = M2 * 400 / (P1 * P2) // Actual differs from desired due to limited M2 fractional
precision
Note: If the desired output frequency cannot be achieved with the valid values of P1, P2, and M2, use a
different screen resolution with a different output frequency.
For P1 = (4,3,2)
For P2 = (20,18,16,14,12,10,9,8,7,6,5,4,3,2,1)
M2 = (Desired Output * P1 * P2) / 400
M2 = ROUNDUP(2^22 * M2) / 2^22
VCO = M2 * 200
If (VCO>=4800) AND (VCO<6700)
Actual Output = M2 * 400 / (P1 * P2)
Error = Actual Output – Desired Output
PPM = 1,000,000 * Error / Desired Output
If PPM < 100 And (P1 * P2) > (Best P1 * Best P2)
Best PPM = 0
Best M2 = M2
Best P1 = P1
Best P2 = P2
End If
If PPM < (Best PPM – 10)
Best PPM = PPM
Best M2 = M2
Best P1 = P1
Best P2 = P2
End If
End If
Next P2
Next P1
Best M2 Integer = INT(Best M2)
Best M2 Fraction = ROUNDUP(2^22 * (Best M2 – Best M2 Integer))
The MIPI DSI PLL block outputs the MIPI A 8X clock and MIPI C 8X clock.
A programmable divider controls the PLL 16X clock frequency, which goes through three other dividers
in parallel to generate the outputs.
The DSI A clock and DSI C clock come from the 16X clock after being divided by 2 (8X), 3 (16X/3), or 4
(4X).
Example Ratios and Corresponding Frequencies (MHz)
Ratio 8X Clk 16X/3 Clk 4X Clk
34 326.4 217.6 163.2
35 336 224 168
40 384 256 192
45 432 288 216
50 480 320 240
55 528 352 264
57 547.2 364.8 273.6
60 576 384 288
63 604.8 403.2 302.4
65 624 416 312
70 672 448 336
75 720 480 360
80 768 512 384
85 816 544 408
Both output dividers must be programmed to valid values any time the PLL is enabled, even if only
one output is used.
The dividers cannot be changed while the PLL is enabled.
The additional MIPI clock dividers further divide the MIPI PLL 8X clock to create the different clocks for
the controller and I/O PHY. The dividers are programmed through the MIPI_CLOCK_CTL register and
must follow the restrictions there.
DE PLL
The DE PLL outputs the CD2X DE PLL clock which is the source for CD clock.
A programmable divider, controlled by the DE_PLL_CTL register, inside the PLL controls the PLL
frequency. The DE PLL CD2X Divider outside the PLL, controlled by the CDCLK_CTL register, provides
additional dividing to create the CD2X clock used by the display engine.
Supported Ratios and Corresponding Frequencies (MHz)
DE PLL Ratio DE CD2X Frequency DE CD2X Divide CD2XCLK CDCLK
65 1248 1 1248 624
60 1152 1 1152 576
60 1152 1.5 768 384
60 1152 2 576 288
60 1152 4 288 144
DE PLL Sequences
Follow the Broxton Sequences for Changing CD Clock Frequency
The CD clock frequency impacts the maximum supported pixel rate and display watermark programming.
The CD clock frequency must be at least twice the frequency of the Azalia BCLK.
Frequency changes required display to be disabled, except if only the DE CD2X Divider is changed.
i. Write CDCLK_CTL with the DE CD2X Pipe selectoin, DE PLL CD2X Divider selection, CD
Frequency Decimal value, and SSA Precharge Enable to match the desired CD clock
frequency
ii. If pipe is enabled, wait for start of vertical blank for change to take effect
4. Inform power controller of the selected frequency
Use 19.2 MHz for the frequency if DE PLL is disabled
a. Write GT Driver Mailbox Data Low with Ceiling[CDCLK frequency / 25].
For CD clock 19.2 MHz (DE PLL disabled), program 1 decimal.
For CD clock 79.2 MHz, program 4 decimal.
For CD clock 144 MHz, program 6 decimal.
For CD clock 288 MHz, program 12 decimal.
For CD clock 384 MHz, program 16 decimal.
For CD clock 576 MHz, program 24 decimal.
For CD clock 624 MHz, program 25 decimal.
For CD clock 156 or 158.4 MHz, program 7 decimal.
For CD clock 312 or 316.8 MHz, program 13 decimal.
b. Write GT Driver Mailbox Interface = 0x80000017.
There is no need to wait for the Run/Busy indication to be cleared before continuing
with display programming.
5. Update programming of functions that use the CD clock frequency
If these features are not currently enabled, the programming can be delayed to when they are
enabled.
Wireless Display 27 MHz frequency in the WD_27_M and WD_27_N registers.
For CD clock 79.2 MHz, program M=15 and N=44 (decimal).
For CD clock 158.4 MHz, program M=15 and N=88 (decimal).
For CD clock 316.8 MHz, program M=15 and N=176 (decimal).
For CD clock 144 MHz, program M=3 and N=16 (decimal).
For CD clock 288 MHz, program M=3 and N=32 (decimal).
For CD clock 384 MHz, program M=9 and N=128 (decimal).
For CD clock 576 MHz, program M=3 and N=64 (decimal).
For CD clock 624 MHz, program M=9 and N=208 (decimal).
For CD clock 156 MHz, program M=9 and N=52 (decimal).
For CD clock 312 MHz, program M=9 and N=104 (decimal).
Resets
NDE_RSTWRN_OPT
The north and south display engines are reset by PCI Function Level Resets (FLR) and the chip level
resets.
An FLR for Bus:Device:Function 0:2:0 resets the north and south display engines and audio codec and
most of the related MMIO, PCI, and I/O configuration registers.
Display configuration registers that are reset by both the chip level reset and by FLR are marked as using
the "soft" reset in the programming specification.
Display configuration registers that are reset only by the chip level reset and not by FLR are marked as
using the "global" reset in the programming specification.
The south display engine runs panel power down sequencing (if configured to do so) before resetting.
This additional programming is needed to bring the display engine to the cold boot state after the FLR for
Bus:Function:Device 0:2:0 completes. This is optional if software can tolerate display not being in the cold boot state
after FLR.
1. Disable PWR_WELL_CTL Power Well 2 Request
2. Clear both PHY_CTL_FAMILY_EDP and PHY_CTL_FAMILY_DDI Common Reset to 0b (Disable)
3. Clear P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR to 0x0
4. Disable PWR_WELL_CTL Power Well 1 Request
The board connections do not match the internal assignments, so software must remap how it assigns the HPDs.
Software needs to activate the DDI A HPD logic and interrupts in order to check the external panel connection, and
enable the DDI C HPD logic and interrupts in order to check the eDP panel connection. PSR on eDP will not
automatically exit when there is a short pulse HPD_IRQ from the eDP panel. Software should set the PSR_MASK
register Mask Hotplug field to prevent false PSR exits casued by the external panel.
Backlight
This section refers to the CPU display backlight control. For PCH display backlight control, see South
Display Engine Registers.
The backlight PWM output frequency is determined by the PWM clock frequency, increment, and
frequency divider.
PWM output frequency = PWM clock frequency / PWM increment / PWM frequency divider
The frequency divider must be greater than or equal to the number of brightness levels required by
software; typically 100 or 256.
Description
PWM output frequency range with PWM clock frequency 19.2 MHz and 100 brightness levels = 0.0004 to 192,000
Hz
PWM output frequency range with PWM clock frequency 19.2 MHz and 256 brightness levels = 0.0004 to 75,000 Hz
Description
1. Set frequency and duty cycle in BLC_PWM_FREQ Frequency and BLC_PWM_DUTY Duty Cycle.
2. Enable PWM output and set polarity in BLC_PWM_CTL PWM Enable and PWM Polarity. Polarity can be
programmed earlier if needed
...
3. Change duty cycle as needed in BLC_PWM_DUTY Duty Cycle.
Backlight Registers
Description
BLC_PWM_CTL
BLC_PWM_FREQ
BLC_PWM_DUTY
Backlight 2 BLC_PWM_*_2 uses the display utility pin for output. To use backlight 2, enable the utility pin with mode
= PWM.
Panel Power
PP_STATUS
PP_CONTROL
PP_ON_DELAYS
PP_OFF_DELAYS
Pin Usage
These GPIO pins allow the support of simple query and control functions such as DDC interface
protocols. The GMBUS controller can be used to run the interface protocol, or the GPIO pins can be
manually programmed for a "bit banging" interface.
The following table describes the expected GPIO pin to register mapping. OEMs have the ability to
remap these functions onto other pins as long as the hardware limitations are observed. The GPIO pins
may also be muxed with other functions such that they are only available when the other function is not
being used.
Port # Name Pull up/down Description
1 DDIB CTLDATA
No DDC for DDI port B.
(Weak pull down on reset)
DDIB CTLCLK No
2 DDIC CTLDATA
No DDC for DDI port C.
(Weak pull down on reset)
DDIC CTLCLK No
3 MISC CTLDATA
No DDC for Miscellaneous usage.
(Weak pull down on reset)
MISC CTLCLK No
DDI C is not connected on the current die, but may be connected in the future.
1. I2C compatible.
2. Bus clock frequency of 50 KHz or 100 KHz.
3. Attaches to any of the GPIO pin pairs.
4. 7-bit or 10-bit Slave Address and 8-bit or 16-bit index.
5. Double buffered data register and a 9 bit counter support 0 byte to 256 byte transfers.
6. Supports stalls generated by the slave device pulling down the clock line (Slave Stall), or delaying
the slave acknowledge response.
7. Status register indicates error conditions, data buffer busy, time out, and data complete
acknowledgement.
8. Detects and reports time out conditions for a stall from a slave device, or a delayed or missing
slave acknowledge.
9. Interrupts may optionally be generated.
10. Does not directly support segment pointer addressing as defined by the Enhanced Display Data
Channel standard.
Segment pointer addressing as defined by the Enhanced Display Data Channel standard:
1. Use bit bashing (manual GPIO programming) to complete segment pointer write without
terminating in a stop or wait cycle.
2. Terminate bit bashing phase with both I2C lines pulled high by tri-stating the data line before the
clock line. Follow EDDC requirement for response received from slave device.
3. Initiate GMBUS cycle as required to transfer EDID following normal procedure.
Program 0x4653C[14] = 0x1 when doing back to back GMBUS transactions. The value can be safely left at 0x1 when
GMBUS is not being used.
This will disable GMBUS unit level clock gating and only rely on partition level clock gating.
DC States
DC_STATE_EN
Proper display buffer allocation is important for Display hardware to function correctly. Optimal
allocation provides better display residency in memory low power modes. Display Buffer allocation must
be recalculated and programmed when pipes/planes get enabled or disabled.
Display Buffer Total Display Buffer Fixed Bypass Path Allocation in Blocks Available for Driver
Size Blocks Blocks Programming
256 KB 512 4 0 - 507
Allocation Requirements
Allocation must not overlap between any enabled planes.
A minimum allocation is required for any enabled plane. See Minimum Allocation Requirements below.
A gap between allocation for enabled planes is allowed.
The allocation for enabled planes should be as large as possible to allow for higher watermarks and
better residency in memory power saving modes.
Planar YUV 420 Surfaces:
For YUV 420 Planar formats (NV12, P0xx), buffer allocation is done for Y and UV surfaces separately. Treat Y and UV
surface as 2 separate planes. Also,the plane height and plane width for the UV plane should be halved.
UV Plane Height = Plane Height/2
UV Plane Width = Plane Width/2
Y tiled minimum allocation = Ceiling [(4 * Plane source width * Plane Bpp)/512] * MinScanLines/4 + 3
Minimum Scanlines for Y Tile
Plane Bpp 0/180 Rotation 90/270 Rotation
1 8 32
2 8 16
4 8 8
8 8 4
Example Method 1:
Single Pipe
Allocate a fixed number of blocks to cursors and then allocate the remaining blocks among planes, based on each
plane's data rate.
BlocksAvailable = TotalBlocksAvailable
1. Allocate 32 blocks for cursor
The driver frequently enables and disables the cursor or changes the cursor pixel format. Fixed allocation is
preferred for cursor to minimize the buffer re-allocation. More allocation might be required to support deeper low
power states (based on the results of watermark calculations).
CursorBufAlloc = 32
BlocksAvailable = BlocksAvailable – 32
2. Check for minimum buffer requirement
In this step the driver may want to use the expected maximum plane source sizes so it does not have to reallocate
for a plane that is changing size.
For each enabled plane
If PlaneScalerEnabled
PlaneScaleFactor = (Plane width/Scaler window X size) * (Plane height/Scaler window Y size)
Else
PlaneScaleFactor = 1
PlaneRelativeDataRate = Plane height * Plane width * plane source bytes per pixel * PlaneScaleFactor
4. Allocate blocks for enabled planes as per the Data rate ratio.
AdjustmentRequired = false
For each plane needs allocation (PlaneBlockAllocFinal == false)
If PlaneBufAlloc < PlaneMinAlloc
AdjustmentRequired = true
PlaneBufAlloc = PlaneMinAlloc
PlaneBlockAllocFinal = true
BlocksAvailable = BlocksAvailable - PlaneMinAlloc
If AdjustmentRequired = true
Go back to step 4
Multi-Pipe
Option 1:
Allocate a fixed number of blocks to cursors, allocate 1/NumPipes of the remaining blocks to each pipe, then
calculate each pipe individually as in the Single Pipe case.
NumPipes = Total number of display pipes in the hardware
1. Allocate 8 blocks for cursor per pipe
The driver frequently enables and disables the cursor or changes the cursor pixel format. Fixed allocation is
preferred for cursor to minimize the buffer re-allocation. More allocation might be required to support deeper low
power states (based on the results of watermark calculations).
For each enabled cursor
CursorBufAlloc = 8
BlocksAvailable = BlocksAvailable/NumPipes
3. Assign blocks to the planes
Example Method 2:
This allocation is based on the Watermark calculations and helps to distribute the buffer more optimally to acheive
consistent latency levels supported in all planes across all pipes.
Allocate fixed number of blocks for cursor (for example 32 blocks).
For each enabled plane in all pipes, calculate buffer allocation needed for all Latency levels 1 to 7.
Calculate the total buffer allocation needed for each latency level by adding the individual allocation of all
enabled planes.
Choose the max latency level that can be supported with the available display buffer. For each enabled
plane, program/enable all watermarks up to that latency level.
Allocate the buffer to the planes as required by the latency level chosen.
VGA
The VGA Control register is located here. The VGA I/O registers are located in the VGA Registers
document.
VGA_CONTROL
Cursor Plane
Planes
PLANE_SURFLIVE
CUR_SURFLIVE
The CUR_CTL and CUR_FBC_CTL active registers will be updated on the vertical blank or when pipe is
disabled, after the CUR_BASE register is written, or when cursor is not yet enabled, providing an atomic
update of those registers together with the CUR_BASE register.
DDI Buffer
Registers
DDI_BUF_CTL
PHY_CTL_DDI
PHY_CTL_FAMILY
PORT_CL1CM_DW0
PORT_CL1CM_DW9
PORT_CL1CM_DW10
PORT_CL1CM_DW28
PORT_CL1CM_DW30
PORT_REF_DW3
PORT_REF_DW6
PORT_REF_DW8
PORT_TX_DW2
PORT_TX_DW3
PORT_TX_DW4
PORT_TX_DW14
PORT_PCS_DW10
PORT_PCS_DW12
P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR
Broxton
DDIB and DDIC share a dual channel PHY, so PHY based programming will impact both DDIs at the same time.
DDIA/EDP uses a single channel PHY, so it is the only port in that PHY.
c. If motherboard DDI RCOMP resistor is 100 Ohms, set PORT_REF_DW8_BC fcomprefsel = 1b, else leave
at default 0b for 400 Ohms.
d. Program PLL Rcomp code offset
i. Write 0xE4 to iref0rcoffset in PORT_CL1CM_DW9_B and PORT_CL1CM_DW9_C
ii. Write 0xE4 to iref1rcoffset in PORT_CL1CM_DW10_B and PORT_CL1CM_DW10_C
e. Program power gating
i. Write 11b to sus_clk_config and 1b to ocl1powerdownen and oldo_dynpwrdownen in
PORT_CL1CM_DW28_BC
ii. Write 1b to oldo_dynpwrdownen in PORT_CL2CM_DW6 [BXT]
f. Copy Rcomp from single channel PHY (EDP A) to dual channel PHY (DDI BC)
i. Poll for PORT_REF_DW3_A grc_done == 1b
ii. Read and save grccode from PORT_REF_DW6_A
iii. Write the saved grccode to ogrccode_fast, ogrccode_slow, and ogrccode_nom in
PORT_REF_DW6_BC
iv. Write 1b to grcdis and grc_rdy_ovrd in PORT_REF_DW8_BC
g. Set PHY_CTL_FAMILY_DDI Common Reset = 1b (Enable)
3. If DDIA/EDP won't be used it can now be disabled
1. Clear PHY_CTL_FAMILY_EDP Common Reset to 0b (disable)
2. Clear P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR CH1_PWRREQ1P0_SUS (DDIA/eDP IO Power On) to
0b (power off)
If the PHY is needed again, follow the initialization sequence, including the DDIA enable and Rcomp
copying.
The table below gives the value to program in PORT_TX_DW14_LN<0,1,2,3>_<DDI> latency_optim for
each lane for a given lane configuration on that DDI. Group access cannot be used here since each lane
can have a unique value, and any later writes to PORT_TX_DW14 must not use group access so that they
don't overwrite the inidivual lane values.
Lane configuration / latency_optim X1 - Reversed and X2 - reversed and X4 - Reversed and non-
setting non-reversed non-reversed reversed
PORT_TX_DW14_LN0_<DDI> 0 1 1
PORT_TX_DW14_LN1_<DDI> 0 0 0
PORT_TX_DW14_LN2_<DDI> 0 1 1
PORT_TX_DW14_LN3_<DDI> 0 0 1
Voltage swing programming for embedded DisplayPorts that support low voltage swings
Voltage Pre- Non- Transition Pre- Scale Enable and Swing
Deemphasis
Swing emphasis Transition mV diff p- emphasis Value
Level1 Level1 mV diff p-p p dB decimal decimal
Broxton