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Tmax Rules

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Tmax Rules

atpg drc's

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®

TetraMAX DRC Messages

Version O-2018.06-SP2, September 2018
TetraMAX DRC Rules O-2018.06

Copyright Notice and Proprietary Information

Copyright © 2018 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and
proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished
under a license agreement and may be used or copied only in accordance with the terms of the license
agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any
form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of
Synopsys, Inc., or as expressly provided by the license agreement.

Destination Control Statement

All technical data contained in this publication is subject to the export control laws of the United States of
America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s
responsibility to determine the applicable regulations and to comply with them.

Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx. All other product or company names may be
trademarks of their respective owners. Inc.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not
endorse and is not responsible for such websites and their practices, including privacy practices, availability,
and content.

Synopsys, Inc.
690 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com

2
TetraMAX DRC Rules O-2018.06

Contents
Category A - Assertion Rules 18

DRC Rule A1 19

DRC Rule A2 20

DRC Rule A3 21

Category B - Build Rules 22

DRC Rule B1 23

DRC Rule B2 24

DRC Rule B3 25

DRC Rule B4 26

DRC Rule B5 27

DRC Rule B6 28

DRC Rule B7 29

DRC Rule B8 30

DRC Rule B9 31

DRC Rule B10 32

DRC Rule B11 33

DRC Rule B12 34

DRC Rule B13 35

DRC Rule B14 36

DRC Rule B15 37

DRC Rule B16 38

DRC Rule B17 39

DRC Rule B18 40

3
TetraMAX DRC Rules O-2018.06

DRC Rule B19 41

DRC Rule B20 42

DRC Rule B21 43

DRC Rule B22 44

DRC Rule B23 45

DRC Rule B24 47

DRC Rule B25 48

DRC Rule B26 49

DRC Rule B27 50

DRC Rule B28 51

DRC Rule B29 52

DRC Rule B30 53

DRC Rule B31 54

DRC Rule B32 55

DRC Rule B33 56

DRC Rule B34 57

Category C - Clock Rules 60

DRC Rule C1 61

DRC Rule C2 63

DRC Rule C3 65

DRC Rule C4 66

DRC Rule C5 68

DRC Rule C6 70

DRC Rule C7 71

DRC Rule C8 72

DRC Rule C9 74

DRC Rule C10 75

DRC Rule C11 76

DRC Rule C12 78

DRC Rule C13 80

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TetraMAX DRC Rules O-2018.06

DRC Rule C14 82

DRC Rule C15 84

DRC Rule C16 85

DRC Rule C17 86

DRC Rule C18 88

DRC Rule C19 89

DRC Rule C20 90

DRC Rule C21 91

DRC Rule C22 92

DRC Rule C23 93

DRC Rule C24 94

DRC Rule C25 95

DRC Rule C26 97

DRC Rule C27 98

DRC Rule C28 99

DRC Rule C29 100

DRC Rule C30 101

DRC Rule C31 102

DRC Rule C34 103

DRC Rule C35 104

DRC Rule C36 106

DRC Rule C37 107

DRC Rule C38 108

DRC Rule C39 109

DRC Rule C40 111

DRC Rule C41 112

Category D DFT Rules 113

DRC Rule D1 114

DRC Rule D2 115

DRC Rule D3 116

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TetraMAX DRC Rules O-2018.06

DRC Rule D4 117

DRC Rule D5 118

DRC Rule D6 119

DRC Rule D7 120

DRC Rule D8 121

DRC Rule D9 122

DRC Rule D10 124

DRC Rule D11 125

DRC Rule D12 126

DRC Rule D13 127

DRC Rule D14 128

DRC Rule D15 129

DRC Rule D16 130

DRC Rule D17 132

DRC Rule D18 133

DRC Rule D20 134

DRC Rule D21 135

DRC Rule D22 136

DRC Rule D23 137

DRC Rule D39 138

Category K - LBIST Rules 139

DRC Rule K1 141

DRC Rule K2 142

DRC Rule K3 144

DRC Rule K4 145

DRC Rule K5 147

DRC Rule K6 148

DRC Rule K7 150

DRC Rule K8 152

DRC Rule K9 154

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TetraMAX DRC Rules O-2018.06

DRC Rule K10 156

DRC Rule K11 158

DRC Rule K1 160

DRC Rule K13 162

DRC Rule K14 163

DRC Rule K15 164

DRC Rule K16 165

DRC Rule K17 166

DRC Rule K18 168

DRC Rule K19 169

DRC Rule K20 170

DRC Rule K21 171

DRC Rule K22 172

DRC Rule K23 173

DRC Rule K24 174

DRC Rule K25 175

DRC Rule K26 176

DRC Rule K27 178

DRC Rule K28 179

DRC Rule K29 180

DRC Rule K30 181

DRC Rule K31 183

DRC Rule K32 184

DRC Rule K3 185

DRC Rule K34 186

DRC Rule K35 187

DRC Rule K36 188

DRC Rule K37 190

DRC Rule K38 192

DRC Rule K39 193

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TetraMAX DRC Rules O-2018.06

DRC Rule K40 194

DRC Rule K41 195

DRC Rule K42 196

DRC Rule K43 197

DRC Rule K44 198

DRC Rule K45 199

DRC Rule K46 200

DRC Rule K47 201

DRC Rule K48 202

DRC Rule K49 203

DRC Rule K50 204

DRC Rule K51 205

DRC Rule K52 206

DRC Rule K53 207

DRC Rule K54 208

DRC Rule K55 209

DRC Rule K56 210

DRC Rule K57 211

DRC Rule K58 212

DRC Rule K59 213

DRC Rule K60 214

DRC Rule K61 215

DRC Rule K62 216

DRC Rule K63 218

DRC Rule K64 219

DRC Rule K65 221

DRC Rule K66 222

DRC Rule K67 223

DRC Rule K68 224

DRC Rule K69 225

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TetraMAX DRC Rules O-2018.06

DRC Rule K70 227

DRC Rule K71 228

DRC Rule K72 230

DRC Rule K73 231

DRC Rule K74 232

DRC Rule K74 233

DRC Rule K74 234

DRC Rule K74 235

DRC Rule K78 236

DRC Rule K79 238

DRC Rule K80 240

DRC Rule K81 241

DRC Rule K82 242

DRC Rule K83 243

DRC Rule K84 244

DRC Rule K85 245

DRC Rule K86 246

DRC Rule K87 247

DRC Rule K88 248

DRC Rule K89 249

DRC Rule K90 250

DRC Rule K91 251

DRC Rule K92 252

DRC Rule K93 253

DRC Rule K94 254

Category N - Netlist Rules 255

DRC Rule N1 256

DRC Rule N2 258

DRC Rule N3 259

DRC Rule N4 260

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TetraMAX DRC Rules O-2018.06

DRC Rule N5 261

DRC Rule N6 262

DRC Rule N7 263

DRC Rule N8 264

DRC Rule N9 265

DRC Rule N10 266

DRC Rule N11 267

DRC Rule N12 268

DRC Rule N13 269

DRC Rule N14 270

DRC Rule N15 271

DRC Rule N16 272

DRC Rule N17 274

DRC Rule N18 275

DRC Rule N19 276

DRC Rule N20 277

DRC Rule N21 279

DRC Rule N22 280

DRC Rule N23 281

DRC Rule N24 283

DRC Rule N25 284

DRC Rule N26 285

DRC Rule N27 286

DRC Rule N28 287

DRC Rule N29 288

DRC Rule N30 289

Category P - Path Delay Rules 290

DRC Rule P1 291

DRC Rule P2 292

DRC Rule P3 293

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TetraMAX DRC Rules O-2018.06

DRC Rule P4 294

DRC Rule P5 295

DRC Rule P6 296

DRC Rule P7 297

DRC Rule P8 299

DRC Rule P9 301

DRC Rule P10 303

DRC Rule P11 304

DRC Rule P12 305

DRC Rule P13 306

DRC Rule P14 307

DRC Rule P15 308

DRC Rule P16 309

DRC Rule P17 310

DRC Rule P18 311

DRC Rule P19 313

DRC Rule P20 314

DRC Rule P21 315

DRC Rule P22 316

DRC Rule P23 317

DRC Rule P24 318

DRC Rule P25 319

DRC Rule P26 320

Category R - Compressor Rules 321

DRC Rule R1 323

DRC Rule R2 324

DRC Rule R3 325

DRC Rule R4 326

DRC Rule R5 327

DRC Rule R6 328

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TetraMAX DRC Rules O-2018.06

DRC Rule R7 329

DRC Rule R8 331

DRC Rule R9 332

DRC Rule R10 333

DRC Rule R11 334

DRC Rule R12 336

DRC Rule R14 337

DRC Rule R15 338

DRC Rule R16 339

DRC Rule R17 340

DRC Rule R18 341

DRC Rule R19 342

DRC Rule R20 343

DRC Rule R21 344

DRC Rule R22 345

DRC Rule R23 346

DRC Rule R24 348

DRC Rule R25 350

DRC Rule R26 351

DRC Rule R27 352

DRC Rule R28 353

DRC Rule R29 354

DRC Rule R30 355

DRC Rule R31 356

DRC Rule R32 357

DRC Rule R33 358

DRC Rule R34 360

DRC Rule R35 361

DRC Rule R36 362

DRC Rule R37 364

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TetraMAX DRC Rules O-2018.06

DRC Rule R38 365

DRC Rule R39 366

DRC Rule R40 367

DRC Rule R42 368

DRC Rule R43 369

DRC Rule R44 370

DRC Rule R45 371

DRC Rule R46 372

DRC Rule R47 373

DRC Rule R48 374

DRC Rule R49 375

DRC Rule R50 376

DRC Rule R51 377

DRC Rule R52 379

DRC Rule R53 380

DRC Rule R54 381

DRC Rule R55 382

DRC Rule R56 383

DRC Rule R57 384

DRC Rule R58 385

DRC Rule R59 386

DRC Rule R60 387

Category S - Scan Chain Rules 388

DRC Rule S1 389

DRC Rule S2 391

DRC Rule S3 392

DRC Rule S4 393

DRC Rule S5 394

DRC Rule S6 395

DRC Rule S7 396

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TetraMAX DRC Rules O-2018.06

DRC Rule S8 397

DRC Rule S9 398

DRC Rule S10 399

DRC Rule S11 400

DRC Rule S12 401

DRC Rule S13 402

DRC Rule S14 403

DRC Rule S15 404

DRC Rule S16 405

DRC Rule S17 406

DRC Rule S18 407

DRC Rule S19 408

DRC Rule S20 410

DRC Rule S21 411

DRC Rule S22 412

DRC Rule S23 414

DRC Rule S24 415

DRC Rule S25 416

DRC Rule S26 417

DRC Rule S27 418

DRC Rule S28 419

DRC Rule S29 420

DRC Rule S30 422

DRC Rule S32 423

Category V - Vector Rules 425

DRC Rule V1 426

DRC Rule V2 427

DRC Rule V3 428

DRC Rule V4 429

DRC Rule V5 430

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TetraMAX DRC Rules O-2018.06

DRC Rule V6 431

DRC Rule V7 432

DRC Rule V8 433

DRC Rule V9 435

DRC Rule V10 436

DRC Rule V11 437

DRC Rule V12 438

DRC Rule V13 439

DRC Rule V14 440

DRC Rule V15 441

DRC Rule V16 442

DRC Rule V17 443

DRC Rule V18 445

DRC Rule V19 446

DRC Rule V20 447

DRC Rule V21 449

DRC Rule V22 450

DRC Rule V23 451

DRC Rule V24 452

DRC Rule V25 454

DRC Rule V26 455

DRC Rule V27 456

DRC Rule V28 457

DRC Rule V29 458

DRC Rule V31 459

DRC Rule V32 461

DRC Rule V33 462

DRC Rule V34 463

DRC Rule V35 465

DRC Rule V36 466

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TetraMAX DRC Rules O-2018.06

DRC Rule V37 467

Category X - X-State Rules 468

DRC Rule X1 469

DRC Rule X2 471

Category Y - PHDS Rules 473

DRC Rule Y1 474

DRC Rule Y2 475

DRC Rule Y3 476

DRC Rule Y4 477

DRC Rule Y5 478

DRC Rule Y6 479

DRC Rule Y7 480

DRC Rule Y8 481

DRC Rule Y9 482

DRC Rule Y10 483

DRC Rule Y11 484

DRC Rule Y12 485

DRC Rule Y13 486

DRC Rule Y14 487

DRC Rule Y15 488

DRC Rule Y16 489

DRC Rule Y17 490

DRC Rule Y18 491

DRC Rule Y19 492

DRC Rule Y20 493

DRC Rule Y21 494

DRC Rule Y22 495

DRC Rule Y23 496

DRC Rule Y24 497

DRC Rule Y25 498

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TetraMAX DRC Rules O-2018.06

Category Z - Tristate Rules 499

DRC Rule Z1 500

DRC Rule Z2 502

DRC Rule Z3 503

DRC Rule Z4 505

DRC Rule Z5 506

DRC Rule Z6 507

DRC Rule Z7 508

DRC Rule Z8 510

DRC Rule Z9 511

DRC Rule Z10 512

DRC Rule Z11 513

DRC Rule Z12 515

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TetraMAX DRC Rules O-2018.06

Category A - Assertion Rules

A1 - assert during shift failure
A2 - assert during capture failure
A3 - assert stable failure

Category A - Assertion Rules 18

TetraMAX DRC Rules O-2018.06

DRC Rule A1
Message Text
A1: Assert [0|1|Stable|Not-X] during shift on Gate [instance_name]
([gate_id]) failed (A1-n).

Severity
Error

Description
This message appears when a user-defined shift assertion for a cell instance fails during DRC. It
displays the type of assertion (0|1|Stable|Not-X), cell instance name (instance_name),
location (gate_id), and message code (A1-n).
An assertion failure indicates that the identified cell instance will likely cause a pattern failure
during VCS simulation. You can find descriptions of all TetraMAX shift assertions in the
Assertions topic.

What Next
A design change is likely required to fix the connection failure. You can downgrade this message
to pass DRC. However, the risk is that TetraMAX generates patterns that will fail during VCS
simulation.

Category A - Assertion Rules 19

TetraMAX DRC Rules O-2018.06

DRC Rule A2
Message Text
A2: Assert [0|1|Stable|Not-X] during capture on Gate [instance_
name]([gate_id]) failed (A2-n).

Severity
Error

Description
This message appears when a user-defined capture assertion for a cell instance fails during
DRC. It displays the type of assertion (0|1|Stable|Not-X), cell instance name (instance_
name), location (gate_id), and message code (A2-n).
An assertion failure indicates that the identified cell instance will likely cause a pattern failure
during VCS simulation. You can find descriptions of all TetraMAX shift assertions in the
Assertions topic.

Category A - Assertion Rules 20

TetraMAX DRC Rules O-2018.06

DRC Rule B23

Message Text
Build Rule B23: Feedback path#ID contains N1 gates and N2 sources.

Severity
Warning

Example
One example, many variations are possible:

Description
A combinational feedback path was identified. As each combinational feedback path is identified,
it is recorded as a B23 violation. ID is the identification number assigned to this feedback path, N1
is the number of gates in the path, and N2 is the number of sources in the path. Feedback path
sources are a subset of the gates in the feedback path that, if removed, would eliminate the
feedback. The sources subset might not be unique. For example, in the picture above, any one
gate can be considered a source. The more sources a feedback path has, the more "branches
and loops" it has.

Message Text
Build Rule B33: Cascaded Buses.

Severity
Warning

Example
One example, many variations are possible:

Description
The flattened model contained two cascaded BUS primitives, or two cascaded BUS primitives
separated by a BUFZ primitive. BUS primitives are inserted during flattening to resolve the output
of tristateable drivers and bus holds.
This condition could cause TetraMAX ATPG to see contention and reject patterns due to
contention that would otherwise be kept. This is because the contention detection algorithm
requires that all gates driving a BUS primitive have an enable (TSD's), or be weak drives
(BUSK's). When a BUFZ occurs between two BUS primitives it is regarded as a gate that can't
be disabled and the BUS prim is marked as having contention.

What Next
The occurrence in the design of logic that would justify cascaded BUS devices is very rare and is
most often an error in the netlist. Carefully check the source of the gates involved, as well as the
defined directions of the ports in the parent module.
If the netlist has no error, you might want to disable contention checking to avoid discarding
patterns due to this false contention condition. Unfortunately, the contention checking is globally
disabled and this cannot be acceptable.
Sometimes insertion into the original design of a unidirectional gate can overcome this issue.

Category B - Build Rules 56

TetraMAX DRC Rules O-2018.06

DRC Rule B34

Message Text
Build Rule B34: Illegal wired net

Severity
Error

Example
The following figure shows one example of the B34 build rule violation; many variations are
possible:

Description
TetraMAX ATPG cannot properly model or represent wired_and or wired_or nets with
bidirectional connections.
The flattened model above contains two primitives in parallel. The BUS primitive is inserted during
flattening to resolve the output of tristateable drivers and bus holds.
If instantiating two of the previous modules and wired_orthe out this cannot be represented
properly in TetraMAX ATPG. When you downgrade the B34 build rule, TetraMAX ATPG builds
the model ignoring the wired statement.

Category B - Build Rules 57

TetraMAX DRC Rules O-2018.06

module top (clkin, clk);

input clkin;
output clk;
wor clk;

clkrow clkrow_i0 ( .out ( clk ) , .in ( clkin ));

clkrow clkrow_i1 ( .out ( clk ) , .in ( clkin ));
endmodule

module clkrow ( out , in );

input in ;
inout out ;

invert_it inv_i1 (.out ( out ) , .in ( in ));

invert_it inv_i2 (.out ( out ) , .in ( in ));
endmodule

module invert_it (out, in);

input in;
output out;

not inv1 (out,in);

endmodule

What Next
When you downgrade the B34 build rule from its default rule violation, TetraMAX ATPG builds the
model ignoring the wired statement. The final netlist might not be the required representation.

Category B - Build Rules 58

TetraMAX DRC Rules O-2018.06

A design with a logic that justifies the wired_and or wired_or devices with bidirectional output
ports is very rare. It is most probably an error in the netlist. Carefully check the source of the gates
involved as well as the defined directions of the ports in the parent module.
To overcome this issue, insert a unidirectional gate or port in the original design.

Category B - Build Rules 59

TetraMAX DRC Rules O-2018.06

Category C - Clock Rules

C1 - Unstable scan cells when clocks off
C2 - Unstable nonscan DFF when clocks off
C3 - No latch transparency when clocks off
C4 - Clock unable to capture
C5 - LS port captured data affected by new capture
C6 - TE port captured data affected by new capture
C7 - LE port captured data affected by new capture
C8 - LS port clock path affected by new capture
C9 - TE port clock path affected by new capture
C10 - LE port clock path affected by new capture
C11 - LS port captured data affected by clock
C12 - LE port captured data affected by clock
C13 - TE port captured data affected by clock
C14 - Clock connected to multiple ports of same cell
C15 - Scan cell port unable to capture
C16 - Nonscan cell port unable to capture
C17 - Clock connected to PO
C18 - Clock connected to PO affected by new capture
C19 - Clock connected to non-contention-free BUS
C20 - Unstable RAM when clocks off
C21 - RAM port unable to capture
C22 - Clock as data for unstable cells
C23 - State element connected to unstable cell clock input
C24 - Nonclock PI connected to unstable cell clock input
C25 - Unstable cell clock input connected from multiple sources
C26 - Clock as data different from capture clock for stable cell
C27 - Missing PLL conditioning data
C28 - Invalid PLL source for internal clock
C29 - Undefined PLL source for internal clock
C30 - Scan PLL conditioning affected by nonscancells
C31 - Scan PLL conditioning not stable during capture
C34 - Unsensitized path between PLL source and internal clock
C35 - Multiple sensitizations between PLL source and internal clock
C36 - Mistimed sensitizations between PLL source and internal clock
C37 - Cannot satisfy all internal clocks off for all cycles
C38 - Bad off-conditioning between PLL source and internal clock
C39 - Nonlogical clock C connects to scancell T
C40 - Internal clock is restricted
C41 - Equivalent clocks are not groupable

Category C - Clock Rules 60

TetraMAX DRC Rules O-2018.06

DRC Rule C1
Message Text
Clock Rule C1: Clock PIs off failed to force off clock input N of
scan S I (G).

Severity
Error

Examples
Example 1: Scan chain with a master-slave configuration

Example 2, below, displays an integrated cell using a latch-based gating style, rising-edge-
triggered. The integrated cell contains test logic scan enable.
Example 2: Rising-Edge Latch-Based Integrated Cell With Post-Control (latch_posedge_

postcontrol)
Example 3, below, displays an integrated cell using a latch-based gating style, falling-edge-
triggered. The integrated cell contains test logic scan enable.
Example 3: Falling-Edge Latch-Based Integrated Cell With Post-Control (latch_negedge_

postcontrol)

Category C - Clock Rules 61

TetraMAX DRC Rules O-2018.06

Description
When all clocks ports are at their off state, all clock/set/reset inputs of scan state elements must be
at their off state. The only exception to this would be if these inputs were causing a capture of data
from within the scan cell in which they reside such as when a slave latch captures data from its
master latch.
N is the input port number of the ATPG primitive (set=0, rst=1, clk1=2, data1=3...), S is the name
of the scan chain, I is the instance pathname, and G is the gate ID number of the device.
Failure to satisfy this rule can result in scan cells failing to hold their value before capture, and
there is a high risk that patterns generated would fail in simulation. Scan based simulation
continues to assume that the values captured during a capture clock cycle are the result of state
element values that existed at the end of the load operation. This assumption might be false if
scan cells fail to hold their value and lead to patterns generated that fail simulation.
This check is performed by simulating the logic values that result when:
l clocks are at their off state
l constrained ports are set to their constrained values
l constant value nonscan cells are set to their constant state
nonscan cells which have constant values are determined automatically during circuit learning.
This rule violation occurs if any clock/set/reset input of any scan cell memory element is not at its
off state.

What Next
A common cause of this violation is a missing clock definition or a clock defined with the wrong
polarity.
Another common cause is a clock which passes through a MUX, and the select line of the MUX is
not constant. If the MUX is controlled by some sort of test mode port, that port should be
constrained with an add_pi_constraint command.
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to clock-off data and displays the failing
cell with all the gates in the backtrace cone of the failing input. This shows the failing
clock/set/reset input and tracing back from this input can assist you in determining how to correct
the problem.

Category C - Clock Rules 62

TetraMAX DRC Rules O-2018.06

DRC Rule C2
Message Text
Clock Rule C2: Clock PIs off failed to force off clock input N of
nonscan DFF I (G).

Severity
Warning

Example
One example, many variations are possible:

Description
When all clocks are at their off state, all clock/set/reset inputs of nonscan DFF primitives must be
at their off state.
N is the input port number of the ATPG primitive (set=0, rst=1, clk1=2, data1=3...), I is the
instance pathname, and G is the gate ID number of the device.
Failure to satisfy this rule results in the DFFs not being usable for Fast-Sequential ATPG
algorithms. This is not harmful but can contribute to a lower test coverage.
This check is performed by simulating the logic values that result when:
l clocks are at their off state
l constant value nonscan cells are set to their constant state
l constrained ports are set to their constrained values
l constant value nonscan cells are set to their constant state
l constant value nonscan cells are set to their constant state
nonscan cells that have constant values are determined automatically during circuit learning.
This rule violation occurs if any clock/set/reset input of any nonscan DFF is not at its off state.

Category C - Clock Rules 63

TetraMAX DRC Rules O-2018.06

A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to clock-off data and displays the failing
cell with all the gates in the backtrace cone of the failing input. This shows the failing
clock/set/reset input and tracing back from this input can assist you in determining how to correct
the problem.

Category C - Clock Rules 64

TetraMAX DRC Rules O-2018.06

DRC Rule C3
Message Text
Clock Rule C3: Clock PIs off failed to allow transparency of
nonscan DLAT I (G).

Severity
Warning

Example
One example, many variations are possible:

Description
When all defined clocks are at their off state, at least one clock input of a nonscan DLAT (latch
primitive) must be capable of being on.
I is the instance pathname, and G is the gate ID number of the device.
Failure to satisfy this rule means the DLAT primitive is not usable as a transparent latch. The
Basic-Scan ATPG algorithm will treat the DLAT as if it were a TIEX device and the coverage that
uses this algorithm might be degraded. The Fast-Sequential or Full-Sequential algorithm might
be required to increase coverage.
This check is performed by simulating the logic values that result when:
l clocks are at their off state
l constrained ports are set to their constrained values
l constant value nonscan cells are set to their constant state
nonscan cells which have constant values are determined automatically during circuit learning.
The rule violation occurs if all clock/set/reset inputs of a nonscan latch are at their off state. DLATs
which fail this rule are treated as if their outputs are at X.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to clock-off data and displays the failing
cell with all the gates in the backtrace cone of the failing input. This shows the failing
clock/set/reset input and tracing back from this input can assist you in determining why the latch
cannot be placed in a transparent mode.
Enabling Fast-Sequential or Full-Sequential ATPG pattern generation might help to reduce test
coverage loss from latches that cannot be made transparent.

Category C - Clock Rules 65

TetraMAX DRC Rules O-2018.06

DRC Rule C4
Message Text
Clock Rule C4: Clock port_name cannot capture data with other
clocks off.
Clock Rule C4: Multiple clocks or a single clock through multiple
paths drives scan-cell instance_name during shift.

Severity
Error

Example
One example, many variations are possible:

Description
There are two different variations of the C4 rule violation message.
The first variation of this rule violation message occurs if all clock/set/reset/write inputs of all
sequential elements (including RAMs) are off during this condition. In this case, each defined
clock port must turn on a clock, set, reset, or write_control input of at least one sequential device
or memory element when all other clocks are off. Failure to satisfy this rule indicates a defined
clock cannot perform a capture operation which can result in some loss of test coverage.
This check is performed by simulating the logic values that result when:
l the specified clock (and any equivalent ports) are set to X
l all other defined clocks are set to their off states
l constrained ports are set to their constrained values
l constant value nonscan cells are set to their constant state
The second variation of the C4 rule violation message occurs when the set_drc -check_
multiple_shift_clocks command is specified. In this case, a C4 violation is reported for
each scan cell whose shift clock comes from multiple clocks that are active during shift, or from a
single clock which fans out through multiple paths that reconverge.

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What Next
The explanation for the first variation of C4 rule violation message (Clock port_name
cannot capture data with other clocks off.) is as follows:
The most common cause of the first variation of this violation is defining a clock that does not
behave as a clock. Removing the invalid clock definition corrects this problem.
Another common cause of the first variation of this violation is circuitry blockage that is in the way
of a clock pulse reaching the internal sequential device or memory element. This can occur when
a clock passes through an AND gate and the control size is 0, or an OR gate with a control side of
1.
Another possibility when the instance is a nonscan device is that there is another pin on the device
such as an asynchronous set or reset that is controlled from a primary input that has not been
defined as a clock. For example, a CLK pin has been defined as a clock but a RESETB pin has
not and so pulsing the CLK pin cannot capture data while RESETB=X. This can be corrected by
defining the missing clock.
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to constrain data and displays the failing
clock with gates along a path to a potential capture cell.
You might also want to switch the display to Clock Off data for a different perspective of the
problem.
After reviewing the cause of the violation you might want to continue by setting the severity of the
C4 rule to a warning using the set_rules command, and then re-issuing the run_drc
command.
There are certain signals identified as clocks that also generate C4 violations. These types of
clock signals are not connected to clock inputs of sequential elements; they are only connected to
data inputs. To review these clocks, use the report_clocks -verbose command, and
determine if a clock uses any sequential elements. You should not define signals without clock
usage as clocks; this affects the usage of these signals. If the design context requires these
signals to be identified as clocks even though they have no clock usage, you can use the set_
rules C4 –autofix command to remove violations for these types of signals. This option
does not remove the blocked clocks from generating C4 violations.

The explanation for the second variation of the C4 rule violation message (Multiple clocks
or a single clock through multiple paths drives scan-cell instance_
name during shift.) is as follows:

This variation of the violation is reported by the set_drc -check_multiple_shift_

clocks command and is normally ignored. But it can cause problems in static timing analysis or
simulations with full delays. Fixing it requires redesign or reconfiguration of the clock generation
circuitry of the affected scan cells.

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DRC Rule C5
Message Text
Clock Rule C5: Clock C can capture new data on LS input N of <type>
I1 (G1).
Source of violation: input N of <type>

Severity
Warning

Example
One example, many variations are possible:

Description
A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data might be
affected by new captured data.
C is the clock port; the <type> is either DLAT or DFF; I1 and I2 are instance pathnames; G1 and
G2 are gate IDs. Input N refers to the ATPG gate's inputs following the scheme 0=set, 1=reset,
2=clk1, 3=data1, 4=clk2, 5=data2...
There is a risk that test generation will not correctly control the new value that is captured, which
will result in a loss of test coverage. In this case, use the Fast-Sequential pattern operator and the
command set_atpg -lete_fastseq.
This check is performed using clock cone data. A potential rule violation occurs on a clock if a
clock input of a LS port is in the clock cone and its data input (including RAM address) is in the
effect cone. This port is called the sink port of a violation.
A list of all potential source ports for the violation is identified by tracing back from the sink data line
through gates in the effect cone. To be considered a violation, the source port must not be a
trailing edge (TE) port, the source port clock must be capable of being at an on state when the
sink port clock is at an on state, and the path from source to sink must be propagatable under this
condition.

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in the paths from the source port to the sink port, the clock to the source port, and the clock to the
sink port.
Use of the -mask option of the set_rules command can also be used to compensate for the
DRC violation. This causes the ATPG algorithm to mask off the observe value in an attempt to
ensure that any ATPG pattern generated will pass simulation. The tradeoff is that in doing this,
there is a reduction of test coverage.

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DRC Rule C6
Message Text
Clock Rule C6: Clock C can capture new data on TE input N of <type>
I1 (G1).
Source of violation: input N of <type> I2 (G2).

Severity
Warning

Example
One example, many variations are possible:

Description
A clock must not capture data into a trailing edge (TE) port if that data might be affected by new
captured data. In the violation message,
C is the clock port; the <type> is either DLAT or DFF; I1 and I2 are instance pathnames; G1 and
G2 are gate ID's.
There is a risk that test generation will not correctly control the new value that is captured resulting
in some loss of test coverage. In this case, use the fast sequential pattern operator and the
command set_atpg -lete_fastseq.
This check is performed using clock cone data and a potential rule violation occurs on a clock if a
clock input of a TE port is in the clock cone and its data input (including RAM address) is in the
effect cone. This port is called the sink port of a violation. To be considered a violation, the source
port must not be a TE port, the source port clock must be capable of being at 1 (0 if LE) when the
sink port clock is at 1, and the path from source to sink must be propagatable under this condition.
Note that C6 violations are not issued on DSLAVE cells. This is because ATPG uses these cells
only for controllability and does not observe data from them during scan chain unload.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to clock cone data and displays all gates
in the paths from the source port to the sink port, the clock to the source port, and the clock to the
sink port.
A list of all potential source ports for the violation is identified by tracing back from the sink clock
line through gates in both the clock and its effect cone.

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DRC Rule C7
Message Text
Clock Rule C7: Clock C can capture new data on LE input I1 of T1 N1
(G1).
Source of violation: input I2 of T2 N2 (G2).

Severity
Ignored

Description
A clock must not capture data into a leading edge (LE) port if that data might be affected by the
newly captured data.
Failure to satisfy this rule is not likely to result in a race condition. However, if a race condition
occurs this can lead to inaccurate simulation results and the creation of ATPG patterns which fail
simulation. Scan based simulation assumes that the values captured during a capture clock cycle
are the result of state element values that existed at the end of the load operation.
This check is performed using clock cone data and a potential rule violation occurs on a clock if a
clock input of a LE port is in the clock cone and its data input (including RAM address) is in the
effect cone. This port is called the sink port of a violation.
A list of all potential source ports for the violation is identified by tracing back from the sink data line
through gates in the effect cone. To be considered a violation, the source port must be an LS port,
the source port clock must be capable of being at 1 when the sink port clock is at 1, and the path
from source to sink must be propagatable under this condition.

What Next
You can analyze a violation using the schematic analysis by selecting its violation ID number. This
sets the gate reporting to the clock cone data and displays all gates in the paths from the source
port to the sink port, the clock to the source port, and the clock to the sink port.
Use the -mask option of the set_rules command to compensate for the DRC violation. By
setting the rule severity to warning and enabling the -mask option, this causes the ATPG
algorithm to mask off the control or observe functions, or both, in an attempt to ensure that any
ATPG pattern generated will pass simulation. The tradeoff is that in doing this, there is a reduction
of test coverage.

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DRC Rule C8
Message Text
Clock Rule C8: C clock path affected by new capture on LS input N
of <type> I1 (G1).
Source of violation: input N of <type> I2 (G2).

Severity
Warning

Example
One example, many variations are possible:

Description
The path from a clock to a level sensitive (LS) port must not be affected by its new captured data.
C is the clock port; the <type> is either DLAT or DFF; I1 and I2 are instance pathnames; G1 and
G2 are gate ID's.
Failure to satisfy this rule can result in a race condition which can create inaccurate ATPG
simulation results and lead to patterns that fail simulation. Scan based simulation continues to
assume that the values captured during a capture clock cycle are the result of state element
values that existed at the end of the load operation. This assumption could be false in the
presence of a race condition and produce patterns that fail simulation.
This check is performed using clock cone data and a potential rule violation occurs on a clock if a
clock input of a level sensitive port is in both the clock cone and effect cone. This port is called the
sink port of a violation. To be considered a violation, the source port must not be a TE port, the
source port clock must be capable of being at 1 when the sink port clock is at 1, and the path from
source to sink must be propagatable under this condition.

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algorithm to mask off the observe value, in an attempt to ensure that any ATPG pattern generated
will pass simulation. The tradeoff is a reduction of test coverage.

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DRC Rule C9
Message Text
Clock Rule C9: C clock path affected by new capture on TE input N1
of T1 I1 (G1).
Source of violation: input N2 of T2 I2 (G2).

Severity
Warning

Example
One example, many variations are possible:

Description
The path from a clock to a trailing edge port must not be affected by its new captured data.
C is the clock port name; N1/N2 are the input numbers of the ATPG primitive (set=0, rst=1,
clk1=2, data1=3...); T1/T2 are the primitive types of either DLAT or DFF; I1/I2 are the
instance pathnames containing the primitive; G1/G2 are the gate ID's of the primitives;
Failure to satisfy this rule results in an additional simulation pass to allow the trailing edge (TE)
port to capture new data from leading edge (LE) or level sensitive (LS) ports. There is also risk
that test generation will not correctly control the new value that is captured, which will result in
some loss of test coverage.
This check is performed using clock cone data and a rule violation occurs on a clock if a clock input
of a TE port is in both the clock cone and effect cone. This port is called the sink port of a violation.
To be considered a violation, the source port must not be a TE port, the source port clock must be
capable of being at 1 (0 if LE) when the sink port clock is at 1, and the path from source to sink
must be propagatable under this condition.

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DRC Rule C10

Message Text
Clock Rule C10: C clock path affected by new capture on LE input N1
of T1 I1 (G1).
Source of violation: input N2 of T2 I2 (G2).

Severity
Ignored

Description
The path from a clock to a leading edge (LE) port must not be affected by its new captured data.
C is the clock port name; N1/N2 are the input numbers of the ATPG primitive (set=0, rst=1,
clk1=2, data1=3...); T1/T2 are the primitive types of either DLAT or DFF; I1/I2 are the
instance pathnames containing the primitive; G1/G2 are the gate ID's of the primitives;
Failure to satisfy this rule is not likely to result in a race condition. If there is a race condition, then
inaccurate simulation results would be possible which would in turn lead to generation of ATPG
patterns which can fail in simulation.
This check is performed using clock cone data, and a potential rule violation occurs on a clock if a
clock input of a LE port is in both the clock cone and effect cone. This port is called the sink port of
a violation. To be considered a violation, the source port must be a level sensitive (LS) port, the
source port clock must be capable of being at 1 when the sink port clock is at 1, and the path from
source to sink must be propagatable under this condition.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZEbutton. This changes the pin data reporting to the clock cone data and displays all
gates in the paths from the source port to the sink port, the clock to the source port, and the clock
to the sink port.
A list of all potential source ports for the violation is identified by tracing back from the sink clock
line through gates in both the clock and its effect cone.
Use of the -mask option of the set_rules command to compensate for the DRC violation. By
setting the rule severity to warning and enabling the mask option, this causes the ATPG algorithm
to mask off the control or observe functions, or both, in an attempt to ensure that any ATPG
pattern generated will pass simulation. The tradeoff is that in doing this, there is a reduction of test
coverage.

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DRC Rule C11

Message Text
Clock Rule C11: Clock C connects to LS clock/data inputs N1/N2 of I
(G).

Severity
Warning

Example
One example, many variations are possible:

Description
A clock has a combinational path to both the data and clock ports of a level sensitive (LS) device.
C is the clock port name; N1/N2 are the input numbers of the ATPG primitive (set=0, rst=1,
clk1=2, data1=3...); I is the instance pathname containing the primitive; G is the gate ID of the
primitive;
A clock must not capture data for a level sensitive (LS) port whose data line is affected by the
clock.
Failure to satisfy this rule can result in a race condition, which can create inaccurate simulation
results. Simulation is performed assuming a captured data value for the clock at an on state. If this
assumption is not correct, patterns can fail simulation.
This check is performed by using clock cone data, and a rule violation occurs on a clock when a
clock input of a level sensitive clock line and its data line are in the same clock cone.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to the clock cone data and displays all
gates in the paths from the clock to both the clock input and data input of the failing port.
If the sequential element involved in the DRC violation is part of a scan chain, you might be able to
define a Cell Constraint of OX (observe X) for this cell and reduce the possibility of generating
ATPG patterns that fail simulation. This however, will result in a lowering of test coverage.
Use the -mask option of the set_rules command to compensate for the DRC violation. By
setting the rule severity to warning and enabling the -mask option, this causes the ATPG
algorithm to mask off the control or observe functions, or both, in an attempt to ensure that any

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ATPG pattern generated will pass simulation. The tradeoff is that in doing this, there is a reduction
of test coverage.

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DRC Rule C12

Message Text
Clock Rule C12: Clock C connects to LE clock/data inputs N1/N2 of I
(G).

Severity
Warning

Example
One example, many variations are possible:

Description
This check is performed using clock cone data. A violation occurs if a common path (a
combinational gate) from a defined clock affects both the data and clock ports of a leading edge
(LE) triggered sequential device.
The C in the diagram is the clock port name; N1/N2 are the input numbers of the ATPG primitive
(set=0, rst=1, clk1=2, data1=3...); I is the instance pathname containing the primitive; G is the
gate ID number of the primitive.
This violation identifies a potential race condition between the changing data input and the clock
capturing that data. TetraMAX ATPG cannot determine the actual timing between the two paths,
so it is not possible to determine which path is faster. By default, TetraMAX ATPG assumes the
clock path is faster for an LE device. When this assumption is incorrect, it is likely that any patterns
generated are incorrect and will fail in simulation.

What Next
You can analyze this violation by clicking the ANALYZE button in the schematic viewer and
selecting the violation ID. This changes the pin data reporting to clock cone data and displays all
gates in the paths from the clock to both the clock input and data input of the failing sequential
device.
After reviewing the design gates and paths, you can fix the violation by doing one or more of the
following:
l C12 violations are masked by default, and ATPG and simulation do not mask every capture
cycle. Determine if the cycle data remains stable and mask only unstable cycles. Also, if the
data change occurs when another register is clocked, the effects of that change are
considered to take place after the capture. In this case, do not mask any cycles.

l A race can be caused by clock skew. In this case, use a Synopsys Design Constraints

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(SDC) hold-time exception to mask the capture. For more information on SDC, see
Specifying Timing Exceptions from an SDC File.

Also note the following:

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to "constrain" data and displays the
failing cell with all of the gates in the back trace cone of the failing clock input.

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DRC Rule C16

Message Text
Clock Rule C16: Clock input N of nonscan T I (G) cannot capture
data.

Severity
Warning

Description
Each clock input of a nonscan cell must be capable of capturing data when a single clock is on and
all other clocks are off. Clock inputs include asynchronous set/reset inputs.
N is the input number of the ATPG primitive (set=0, rst=1, clk1=2, data1=3...); T is a gate type of
DFF or DLAT; I is the instance pathname to the device; G is the gate ID number of the device.
This check is performed using the simulated values that result when one clock is set to X, all other
clocks are at their off state, the constrained pins are set to their constrained value, and the
constant value nonscan cells are set to their constant state. The rule violation occurs when a clock
input of a scan cell always remains off.
A violation of this rule introduces no danger of generating bad patterns but is a warning that a
potential reduction of test coverage can result because the clock/set/reset input cannot be used
when performing Fast-Sequential ATPG.

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DRC Rule C17

Message Text
Clock Rule C17: Clock C is connected to primary output P.

Severity
Warning

Example
One example, many variations are possible:

Description
A clock should not have a path to a primary output consisting only of combinational gates. This
type of connection is referred to as a clock PO output. Faults along this path which require the
clock to be asserted for detection require a special type of pattern called a "Clock ON" pattern
which is, by default, not produced by TetraMAX ATPG. However, patterns are generated for
faults that can be detected with the clock off.
C is the clock port name; P is the primary output port name.
This check is performed by using the clock cone data, and a violation occurs when a primary
output (PO) is in a clock cone.
A violation of this rule introduces no danger of generating bad patterns but is a warning that there
might be a reduction in test coverage. The ATPG algorithm simulates an additional time frame,
which occurs before the capture clock. This is used to determine the correct values for the primary
outputs identified.

What Next
The generation of Clock ON patterns is enabled by using the -allow_clockon_measures of
the set_atpg command and by supplying appropriate procedures in the DRC procedure file.
Please Note that not all testers can support this type of pattern.
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to "clock cone" data and displays all
gates in the path from the clock to the failing primary output (PO).
One potential cause of this violation, in addition to the direct combinational path shown above, is a
bidirectional port used as a clock. You can ignore C17's occurring on bidirectional clock ports.

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DRC Rule C20

Message Text
Clock Rule C20: Clock PIs off failed to force off clock input N of
RAM I (G).

Severity
Warning

Example
One example, many variations are possible:

Description
When all clocks are at their off state, all clock/set/reset inputs of a MEMORY gate must be in their
inactive state.
N is an input starting with 0 at the top and counting down; I is an instance pathname to the
MEMORY; G is the gate ID of the MEMORY primitive.
Failure to satisfy this rule will result in the MEMORY gate being the equivalent of a TIEX gate for
Basic-Scan and Fast-Sequential pattern generation. A reduction in test coverage can occur but
can be recovered by using Full-Sequential pattern generation.
This check is performed using the simulated values that result when clocks are at their off state,
the constrained pins are set to their constrained value, and the constant value nonscan cells are
set to their constant state. The rule violation occurs if any clock/set/reset input of a MEMORY gate
is not at its inactive state.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This sets the pin data reporting to the simulation values of the clock-off
pattern and displays the failing MEMORY gate with all the gates in the backtrace cone of the
failing input. This identifies the failing clock input, and tracing back from this input can help you
identify how to correct the problem.
A common cause of this violation is having a primary input which controls MEMORY reads or
writes which is not defined as a clock.
If this violation cannot be corrected and the test coverage loss around the memory device is not
acceptable, you might wish to explore the use of Full-Sequential pattern generation to attempt to
create patterns which make use of the memory, despite this violation.

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Message Text
Clock Rule C26: clock as data different from capture clock for
stable cell.

Message Text
Clock Rule C35: Multiple sensitizations between PLL source and
internal clock.

Severity
Error

Description
The conditions defined for each cycle of an internal clock must sensitize the path between the
corresponding PLL source and the internal clock for a single PLL clock pulse.
TetraMAX ATPG expects control over the conditioning of internal clocks from one capture cycle to
the next (cycle-specific conditioning).
This check cannot be performed on a clock that fails a C34 check.

What Next
Some OCC controllers use one control bit to enable a double pulse. This type of controller violates
a C35 check because it is impossible to control the pulses separately. This clock conditioning is
suitable for two-clock transition-delay testing using common launch and capture clocks, but not for
any other purpose. If this limitation is acceptable, you can downgrade the C35 rule using the
command set_rules C35 warning.

You should verify that the PLL clock controller can accommodate cycle-specific conditioning of the
internal clocks. A PLL cycle counter is a typical solution, in which the outputs of the counter are
used to gate the internal clock conditioning values.
The following examples show how to define internal clocks:

add_clocks 0 intclk3 -intclock -pll_source u1/pllclk3 \

-cycle { 0 clock_chain/cell[5]/Q 1 \
1 clock_chain/cell[4]/Q 1 }

add_clocks 0 intclk2 -intclock -pll_source u1/pllclk2 \

-cycle { 0 clock_chain/cell[3]/Q 1 \
1 clock_chain/cell[2]/Q 1 }

add_clocks 0 intclk1 -intclock -pll_source u1/pllclk1 \

-cycle { 0 clock_chain/cell[1]/Q 1 \
1 clock_chain/cell[0]/Q 1 }

A counter keeps track of the number of clock pulses from the PLL since the start of the capture
cycle. It needs to keep track of as many cycles as the maximum number defined in any one single
add_clocks command. Each cycle number is ANDed with the corresponding clock chain bit
and the results are then ORed together to enable the clock pulse to pass through the clock MUX.

Count (value) 1 is ANDed with bit[1]

Severity
Error

Example
One example, many variations are possible:

Description
This violation occurs when a nonlogical clock propagates to any scan cell input. Nonlogical clocks
include reference clocks and controller clocks declared with the set_drc -controller_
clock command.
TetraMAX ATPG will not simulate the effect of pulsing the nonlogical clocks on scan cells. Failure
to satisfy this rule can result in patterns which fail in simulation.

What Next
A PLL that is not modeled as a black box is a common source of this violation. In this case,
reference clocks might propagate to the scan cell through the PLL logic. You can use the set_
build -black_box command to explicitly declare a PLL module as a black box.
If the C39 violation appears, the patterns might fail simulation because clock pulses that are
unsimulated by both ATPG and run_simulation can appear before, during, and after the
ATPG capture cycles. If a C39 violation cannot be prevented, you can downgrade it to a warning
using the set_rules command. In addition, you should use the command add_cell_
constraints XX to both load and unload all unknown values on the affected registers.
By default, TetraMAX ATPG prints only one message for each clock that causes a C39 violation.
You can use the set_rules c39 warning -verbose command to print out an expanded
list of C39 clock rules violation information. In this case, every scan cell affected by a C39 violation
is printed.

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The following example shows the default output that result after specifying the set_rules c39
warning command:
set_rules c39 warning
report_violations C39

Warning: Nonlogical clock dft_clock connects to 4 scancells

(u1/ci_reg_3_ (827)). (C39-1)
Warning: Nonlogical clock clkref connects to 19 scancells
(u8/LOCKUP (812)). (C39-2)
The next example shows the output after using the set_rules c39 warning -verbose
option. Note, in this case, that the set_rules command must be specified before the run_drc
command or the violations will not be calculated using a verbose methodology.
set_rules c39 warning -verbose
...
run_drc
...
report_violations C39

Warning: Nonlogical clock dft_clock connects to scancell u1/ci_

reg_3_ (827). (C39-1)
Warning: Nonlogical clock dft_clock connects to scancell u1/ci_
reg_2_ (828). (C39-2)
Warning: Nonlogical clock dft_clock connects to scancell u1/ci_
reg_0_ (829). (C39-3)
Warning: Nonlogical clock dft_clock connects to scancell u1/ci_
reg_1_ (836). (C39-4)
Warning: Nonlogical clock clkref connects to scancell u8/LOCKUP
(812). (C39-5)
Warning: Nonlogical clock clkref connects to scancell u8/ai_reg_3_
(873). (C39-6)
.
.
.

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DRC Rule C40

Message Text
Clock Rule C40
Internal clock gate_id is restricted due to <reason>.
Clock Rule C40-1 Internal clock name is restricted due to its
<time> latency not aligning with its controller's <time> latency.

Severity
Warning

Description
The C40 rule applies only to synchronized internal clocks (declared in a SynchronizedClocks
block of the STIL procedure file). TetraMAX ATPG manipulates the clock chain data for
synchronized clocks to compensate for different periods or start-up latencies. This warning
indicates that DRC has encountered a configuration that prevents such manipulation, and the
clock is flagged as restricted. A restricted clock cannot be activated in the same pattern as another
clock of the same sync group, unless both clocks have the same period and latency. Internal
clocks with the same period and latency do not require special clock chain manipulation.
The C40 warning is triggered by ATPG or cell constraints on the clock chain or PLL condition
nets. It is also triggered by unsupported clock controller configurations in which the one-to-one
relationship between clock chain bits and internal clock pulses is violated. Some examples of
unsupported configurations are shared clock chain bits (either within or across clock controllers),
or complex logic driving the PLL conditions.

What Next
You should evaluate the described constraints to see if they can be eliminated or moved away
from the clock controller logic.
In most cases, you can ignore this warning and accept the clocking restrictions. This might result
in pattern inflation or a reduction in fault coverage.
As a last resort, you can remove the clock from the SynchronizedClocks block of the STIL
procedure file. This will eliminate all of the synchronized clock ATPG restrictions, as TetraMAX
ATPG is ignorant of the timing for this clock. In this case, you should be careful to simulate the
patterns outside of TetraMAX ATPG to validate the ATPG timing assumptions.
If you get a C40-1 message, you will need to adjust the latency for multiple synchronized clocks on
the same controller, and should refer to the details specified in the corresponding M722 message.

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DRC Rule C41

Message Text
Clock Rule C41:Internal clocks gate_id and gate_id are equivalent.

Severity
Warning

Description
The two clocks noted in this message have been identified as equivalent clocks, which means
they will always both be active or inactive together. However, clock-grouping analysis has
determined that these two clocks cannot both be active in the same capture context.
This conflict of clocking behavior must be resolved to generate patterns that will work at test.
Downgrading this error to pass DRC will likely generate patterns with M285 messages during
ATPG. Continuing to APTG will likely result in patterns that will fail at test.

What Next
If the clocks always pulse simultaneously and are skew-balanced in the design, the patterns
generated by ATPG will be correct. However, if the clocks are not both simultaneous and skew-
balanced, the patterns generated with M285 messages will be incorrect and will fail at test or with
full-timing simulation.

Review the grouping opportunities for these clocks using the command report_clocks -
matrix. Consider design or constraint changes to allow these clocks to be grouped.
Review the conditions or constraints on these clocks that cause them to be identified as
equivalent. For instance, "always on" conditions for internal clocks will cause these clocks to be
equivalent. Consider reducing these constraints to allow the clocks to be independent.
As a last resort, consider removing the definition of one or the other clock, and running DRC
without the combination of clocks present. This will require multiple DRC and ATPG passes to
process each clock separately.

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DRC Rule D8
Message Text
DRC Rule D8: Clock C cannot capture data with other clocks off

Message Text
DRC Rule D16: C clock path affected by new capture on TE input I1
of <type> S1.
Source of violation: input I2 of <type> S2.

Severity
Warning

Example
One example, many variations are possible:

Description
The path from a clock to a trailing edge input must not be affected by its new captured data.
C is the clock port; the <type> is either DLAT (latch) or DFF (flip-flop); I1 and I2 are input pin
names; S1 and S2 are cell names.
Failure to satisfy this rule results in an additional simulation pass to allow the trailing edge (TE)
port to capture new data from leading edge (LE) or level sensitive (LS) ports. There is also risk
that test generation will not correctly control the new value that is captured, which will result in
some loss of test coverage.
This check is performed using clock cone data and a rule violation occurs on a clock if a clock input
of a TE port is in both the clock cone and effect cone. This port is called the sink port of a violation.
To be considered a violation, the source port must not be a TE port, the source port clock must be
capable of being at 1 (0 if LE) when the sink port clock is at 1, and the path from source to sink
must be propagatable under this condition.

TetraMAX DRC Rules O-2018.06

K46
K47
K48
K49
K50
K51
K52
K53
K54
K55
K56
K57
K58
K59
K60
K61
K62
K63
K64
K65
K66
K67
K68
K69
K70
K71
K72
K73
K74
K75
K76
K77

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DRC Rule K1

Message
DFTMAX LBIST Rule K1: Invalid length of codec_drc_chain compressor
chain length L1 did not equal expected length L2.

Severity
Fatal Error

Description
Note the following:
l L1 indicates calculated length of codec_drc_chain

l L2 indicates expected length of codec_drc_chain from the STL procedures file (SPF)

The codec_drc_chain is traced back from its defined chain output port using the simulated values
of the CODEC_DRC_LOAD_UNLOAD and CODEC_DRC_SHIFT procedures. If the number of
scan cells identified by this tracing does not equal the expected number of cells, the K1 rule
violation is issued. The expected number of cells in the particular codec_drc_chain is the sum of
the lengths of the following registers defined in the SPF:
l CarePRPG registers

l XTOLPRPG registers

l MISR registers

l PRPGShadow registers

l CARE_shadow registers

l XTOLShadow registers

l XTOL_enable registers (always 1)

Description
Note the following:
l S indicates name of failing DFTMAX LBIST CODEC

l N is the failing output ID

The nodes corresponding to the CarePRPG hold output, the XTOLPRPG hold output, and the
XTOLPRPG observe mode selection outputs are inferred based on their defined connections to
their associated PRPGs. This inference is accomplished by performing parallel (32) pattern
simulation using the simulated values of the SHIFT procedure and placing random values on the
PRPG cells. Gates connected to the cone of influence of the PRPGs cells are inspected to identify
any gate which is at the expected values or the inverse value. Expected values are calculated by
exclusive-ORing the values assigned to the associated connecting PRPG cells. A violation is
issued if a gate cannot be found at the expected value.

What Next
To correct this problem, edit the netlist or the STL procedure file so the failing PRPG output can
be identified. You can use automated violation analysis to help debug this problem. This analysis
displays the PRPG cells connected to the failing PRPG output. The displayed pin data is set to the
simulated values of the SHIFT procedure with binary values assigned to the connecting PRPG
cells. Gates which are at a binary value that are in the fanout cone of the PRPG cells are also
displayed.

You can use the -hold_connections option of the report_compressors command to

report the connecting PRPG cells.

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DRC Rule K4

Message
DFTMAX LBIST Rule K4: Chain output could not be identified
Output of chain C in compressor S could not be identified.

Severity
Fatal Error

Description
Note the following:
l C indicates name of failing chain

l S indicates name of DFTMAX SEQ CODEC used for failing chain

The nodes corresponding to the outputs of internal chains are inferred based on their defined
connections to their associated MISR during single observe mode conditions. This inference is
done by performing simulation using the simulated values of the SHIFT procedure, and placing
the XTOL_enable cells to their on state, and XTOLPRPG outputs to select the single observe
mode of the given chain. A traceback is performed from the data input of the first connecting
MISR cell through gates set to X identifying potential chain output cell candidates. If no candidates
or more than one candidate can be found, a violation is issued.

What Next
To correct this problem, the netlist or the STIL protocol file must be changed so that the failing
chain output can be identified. The automated violation analysis can be used to help debug this
problem. This analysis will display the first connecting MISR cell for the failing chain. The
displayed pin data is set to the simulated values of the SHIFT procedure with XTOL_enable cells
set on and XTOLPRPG outputs set to the single observe mode of the failing chain. Gates in the
traceback cone from the first connecting MISR cell which are set to X are also displayed.

After you pull a K4 violation up in the GSV, start tracing back from the MISR bit on the right. That
bit should have an x on its D input (but from the scan chain, not from an X (unknown) driving the
scan chain…). 0 and 1 are wrong (bad) values. Following back in the circuit from this bit, you will
run into another MISR bit. That is the wrong path. Keep going back on the other path (of the XOR)
until you get deep into the XOR tree of the compactor. These XORs lead back to AND or OR
gates. These are the masking gates. MOST of these AND/OR gates will have a 0/1 on one leg
and an X on the other. The 0s and 1s are BLOCKING the x. The x is from a scan chain. Find the
AND/OR gate with a 1/0 on one leg and a 0/1/X on the other. X (as I mentioned) is “good” unless it
is from a real UNKNOWN… 0 and 1 on the scan data path are likely from static values or reset
signals.

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until you get deep into the XOR tree of the compactor. These XORs lead back to AND or OR
gates. These are the masking gates. MOST of these AND/OR gates will have a 0/1 on one leg
and an X on the other. The 0s and 1s are BLOCKING the x. The x is from a scan chain. Find the
AND/OR gate with a 1/0 on one leg and a 0/1/X on the other. X (as I mentioned) is “good” unless it
is from a real UNKNOWN… 0 and 1 on the scan data path are likely from static values or reset
signals.

Following the XOR tree back goes to a lot of AND and OR gates (the mask gates, as mentioned).
You are looking for the non-XOR gates which have NO “x” on the inputs. Usually, that x is being
blocked (a good thing) by the other gate inputs (0 on AND, 1 on OR). You will eventually find an
XOR fed by a gate that has all 1s and 0s on the inputs. Or a passing value on most inputs, but an X
on the last. This is an "unknown" X value.

In summary: analyze_violation; trace XOR tree until you hit some OTHER logic gates; see
if these gates are set to BLOCK or PASS a value. If passing a value, that value should be x. If it IS
an X (all the way to the initial MISR bit pulled up by analyze_violation) then why is it X? If a 1 or 0,
why is it 1 or 0 and not x?

The -lfsr_connections option of the report_compressors command can be used to

report the chain-to-MISR connections.

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DRC Rule K5

Message
DFTMAX LBIST Rule K5 : Invalid MISR capture value for no_observe
mode
N MISR cells (P/G) in compressor S had invalid capture data for no_
observe mode.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select the no observe mode, the data inputs of MISR cells are checked to ensure that they are
successfully blocked (set to 0). This checking is done by performing parallel (32) pattern
simulation using the simulated values of the SHIFT procedure, and placing MISR cells to 0,
XTOL_enable cells to their on state, and XTOLPRPG outputs to select the no observe mode.
Data inputs of MISR cells which are not at 0 for all of the simulated parallel patterns will result in a
violation of this rule. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
input of the failing MISR cell is properly blocked in no observe mode. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell for
the failing MISR. The displayed pin data is set to the simulated values of the SHIFT procedure
with MISR cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG outputs set to
select the no observe mode. Gates in the paths between XTOLPRPG outputs used to select the
no observe mode and the failing MISR cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause patterns which exercise the no observe mode to be incorrect.

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DRC Rule K6

Message
DFTMAX LBIST Rule K6: Invalid MISR capture value for single_observe
mode unblocked cell
N MISR unblocked cells (P/G1) in compressor S had invalid capture
data for single_observe mode of chain C (G2).

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G1 indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l C indicates name of chain observed with single observe mode

l G2 indicates gate ID of chain output

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select the single observe mode for a given chain, the data inputs of unblocked MISR cells are
checked to ensure that they are successfully capturing data from the chain output. This checking
is done by performing parallel (32) pattern simulation using the simulated values of the SHIFT
procedure, and placing the chain outputs to random values, MISR cells to 0, XTOL_enable cells
to their on state, and XTOLPRPG outputs to select the single observe mode for the desired chain.
Data inputs of unblocked MISR cells which are not at the same value as the chain output (or
inverted) for all of the simulated parallel patterns will result in a violation of this rule. Only one
violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
input of the failing MISR cell is successfully capturing data from the chain output in the single
observe mode of the failing chain. The automated violation analysis can be used to help debug
this problem. This analysis will display the first failing cell for the failing MISR. The displayed pin
data is set to the simulated values of the SHIFT procedure with chain outputs set to a random
binary value, MISR cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG
outputs set to select the single observe mode for the chain. Gates in the paths between
XTOLPRPG outputs used to select the single observe mode and the failing MISR cell are also
displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

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The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -chain_modes option of the report_compressors command can be used to report the
XTOLPRPG output values for the single observe mode for chains.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the single observe mode for this chain to be incorrect.

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DRC Rule K7

Message
DFTMAX LBIST Rule K7: Invalid MISR capture value for single_observe
mode blocked cell
N MISR blocked cells (P/G1) in compressor S had invalid capture
data for single_observe mode of chain C (G2).

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G1 indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l C indicates name of chain observed with single observe mode

l G2 indicates gate ID of chain output

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select the single observe mode for a given chain, the data inputs of blocked MISR cells are
checked to ensure that they are successfully blocked (set to 0). This checking is done by
performing parallel (32) pattern simulation using the simulated values of the SHIFT procedure,
and placing the chain outputs to random values, MISR cells to 0, XTOL_enable cells to their on
state, and XTOLPRPG outputs to select the single observe mode for the desired chain. Data
inputs of blocked MISR cells which are not at 0 for all of the simulated parallel patterns will result in
a violation of this rule. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
input of the failing MISR cell is properly blocked in the single observe mode of the failing chain.
The automated violation analysis can be used to help debug this problem. This analysis will
display the first failing cell for the failing MISR. The displayed pin data is set to the simulated
values of the SHIFT procedure with chain outputs set to a random binary value, MISR cells set to
0, XTOL_enable cells set to their on state, and XTOLPRPG outputs set to select the single
observe mode for the chain. Gates in the paths between XTOLPRPG outputs used to select the
single observe mode and the failing MISR cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

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The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -chain_modes option of the report_compressors command can be used to report the
XTOLPRPG output values for the single observe mode for chains.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

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DRC Rule K8

Message
DFTMAX LBIST Rule K8: Different chain output to MISR inversion
parity
Cells P1/G1 and P2/G2 of MISR in compressor S had different
inversion parity for single_observe mode of chain C (G3)

Severity
Error

Description
Note the following:
l P1 indicates position of first cell of failing pair in the MISR

l G1indicates gate ID of first cell of failing pair in the MISR

l P2 indicates position of second cell of failing pair in the MISR

l G2 indicates gate ID of second cell of failing pair in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l C indicates name of chain observed with single observe mode

l G3 indicates gate ID of chain output

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select the single observe mode for a given chain, the inversion parity between data inputs of
unblocked MISR cells and the chain output are checked to ensure they are all the same. This
checking is done by performing parallel (32) pattern simulation using the simulated values of the
SHIFT procedure, and placing the chain outputs to random values, MISR cells to 0, XTOL_
enable cells to their on state, and XTOLPRPG outputs to select the single observe mode for the
desired chain. Any 2 data inputs of unblocked MISR cells which have differing inversion parity will
result in a violation of this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
inputs of the failing MISR cells have the same inversion parity in the single observe mode of the
failing chain. The automated violation analysis can be used to help debug this problem. This
analysis will display the 2 failing cells for the failing MISR. The displayed pin data is set to the
simulated values of the SHIFT procedure with chain outputs set to a random binary value, MISR
cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG outputs set to select the
single observe mode for the chain. Gates in the paths between the chain output and the failing
MISR cells are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

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The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -chain_modes option of the report_compressors command can be used to report the
XTOLPRPG output values for the single observe mode for chains.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause incorrect patterns for all observe modes.

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DRC Rule K9

Message
DFTMAX LBIST Rule K9: Invalid MISR capture value for full_observe
mode
N MISR cells (P/G) in compressor S had invalid capture data for
full_observe mode.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select the full observe mode, the data inputs of MISR cells are checked to ensure that they are
successfully capturing data from their connecting chains. This checking is done by performing
parallel (32) pattern simulation using the simulated values of the SHIFT procedure, and placing
the chain outputs to random values, MISR cells to 0, XTOL_enable cells to their on state, and
XTOLPRPG outputs to select the full observe mode. Data inputs of MISR cells which are not at
their expected value for all of the simulated parallel patterns will result in a violation of this rule.
The expected value is calculated by exclusiving-ORing the values for all the chain outputs that are
connected to a MISR cell input with consideration given to their precalculated inversion parity.
Only one violation is issued for a given MISR.

If the previous check passes and the XTOLPRPG outputs are not all initialized to binary values
during the test-setup procedure, the full-observe capture mode is also checked to ensure it works
correctly when the XTOL_enable cells are set to their off state and the XTOLPRPG outputs are
set to X. When a failure occurs due to this check of K9, the text of the violation message is
changed to indicate global full_observe mode.

If there are no failures due to either of the previous checks, the full-observe capture mode is also
checked for each X-chain to ensure it works correctly when the XTOL_enable cells are set to their
on state and the XTOLPRPG outputs are set to select the single observe mode for that X-chain.
When a failure occurs due to this check of K9, the text of the violation message is changed to
indicate global full_observe mode and also report the name of a failing X-chain.

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analysis will display the first failing cell for the failing MISR. Gates in the paths between
XTOLPRPG outputs used to select the full observe mode and the failing MISR cell are also
displayed. The displayed pin data is set to one of the following:

type 1 - The simulated values of the SHIFT procedure with chain outputs set to a random binary
value, MISR cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG outputs set to
select the full observe mode.

type 2 - The simulated values of the SHIFT procedure with chain outputs set to a random binary
value, MISR cells set to 0, XTOL_enable cells set to their off state, and XTOLPRPG outputs set to
X. A frequent cause of this failure type is the usage of complex synthesized circuitry which exploit
X and X-BAR effects to force the full observe mode when XTOL_enable is set off. This can be
corrected by either initializing the XTOLPRPG outputs in test_setup or running synthesis using
options that avoid this problem.

type 3 - The simulated values of the SHIFT procedure with chain outputs set to a random binary
value, MISR cells set to 0, XTOL_enable cells set to their off state, and XTOLPRPG outputs set to
select the single observe mode of the failing X-chain.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the full observe mode to be incorrect.

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DRC Rule K10

Message
DFTMAX LBIST Rule K10: Invalid MISR capture value for multiple_
observe mode
N MISR cells (P/G) in compressor S had invalid capture data for F
multiple_observe mode.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l F indicates fraction of scancells observed by multiple_observe mode

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select a multiple observe mode, the data inputs of MISR cells are checked to ensure that they are
successfully capturing data from their connecting chains. This checking is done by performing
parallel (32) pattern simulation using the simulated values of the SHIFT procedure, and placing
the chain outputs to random values, MISR cells to 0, XTOL_enable cells to their on state, and
XTOLPRPG outputs to select the multiple observe mode. Data inputs of MISR cells which are not
at their expected value for all of the simulated parallel patterns will result in a violation of this rule.
The expected value is calculated by exclusiving-ORing the values for all the chain outputs that are
connected to a MISR cell input with consideration given to their precalculated inversion parity.
Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
input of the failing MISR cell is properly capturing data from all of its chain connections in the
multiple observe mode. The automated violation analysis can be used to help debug this problem.
This analysis will display the first failing cell for the failing MISR. The displayed pin data is set to
the simulated values of the SHIFT procedure with chain outputs set to a random binary value,
MISR cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG outputs set to select
the multiple observe mode. Gates in the paths between XTOLPRPG outputs used to select the
multiple observe mode and the failing MISR cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

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The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -chain_modes option of the report_compressors command can be sed to report the
XTOLPRPG output values for the multiple observe modes for chains.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this multiple observe mode to be incorrect.

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DRC Rule K11

Message
DFTMAX LBIST Rule K11: Invalid MISR capture value for complement
multiple_observe mode
N MISR cells (P/G) in compressor S had invalid capture data for F
multiple_observe mode.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l F indicates fraction of scancells observed by multiple_observe mode

When the XTOL_enable cells are set to their on state and the XTOLPRPG outputs are set to
select a complement multiple observe mode, the data inputs of MISR cells are checked to ensure
that they are successfully capturing data from their connecting chains. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the SHIFT procedure,
and placing the chain outputs to random values, MISR cells to 0, XTOL_enable cells to their on
state, and XTOLPRPG outputs to select the complement multiple observe mode. Data inputs of
MISR cells which are not at their expected value for all of the simulated parallel patterns will result
in a violation of this rule. The expected value is calculated by exclusiving-oring the values for all
the chain outputs that are connected to a MISR cell input with consideration given to their
precalculated inversion parity. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the data
input of the failing MISR cell is properly capturing data from all of its chain connections in the
complement multiple observe mode. The automated violation analysis can be used to help debug
this problem. This analysis will display the first failing cell for the failing MISR. The displayed pin
data is set to the simulated values of the SHIFT procedure with chain outputs set to a random
binary value, MISR cells set to 0, XTOL_enable cells set to their on state, and XTOLPRPG
outputs set to select the complement multiple observe mode. Gates in the paths between
XTOLPRPG outputs used to select the complement multiple observe mode and the failing MISR
cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or MISR cells.

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The -lfsr_connections option of the report_compressors command can be used to

report the XTOLPRPG outputs.

The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values for all observe modes.

The -chain_modes option of the report_compressors command can be used to report the
XTOLPRPG output values for the complement multiple observe modes for chains.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this complement multiple observe mode to be incorrect.

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DRC Rule K1

Message
DFTMAX LBIST Rule K12: Invalid MISR capture shift operation
N MISR cells (input I of P/G) in compressor S had invalid shift
values during X procedure.
Severity:Error

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l F indicates fraction of scancells observed by multiple_observe mode

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the MISR cells are
checked to ensure that they are successfully capturing data as expected for full observe mode
during the SHIFT and RESEED_OVERLAP_SHIFT procedures. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, and placing the chain outputs to random values, XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. MISR cells which do not
successfully capture their expected value for all of the simulated parallel patterns will result in a
violation of this rule. The expected value is calculated by exclusiving-ORing the values for all the
chain outputs that are connected to a MISR cell input with consideration given to their
precalculated inversion parity and also for MISR tapping. Only one violation is issued for a given
MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that MISR cells
are properly capturing data in full observe mode as controlled directly by the XTOL_enable cells
during the specified procedure. The automated violation analysis can be used to help debug this
problem. This analysis will display the first failing cell for the failing MISR. If the failure occurred on
a clock/set/reset input, then the pindata is the simulated value for the indicated procedure and all
gates in the traceback cone of this input are also displayed. Otherwise, the displayed pin data is
set to one of the parallel pattern values that failed and gates in the paths between connecting
chains and the failing MISR cell are also displayed.

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The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or MISR cells.

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this MISR capture shift operation to be incorrect.

Category K - LBIST Rules 161

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DRC Rule K13

Message
DFTMAX LBIST Rule K13: Invalid MISR unload operation
N MISR cells (input I of P/G) in compressor S had invalid unload
value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l I indicates input ID of first failing cell in the MISR

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR
l S indicates name of DFTMAX CODEC associated with failing MISR
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the MISR cells are
checked to ensure that they are successfully unloading data during the RESEED_WITH_MISR_
SHIFT procedure. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing the chain outputs to random values,
XTOL_enable and Power_enable cells to their off state, and all other register types to random
values. MISR cells which do not successfully unload their value for all of the simulated parallel
patterns will result in a violation of this rule. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that MISR cells
are properly unloading data during the specified procedure. The automated violation analysis can
be used to help debug this problem. This analysis will display the first failing cell for the failing
MISR. If the failure occurred on a clock/set/reset input, then the pindata is set to the simulated
values for the indicated procedure and all gates in the traceback cone of this input are also
displayed. Otherwise, the displayed pin data is set to one of the parallel pattern values that failed
and gates in the path between the failing MISR cell and the its adjacent cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or MISR cells

The -lfsr_connections option of the report_compressors command can be used to

report the connections between chains and the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this MISR capture shift operation to be incorrect.

Category K - LBIST Rules 162

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DRC Rule K14

Message
DFTMAX LBIST Rule K14: Invalid MISR load input
N MISR cells (P/G) in compressor S had invalid load input value
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the MISR cells at the
beginning of an unload segment are checked to ensure that they are successfully resetting the
MISR to 0 during the RESEED_WITH_MISR_SHIFT procedure. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, and placing the chain outputs to random values, XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. MISR cells at the beginning of
a segment which do not successfully capture a 0 for all of the simulated parallel patterns will result
in a violation of this rule. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that MISR input
ports are properly propagating values to the MISR during the specified procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
first failing cell for the failing MISR. If the failure occurred on a clock/set/reset input, then the
pindata is set to the simulated values for the indicated procedure and all gates in the traceback
cone of this input are also displayed. Otherwise, the displayed pin data is set to one of the parallel
pattern values that failed and gates in the path between the failing MISR input port and the its
associated MISR cell are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or PRPG_shadow cells.

The -chain_segments option of the report_compressors command can be used to

report the unload segments of the MISRs.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this MISR reset operation to be incorrect.

Category K - LBIST Rules 163

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DRC Rule K15

Message
DFTMAX LBIST Rule K15: Invalid MISR unload output
MISR output O value not equal MISR cell (P/G) in compressor S
during X procedure

Severity
Error

Description
Note the following:
l O indicates name of MISR output port

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the MISR output ports
are checked to ensure that they are successfully unloading data during the RESEED_WITH_
MISR_SHIFT procedure. This checking is done by performing parallel (32) pattern simulation
using the simulated values of the appropriate procedure, and placing the chain outputs to random
values, XTOL_enable cells and Power_enable to their off state, and all other register types to
random values. MISR output ports which do not successfully have the same value as their
associated MISR cell for all of the simulated parallel patterns will result in a violation of this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that MISR
output ports are properly receiving values from the MISR during the specified procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
failing cell for the failing MISR. The displayed pin data is set to one of the parallel pattern values
that failed and gates in the path between the failing MISR output port and its associated MISR cell
are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or PRPG_shadow cells

The -chain_segments option of the report_compressors command can be used to

report the output ports of the MISR.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this MISR unload operation to be incorrect.

Category K - LBIST Rules 164

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DRC Rule K16

Message
DFTMAX LBIST Rule K16: MISR cell disturb
N MISR cells (P/G) in compressor S were disturbed during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the MISR cells are
checked to ensure that they hold state during the RESEED_SHIFT, SHADOW_TO_
CAREPRPG, SHADOW_TO_XTOLPRPG, and OCC_SHIFT procedures and also during the
capture cycles. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing the chain outputs to random values,
XTOL_enable and Power_enable cells to their off state, and all other register types to random
values. MISR cells which do not hold state for all of the simulated parallel patterns will result in a
violation of this rule. Only one violation is issued for a given MISR.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that MISR cells
hold state during the specified procedure. The automated violation analysis can be used to help
debug this problem. This analysis will display the first failing cell for the failing MISR with all the
gates in the traceback cone of the input which was believed to have caused the problem. If the
failing procedure was the capture procedure, then the displayed pin data is set to one of the
parallel pattern values that failed. Otherwise, the pindata is set to the simulated values of the
failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or PRPG_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise this MISR unload operation to be incorrect.

Category K - LBIST Rules 165

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DRC Rule K17

Message
DFTMAX LBIST Rule K17: Invalid PRPG_shadow load operation
N PRPG_shadow cells (input I of P/G) in compressor S had invalid
value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing PRPG_shadow cells

l I indicates input ID of first failing cell in the PRPG_shadow register

l Pindicates position of first failing cell in the PRPG_shadow register

l G indicates gate ID of first failing cell in the PRPG_shadow register
l S indicates name of DFTMAX CODEC associated with the failing PRPG_shadow register
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the PRPG_shadow
cells are checked to ensure that they are successfully loading data during the RESEED_WITH_
MISR_SHIFT, RESEED_SHIFT, and RESEED_OVERLAP_SHIFT procedures. This checking
is done by performing parallel (32) pattern simulation using the simulated values of the
appropriate procedure, and placing the PRPG_shadow input ports to random values, XTOL_
enable and Power_enable cells to their off state, and all other register types to random values.
Prpg_shadow cells which do not successfully capture their expected value for all of the simulated
parallel patterns will result in a violation of this rule. The expected value for cells which connect to
PRPG_shadow input ports are the values assigned to the input port (or inverted). The expected
values for all other cells are the values assigned to the adjacent cells. Only one violation is issued
for a given PRPG_shadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that PRPG_
shadow cells are properly capturing data during the specified procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell of the
failing PRPG_shadow register. If the failure occurred on a clock/set/reset input, then the pindata
is set to the simulated values for the indicated procedure and all gates in the traceback cone of this
input are also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern
values that failed and gates in the path between the failing cell and the source of its capture data
are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or PRPG_shadow cells

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The -chain_segments option of the report_compressors command can be used to

report the unload segments of the MISRs.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the reseed operation to be incorrect.

Category K - LBIST Rules 167

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DRC Rule K18

Message
DFTMAX LBIST Rule K18: PRPG_shadow cell disturb
N PRPG_shadow cells (P/G) in compressor S were disturbed during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing MISR cells

l Pindicates position of first failing cell in the MISR

l G indicates gate ID of first failing cell in the MISR

l S indicates name of DFTMAX CODEC associated with failing MISR

l X indicates name of procedure

This rule is not currently checked.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or CarePRPG cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the scan chain load operation from PRPGs to be incorrect.

Category K - LBIST Rules 171

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DRC Rule K22

Message
DFTMAX LBIST Rule K22: Invalid XTOLPRPG shift operation
(input I of P/G) in compressor S had invalid shift values during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLPRPG

l I indicates input ID of first failing cell in the XTOLPRPG

l Pindicates position of first failing cell in the XTOLPRPG

l G indicates gate ID of first failing cell in the XTOLPRPG
l S indicates name of DFTMAX CODEC associated with failing XTOLPRPG
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the XTOLPRPG cells
are checked to ensure that they are successfully shifting data during the SHIFT and RESEED_
OVERLAP_SHIFT procedures. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, and placing XTOL_enable
and Power_enable cells to their off state, and all other register types to random values.
XTOLPRPG cells which do not successfully capture their expected value for all of the simulated
parallel patterns will result in a violation of this rule. The expected value for cells considers the
PRPG definition with tapping. Only one violation is issued for a given XTOLPRPG.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that
XTOLPRPG cells are properly shifting during the specified procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell of the
failing XTOLPRPG register. If the failure occurred on a clock/set/reset input, then the pindata is
set to the simulated values for the indicated procedure and all gates in the traceback cone of this
input are also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern
values that failed, and gates in the path between the failing cell and the sources of its capture data
are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or XTOLPRPG cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the observe mode control during the MISR capture operation from
internal chains to be incorrect.

Category K - LBIST Rules 172

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DRC Rule K23

Message
DFTMAX LBIST Rule K23: Invalid XTOLPRPG reload operation
Seq compressor chain length L1 did not equal expected length L2.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLPRPG

l I indicates input ID of first failing cell in the XTOLPRPG

l Pindicates position of first failing cell in the XTOLPRPG

l X indicates name of procedure

When the Power_enable cell is set to its on state and the hold ability is activated for CarePRPGs,
the CARE_shadow cells are checked to ensure that they are successfully holding state during the
SHIFT and RESEED_OVERLAP_SHIFT procedures. This checking is done by performing
parallel (32) pattern simulation using the simulated values of the appropriate procedure, and
placing Power_enable to its on state, activating the hold ability of the CarePRPG, and placing all
other register types to random values. CARE_shadow cells which do not successfully hold their
value for all of the simulated parallel patterns will result in a violation of this rule. Only one violation
is issued for a given CARE_shadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that CARE_
shadow cells are properly holding values during the specified procedure under hold conditioning.
The automated violation analysis can be used to help debug this problem. This analysis will
display the first failing cell of the failing CARE_shadow register. If the failure was believed to be
due to a problem on a clock/set/reset input, then the pindata is set to the simulated values for the
indicated procedure and all gates in the traceback cone of this input are also displayed.
Otherwise, the displayed pin data is set to one of the parallel pattern values that failed and gates in
the path between the failing cell and the hold control sources are also displayed. The hold control
sources are the Power_enable cell and the cells of the CarePRPG which are used to create the
hold signal.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or CARE_shadow cells.

The -hold_connections option of the report_compressors command can be used to

report the CarePRPG cells which are used to create the hold signal.

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This rule violation can be downgraded to warning. Since the hold ability is not currently used
during test generation, this will not create any problems with current patterns.

Category K - LBIST Rules 177

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DRC Rule K27

Message
DFTMAX LBIST Rule K27: Invalid CARE_shadow reload operation
N CARE_shadow cells (input I of P/G) in compressor S had invalid
value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing CARE_shadow cells

l I indicates input ID of first failing cell in the CARE_shadow register

l Pindicates position of first failing cell in the CARE_shadow register

l G indicates gate ID of first failing cell in the CARE_shadow register
l S indicates name of DFTMAX CODEC associated with failing CARE_shadow register
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the CARE_shadow
cells are checked to ensure that they are successfully loading data from the CarePRPG during
the SHADOW_TO_CAREPRPG procedure. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, and placing XTOL_
enable and Power_enable cells to their off state, and all other register types to random values.
CARE_shadow cells which do not successfully capture their expected value for all of the
simulated parallel patterns will result in a violation of this rule. The expected values for a CARE_
shadow cell are the value assigned to the associated cell in the CarePRPG. Only one violation is
issued for a given CARE_shadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that CARE_
shadow cells are properly capturing data from its CarePRPG during the specified procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
first failing cell of the failing CARE_shadow register. If the failure occurred on a clock/set/reset
input, then the pindata is set to the simulated values for the indicated procedure and all gates in
the traceback cone of this input are also displayed. Otherwise, the displayed pin data is set to one
of the parallel pattern values that failed and gates in the path between the failing cell and the
associated cell in the CarePRPG are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or CARE_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the CarePRPG reseed operation to be incorrect.

Category K - LBIST Rules 178

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DRC Rule K28

Message
DFTMAX LBIST Rule K2: CARE_shadow cell disturb
N CARE_shadow cells (P/G) in compressor S were disturbed during X
procedure..

Severity
Error

Description
Note the following:
l N indicates number of failing CARE_shadow cells

l Pindicates position of first failing cell in the CARE_shadow register

l G indicates gate ID of first failing cell in the CARE_shadow register

l S indicates name of DFTMAX CODEC associated with failing CARE_shadow register

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the CARE_shadow
register cells are checked to ensure that they hold state during the SHADOW_TO_XTOLPRPG
procedure. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing the chain outputs to random values,
XTOL_enable and Power_enable cells to their off state, and all other register types to random
values. CARE_shadow cells which do not hold state for all of the simulated parallel patterns will
result in a violation of this rule. Only one violation is issued for a given CARE_shadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that CARE_
shadow cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the first failing cell for the failing CARE_
shadow register with all the gates in the traceback cone of the input which was believed to have
caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or CARE_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the CarePRPG reseed operation to be incorrect.

Category K - LBIST Rules 179

TetraMAX DRC Rules O-2018.06

DRC Rule K29

Message
DFTMAX LBIST Rule K29: Invalid XTOLShadow shift operation
N XTOLShadow cells (input I of P/G) in compressor S had invalid
shift values during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLShadow cells

l I indicates input ID of first failing cell in the XTOLShadow register

l Pindicates position of first failing cell in the XTOLShadow register

l G indicates gate ID of first failing cell in the XTOLShadow register
l S indicates name of DFTMAX CODEC associated with failing XTOLShadow register
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the XTOLShadow cells
are checked to ensure that they are successfully shifting data during the SHIFT and RESEED_
OVERLAP_SHIFT procedures. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, and placing XTOL_enable
and Power_enable cells to their off state, and all other register types to random values.
XTOLShadow cells which do not successfully capture their expected value for all of the simulated
parallel patterns will result in a violation of this rule. The expected values for an XTOLShadow cell
are the values assigned to the associated cell in the XTOLPRPG. Only one violation is issued for a
given XTOLShadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that CARE_
shadow cells are properly shifting during the specified procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell of the
failing CARE_shadow register. If the failure occurred on a clock/set/reset input, then the pindata
is set to the simulated values for the indicated procedure and all gates in the traceback cone of this
input are also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern
values that failed and gates in the path between the failing cell and the source of its capture data
are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or XTOLShadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 180

TetraMAX DRC Rules O-2018.06

DRC Rule K30

Message
DFTMAX LBIST Rule K30: Invalid XTOLShadow hold operation
N XTOLShadow cells (P/G) in compressor S failed hold during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLShadow cells

l Pindicates position of first failing cell in the XTOLShadow register

l G indicates gate ID of first failing cell in the XTOLShadow register

l S indicates name of DFTMAX CODEC associated with failing XTOLShadow register

l X indicates name of procedure

When the XTOL_enable cells are set to their on state and the hold ability is activated for x-
tolerance control, the XTOLShadow cells are checked to ensure that they are successfully
holding state during the SHIFT and RESEED_OVERLAP_SHIFT procedures. This checking is
done by performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, and placing XTOL_enable cells to their on state, activating the hold ability for x-
tolerance control, and placing all other register types to random values. XTOLShadow cells which
do not successfully hold their value for all of the simulated parallel patterns will result in a violation
of this rule. Only one violation is issued for a given XTOLShadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that
XTOLShadow cells are properly holding state during the specified procedure under hold
conditioning. The automated violation analysis can be used to help debug this problem. This
analysis will display the first failing cell of the failing XTOLShadow register. If the failure was
believed to be due to a problem on a clock/set/reset input, then the pindata is set to the simulated
values for the indicated procedure and all gates in the traceback cone of this input are also
displayed. Otherwise, the displayed pin data is set to one of the parallel pattern values that failed
and gates in the path between the failing cell and the hold control sources are also displayed. The
hold control sources are the Power_enable cell and the cells of the XTOLPRPG which are used
to create the hold signal.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or XTOLShadow cells.

The -hold_connections option of the report_compressors command can be used to

report the XTOLPRPG cells which are used to create the hold signal.

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The -mode_data option of the report_compressors command can be used to report the
XTOLPRPG output values used for the hold observe mode.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 182

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DRC Rule K31

Message
DFTMAX LBIST Rule K31: Invalid XTOLShadow reload operation
N XTOLShadow cells (input I of P/G) in compressor S had invalid
value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLShadow cells

l I indicates input ID of first failing cell in the XTOLShadow register

l Pindicates position of first failing cell in the XTOLShadow register

l G indicates gate ID of first failing cell in the XTOLShadow register
l S indicates name of DFTMAX CODEC associated with failing XTOLShadow register
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the XTOLShadow cells
are checked to ensure that they are successfully loading data from the XTOLPRPG during the
SHADOW_TO_XTOLPRPG procedure. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, and placing XTOL_
enable and Power_enable cells to their off state, and all other register types to random values.
XTOLShadow cells which do not successfully capture their expected value for all of the simulated
parallel patterns will result in a violation of this rule. The expected values for an XTOLShadow cell
are the values assigned to the associated cell in the XTOLPRPG. Only one violation is issued for a
given XTOLShadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that
XTOLShadow cells are properly capturing data from its XTOLPRPG during the specified
procedure. The automated violation analysis can be used to help debug this problem. This
analysis will display the first failing cell of the failing XTOLShadow register. If the failure occurred
on a clock/set/reset input, then the pindata is set to the simulated values for the indicated
procedure and all gates in the traceback cone of this input are also displayed. Otherwise, the
displayed pin data is set to one of the parallel pattern values that failed and gates in the path
between the failing cell and the associated cell in the XTOLPRPG are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or XTOLShadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 183

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DRC Rule K32

Message
DFTMAX LBIST Rule K32: XTOLShadow cell disturb
N XTOLShadow cells (P/G) in compressor S were disturbed during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing XTOLShadow cells

l Pindicates position of first failing cell in the XTOLShadow register

l G indicates gate ID of first failing cell in the XTOLShadow register

l S indicates name of DFTMAX CODEC associated with failing XTOLShadow register

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the XTOLShadow
register cells are checked to ensure that they hold state during the SHADOW_TO_CAREPRPG
procedure. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing the chain outputs to random values,
XTOL_enable and Power_enable cells to their off state, and all other register types to random
values. XTOLShadow cells which do not hold state for all of the simulated parallel patterns will
result in a violation of this rule. Only one violation is issued for a given XTOLShadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that
XTOLShadow cells hold state during the specified procedure. The automated violation analysis
can be used to help debug this problem. This analysis will display the first failing cell for the failing
XTOLShadow register with all the gates in the traceback cone of the input which was believed to
have caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or XTOLShadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 184

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DRC Rule K3

Message
DFTMAX LBIST Rule K33: Invalid XTOL_enable reload operation
XTOL_enable cell (input I of G) in compressor S had invalid capture
during X procedure.

Severity
Error

Description
Note the following:
l I indicates input ID of first failing cell in the XTOL_enable register

l G indicates gate ID of first failing cell in the XTOL_enable register

l S indicates name of DFTMAX CODEC associated with failing XTOL_enable register
l X indicates name of procedure

The XTOL_enable cells are checked to ensure that they are successfully loading data from the
PRPG_shadow during the SHADOW_TO_CAREPRPG and SHADOW_TO_XTOLPRPG
procedures. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. XTOL_enable cells which do
not successfully capture their expected value for all of the simulated parallel patterns will result in
a violation of this rule. The expected values for a XTOL_enable cell are the values assigned to the
associated cell in the PRPG_shadow.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that XTOL_
enable cells are properly capturing data from its PRPG_shadow during the specified procedure.
The automated violation analysis can be used to help debug this problem. This analysis will
display the failing XTOL_enable cell. If the failure occurred on a clock/set/reset input, then the
pindata is set to the simulated values for the indicated procedure and all gates in the traceback
cone of this input are also displayed. Otherwise, the displayed pin data is set to one of the parallel
pattern values that failed and gates in the path between the failing cell and the associated cell in
the PRPG_shadow are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or PRPG_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 185

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DRC Rule K34

Message
DFTMAX LBIST Rule K3: XTOL_enable cell disturb
XTOL_enable cell (G) in compressor S was disturbed during X
procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of first failing cell in the XTOL_enable register
l S indicates name of DFTMAX CODEC associated with failing XTOL_enable register

l X indicates name of procedure

The XTOL_enable cells are checked to ensure that they hold state during the SHIFT and
RESEED_OVERLAP_SHIFT procedures. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, and placing the chain
outputs to random values, XTOL_enable and Power_enable cells to their off state, and all other
register types to random values. XTOL_enable cells which do not hold state for all of the
simulated parallel patterns will result in a violation of this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that XTOL_
enable cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing XTOL_enable cell with all the
gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 186

TetraMAX DRC Rules O-2018.06

DRC Rule K35

Message
DFTMAX LBIST Rule K35: Invalid internal chain input value
Input node G of chain C in compressor S had invalid simulated value
during X procedure..

Severity
Error

Description
Note the following:
l G indicates gate ID of chain input node
l C indicates name of chain whose input had invalid value

l S indicates name of DFTMAX CODEC associated with failing chain

l X indicates name of procedure

Chain inputs are checked to ensure that they are at the correct value during the SHIFT
procedure. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the appropriate procedure, and placing XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. Chain inputs which are not at
their expected value for all of the simulated parallel patterns will result in a violation of this rule.
The expected values for a chain input are calculated from the values assigned to the CARE_
shadow cells considering the CarePRPG tapping.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that chain inputs
have the correct value during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing chain input node. The
displayed pin data is set to one of the parallel pattern values that failed and gates in the path
between the failing chain input and the connecting CARE_shadow cells are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or CARE_shadow cells.

The -lfsr_connections option of the report_compressors command can be used to

report the CarePRPG tapping and the chain to CarePRPG connections.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 187

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DRC Rule K36

Message
DFTMAX LBIST Rule K36: Invalid internal chain shift operation
N internal chain cells (input I of G) of chain C had invalid value
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing internal cells

l Iindicates input ID of first failing internal cell

l G indicates gate ID of first failing cell

l C indicates name of chain whose cell failed shift checking

l X indicates name of procedure

Internal cells are checked to ensure that they are correctly shifting data during the RESEED_
OVERLAP_SHIFT procedure. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, and placing internal cells at
random values, XTOL_enable and Power_enable cells to their off state, and all other register
types to random values. Internal cells which do not capture their expected shift value for all of the
simulated parallel patterns will result in a violation of this rule. The expected values for an internal
cell are calculated from the values assigned to their adjacent cell considering cell-to-cell inversion.
The expected shift values for the cell closest to the scan input are the values assigned to the chain
input node. Only one violation is issued for a given chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that internal cells
successfully capture the correct shift values during the specified procedure. The automated
violation analysis can be used to help debug this problem. This analysis will display the failing
internal cell. If the failure occurred on a clock/set/reset input, then the pindata is set to the
simulated values for the indicated procedure and all gates in the traceback cone of this input are
also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern values that
failed and gates in the path between the failing cell and the adjacent cell (or chain input) are also
displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or Power_enable cells.

The report_scan_chains command can be used to report the chain input nodes or report the
internal cells with their inversion.

Category K - LBIST Rules 188

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This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 189

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DRC Rule K37

Message
DFTMAX LBIST Rule K37: Internal chain cell disturb
N internal chain cells (P/G of chain C) in compressor S were
disturbed during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing internal cells in the failing chain

l P indicates position of first failing cell in the failing internal chain

l G indicates gate ID of first failing cell in the failing internal chain

l C indicates the name of chain whose cells failed disturb checking

l S indicates name of DFTMAX CODEC associated with failing XTOL_enable cell
l X indicates name of procedure

Internal scan cells are checked to ensure that they hold state during the RESEED_WITH_MISR_
SHIFT, RESEED_SHIFT, SHADOW_TO_CAREPRPG, SHADOW_TO_XTOLPRPG, and
OCC_SHIFT procedures. This checking is done by performing parallel (32) pattern simulation
using the simulated values of the appropriate procedure, and placing the chain outputs to random
values, XTOL_enable and Power_enable cells to their off state, and all other register types to
random values. Internal scan cells which do not hold state for all of the simulated parallel patterns
will result in a violation of this rule.

What Next
To correct this problem, the netlist or the STIL procedure file must be changed so that internal
scan cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing internal scan cell with all the
gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable or Power_enable cells.

The report_scan_chains command can be used to report the chain input nodes.

The report_scan_cells command can be used to report the internal cells with their
inversion.

Category K - LBIST Rules 190

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This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 191

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DRC Rule K38

Message
DFTMAX LBIST Rule K38: Invalid Power_enable value from test_setup
Power_enable cell (G) had incorrect value (V) at end of test_setup
procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing Power_enable cell
l V indicates value of Power_enable cell at end of test_setup procedure

The Power_enable cell is checked to ensure that it is successfully initialized to its off-state during
the test_setup procedure. This checking is done by comparing the simulated value of the Power_
enable cell at the end of the test_setup procedure and its off-state value.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the Power_
enable cell is properly initialized to its off-state in the test_setup procedure. The automated
violation analysis can be used to help debug this problem. This analysis will display the failing
Power_enable cell. The pindata is set to the simulated values of the test_setup procedure and all
gates in the traceback cone of this gate are also displayed.

The -cells option of the report_compressors command can be used to report the Power_
enable cell with its off state.

The test_setup option of the set_pindata command can be used to report the stored
simulated values of the test_setup procedure.

The -store_setup option of the set_drc command can be used to store the simulated
values for all patterns of the test_setup procedure. The default is to only store the final pattern
value.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 192

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DRC Rule K39

Message
DFTMAX LBIST Rule K39: Invalid Power_enable value from low_power_
setup
Power_enable cell (G) had incorrect value (V) at end of low_power_
setup procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing Power_enable cell
l V indicates value of Power_enable cell at end of low_power_setup procedure

The Power_enable cell is checked to ensure that it is successfully initialized to its on-state during
the low_power_setup procedure. This checking is done by comparing the simulated value of the
Power_enable cell at the end of the low_power_setup procedure and its on-state value.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the Power_
enable cell is properly initialized to its on-state in the low_power_setup procedure. The automated
violation analysis can be used to help debug this problem. This analysis will display the failing
Power_enable cell. The pindata is set to the simulated values of the low_power_setup procedure
and all gates in the traceback cone of this gate are also displayed.

The -cells option of the report_compressors command can be used to report the Power_
enable cell with its off state.

The low_power_setup option of the set_pindata command can be used to report the
stored simulated values of the test_setup procedure.

This rule violation can be downgraded to warning. Since there is currently no support for using the
low_power_setup procedure, it will have no effect until support is available for this procedure.

Category K - LBIST Rules 193

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DRC Rule K40

Message
DFTMAX LBIST Rule K40: Power_enable cell disturb
Power_enable cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing Power_enable cell
l X indicates the name of the procedure

The Power_enable cell is checked to ensure that it holds state during the SHIFT, RESEED_
WITH_MISR_SHIFT, RESEED_SHIFT, RESEED_OVERLAP_SHIFT, SHADOW_TO_
CAREPRPG, SHADOW_TO_XTOLPRPG, OCC_SHIFT, and capture procedures. This
checking is done by performing parallel (32) pattern simulation using the simulated values of the
appropriate procedure, and placing XTOL_enable and Power_enable cells to their off state, and
all other register types to random values. If the Power_enable cell does not hold state for all of the
simulated parallel patterns, it will result in a violation of this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that Power_
enable cell holds state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing Power_enable cell with all
the gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the Power_
enable cell with its off state.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 194

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DRC Rule K41

Message
DFTMAX LBIST Rule K41: Invalid occ_chain_load operation
N OCC_chain_cells (input I of P/G) had invalid value during X
procedure..

Severity
Error

Description
Note the following:
l N indicates number of failing occ_chain cells

l I indicates input ID of first failing cell in the occ_chain

l Pindicates position of first failing cell in the occ_chain

l G indicates gate ID of first failing cell in the occ_chain
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the occ_chain cells are
checked to ensure that they are successfully loading data during the OCC_SHIFT procedure.
This checking is done by performing parallel (32) pattern simulation using the simulated values of
the appropriate procedure, and placing the occ_chain input ports to random values, XTOL_
enable and Power_enable cells to their off state, and all other register types to random values.
occ_chain cells which do not successfully capture their expected value for all of the simulated
parallel patterns will result in a violation of this rule. The expected value for cells which connect to
occ_chain input ports are the values assigned to the input port (or inverted). The expected values
for all other cells are the values assigned to the adjacent cells. Only one violation is issued for a
given occ_chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that occ_chain
cells are properly capturing data during the specified procedure. The automated violation analysis
can be used to help debug this problem. This analysis will display the first failing cell of the failing
occ_chain. If the failure occurred on a clock/set/reset input, then the pindata is set to the simulated
values for the indicated procedure and all gates in the traceback cone of this input are also
displayed. Otherwise, the displayed pin data is set to one of the parallel pattern values that failed
and gates in the path between the failing cell and the source of its capture data are also displayed.

The -chain_segments option of the report_compressors command can be used to

report the input ports of the occ_chain.

Category K - LBIST Rules 195

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DRC Rule K42

Message
DFTMAX LBIST Rule K4: occ_chain cell disturb
N occ_chain cells (P/G) were disturbed during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing occ_chain cells

l Pindicates position of first failing cell in the occ_chain

l G indicates gate ID of first failing cell in the occ_chain

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the occ_chain cells are
checked to ensure that they hold state during the SHIFT, RESEED_WITH_MISR_SHIFT,
RESEED_SHIFT, RESEED_OVERLAP_SHIFT, SHADOW_TO_CAREPRPG, and
SHADOW_TO_XTOLPRPG procedures. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, XTOL_enable and
Power_enable cells to their off state, and all other register types to random values. occ_chain
cells which do not hold state for all of the simulated parallel patterns will result in a violation of this
rule. Only one violation is issued for a given occ_chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that occ_chain
cells hold state during the specified procedure. The automated violation analysis can be used to
help debug this problem. This analysis will display the first failing cell for the failing occ_chain with
all the gates in the traceback cone of the input which was believed to have caused the problem.
The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or occ_chain cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the occ_chain load operation to be incorrect.

Category K - LBIST Rules 196

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DRC Rule K43

Message
DFTMAX LBIST Rule K43: misr_mode cell disturb
Misr_mode cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing misr_mode cell
l X indicates name of procedure

The MISR cells are checked to ensure that they hold state during the SHIFT, RESEED_WITH_
MISR_SHIFT, RESEED_SHIFT, RESEED_OVERLAP_SHIFT, SHADOW_TO_CAREPRPG,
SHADOW_TO_XTOLPRPG, OCC_SHIFT, and capture procedures. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, and placing XTOL_enable and Power_enable cells to their off state, and all other
register types to random values. If any misr_mode cell does not hold state for all of the simulated
parallel patterns, it will result in a violation of this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that the failing
misr_mode cell holds state during the specified procedure. The automated violation analysis can
be used to help debug this problem. This analysis will display the failing misr_mode cell with all the
gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the misr_
mode cells with their accumulator mode enable values.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 197

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DRC Rule K44

Message
DFTMAX LBIST Rule K44: Invalid misr_mode value from test_setup
Misr_mode cell (G) had incorrect value V at end of test_setup
procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of of failing misr_mode cell
l V indicates the incorrect value that was set by the test_setup procedure

At the end of the test_setup procedure (and extended test_setup if used), the misr_mode cells are
checked to ensure that they are at the correct value as determined by the selected accumulator
mode usage. If the accumulator mode is enabled, then the misr_mode cells must be set to their
enable values. Otherwise, the misr_mode cells must be set to the complement of their enable
values. Misr_mode cells which are not at their correct value at this time will result in a violation of
this rule.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that misr_mode
cells are at their intended value at the end of test_setup. The active accumulator mode selection
may have to be changed to reflect the intended usage. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing misr_mode cell with all the
gates in its traceback cone. The pindata is set to the simulated values at the end of the test_setup
procedure(s).

The -cells option of the report_compressors command can be used to report the misr_
mode cells with their accumulator mode enable values.

The drc option of the report_settings command can be used to report the current
selection of the accumulator mode usage.

The test_setup option of the set_pindata command can be used to report the stored
simulated values of the test_setup procedure.

The -store_setup option of the set_drc command can be used to store the simulated
values for all patterns of the test_setup procedure.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 198

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DRC Rule K45

Message
DFTMAX LBIST Rule K45: Invalid seed_type shift operation
Seed_type cell (input I of G) had invalid shift value during X
procedure.

Severity
Error

Description
Note the following:
l I indicates input ID of failing seed_type cell

l G indicates gate ID of failing seed_type cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the seed_type cells are
checked to ensure that they are successfully shifting data during the RESEED_PARTIAL_
OVERLAP_SHIFT procedures. This checking is done by first simulating the JTAG load
procedure to set values on the JTAG controller. This is followed by performing parallel (32)
pattern simulation using the simulated values of the RESEED_PARTIAL_OVERLAP_SHIFT
procedure, and placing XTOL_enable and Power_enable cells to their off state, and all other
register types to random values. Seed_type cells which do not successfully capture their expected
value for all of the simulated parallel patterns will result in a violation of this rule. This rule is only
checked if JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that seed_type
cells correctly shift during the RESEED_PARTIAL_OVERLAP_SHIFT procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
failing seed_type cell with all the gates in the traceback cone of the input which was believed to
have caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or seed_type cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 199

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DRC Rule K46

Message
DFTMAX LBIST Rule K4: seed_type cell disturb
Seed_type cell (G) was disturbed during X procedure..

Severity
Error

Description
Note the following:
l G indicates gate ID of failing seed_type cell
l X indicates name of procedure

To correct this problem, the netlist or the STL procedure file must be changed so that seed_type
cells hold state during the specified procedure. The automated violation analysis can be used to
help debug this problem. This analysis will display the failing seed_type cell with all the gates in
the traceback cone of the input which was believed to have caused the problem. The pindata is
set to the simulated values of the failing procedure.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that seed_type
cells hold state during the specified procedure. The automated violation analysis can be used to
help debug this problem. This analysis will display the failing seed_type cell with all the gates in
the traceback cone of the input which was believed to have caused the problem. The pindata is
set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or seed_type cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 200

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DRC Rule K47

Message
DFTMAX LBIST Rule K47: Invalid capture_enable_shadow shift
operation
Capture_enable_shadow cell (input I of G) had invalid shift value
during X procedure.

Severity
Error

Description
Note the following:
l I indicates input ID of failing capture_enable_shadow cell

l G indicates gate ID of failing capture_enable_shadow cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the capture_enable_
shadow cells are checked to ensure that they are successfully shifting data during the RESEED_
PARTIAL_OVERLAP_SHIFT procedures. This checking is done by first simulating the JTAG_
RESEED_SETUP procedure to set values on the JTAG controller. This is followed by performing
parallel (32) pattern simulation using the simulated values of the RESEED_PARTIAL_
OVERLAP_SHIFT procedure, and placing XTOL_enable and Power_enable cells to their off
state, and all other register types to random values. Capture_enable_shadow cells which do not
successfully capture their expected value for all of the simulated parallel patterns will result in a
violation of this rule. This rule is only checked if JTAG LBIST or JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that capture_
enable_shadow cells correctly shift during the RESEED_PARTIAL_OVERLAP_SHIFT
procedure. The automated violation analysis can be used to help debug this problem. This
analysis will display the failing capture_enable_shadow cell with all the gates in the traceback
cone of the input which was believed to have caused the problem. The pindata is set to the
simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or capture_enable_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 201

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DRC Rule K48

Message
DFTMAX LBIST Rule K48: Capture_enable_shadow cell disturb
Capture_enable_shadow cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing capture_enable_shadow cell
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the capture_enable_
shadow cells are checked to ensure that they hold state during selected procedures. This
checking is done by performing parallel (32) pattern simulation using the simulated values of the
appropriate procedure, XTOL_enable and Power_enable cells to their off state, and all other
register types to random values. Capture_enable_shadow cells which do not hold state for all of
the simulated parallel patterns will result in a violation of this rule. This rule is not currently checked
for any procedure.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that capture_
enable_shadow cells hold state during the specified procedure. The automated violation analysis
can be used to help debug this problem. This analysis will display the failing capture_enable_
shadow cell with all the gates in the traceback cone of the input which was believed to have
caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or capture_enable_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 202

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DRC Rule K49

Message
DFTMAX LBIST Rule K49: Invalid capture_enable reload operation
Capture_enable cell (input I of G) had invalid reload value during
X procedure.

Severity
Error

Description
Note the following:
l I indicates input ID of failing capture_enable cell

l G indicates gate ID of failing capture_enable cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the capture_enable
cells are checked to ensure that they successfully load data from their associated capture_
enable_shadow cells during the SHADOW_TO_CAREPRPG and SHADOW_TO_XTOLPRPG
procedures. This checking is done by first simulating the JTAG_RESEED_SETUP procedure to
set values on the JTAG controller. This is followed by performing parallel (32) pattern simulation
using the simulated values of the failing procedure, and placing XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. Capture_enable cells which
do not successfully capture their expected value for all of the simulated parallel patterns will result
in a violation of this rule. This rule is only checked if JTAG LBIST or JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that capture_
enable cells capture their expected values from their associated capture_enable_shadow cells
during the failing procedure. The automated violation analysis can be used to help debug this
problem. This analysis will display the failing capture_enable cell with all the gates in the
traceback cone of the input which was believed to have caused the problem. The pindata is set to
the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, capture_enable, or capture_enable_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 203

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DRC Rule K50

Message
DFTMAX LBIST Rule K50: capture_enable cell disturb
Capture_enable cell (G) was disturbed during X procedure..

Severity
Error

Description
Note the following:
l G indicates gate ID of failing capture_enable cell
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the capture_enable
cells are checked to ensure that they hold state during the RESEED_PARTIAL_OVERLAP_
SHIFT, JTAG_RESEED_SETUP, and JTAG_MISR_SHIFT procedures. This checking is done
by performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, XTOL_enable and Power_enable cells to their off state, and all other register types to
random values. Capture_enable cells which do not hold state for all of the simulated parallel
patterns will result in a violation of this rule. This rule is only checked if JTAG LBIST or JTAG
ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that capture_
enable cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing capture_enable cell with all
the gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, capture_enable, or capture_enable cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 204

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DRC Rule K51

Message
DFTMAX LBIST Rule K51: Invalid shift_counter_shadow shift operation
N shift_counter_shadow cells (input I of P/G) had invalid shift
values during X procedure.
Severity:Error

Severity
Error

Description
Note the following:
l N indicates number of failing shift_counter_shadow cells

l P indicates position of first failing shift_counter_shadow cell

l G indicates gate ID of first failing shift_counter_shadow cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the shift_counter_
shadow cells are checked to ensure that they are successfully shifting data during the RESEED_
PARTIAL_OVERLAP_SHIFT procedures. This checking is done by first simulating the JTAG_
RESEED_SETUP procedure to set values on the JTAG controller. This is followed by performing
parallel (32) pattern simulation using the simulated values of the RESEED_PARTIAL_
OVERLAP_SHIFT procedure, and placing XTOL_enable and Power_enable cells to their off
state, and all other register types to random values. Shift_counter_shadow cells which do not
successfully capture their expected value for all of the simulated parallel patterns will result in a
violation of this rule. This rule is only checked if JTAG LBIST or JTAG ULTRA is used. Only one
violation is issued for a given shift_counter_shadow chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that shift_
counter_shadow cells correctly shift during the RESEED_PARTIAL_OVERLAP_SHIFT
procedure. The automated violation analysis can be used to help debug this problem. This
analysis will display the failing shift_counter_shadow cell with all the gates in the traceback cone
of the input which was believed to have caused the problem. The pindata is set to the simulated
values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or shift_counter_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 205

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DRC Rule K52

Message
DFTMAX LBIST Rule K52: shift_counter_shadow cell disturb
Shift_counter_shadow cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of shift_counter_shadow cell
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the shift_counter_
shadow cells are checked to ensure that they hold state during the SHADOW_TO_CAREPRPG
and SHADOW_TO_XTOLPRPG procedures. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, XTOL_enable and
Power_enable cells to their off state, and all other register types to random values. Shift_counter_
shadow cells which do not hold state for all of the simulated parallel patterns will result in a
violation of this rule. This rule is only checked if JTAG LBIST or JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that shift_
counter_shadow cells hold state during the specified procedure. The automated violation analysis
can be used to help debug this problem. This analysis will display the failing shift_counter_
shadow cell with all the gates in the traceback cone of the input which was believed to have
caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or shift_counter_shadow cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 206

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DRC Rule K53

Message
DFTMAX LBIST Rule K53: Invalid shift_counter reload operation
N shift_counter cells (input I of P/G) had invalid reload values
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing shift_counter cells

l I indicates input ID of failing shift_counter cellP

l P indicates position of first failing shift_counter cell

l G indicates gate ID of first failing shift_counter cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the shift_counter cells
are checked to ensure that they successfully load data from their associated shift_counter_
shadow cells during the SHADOW_TO_CAREPRPG and SHADOW_TO_XTOLPRPG
procedures. This checking is done by first simulating the JTAG_RESEED_SETUP procedure to
set values on the JTAG controller. This is followed by performing parallel (32) pattern simulation
using the simulated values of the failing procedure, and placing XTOL_enable and Power_enable
cells to their off state, and all other register types to random values. Shift_counter cells which do
not successfully capture their expected value for all of the simulated parallel patterns will result in
a violation of this rule. This rule is only checked if JTAG LBIST or JTAG ULTRA is used. Only one
violation is issued for a given shift_counter chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that shift_
counter cells capture their expected values from their associated shift_counter_shadow cells
during the failing procedure. The automated violation analysis can be used to help debug this
problem. This analysis will display the failing shift_counter cell with all the gates in the traceback
cone of the input which was believed to have caused the problem. The pindata is set to the
simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or shift_counter_shadow cells.

This rule violation might be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 207

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DRC Rule K54

Message
DFTMAX LBIST Rule K54: Invalid shift_counter count operation
N shift_counter cells (P/G) had invalid count values during LBIST
shifting.

Severity
Error

Description
Note the following:
l N indicates number of failing shift_counter cells

l P indicates position of first failing shift_counter cell

l G indicates gate ID of first failing shift_counter cell

Shift_counter cells are checked to ensure that their count operation is correctly performed during
the internal scanchain shift process. This checking is done by first initializing the state of the circuit
to their values at the beginning of the SHIFT procedure. Then the capture_enable cell is set to its
capture_enable_value, seed_type cell is set to its CarePRPG_select_value, shift_counter cells
set to a value equal to the number shifts per load, shift_counter_shadow cells set to a value equal
to the number shifts per load, and the pattern_counter cells are set to a value of 2. Finally, the
SHIFT procedure is simulated a number of times equal to the number of shifts per load plus the
minimum number of ATE clock cycles. The shift counter should end up at a value equal to the
number of shifts per load. Shift_counter cells which are not at their correct value will result in a
violation of this rule. This rule is only checked if JTAG LBIST is used. Only one violation is issued
for a given shift_counter chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that shift_
counter cells count properly during LBIST shifting. The shift counter and pattern counter values
for each shift can be displayed during the rules checking by using the -compressor_debug_data
option of the set_drc command. The automated violation analysis can be also used to help debug
this problem. This analysis will display all of the cells of the failing shift counter with all connections
beween the cells. The pindata is set to the simulated values during the number_shifts_per_load +
1 shift cycle.

The -cells option of the report_compressors command can be used to report the shift_
counter cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 208

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DRC Rule K55

Message
DFTMAX LBIST Rule K55: shift_counter cell disturb
Shift_counter cell (G) was disturbed during X procedure.
Severity:Error

Severity
Error

Description
Note the following:
l G indicates gate ID of failing shift_counter cell
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the shift_counter cells
are checked to ensure that they hold state during the JTAG_RESEED_SETUP and JTAG_
MISR_SHIFT procedures. This checking is done by performing parallel (32) pattern simulation
using the simulated values of the appropriate procedure, XTOL_enable and Power_enable cells
to their off state, and all other register types to random values. Shift_counter cells which do not
hold state for all of the simulated parallel patterns will result in a violation of this rule. This rule is
only checked if JTAG LBIST or JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that shift_
counter cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing shift_counter cell with all the
gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or shift_counter cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 209

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DRC Rule K56

Message
DFTMAX LBIST Rule K56: Invalid pattern_counter shift operation
N pattern_counter cells (input I of P/G) had invalid shift values
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing pattern_counter cells

l I indicates input ID of failing pattern_counter cellP

l P indicates position of first failing pattern_counter cell

l G indicates gate ID of first failing pattern_counter cell

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the pattern_counter
cells are checked to ensure that they are successfully shifting data during the PATCOUNTER_
SHIFT procedure. This checking is done by performing parallel (32) pattern simulation using the
simulated values of the PATCOUNTER_SHIFT procedure, and placing XTOL_enable and
Power_enable cells to their off state, and all other register types to random values. Pattern_
counter cells which do not successfully shift their expected value for all of the simulated parallel
patterns will result in a violation of this rule. This rule is only checked if JTAG LBIST is used. Only
one violation is issued for a given shift_counter_shadow chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that pattern_
counter cells correctly shift during the failing procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing pattern_counter cell with all
the gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or pattern_counter cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 210

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DRC Rule K57

Message
DFTMAX LBIST Rule K57: Invalid pattern_counter count operation
N pattern_counter cells (P/G) had invalid count values during LBIST
shifting.

Severity
Error

Description
Note the following:
l N indicates number of failing shift_counter cells

l P indicates position of first failing shift_counter cell

l G indicates gate ID of first failing shift_counter cell

Pattern_counter cells are checked to ensure that their count operation is correctly performed
during the internal scanchain shift process. This checking is done by first initializing the state of the
circuit to their values at the beginning of the SHIFT procedure. Then the capture_enable cell is set
to its capture_enable_value, seed_type cell is set to its CarePRPG_select_value, shift_counter
cells set to a value equal to the number shifts per load, shift_counter_shadow cells set to a value
equal to the number shifts per load, and the pattern_counter cells are set to a value of 2. Finally,
the SHIFT procedure is simulated a number of times equal to the number of shifts per load plus
the minimum number of ATE clock cycles. The pattern counter should end up at a value equal to
1. Pattern_counter cells which are not at their correct value will result in a violation of this rule.
This rule is only checked if JTAG LBIST is used. Only one violation is issued for a given pattern_
counter chain.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that pattern_
counter cells count properly during shifting. The shift counter and pattern counter values for each
shift can be displayed during the rules checking by using the -Compressor_debug_data option of
the set_drc command. The automated violation analysis can be also used to help debug this
problem. This analysis will display all of the cells of the failing pattern_counter with all connections
beween the cells. The pindata is set to the simulated values during the number_shifts_per_load +
1 shift cycle.

The -cells option of the report_compressors command can be used to report the pattern_
counter cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 211

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DRC Rule K58

Message
DFTMAX LBIST Rule K58: pattern_counter cell disturb
Pattern_counter cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing pattern_counter cell
l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the pattern_counter
cells are checked to ensure that they hold state during the RESEED_PARTIAL_OVERLAP_
SHIFT, SHADOW_TO_CAREPRPG, SHADOW_TO_XTOLPRPG, JTAG_RESEED_SETUP,
and JTAG_MISR_SHIFT procedures. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, XTOL_enable and Power_
enable cells to their off state, and all other register types to random values. Pattern_counter cells
which do not hold state for all of the simulated parallel patterns will result in a violation of this rule.
This rule is only checked if JTAG LBIST or JTAG ULTRA is used.

What Next
To correct this problem, the netlist or the STL procedure file must be changed so that pattern_
counter cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing pattern_counter cell with all
the gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or pattern_counter cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

Category K - LBIST Rules 212

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DRC Rule K59

Message
DFTMAX LBIST Rule K59: Scan cells with same erroneous signatures
Scan cells N1 (G1) and N2 (G2) have same signature.

Severity
Error

Description
Note the following:
l N1 indicates name of scan cell

l G1 indicates gate ID of scan cell

l N2 indicates name of scan cell

l G2 indicates gate ID of scan cell

Uniqueness of erroneous signatures is required improving mapping features back to scan cells for
debugging and diagnosis. In certain cases, the MISR might fail to satisfy this condition and two or
more failing scan cells might generate the same erroneous signature. In this case, the failing scan
cell cannot be uniquely determined even when a single scan cell fails for a particular pattern.

What Next
Need to redesign the MISR to meet this condition.

Category K - LBIST Rules 213

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DRC Rule K60

Message
DFTMAX LBIST Rule K6: chain_mask cell disturb
N chain_mask cells (P/G) in compressor S were disturbed during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing chain_mask chain

l P indicates position of failing chain_mask chain

l G indicates gate ID of failing cell in the chain_mask chain

l S indicates name of CODEC associated with failing chain_mask chain

l X indicates name of procedure

When the XTOL_enable and Power_enable cells are set to their off state, the chain_mask cells
are checked to ensure that they hold state during the SHIFT, RESEED_WITH_MISR_SHIFT,
RESEED_SHIFT, RESEED_OVERLAP_SHIFT, RESEED_PARTIAL_OVERLAP_SHIFT,
SHADOW_TO_CAREPRPG, SHADOW_TO_XTOLPRPG, JTAG_RESEED_SETUP, JTAG_
MISR_SHIFT, RESEED_STREAMING_SHIFT, and OCC_SHIFT procedures. This checking is
done by performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, XTOL_enable and Power_enable cells to their off state, and all other register types to
random values. Chain_mask cells which do not hold state for all of the simulated parallel patterns
will result in a violation of this rule. Only one violation is issued for a given chain_mask chain.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that chain_mask
cells hold state during the specified procedure. The automated violation analysis can be used to
help debug this problem. This analysis will display the first failing cell for the failing chain_mask
chain with all the gates in the fanin cone of the input which was believed to have caused the
problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or chain_mask cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the OCC_chain load operation to be incorrect.

Category K - LBIST Rules 214

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DRC Rule K61

Message
DFTMAX LBIST Rule K61: Invalid xchains_register reload operation
N xchains_register cells (input I of P/G) in compressor S had
invalid value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing xchains_register cells

l I indicates input ID of first failing cell in the xchains_register

l P indicates position of failing cell in the xchains_register

l G indicates gate ID of failing cell in the xchains_register

l S indicates name of CODEC associated with failing cell in the xchains_register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state, the xchains_register cells
are checked to ensure that they are successfully capturing reseed data from the prpg_shadow
during the SHADOW_TO_Xtolprpg procedure. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, and placing xtol_
enable/power_enable cells to their off state, and all other register types to random values.
Xchains_register cells which do not successfully capture their expected value for all of the
simulated parallel patterns will result in a violation of this rule. The expected value for cells are
determined by the values from the associated cell in the prpg_shadow. Only one violation is
issued for a given xchains_register.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that xchains_
register cells are properly capturing data during the specified procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell of the
failing xchains_register register. If the failure occurred on a clock/set/reset input, then the pindata
is set to the simulated values for the indicated procedure and all gates in the traceback cone of this
input are also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern
values that failed and gates in the path between the failing cell and the source of its capture data
are also displayed.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or xchains_register cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the scan chain load operation from PRPGs to be incorrect.

Category K - LBIST Rules 215

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DRC Rule K62

Message
DFTMAX LBIST Rule K62: xchains_register cell disturb
N xchains_register cells (P/G) in compressor S were disturbed
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing xchains_register cells

l P indicates position of failing cell in the xchains_register

l G indicates gate ID of failing cell in the xchains_register

l S indicates name of CODEC associated with failing cell in the xchains_register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state and codec enables are set
to their active state, the xchains_register cells are checked to ensure that they hold state during
the SHIFT, SHADOW_TO_CAREPRPG, RESEED_WITH_MISR_SHIFT, RESEED_SHIFT,
RESEED_PARTIAL_OVERLAP_SHIFT1. RESEED_PARTIAL_OVERLAP_SHIFT2,
RESEED_LOAD, JTAG_RESEED_SETUP, JTAG_MISR_SHIFT, RESEED_OVERLAP_
SHIFT, RESEED_PARTIAL_OVERLAP_SHIFT1, RESEED_PARTIAL_OVERLAP_SHIFT2,
RESEED_STREAMING_SHIFT1, RESEED_STREAMING_SHIFT2, and OCC_SHIFT
procedures.

When the xtol_enables are set active, power_enable cells are set inactive, and codec enables are
set active, the xchains_register cells are also checked to ensure that they hold state during the
SHADOW_TO_XTOLPRPG procedure.

This checking is done by performing parallel (32) pattern simulation using the simulated values of
the appropriate procedure, xtol_enable/power_enable cells to their off state, codec enables are
set to their active state, and all other register types to random values. xXchains_register cells
which do not hold state for all of the simulated parallel patterns will result in a violation of this rule.
Only one violation is issued for a given procedure.

When xchains_registers are used, some procedures are also checked considering CODEC
disabling variations. This checks all combinations of a single CODEC disabled (used as an xchain
and only observable in single observe mode) and all other codecs enabled. When failures occur
during checking with a codec disabled, the error message will include an extra line indicating
which codec was disabled.

Category K - LBIST Rules 216

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What Next
To correct this problem, the netlist or the test procedure file must be changed so that xchains_
register cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the first failing cell for the failing
xchains_register with all the gates in the traceback cone of the input which was believed to have
caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or xchains_register cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns which exercise the xchains_register operation to be incorrect.

Category K - LBIST Rules 217

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DRC Rule K63

Message
DFTMAX LBIST Rule K6: Invalid value from jtag_reseed_setup
Register T cell (G) had incorrect value (V) at end of jtag_reseed_
setup procedure.

Severity
Error

Description
Note the following:
l T indicates type of failing register cell

l G indicates gate ID of failing register cell

l V indicates the incorrect value that was set by the jtag_reseed_setup procedure

At the end of the jtag_reseed_setup procedure, the address, broadcast, and increment_address
cells are checked to ensure that they are at the correct value. The address cells must indicate a
value of 0, the broadcast cell must be at the defined broadcast value, and the increment address
cell must be at the complement of the increment_address_value. Cells which are not at their
correct value at this time will result in a violation of this rule.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the failing
cells are at their intended value at the end of the jtag_reseed_setup procedure. The automated
violation analysis can be used to help debug this problem. This analysis will display the failing cell
with all the gates in its traceback cone. The pindata is set to the simulated values of the jtag_
reseed_setup procedure.

The -cells option of the report_compressors command can be used to report the
address, broadcast (with broadcast values), or increment_address cells (with increment_address
values).

The -summary option of the report_compressors command can be used to report the
codec_enables with their associated enable values.

The jtag_reseed_setup option of the set_pindata command can be used to report the
stored simulated values of the jtag_reseed_setup procedure.

This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K64

Message
DFTMAX LBIST Rule K64: Invalid instruction_register reload
operation
N instruction register cells (input I of P/G) had invalid value
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing failing instruction register cells

l I indicates input ID of first failing cell in the instruction register

l P indicates position of failing cell in the instruction register

l G indicates gate ID of failing cell in the instruction register

l X indicates name of procedure

hen the xtol enable cells are set off and power_enable cells are set off and idu_enable cells are
set active and codec enables are set active, the instruction register cells are checked to ensure
that they are successfully loading reseed data during the RESEED_SHIFTA, RESEED_
SHIFTB, and RESEED_PARTIAL_OVERLAP_SHIFT2 procedures. The instruction register
contains the cells of the broadcast, address, seed_type, capture_enable_shadow, and shift_
counter_shadow register types. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, and placing xtol_
enable/power_enable cells to their off state, idu_enable/codec enable to their active state and all
other register types to random values. Instruction register cells which do not successfully capture
their expected value for all of the simulated parallel patterns will result in a violation of this rule.
The expected value for cells are determine by the values from the associated cell in the prpg_
shadow. Only one violation is issued for a given procedure.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, codec_enable, and instruction register cells. The -cells option can also be

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used to to report the individual register types used in the instruction register. These register types
include broadcast, address, seed_type, capture_enable_shadow, and shift_counter_shadow.

The -summary option of the report_compressors command can be used to report the idu_
enables with their associated enable values.

This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K65

Message
DFTMAX LBIST Rule K65: Address cell disturb
N address cells (P/G) were disturbed during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing address cells

l P indicates position of failing cell in the address register

l G indicates gate ID of failing cell in the xchains_register

l S indicates name of CODEC associated with failing cell in the address register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state and codec_enables are set
to their active state, the address cells are checked to ensure that they hold state during the
SHIFT, RESEED_SHIFTC, RESEED_LOAD, RESEED_PARTIAL_OVERLAP_SHIFT1,
SHADOW_TO_CAREPRPG, and SHADOW_TO_XTOLPRPG procedures. This checking is
done by performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, xtol_enable/power_enable cells set to their off state, codec_enables set to their active
state, and all other register types set to random values. Address cells which do not hold state for
all of the simulated parallel patterns will result in a violation of this rule. Only one violation is issued
for a given procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that address cells
hold state during the specified procedure. The automated violation analysis can be used to help
debug this problem. This analysis will display the first failing cell for the failing address cell with all
the gates in the traceback cone of the input which was believed to have caused the problem. The
pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power_enable, codec_enable, or address cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K66

Message
DFTMAX LBIST Rule K66: Broadcast cell disturb
Broadcast cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing broadcast cell
l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state and codec_enables are set
to their active state, the broadcast cell is checked to ensure that it holds state during the SHIFT,
RESEED_SHIFTC, RESEED_LOAD, RESEED_PARTIAL_OVERLAP_SHIFT1, SHADOW_
TO_CAREPRPG, and SHADOW_TO_XTOLPRPG procedures. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, xtol_enable/power_enable cells set to their off state, codec_enables set to their active
state, and all other register types set to random values. Broadcast cells which do not hold state for
all of the simulated parallel patterns will result in a violation of this rule. Only one violation is issued
for a given procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so the broadcast cell
holds state during the specified procedure. The automated violation analysis can be used to help
debug this problem. This analysis will display the failing broadcast cell with all the gates in the
traceback cone of the input which was believed to have caused the problem. The pindata is set to
the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used tobroadcast cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K67

Message
DFTMAX LBIST Rule K6: Invalid increment_address set operation
Increment_address cell (G) had invalid set value (V1/V2) during X
procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing cell in the xchains_register
l V1 indicates simulated value of failing increment_address cell

l V2 indicates expected value of failing increment_address cell

l X indicates name of procedure

At the end of an application of certain shift procedures which are intended to set the increment
address cell, the increment_address cell is checked to ensure that it is at the correct value. The
increment_address cell must be set to the complement of its increment_address_value for the
RESEED_SHIFTA and RESEED_SHIFTB procedures. The increment_address cell must also
be set to the its increment_address_value for the RESEED_SHIFTC, RESEED_PARTIAL_
OVERLAP_SHIFT1, and RESEED_LOAD postamble procedures. Cells which are not at their
correct value will result in a violation of this rule.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the failing
cells are at their intended value at the end of the failing procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the failing cell with all
the gates in its traceback cone. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the
increment_address cells (with increment_address values).

The -summary option of the report_compressors command can be used to report the
codec_enables with their associated enable values.

The RESEED_SHIFTA, RESEED_SHIFTB, RESEED_SHIFTC, RESEED_PARTIAL_

OVERLAP_SHIFT1, and RESEED_LOAD options of the set_pindata command can be used
to report the stored simulated values of the failing procedure.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K68

Message
DFTMAX LBIST Rule K68: Increment_address cell disturb
Increment_address cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing increment_address cell
l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state and codec enables are set
to their active state, the increment_address cells are checked to ensure that they hold state during
the SHIFT, RESEED_LOAD, RESEED_PARTIAL_OVERLAP_SHIFT2, SHADOW_TO_
CAREPRPG, and SHADOW_TO_XTOLPRPG procedures. This checking is done by performing
parallel (32) pattern simulation using the simulated values of the appropriate procedure, xtol_
enable/power_enable cells set to their off state, codec enables set to their active state, and all
other register types set to random values. Increment_address cells which do not hold state for all
of the simulated parallel patterns will result in a violation of this rule. Only one violation is issued for
a given procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that increment_
address cell holds state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the failing increment_address cell with
all the gates in the traceback cone of the input which was believed to have caused the problem.
The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or address cells.

The -summary option of the report_compressors command can be used to report the
codec_enables with their associated enable values.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K69

Message
DFTMAX LBIST Rule K69: Invalid codec_enable set decode value
operation
N codec_enable cells (input I of P/G) had invalid decode value
during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing codec_enable cells

l I indicates input ID of first failing cell in the codec_enable register

l P indicates position of failing cell in the codec_enable register

l G indicates gate ID of failing cell in the codec_enable register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set off, the codec_enable cells are checked to
ensure that they successfully perform the decode operation during the RESEED_LOAD (third
preamble shift) and RESEED_PARTIAL_OVERLAP_SHIFT2 procedures. This checking is
done by performing parallel (32) pattern simulation using the simulated values of the appropriate
procedure, and placing xtol_enable/power_enable cells to their off state, and all other register
types to random values. Codec_enable cells which do not successfully capture their expected
value for all of the simulated parallel patterns will result in a violation of this rule. The expected
values for codec_enable cells are calculated considering the values that were randomly assigned
to the increment_address, address, and broadcast cells. For patterns where the increment_
address is set to its increment_address_value, the expected value is calculated as follows:

l The expected value for the first cell is 0.

l Else if expected value of preceding codec_enable cell was 1, the expected value is 1.
l Else expected value is value assigned to preceding codec_enable cell.
For patterns where the increment_address is not set to its increment_address_value, the
expected value is calculated as follows:

l Calculate the address and broadcast values for given pattern.

l For cells whose ID<address, the expected value is 0.
l For cells whose ID=address, the expected value is 1.
l For cells whose ID>address, if broadcast=broadcast_value, the expected value is 1, else
expected value is 0.
Only one violation is issued for a given procedure.

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What Next
To correct this problem, the netlist or the test procedure file must be changed so that the failing
codec_enable cells are properly capturing data during the specified procedure. The automated
violation analysis can be used to help debug this problem. This analysis will display the first failing
cell of the failing codec_enable register. If the failure occurred on a clock/set/reset input, then the
pindata is set to the simulated values for the indicated procedure and all gates in the traceback
cone of this input are also displayed. Otherwise, the displayed pin data is set to one of the parallel
pattern values that failed and gates in the path between the failing cell and the source of its
capture data are also displayed.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, codec_enable, increment_address, address, and broadcast cells

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K70

Message
DFTMAX LBIST Rule K70: codec_enable cell disturb
N codec_enable cells (P/G) were disturbed during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing codec_enable cells

l P indicates position of failing cell in codec_enable register

l G indicates gate ID of failing cell in codec_enable register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state, the codec_enable cells
are checked to ensure that they hold state during the RESEED_SHIFTA, RESEED_SHIFTB,
RESEED_SHIFTC, and RESEED_PARTIAL_OVERLAP_SHIFT1 procedures. This checking
is done by performing parallel (32) pattern simulation using the simulated values of the
appropriate procedure, xtol_enable/power_enable cells to their off state, and all other register
types to random values. Codec_enable cells which do not hold state for all of the simulated
parallel patterns will result in a violation of this rule. Only one violation is issued for a given
procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that codec_
enable cells hold state during the specified procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the first failing cell of the failing codec_
enable register with all the gates in the traceback cone of the input which was believed to have
caused the problem. The pindata is set to the simulated values of the failing procedure.

The -cells option of the report_compressors command can be used to report the XTOL_
enable, Power_enable, or codec_enable cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K71

Message
DFTMAX LBIST Rule K71: Invalid cumulative_codec_enable set decode
value operation
N cumulative_codec_enable cells (input I of P/G) had invalid decode
value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing cumulative_codec_enable cells

l I indicates input ID of first failing cell in the cumulative_codec_enable

l P indicates position of failing cell in the cumulative_codec_enable

l G indicates gate ID of failing cell in the cumulative_codec_enable

l X indicates name of procedure

When the xtol_enable and power_enable cells are set off, the cumulative_codec_enable cells are
checked to ensure that they successfully perform the decode operation during the RESEED_
LOAD (third preamble shift) procedure. This checking is done by performing parallel (32) pattern
simulation using the simulated values of the appropriate procedure, and placing xtol_
enable/power_enable cells to their off state, and all other register types to random values.
Cumulative_codec_enable cells which do not successfully capture their expected value for all of
the simulated parallel patterns will result in a violation of this rule. The expected values for
cumulative_codec_enable cells are calculated considering the values that were randomly
assigned to the increment_address, address, and broadcast cells. For patterns where the
increment_address is set to its increment_address_value, the expected value is calculated as
follows:

l The expected value for the first cell is 0.

l Else if expected value of preceding cumulative_codec_enable cell was 1, the expected
value is 1.
l Else expected value is value assigned to codec_enable cell whose ID is 1 less than ID of the
cumulative_codec_enable cell.
For patterns where the increment_address is not set to its increment_address_value, the
expected value is calculated as follows:

l Calculate the address and broadcast values for given pattern.

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Only one violation is issued for a given procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the failing
cumulative_codec_enable cells are properly capturing data during the specified procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
first failing cell of the failing cumulative_codec_enable register. If the failure occurred on a
clock/set/reset input, then the pindata is set to the simulated values for the indicated procedure
and all gates in the traceback cone of this input are also displayed. Otherwise, the displayed pin
data is set to one of the parallel pattern values that failed and gates in the path between the failing
cell and the source of its capture data are also displayed.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, cumulative_codec_enable, increment_address, address, and broadcast
cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K72

Message
DFTMAX LBIST Rule K72: Invalid cumulative_codec_enable set
accumulate value operation)
N cumulative_codec_enable cells (input I of P/G) had invalid
accumulate value during X procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing cumulative_codec_enable cells

l I indicates input ID of first failing cell in the cumulative_codec_enable register

l P indicates position of failing cell in the cumulative_codec_enable register

l G indicates gate ID of failing cell in the cumulative_codec_enable register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set off, the cumulative_codec_enable cells are
checked to ensure that they successfully perform the accumulate operation during the RESEED_
PARTIAL_OVERLAP_SHIFT2 procedure. This checking is done by performing parallel (32)
pattern simulation using the simulated values of the appropriate procedure, and placing xtol_
enable/power_enable cells to their off state, and all other register types to random values.
Cumulative_codec_enable cells which do not successfully capture their expected value for all of
the simulated parallel patterns will result in a violation of this rule. The expected value for a
cumulative_codec_enable cell is calculated by ORing its randomly assigned value with the
randomly assigned value of its asscoiated codec_enable cell. Only one violation is issued for a
given procedure.

What Next
o correct this problem, the netlist or the test procedure file must be changed so that the failing
cumulative_codec_enable cells are properly capturing data during the specified procedure. The
automated violation analysis can be used to help debug this problem. This analysis will display the
first failing cell of the failing cumulative_codec_enable register. If the failure occurred on a
clock/set/reset input, then the pindata is set to the simulated values for the indicated procedure
and all gates in the traceback cone of this input are also displayed. Otherwise, the displayed pin
data is set to one of the parallel pattern values that failed and gates in the path between the failing
cell and the source of its capture data are also displayed.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, cumulative_codec_enable, and codec_enable cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K73

Message
DFTMAX LBIST Rule K73: Cumulative_codec_enable cell disturb)
N cumulative_codec_enable cells (P/G) were disturbed during X
procedure.

Severity
Error

Description
Note the following:
l N indicates number of failing xchains_register cells

l I indicates input ID of first failing cell in the xchains_register

l P indicates position of failing cell in the xchains_register

l G indicates gate ID of failing cell in the xchains_register

l S indicates name of CODEC associated with failing cell in the xchains_register

l X indicates name of procedure

When the xtol_enable and power_enable cells are set to their off state, the cumulative_codec_
enable cells are checked to ensure that they hold state during the RESEED_SHIFTA, RESEED_
SHIFTB, RESEED_SHIFTC, RESEED_PARTIAL_OVERLAP_SHIFT1, and RESEED_LOAD
(postamble) procedures. This checking is done by performing parallel (32) pattern simulation
using the simulated values of the appropriate procedure, xtol_enable/power_enable cells to their
off state, and all other register types to random values. Cumulative_codec_enable cells which do
not hold state for all of the simulated parallel patterns will result in a violation of this rule. Only one
violation is issued for a given procedure.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that cumulative_
codec_enable cells hold state during the specified procedure. The automated violation analysis
can be used to help debug this problem. This analysis will display the first failing cell of the failing
cumulative_codec_enable register with all the gates in the traceback cone of the input which was
believed to have caused the problem. The pindata is set to the simulated values of the failing
procedure.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, or cumulative_codec_enable cells.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K74

Message
DFTMAX LBIST Rule K74: xtol_enable inversion difference
Seq compressors S1 and S2 had different inversion parity to xtol_
enable port P.

Severity
Error

Description
Note the following:
l S1 indicates name of first seq_compressor associated with failure

l S2 indicates name of second seq_compressor associated with failure

l P indicates name of port associated with xtol_enable

For all CODECs, the inversion parity between the xtol_enable port and the connecting prpg_
shadow register cell must be the same. The inversion parity of the first CODEC is compared to
the inversion parity of all other CODECs. A violation is issued for each CODEC which has an
inversion difference.

What Next
To correct this problem, the netlist must be changed so that the inversion parity is the same for all
CODECs. The automated violation analysis can be used to help debug this problem. This
analysis will display the prpg_shadow cells assocated with the xtol_enable of the two failing
CODECS and their connection path to the xtol_enable port. There is no pindata used for this
analysis.

The -cells Prpg_shadow option of the report_compressors command can be used to

report the xtol_enable cell for a given CODEC.

The -scan_input_ports option of the report_compressors command can be used to

report the xtol_enable port. This port is the first port in the port list.

This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K74

Message
DFTMAX LBIST Rule K75: Invalid pattern_start set operation
Pattern_start cell (G) had invalid set value (V1/V2) during X
procedure.

Severity
Error

Description
Note the following:
l G indicates gate_id of failing register cell

l V1 indicates the simulated value of failing cell for failing procedure

l V2 indicates the expected value of failing cell for failing procedure

l X indicates name of failing procedure

At the end of the test_setup and shadow_to_careprpg (with capture_enable set to capture_
enable value) procedures, the pattern_start cell is checked to ensure that it is at the pattern_start
value. At the end of the jtag_reseed_setup (with pattern_start cell initialized to pattern_start
value) and jtag_reseed_setup2 (with pattern_start cell initialized to complement of pattern_start
value) procedures, the pattern_start cell is checked to ensure that it is at the complement of
pattern_start value. Cells which are not at their correct value at the end of checked procedure will
result in a violation of this rule.

The -cells option of the report_compressors command can be used to report the pattern_
start cell with its associated pattern_start value. The command usage is:

report_compressors <-all | comp_name> [-cells <PATTERN_Start>]

The test_setup, jtag_reseed_setup, jtag_reseed_setup2, and shadow_to_
careprpg options of the set _pindata command can be used to report the stored simulated
values of the failing procedure. The command usage is:

set_pindata [test_setup | jtag_reseed_setup | jtag_reseed_setup2 |

shadow_to_careprpg]
This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K74

Message
DFTMAX LBIST Rule K76: Pattern_start cell disturb
Pattern_start cell (G) was disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates gate_id of failing increment_address cell

l X indicates the name of the procedure

When the xtol_enable and power_enable cells are set to their off state and codec enables are set
to their active state, the pattern_start cell is checked to ensure that it holds state during the SHIFT,
RESEED_SHIFTA, RESEED_SHIFTB, RESEED_SHIFTC, RESEED_SHIFTD, RESEED_
SHIFTE, RESEED_LOAD, RESEED_PARTIAL_OVERLAP_SHIFT1, RESEED_PARTIAL_
OVERLAP_SHIFT2, SHADOW_TO_CAREPRPG (with capture_enable set to complement of
capture_enable value), JTAG_MISR_SHIFT, OCC_SHIFT, and capture procedures. This
checking is done by performing parallel (32) pattern simulation using the simulated values of the
appropriate procedure, xtol_enable/power_enable cells set to their off state, codec enables set to
their active state, and all other register types set to random values. Pattern_start cells which do
not hold state for all of the simulated parallel patterns will result in a violation of this rule.

The -cells option of the report_compressors command can be used to report the xtol_
enable, power enable, or pattern_start cells. The command usage is:

report_compressors <-all | comp_name> [-cells <-All | comp_name> [-

CElls <XTOL_Enable | PWR_Enable | PATTERN_Start>]]
The -summary option of the report_compressors command can be used to report the
codec_enables with their associated enable values. The command usage is:

report_compressors -summary
This rule violation can be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K74

Message
DFTMAX LBIST Rule K77: TE last cell of chain connected to TE MISR
TE last cell (G) of chain C was connected to TE MISR in compressor
S.

Severity
Error

Description
Note the following:
l G indicates gate_id of failing register cell

l C indicates the name of the failing chain

l S indicates the name of compressor associated with failing chain

If the MISR captures data from the scan chains on the trailing edge of MISR clock, then the scan
cells closest to each chain output are checked to ensure they capture data on the leading edge of
the scancell shift clocks. If a chain output cell captures on its trailing edge when the MISRs
capture on its trailing edge, a violation is issued.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that either the
MISR captures on the leading edge or the failing scancells capture data on the leading edge. The
automated violation analysis can be used to help debug this problem. This analysis will display the
failing cell with pin data set to the simulated values of the SHIFT procedure.

The -cells option of the report_compressors command can be used to report the MISR
cells. The command usage is:

report_compressors <-all | comp_name> [-cells < Misr>]

The shift option of the set_pindata command can be used to display the simulated values of the
SHIFT procedure. The command usage is:

set_pindata [shift]
This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause the ATPG patterns to be incorrect due to simulation assuming MISRs capture the newly
captured values for all shift cycles.

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DRC Rule K78

Message
DFTMAX LBIST Rule K78: T cell (G) using cycle C failed load
operation from port P.

Severity
Error

Description
Note the following:
l T indicates the register type of the failing cell. It may be a PRPG shadow input, OCC

SERDES cell, MISR_shadow SERDES (serializer/deserializer) cell, or Pattern_counter

SERDES cell)
l G indicates the gate ID of the failing register cell

l C indicates the name of the failing chain

l P indicates the name of the port that loads the data for the failing cell

When external_cycles_per_shift is set to a nonzero number, the SERDES circuitry (which

includes pipeline and serializer cells) associated with several register types is checked to ensure
that it is loaded correctly from its port inputs. The checking inserts data on the inputs of the
SERDES circuitry, simulates the associated shift procedure and the adequate number of cycles,
and then ensures that the SERDES outputs achieve the intended values at the right time. The
following SERDES register types are checked:

l PRPG_shadow register – Uses the RESEED_PARTIAL_OVERLAP_SHIFT1 procedure

and can store patterns in the SERDES_PRPG_INPUT_SHIFT

l OCC register – Uses the OCC_SHIFT procedure and can store patterns in the SERDES_
OCC_INPUT_SHIFT

l MISR_shadow register – Uses the MISR_SHADOW_SHIFT procedure and can store

patterns in the SERDES_MISR_SHADOW_INPUT_SHIFT

l Pattern_counter register – Uses the PAT_COUNTER_SHIFT procedure and can store

patterns in the SERDES_PAT_COUNTER_INPUT_SHIFT

The inputs of the SERDES circuitry are stored in the associated port list and are reported using
the report_compressors -scan_input_ports command. The outputs of the SERDES
circuitry are the segment outputs associated with the register types and can be displayed using
the report_compressors -chain_segments command.

Simulation is performed by first setting all gates to the values at the beginning of the shift
procedure associated with the selected register type. This shift procedure is then simulated for
three slow cycles (3 * N applications). Selected binary data is placed on the SERDES inputs at

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the beginning of each fast shift cycle. After the first three slow cycles, the SERDES inputs are set
to X.

The simulation of the shift procedure is repeated until all loaded binary values are fully propagated
to the SERDES outputs and compared with expected values. The SERDES outputs that do not
achieve the intended value at the appropriate time cause a violation of the K78 rule. The patterns
that were simulated during this checking can be stored during DRC using the following command:

set_drc -store_full_cycles pattern_type_for_selected_register

This data is then available for display using the following command:

set_pindata -serdes_full_cycle_period_display begin_period end_

period

What Next
To correct this problem, you need to change the netlist or the test procedure file so that the failing
SERDES load operation operates correctly. You can use automated violation analysis to help
debug this problem. This analysis displays the SERDES input and output gates associated with
the failure with pin data set to the simulated values of the associated SHIFT procedure used for
the simulation.

Since external_cycles_per_shift is set to a nonzero number, this simulation is for a full slow cycle
of N applications of the shift procedure, but the displayed data only includes three time periods:
the initial value of the first application of the shift procedure, the clock-on time of the application of
the shift procedure expected to capture, and the final time period of the last application of the shift
procedure. All slow cycle simulation data used during the analysis can be stored and displayed
using the -store_full_cycles option of the set_drc command and the -serdes_full_
cycle_period_display option of the set_pindata command. The syntax for these
options is as follows:

set_drc -store_full_cycles <serdes_prpg_input_shift | serdes_occ_

input_shift | serdes_patcounter_input_shift | serdes_misr_shadow_
input_shift>

set_pindata -serdes_full_cycle_period_display begin_period end_

period

This rule violation can be downgraded to a warning but it is not recommended since this will likely
cause corrupted patterns due to invalid loading of data through the SERDES circuitry.

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DRC Rule K79

Message
DFTMAX LBIST Rule K79: SERDES MISR cell (G) using cycle C failed
unload operation to port P.

Severity
Error

Description
Note the following:
l G indicates gate ID of the failing register cell

l C indicates the name of the failing chain

l P indicates the name of the port that loads the data for the failing cell

When external_cycles_per_shift is set to a nonzero number, the SERDES circuitry (which

includes pipeline and serializer cells) associated with several register types is checked to ensure
that it is loaded correctly from its port inputs. The checking inserts data on the inputs of the
SERDES circuitry, simulates the associated shift procedure and an adequate number of cycles,
and then ensures that the SERDES outputs achieve the intended values at the right time.

set_drc -store_full_cycles serdess_output_shift

This data is then available for display using the following command:

set_pindata -serdes_full_cycle_period_display begin_period end_

period

What Next
To correct this problem, you need to change the netlist or the test procedure file so that the failing
SERDES MISR load operation operates correctly. You can use automated violation analysis to
help debug this problem. This analysis displays the SERDES input and output gates associated
with the failure that is the pin data set to the simulated values of the associated MISR_SHIFT
procedure used for the simulation.

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set_drc -store_full_cycles serdes_output_shift

set_pindata -serdes_full_cycle_period_display begin_periodend_

period

This rule violation can be downgraded to a warning but it is not recommended since this will likely
cause corrupted patterns due to invalid loading of data through the SERDES circuitry.

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DRC Rule K80

Message
DFTMAX LBIST Rule K80: T cell (G) in position P had extended test_
setup simulation mismatch (V1/V2).

Severity
Error

Description
Note the following:
l T indicates the register type of the failing cell

l G indicates the gate_id of the failing register cell

l P indicates the name of the failing chain

l V1 indicates the simulated value of the failing cell

l V2 indicates the expected value of the failing cell

At the end of the simulation of the extended test setup using the CODEC-DRC load and shift
procedures, CODEC-DRC cells are checked to ensure they have attained their intended values.
Cells without the intended value cause this rule violation.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the
CODEC_DRC load process is working correctly. You can use automated violation analysis to
debug this problem. This analysis will display the failing cell and all gates in its traceback cone with
pindata set to the simulated values of the CODEC_DRC LOAD procedure.

This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause the ATPG patterns to be incorrect due to invalid loading of the CODEC DRC chain, which
is a critical part of the state initialization process.

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DRC Rule K81

Message
DFTMAX LBIST Rule K81: N misr_shadow cells (input I of P/G) had
invalid update values during X procedure.

Severity
Error

Description
Note the following:
l N indicates the number of failing misr_shadow cells in the failing MISR (multiple-input

signature register) shadow register

l I indicates the input that caused problem of first failing cell

l P indicates the position of the first failing cell in the MISR_shadow register

l G indicates the gate ID of the failing register cell

l X indicates the name of the procedure

The misr_shadow cells are checked to ensure that they successfully capture data from the MISR
register during the MISR_SHIFT procedure. This check performs parallel pattern simulation
using the simulated values of the MISR_SHIFT procedure and placing random values on the
MISR cells. Misr_shadow cells that do not successfully capture the expected value for all of the
parallel patterns simulated cause a violation of this rule. The expected values for a misr_shadow
cell are the values assigned to the associated cell in the MISR register. Only one violation is
issued for each misr_shadow register.

What Next
To correct this problem, you need to change the netlist or the test procedure file so that either the
MISR captures on the leading edge or the failing scancells capture data on the leading edge. You
can use automated violation analysis to debug this problem. This analysis displays the failing cell
with the pin data set to the simulated values of the SHIFT procedure.

You can use the -cells option of the report_compressors command to report the MISR
shadow cells. The syntax is as follows:

report_compressors <-all | comp_name> [-cells misr_shadow]

You can downgrade this rule violation to a warning, but it is not recommended since this will likely
cause the patterns to be incorrect due to invalid measures associated with unloading misr_
shadow_status_cells.

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DRC Rule K82

Message
DFTMAX LBIST Rule K82: N misr_shadow cells ( P/G) in compressor S
were disturbed during X procedure.

Severity
Error

Description
Note the following:
l N indicates the number of failing misr_shadow cells in the failing MISR_shadow register

l P indicates the position of the first failing cell in the MISR_shadow register

l G indicates gate ID of the failing MISR_shadow register cell

l S indicates the name of the sequential compressor associated with the failing misr_shadow

cell
l X indicates the name of the procedure

The misr_shadow register cells are checked to ensure that they hold state during the MISR_
UNLOAD procedure and all other procedures in which the MISR (multiple-input signature
register) must hold state that are not associated with MISR_SHADOW and MISR_SHADOW_
STATUS operations. This check is done by performing parallel pattern simulation using the
simulated values of the appropriate procedure. The misr_shadow cells that do not hold state for
all of the simulated parallel patterns cause a violation of this rule. Only one violation is issued for a
given misr_shadow register.

What Next
To correct this problem, you need to change the netlist or the test procedure file so that misr_
shadow cells hold state during the specified procedure. You can use automated violation analysis
to debug this problem. This analysis displays the failing cell for the failing misr_shadow register
with the pin data set to the simulated values of the failing procedure.

You can use the -cells option of the report_compressors command to report the MISR
shadow cells. The syntax is as follows:

This rule violation can be downgraded to warning, but it is not recommended since this will likely
cause the ATPG patterns to be incorrect due to simulation assuming MISRs capture the newly
captured values for all shift cycles.

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DRC Rule K86

Message
DFTMAX LBIST Rule K86 (CODEC DRC chain cell disturb)
CODEC DRC chain cell G was disturbed during T time D of X
procedure.
N DRC chain cells (P/G2) in seq compressor S were disturbed during X procedure.

Severity
Error

Description
Note the following:
l G indicates the gate_id of failing CODEC_DRC chain cell

l T indicates the time during which failure ocurred (preamble or postamble)

l X indicates name of procedure

l N indicates the number of failing cells in failing prpg_shadow register

l P indicates the position of first failing cell in the failing prpg_shadow register

l G2 indicates the gate_id of first failing cell

l S indicates the name of the sequential compressor associated with the failing cell

There are two distinct variations of this rule:

l The slow CODEC DRC chain cells are checked to ensure that they hold state during the
preamble cycles and nonshifting postamble cycles of the CODEC_DRC_LOAD_UNLOAD
procedure. This checking is done using the precalculated simulated values of the CODEC_
DRC_LOAD_UNLOAD procedure. Slow CODEC DRC chain cells which do not hold state
for all of the checked time periods will result in a violation of this rule.

l The prpg_shadow cells are checked to ensure that they hold state during the SHADOW_
TO_CAREPRPG and SHADOW_TO_XTOLPRPG procedures. This checking is done by
performing parallel (32) pattern simulation using the simulated values of the selected
procedure. Prpg_shadow cells which do not hold state for all of the parallel patterns
simulated will result in a violation of this rule. Only one violation is issued for a given prpg_
shadow register.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that failing cells
hold state during the specified procedure. The automated violation analysis can be used to help
debug this problem. This analysis will display the failing cell with pin data set to the simulated
values of the failing procedure.

This rule violation can be downgraded to warning, but it is not recommended since this will
likelycause the IP test patterns to be incorrect.

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DRC Rule K87

Message
DFTMAX LBIST Rule K87: invalid fast shifting
Misr_shadow_status cell (G) in seq compressor C was disturbed
during X procedure.
Scan cell (G) in chain C for seq compressor S had invalid fast
shifting during X procedure.

Severity
Error

Description
Note the following:
l G indicates the gate_id of failing internal scan cell

l C indicates the name of the failing chain

l S indicates the name of compressor associated with failing chain

l X indicates the name of the procedure

When external_cycles_per_shift (N) is set to a nonzero number, all scan cells are checked to
identify how many times they are pulsed during N applications of the SHIFT procedure. Scan cells
which are pulsed more than once will result in a violation of this rule. Only one violation is issued
for an internal scan chain.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that internal scan
cells shift once per N applications of the SHIFT procedure. The automated violation analysis can
be used to help debug this problem. This analysis will display the failing cell with pindata set to the
normally stored simulated values of the SHIFT procedure. When external_cycles_per_shift is set
to a nonzero number, this data only includes 3 time periods which are the initial value of the first
application of the shift procedure, the clock-on time of the application of the shift procedure
expected to capture, and the final time period of the last application of the shift procedure. To view
all time periods of all N cycles, the -store_full_cycles option of the set_drc command
can be used prior to running DRC to collect this simulation data. These values can then be
displayed using the -serdes_full_cycle_period_display option of the set_pindata
command. The command usages are:

set_drc -store_full_cycles serdes_internal_shift

set_pindata -serdes_full_cycle_period_display begin_period end_

period

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect due to invalid loading and unloading of data into and out of the
internal scan chains.

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DRC Rule K88

Message
DFTMAX LBIST Rule K88: MISR_SHADOW_STATUS cell disturb
MISR_SHADOW_STATUS cell G was disturbed during T time D of X
procedure.

Severity
Error

Description
Note the following:
l G indicates gate_id of failing MISR_SHADOW_STATUS cell

l T indicates time during which failure ocurred (preamble or postamble)

l X indicates the name of the procedure

The slow MISR_SHADOW_STATUS cells are checked to ensure that they hold state during the
preamble cycles and nonshifting postamble cycles of the MISR_SHADOW_STATUS_UNLOAD
procedure. This checking is done using the precalculated simulated values of the MISR_
SHADOW_STATUS_UNLOAD procedure. Slow MISR_SHADOW_STATUS cells which do not
hold state for all of the checked time periods will result in a violation of this rule.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that failing cells
hold state during the specified procedure. The automated violation analysis can be used to help
debug this problem. This analysis will display the failing cell with pindata set to the simulated
values of the failing procedure.

The -cells option of the report_compressors command can be used to report the MISR_
SHADOW_STATUS cells. The command usage is:

report_compressors -cells misr_shadow_status

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause the IP test patterns to be incorrect.

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DRC Rule K89

Message
DFTMAX LBIST Rule K89: Invalid ShadowMISR shift operation
N ShadowMISR cells (input I of P/G) in seq compressor S had invalid
shift values during X procedure.

Severity
Error

Description
Note the following:
l N indicates the number of failing ShadowMISR cells

l I indicates the input ID of the first failing cell in the ShadowMISR register

l P indicates the position of the failing cell in the ShadowMISR register

l G indicates the gate ID of the failing cell in the ShadowMISR register

l S indicates the name of the DFTMAX Seq CODEC associated with the failing

ShadowMISR register
l X indicates the name of the procedure

The misr_shadow_load procedure is used to ensure that ShadowMISR cells are shifting data
successfully.

What Next
To correct this problem, the netlist or the STIL protocol file must be changed so that
ShadowMISR cells are properly shifting during the specified procedure. The automated violation
analysis can be used to help debug this problem. This analysis will display the first failing cell of the
failing ShadowMISR register. If the failure occurred on a clock/set/reset input, then the pindata is
set to the simulated values for the indicated procedure and all gates in the traceback cone of this
input are also displayed. Otherwise, the displayed pin data is set to one of the parallel pattern
values that failed and gates in the path between the failing cell and the source of its capture data
are also displayed.

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause patterns to be incorrect.

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DRC Rule K90

Message
DFTMAX LBIST Rule K90: Codec "name1" differs from
MasterCODECAddress n("name2") by condition (n1/n2)

Severity
Error

Description
When MasterCODECAddress keywords are used to identify an expected relationship between
two codecs, DRC validates the required structural relationships between the two codecs. If the
structural requirements are not satisfied the MasterCODEC relationship will not be supportable.
The list of checked conditions are below. The error message also identifies the difference in value
between the first code (the "slave", reported as value n1) and the second codec (the "master"
reported as value n2).

The condition is one of the following:

l number of multiple observe modes
l full observe mode value
l full observe mode mask
l number of full-observable scanchains
l the length of scan chains on connection n (chains "ch_name1"/"ch_name2")
l the parity of scan chains on connection n (chains "ch_name1"/"ch_name2")
l the number of taps on connection n
l the tap positions on connection n, index n

What Next
To correct this problem, the codecs in the netlist and the SPF description must be aligned, or the
MasterCODECAddress reference in the SPF can be removed to not match these two codecs as
similar.

This rule violation can be downgraded to warning, but it is not recommended as this will likely
impact performance and QoR as the ATPG flow will attempt to generate patterns to apply to both
codes and will not be successful.

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DRC Rule K91

Message
DFTMAX LBIST Rule 91: Invalid initialization of MISRs
N misr (M) cells (C/G) in seq compressor S had incorrect value at
end of test_setup procedure.

Severity
Error

Description
Note the following:
l N indicates the number of failing cells in the failing MISR

l M indicates the name of the failing MISR (only used if multiple MISRs per CODEC)

l C indicates the cell ID of the first failing cell in MISR

l G indicates the gate ID of the first failing cell in MISR

l S indicates the name of the compressor associated with the failing chain

When the MASK_ALL_CHAINS cell is defined and extended test setup is not used, all MISRs are
checked to ensure they are initialized to 0 at the end of the test setup procedure. MISR cells which
are not at 0 will result in a violation of this rule. Only one violation is issued for a MISR.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that MISR cells
are set to 0 at the end of the TEST_SETUP procedure. The automated violation analysis can be
used to help debug this problem. This analysis will display the first failing MISR cell with pindata
set to the stored simulated values of the TEST_SETUP procedure. This problem can also be
corrected by supporting the usage of the extended test setup procedure in the test procedure file.

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause the first BIST pattern interval to be incorrect.

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DRC Rule K92

Message
DFTMAX LBIST Rule K92: Invalid initialization of MASK_ALL_CHAINS
cell
MASK_ALL_CHAINS cell (G) had incorrect value (V) at end of the
test_setup procedure.

Severity
Error

Description
Note the following:
l G indicates gate ID of failing cell

l V indicates the gate ID of the failing chain

When the MASK_ALL_CHAINS cell is defined and extended test setup is not used, the MASK_
ALL_CHAINS cell is checked to ensure it is initialized to the complement of the mask_all_chains_
value at the end of the test setup procedure. An incorrect value will result in a violation of this rule.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the MASK_
ALL_CHAINS cell is set to the mask_all_chains_value at the end of the TEST_SETUP
procedure. The automated violation analysis can be used to help debug this problem. This
analysis will display the MASK_ALL_CHAINS cell with pindata set to the stored simulated values
of the TEST_SETUP procedure. This problem can also be corrected by supporting the usage of
the extended test setup procedure in the test procedure file.

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause the first SEQ pattern to be incorrect.

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DRC Rule K93

Message
DFTMAX LBIST Rule K93: Invalid setting of MASK_ALL_CHAINS cell
MASK_ALL_CHAINS cell (G) had incorrect set value (V) at end of P
procedure.

Severity
Error

Description
Note the following:
l G indicates the gate_id of failing cell

l V indicates the incorrect value at end of procedure

l P indicates the name of the failing procedure

When the MASK_ALL_CHAINS cell is defined, the MASK_ALL_CHAINS cell is checked to

ensure it is set to the mask_all_chains_value at the end of the PATCOUNTER_LOAD procedure
and is set to its complement value at the end of the LOAD procedure. An incorrect value will result
in a violation of this rule.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that the MASK_
ALL_CHAINS cell is set to the correct value at the end of the PATCOUNTER_LOAD and the
LOAD procedure. The automated violation analysis can be used to help debug this problem. This
analysis will display the MASK_ALL_CHAINS cell with pindata set to the stored simulated values
of the failing procedure.

This rule violation may be downgraded to warning but it is not recommended since this will likely
cause BIST pattern intervals to be incorrect.

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DRC Rule K94

Message
DFTMAX LBIST Rule K94: Invalid MISR hold for first unload
N misr (M) cells (C/G) in seq compressor S had incorrect value at
end of test_setup procedure.
N misr (M) cells (C/%G) in seq compressor S did not hold value
during first unload.

Severity
Error

Description
Note the following:
l N indicates the number of failing cells in failing MISR

l M indicates the name of the failing MISR (only used if multiple MISRs per CODEC)

l C indicates the cell ID of first failing cell in MISR

l G indicates the gate ID of first failing cell in MISR

l S indicates the name of the seq compressor associated with the failing MISR

When the MASK_ALL_CHAINS cell is defined, all MISRs are checked to ensure they hold their
value during the first scanchain unload of a BIST pattern interval. MISR cells which do not hold
will result in a violation of this rule. Only one violation is issued for a MISR.

What Next
To correct this problem, the netlist or the test procedure file must be changed so that MISR cells
hold their value during the first scanchain unload of a BIST pattern interval. The automated
violation analysis can be used to help debug this problem. This analysis will display the first failing
MISR cell with pindata set to the stored simulated values of the TEST_SETUP procedure.

This rule violation may be downgraded to a warning but it is not recommended since this will likely
cause the BIST pattern intervals to be incorrect.

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See Also
Netlist Requirements
Working with Design Netlists and Libraries

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DRC Rule N1
Message Text
Netlist Rule N1: Line L (filename), parsing error (additional_
info).

if (READ) data_out = memory[ADDR];
// After correction

always @(READ or ADDR or WRITE_OP)

if (READ) data_out = memory[ADDR];

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DRC Rule N9
Message Text
Netlist Rule N9: Li9ne L (filename), nameless instance (<additional
info>).

Severity
Ignored

Description
A module instance is not given a name (this is an N1 error in netlist formats that require a name).

What Next
A unique name for the nameless instance is automatically generated. You can view all instance
names with the -verbose option of the report_modules command.

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Message Text
Netlist Rule N15: Line L (filename), incomplete UDP (<additional
info>).

Message Text
Netlist Rule N17: Gate-level model of UDP failed validation.
UDP not validated (<additional info>).

Severity
Error

Description
The symbolic comparison between the circuit as defined in the UDP table and the extracted
Boolean gate representation failed.

What Next
The extracted gate representation can still be correct, but too complex or not correctly defined.
You can review the derived ATPG gate model which is used by using the run_build_model
command to specify the module name in question. Then use the graphical schematic viewer to
draw the module. Start by using SETUP to select a primitive view and then using the SHOW
button and specifying a port name or the gate ID of 0. Then click the net expansion diamonds until
all gates have been drawn.

See Also
Interpreting UDP Warning Messages

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DRC Rule N18

Message Text
Netlist Rule N18: Line L (filename), Internal net and port have the
same name (additional_info).

Severity
Warning

Description
An internal net has the same name as an external port of the same module.

What Next
If the setting is not error, the internal net is renamed by suffixing "_intern". If a net by this name
already exists, a unique number is also appended to the name.
Note that renaming the net name due to this violation might cause the following issues:
l Bridging fault annotation might not match.

l Milkyway database might not match netlist in diagnostics.

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DRC Rule N19

Message Text
Netlist Rule N19: Line L (filename), unused construct (<additional
info>).

Severity
Ignored

Description
The netlist contains a construct not used for model build (such as a timing construct).

What Next
TetraMAX ATPG ignores all timing, so no user action is required.

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DRC Rule N20

Message Text
Netlist Rule N20: Line L (filename), underspecified UDP (Expected
string got string).

Severity
Warning

Description
The UDP table defined an input combination for which the output produced is X but the ATPG
derived gate-level model for the table predicts a non-X value. The line number (L) will reference
the "endtable" line from the UDP.
The most common cause of this rule violation is a missing table entry. By definition, any input
combination not explicitly given in the UDP table is assumed to produce an X for an output. When
a violation occurs the derived ATPG gate-level model predicts a non-X output where the UDP
table predicts an X either by an explicit line or by omitting a line.
Violation of this rule will not affect test coverage but can result in patterns created which fail in
simulation. When the ATPG model predicts a non-X but the simulation model predicts X there is a
potential for a mismatch. The patterns can actually work fine on real silicon but this is hard to
validate if the simulation is failing.

What Next
Usually the derived gate-level is correct with respect to silicon and the UDP table has omitted
some entries either intentionally or unintentionally that are needed to reduce modeling pessimism.
It is rare that patterns will fail simulation. You should generate some test patterns to check the
outcome. If simulation of patterns is failing, discuss with your model supplier the particular UDPs
which experience these N20 violations and see if some of the pessimism can't be removed.
If you are a library developer or simulation model builder, you might be interested in reviewing the
original UDP table. Perhaps a few edits will eliminate the warning messages.
You can review the derived ATPG gate model which is used by using the run_build_model
command to specify the module name in question. Then use the graphical schematic viewer to
draw the module. Start by using SETUP to select a primitive view and then using the SHOW
button and specifying a port name or the gate ID of 0. Then click on the net expansion diamonds
until all gates have been drawn.
# An example which results in N20 violations.

primitive MUX ( Q, A, B, SL );

output Q;
input A, B, SL;
   table
   # A B SL: Q
   # ----------------------
         0 ? 0 : 0;
         1 ? 0 : 1;
         ? 0 1 : 0;
         ? 1 1 : 1;

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# omitting the following lines produces N20 violations of:

# underspecified UDP (Expected "??x:t" got "x"). (N20-1)

  # 0 0 x : 0;
  # 1 1 x : 1;
    endtable
endprimitive
# A second example which results in N20 violations where the
intended functionality was a 2-input majority logic gate but a
number of entries to reduce pessimism were missing.

primitive MAJORITY (Z, A, B, C);

    output Z;
    input A, B, C;
    table
       # A B C : Z
       # -- -- -- : ----
          0 0 0 : 0 ;
          0 0 1 : 0 ;
          0 1 0 : 0 ;
          0 1 1 : 1 ;
          1 0 0 : 0 ;
          1 0 1 : 1 ;
          1 1 0 : 1 ;
          1 1 1 : 1 ;
    endtable
endprimitive

# The revised model to remove pessimism and eliminate N20.

Severity
Warning

Description
An entry in the UDP table conflicts with clock information derived from previous entries. This entry
is ignored in deriving the ATPG gate-level model. The line number (L) indicates the line in the file
on which the violation occurred.
A common cause of this violation is an entry which is inconsistent with prior entries defining clock
or asynchronous set/reset behavior. For example, from previous entries it has been inferred that
input Sis the asynchronous set of a latch and that input R is its asynchronous reset. If there exists
an entry that shows the state of the latch being unchanged when S and R are simultaneously
active then this is considered inconsistent with prior inferred behavior. This entry would not be
considered inconsistent if a previous entry in the UDP table had explicitly defined an input
combination with Sand R simultaneously on.
A violation of this rule will not affect test coverage but might be an indication that patterns
generated could fail simulation. This is possible whenever the derived ATPG gate-level model
does not match the simulation model.

What Next
The extracted gate representation can still be correct. However, the inconsistent entry represents
a potential problem and can indicate that the UDP is flawed. Generate some sample ATPG
patterns and then simulate them to see if there is a problem. If so, consult with your library supplier
on the UDP in question.
You can review the derived ATPG gate model which is used by using the run_build_model
command to specify the module name in question. Then use the graphical schematic viewer to
draw the module. Start by using SETUP to select a primitive view and then using the SHOW
button and specifying a port name or the gate ID of 0. Then click the net expansion diamonds until
all gates have been drawn.
# An example which produces an N23 violation of:
# (Entry ?1*?:- conflicts with clocks offstate)

primitive N23_SAMPLE ( Q, D, CK, V );

input D, CK, V;
output Q;
reg Q ;
  table
    # D CK V : Q- : Q+
    #---- ---- ---- ---- -----
(?0) 1 ? : ? : 0 ; # CK=1, latch open
(?1) 1 ? : ? : 1 ;

* 0 ? : ? : - ; # CK=0, hold

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0 (?1) ? : ? : 0 ; # open latch

1 (?1) ? : ? : 1 ;

? (?0) 0 : ? : - ; # close latch, hold

DRC Rule N28

Message Text
Netlist Rule N28: Line L (filename), unsupported priority
(<additional info>).

Severity
Warning

Description
This violation occurs when a Verilog UDP model describes behavior in which the simultaneous
application of set and reset, or set and clock, or reset and clock produces known results. The
TetraMAX ATPG primitive for a DLAT does not fully support this priority behavior for all ATPG
algorithms.

What Next
This message is mainly information of the current limitations of the ATPG tool for modeling
set/reset priorities and other types of priorities. There is really very little you can do. The
pessimistic ATPG model can result in a lower test coverage, but does not present a danger of
creating patterns that fail in simulation.
Most common forms of set/rst/clk prioritization are supported for fault grading of functional
patterns. This warning can be ignored as its effect has a potential lowering of test coverage.

See Also
Interpreting UDP Warning Messages

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DRC Rule N29

Message Text
Netlist Rule N29: Line L (filename), inout net tied to supply
(<additional info>).

Severity
Error

Description
This violation occurs when module port defined to be a bidirectional port is connected to a strong
driver such as a supply0 or supply1 net. This usually indicates a netlist error.

What Next
After reviewing the source of the error you might want to modify the netlist. If you wish to ignore
this error and continue, then change the severity of this rule to either warning or ignore using the
set_rules command and retry the run_build_model command.

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DRC Rule N30

Message Text
Netlist Rule N30: Inconsistent memory definition

Severity
Error

Description
TetraMAX ATPG has limited support for a single model that supports both simulation and ATPG
by ignoring the #nnn delays when they appear. In order to get the simulation of a RAM model to
work, it is necessary to have non-zero delay between the write port clock and the data appearing
at the read port outputs. This is accomplished by putting "#nnn" delays into the model. TetraMAX
ATPG can limitly support a single model that supports both simulation and ATPG by ignoring the
#nnn delays when they appear.

What Next
Examples and explanations:
"Edge-triggered read port", clk->name(), "cannot capture new memory
data"
"Previous edge-triggered read port",rconn->net->name(),"cannot
capture new memory data"

Edge-triggered ports always capture old data; that's the nature of edge-triggered.
You need to modify your memory model.
"Write port delays reflect dominance, not X-behavior"

Mismatch between the read/write delays and the explicitly declared behavior (`define). You need
to modify your memory model.
"LS read always reads new data and its delay should be > write port
delay %d", maxWdelay
"LS read always reads new data and its delay %d should be > write
port delay %d", minLSRdelay,
maxWdelay
"Edge-read delay should be > write delay %d for read_write=new",
minWdelay
"Edge-read delay %d should be > write delay %d for read_write=new",
maxERdelay, minWdelay
"Write delay should be > edge-read delay %d for read_write=mixed",
minERdelay
"Write delay %d should be > edge-read delay %d for read_
write=mixed", maxWdelay, minERdelay

Definition of the error is provided in the statements above.

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Category P - Path Delay Rules

P1 - parsing error
P2 - missing delay path name
P3 - duplicate delay path name
P4 - invalid pin pathname
P5 - path contains unconnected combinational node
P6 - path traverses a sequential cell
P7 - capture earlier than path cycle time
P8 - capture later than path cycle time
P9 - invalid transition indicator
P10 - path contains less than 2 nodes
P11 - duplicate delay path
P12 - multiple source delay path
P13 - multiple destination delay path
P14 - ambiguous path segment
P15 - ambiguous launch clock
P16 - ambiguous capture clock
P17 - path not connected to valid capture node
P18 - path contains duplicate node
P19 - tied value blocks path propagation
P20 - constrained value blocks path propagation
P21 - path node values not satisfiable
P22 - off-path node values not satisfiable
P23 - path conditions not satisfiable with path values
P24 - path traverses tristate enable with unresolved Z
P25 - path contains sensitizable feedback loop

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DRC Rule P1
Message Text
Path Delay Rule P1: Line L (file), parsing error (<additional
info>).

Severity
Fatal Error

Example
One example, many variations are possible:
Listing of delay paths file ckt.path with syntax error on lines 4 and 5:
    $path {
      $transition {
        reg_fd1/Q v
        XOR_2/Z ^
      }
    }

In this case, the following error is delivered:

Error: Line 4 (ckt.path), parsing error (missing ';' delimiter).
(P1-1)

Description
The file must satisfy parsing rules. The problem was first identified on line L but can have occurred
before this line in the file. Also note that there might be other errors following the first.

What Next
Identify the location of the error and correct the syntax.

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DRC Rule P2
Message Text
Path Delay Rule P2: Line L (file), missing delay path name
(assigned name = "pathP").

See Also
set_rules

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DRC Rule P7
Message Text
Path Delay Rule P7 : Capture time (T1ns) for path P occurred T2ns
earlier than path cycle time.

Severity
Error

TetraMAX DRC Rules O-2018.06

DRC Rule P10

Message Text
Path Delay Rule P10: Path defined on line L (file) contains less
than 2 nodes.

Severity
Error

Example
One example, many variations are possible:
Listing of delay paths file ckt.path with P10 error:
$path {
    $transition {
      XOR_2/A v;
    }
  }

In this case, the following error is delivered:

Error: Path defined on line 1 (ckt.path) contains less than 2
nodes. (P10-1)

Description
A delay path definition defined on line L of the delay paths file contained less than two nodes. In
order for a delay path test to be created, a delay path must be defined between at least two nodes
in the circuit. One node path might be referring to a transition fault node, not a delay fault path.
This path is invalid and will not be added to the internal delay path list.

What Next
Either remove this path from the delay path definition file or add more circuit nodes to the delay
path definition.
If both P4 and P10 messages exist, P4 might be the source of the P10 message. One example
could be that the hierarchical delimiter is "." instead of "/". The "/" is the default hierarchical
delimiter in TetraMAX ATPG.

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DRC Rule P11

Message Text
Path Delay Rule P11 : Path defined on line L (file) identical to
path P.

Severity
Warning

Message Text
Path Delay Rule P17 : Path not connected to valid capture node.

Severity
Error

Example
One example, many variations are possible:

Description
The delay path definition named P defines a path which terminates at the clock input of a state
element.

What Next
A violation can be analyzed using the graphical schematic viewer (GSV) by selecting its violation
ID number from the Analyze button dialog box. This changes the pindata reporting to delay_data
and displays the delay path segment terminating at a clock input pin of a design element or at the
input of a black box module. This path is invalid and will not be added to the internal delay path list.
This type of delay path is not supported by TetraMAX ATPG and should be removed from the
delay path definition file.

See Also
set_rules

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DRC Rule P18

Message Text
Path Delay Rule P18 : Path P has a duplicate node <pin pathname>
(G).

Severity
Error

Example
One example, many variations are possible:

Listing of delay paths file ckt.path with duplicate node error:

  $path {
    $name path0 ;
    $transition {
      XOR_8/Z v ;
      XOR_6/Z ^ ;
      XOR_8/Z ^ ;
    }
  }

In this case, the following error is delivered:

Error: Path path0 had a duplicate node XOR_8/Z (22). (P18-1)

Severity
Error

R42 - Load compressor pipeline cell ID disturbed at time T of P procedure
R43 - Load compressor pipeline cell ID disturbed during serializer initial shift cycles
at time T of P procedure
R44 - Pipeline cell ID between load serializer and load compressor does not hold
state during capture
R45 - Load compressor pipeline cell ID must not be constrained on PI_NAME
R46 - Serializer output compressor pipeline discrepancy
R47 - Nonscan cell cannot control PLL internal clocking
R48 - Load pipeline path cannot have multiple outputs with inconsistent inversions
on different paths
R49 - Load compressor is driven by a scan input with only dynamic bits
R50 - Incorrect SPC chain structure
R51 - Incorrect SPC update latch asynchronous control
R52 - Incorrect SPC load compressor propagation
R53 - SPC control register not holding state
R54 - SPC control register is not capturing a constant value
R55 - SPC chain is not in one to one mode
R56 - Decompressor or compressor has different tail or pipeline stages
R57 - Compressor scan assignment is missing in the load_unload procedure shift
vector
R58 - ScanEnable not constrained to LOGICAL LOW
R59 - Failed to extract SPC register due to incorrect number of pipeline stages
R60 - Unload compressor output pipeline cell name on output_signal does not hold
during capture

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DRC Rule R1
Message Text
Compressor Rule R1: Compressor references an undefined chain.

Severity
Fatal Error

Description
Indicates an Error in protocol file. A chain referred to in CompressorStructures section is not
defined as scan chain in the ScanChain section

What Next
If the protocol file is generated by DFT Compiler, please submit a testcase.

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DRC Rule R2
Message Text
Compressor Rule R2: Chain input not connected to a load compressor.

Severity
Fatal Error

Description
Indicates an error in the netlist file. An internal chain input is not connected to the decompressor.

What Next
If the netlist is generated by the DFT Compiler, please submit a testcase.

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DRC Rule R3
Message Text
Compressor Rule R3: Chain output not connected to an unload
compressor.

Severity
Fatal Error

Description
Indicates an error in the netlist file. An internal chain output is not connected to the compressor.

What Next
If the netlist is generated by the DFT Compiler, please submit a testcase.

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DRC Rule R4
Message Text
Compressor Rule R4: Load compressor U_decompressor does not have an
internal connection for output X during mode Y.

TetraMAX DRC Rules O-2018.06

Connection 0 "2" "9" "15" "20" "26" "32" "38" "45" "51"
"56" "63"
"69" "74" "80" "85" "91" "96";
…
Search for chain “X” in the list of connections listed under the mode “Y” specified in the R7 rule
violation. The mode control pins are listed in the ModeControls block.
Connection 0 (as in the example, above) refers to “sccompin0” which points to the pin "ci_i_rdata_
de[1]", as shown below:
ScanChain "sccompin0" {
ScanIn "ci_i_rdata_de[1]";
}
In the example, "Connection 0" would list the chain “X” called out by the R7 violation. The “0” of
“Connection 0” is the same as the “0” of “sccompin0”. Make sure you use the Connection and
Mode with chain “X” listed in it, and called out by the R7 violation.

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DRC Rule R8
Message Text
Compressor Rule R8: Incorrect unload compressor operation Default
Severity: Error

Severity
Error

Description
This violation indicates that the compressor connections specified in protocol file do not match the
connections in the netlist.

What Next
If you used DFT compiler to add compressors and generate the netlist, please submit a test case
to Synopsys. For more information, see the -set_unload_mode_ports_to_x option of the
set_drc command.

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DRC Rule R9
Message Text
Compressor Rule R9: Two chains always have the same load value

Severity
Warning

Description
This message indicates that the current chain count exceeds the maximum load-independence
threshold. This threshold is the maximum number of chains that can used when creating a load
decompressor in which any two chains can be load-independent values (for example, any two
chains can load 00, 01, 10, or 11, as needed).
The following table shows the threshold levels for the number of scan inputs and the maximum
number of any two load-independent chains for a high X-tolerance codec:

Number of Maximum Number of Any

Scan Inputs* Two Load-Independent
Chains
2 1
3 2
4 4
5 16
6 81
7 256
8 625
9 1296
10 2401
11 4096
12 6561
13 10000
14 14641
15 20736
20 83521
25 234256
30 531441
* In a serializer flow, the first column ("Number of Scan Inputs") refers to the number of
combinational decompressor scan inputs driven by the deserializer, as specified by the -inputs
option of the set_scan_compression_configuration command in DFT Compiler.

What Next
Either increase the number of scan input pins or decrease the number of chains in the load
decompressor.

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DRC Rule R10

Message Text
Compressor Rule R10: Two chains always have the same unload
signature was violated X times.

Severity
Warning

Description
This message indicates that the threshold was exceeded for the maximum number of chains that
can be used to create an unload compressor without aliasing (no two chains have errors that
cancel out each other). This violation is dependent on the compressor architecture and not the
design; it might reduce diagnostic effectiveness and lower diagnostic precision.

The following table shows the thresholds for the number of scan outputs and the maximum
number of chains for creating an unload compressor with no aliasing:

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DRC Rule R23

Message Text
Compressor Rule R23 : Unload mode enable port_name at off_state
does not condition full compression on output port of port_name
(description)
Note that the description can be one of the following:
1. No sensitized path from chain chain_name.
2. No sensitized XOR path from chain chain_name.
3. Unexpected sensitized path from chain chain_name blocked by X
value.
4. Blocked by X value.

Severity
Error

Description
DFTMAX compression with enhanced X-tolerance may operate in two modes:
l The default mode is Full XOR. In this mode, the DFTMAX circuitry does not use any

additional X masking and operates as if classic DFTMAX is being used.

l In selective mask mode, DFTMAX compression enables additional X masking. Most shift

cycles do not require a selective mode for masking and could achieve higher observability in
full compression (full XOR) mode. The unload mode enable should create the full
compression condition on a per-shift basis.
Note that downgrading this rule to pass DRC might result in increased pattern count
In the description #1 version of the message, the value placed on the named chain has NO effect
on the named output. Only the first problem chain is listed.
In the description #2 version of the message, the value placed on the named chain has an effect
on the named output, but the effect is not that of an XOR. Only the first problem chain is listed.
In the description #3 version of the message, the value placed on the named chain has an effect
on the named output, but no connection was expected based on the protocol file description of the
compressor. Only the first problem chain is listed.
In the description #4 version of the message, the named output is blocked by an X value, so it
does not reflect the XOR of the chain values.

What Next
1. Specify the following:
set_pindata -drcdata unload_enable
2. Browse in the GSV and see what happens during shift with unload_enable at
off_state: it should be full-XOR mode. Follow the shift path (X) from the DFF
on the output of chains to the output ports; or back from the output ports to
the DFF.
Note that the schematic is annotated with a value per gate derived from the shift procedure, plus
the unload_enable primary inputs at their off_state. The output gates of internal scan chains are
placed at X, so that you can trace the sensitized path in the GSV -- except in the case of "Blocked

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by X value." In this case, the output gates of internal scan chains are placed at random binary
values -- thus enabling you to use the GSV to trace X-blockage.
For more information, see the -set_unload_mode_ports_to_x option of the set_drc
command.

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DRC Rule R24

Message Text
Compressor Rule R24 : Unable to infer output of chain C for unload
compressor

Severity
Fatal Error

Description
TetraMAX DRC initially tries to infer the connection between scan chains and the unload
compressor. It traces from the scanout ports back through the unload compressor until it reaches
a scan flip-flop. Since each scanout port is fed by multiple scan chains, tracing back from a
scanout port creates a collection of scan chains that drive that particular scanout port. From this
information, DRC infers the scanout ports driven by each scan chain. The CompressorStructures
block in the STL procedure file used for DRC contains similar information. When
TetraMAX ATPG infers the scanout ports driven by a scan chain, the DRC process does not
match the same ports as specified in the protocol file, and an R24 message is printed.
An R24 error can also be reported in the following cases when running DFTMAX Ultra
compression:
l The deserializer chain was incorrectly traced.

l A scan chain tracing failure occurred because of incomplete shift DRC tracing.

What Next

1. Specify the following:

set_drc -compressor_debug_data
2. Execute the run_drc command to produce verbose output for debugging.
3. Add the missing element to the graphical schematic viewer (GSV).
4. Set the pindata to shift.
5. Analyze the violation.

If the ScanDataOut pin for a ScanChain is specified in a design’s ScanStructures section of the
protocol, make sure that the Place-and-Route tool does not make any changes from that pin.
Failure to do this can result in pattern mismatches in simulation and on the ATE.

Example

Begin compressor chain I/O checking: #undefined_io=6576 ...

Warning: #candidate chains (3287) and #connecting chains (3288)

for unload compressor SUB_AudioVideo_U_compressor are different.
(M620)

Error: Unable to infer output of chain 1877 for unload compressor.

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(R24-1)

Begin R24 debug data: Chain=1877, connection_ports = test_so54

test_so91

------------------------------------------------------

output_id instance_name of cell on chain output

connections
--------- -------------------------------------------------------
----------------------- --------------

364962 c8compo1_7100_top_0/i_compo_gen/i2_vp_mdl/i_vp_reg_
mdl/vp_reg_coeff1r_regx17x test_so1 test_so23

There are many lines similar to the previous example. In the previous example, gate id 364962
has been identified as the output of an internal chain that connects, through the unload
compressor, to POs test_so1 test_so23; this chain will then be matched to a chain defined in the
STL procedure file that connects to the same outputs.
To see the connections, run set_pindata shift and trace through the GSV.

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Message Text
Compressor Rule R28: Clock chain connected to multiple ports

Severity
Error

Description
This message indicates that the clock chain (that is, a scan chain that contains one or more scan
cells used to control internal clocking) must connect to the same scan input and must be
independent of the load decompressor mode. Note that the clock cells are always care bits, so
they must be set to 0 or 1 in every pattern. If this requirement is not met, there might be a loss of
test coverage and pattern inflation because of the additional load decompressor dependencies
between the clock cells and other scan cells.

What's Next
Because of the potential for test coverage degradation and pattern inflation, you should not
downgrade this rule to pass DRC. Instead, you should change the DFT implementation. In this
case, DFTMAX constructs and connects a compressor to prevent this rule violation -- but only if it
is specified with a clock chain.
A common error in the OCC controller recognition flow is to omit the set_scan_path -class
occ command to force the DFT architect to recognize the clock chain. It is important to specify
this command at the hierarchical level in which the OCC controller is first declared. In a
hierarchical flow, this problem might occur only at a higher level.

In all cases, the preview_dft command report should show that the clock chain is a segment
with the "occ" property. For example:

Scan chain '1' contains 4 cells

Active in modes: ScanCompression_mode :
CORE/clock_chain (s) (o) (m) (CORE/duto/clk, 45.0, rising)
The string "(o)" refers to a clock chain. All clock chain segments should have this tag. If it is
missing, then DFTMAX compression might stitch the clock chain to cause a rule violation.

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DRC Rule R29

Message Text
Compressor Rule R29 : Clock chain port used for X-tolerance control

Severity
Error

Description
This message indicates that the chain (that is, a scan chain that contains one or more scan cells
used to control internal clocking) must connect to a scan input which is not used to control X-
tolerance. Note that the clock cells are always care bits, so they must be set to 0 or 1 in every
pattern. If this requirement is not met, there might be a loss of test coverage and pattern inflation
because of the additional load decompressor dependencies between clock cells and X-tolerance
controls.

What Next
Because of the potential for test coverage degradation and pattern inflation, you should not
downgrade this rule to pass DRC. Instead, you should change the DFT implementation. In this
case, DFTMAX constructs and connects a compressor to prevent this rule violation -- but only if it
is specified with a clock chain.
A common error in the OCC controller recognition flow is to omit the set_scan_path -class
occ command to force the DFT architect to recognize the clock chain. It is important to specify
this command at the hierarchical level in which the OCC controller is first declared; in a
hierarchical flow, the problem might only occur at a higher level.

In all cases, the preview_dft command report should show that the clock chain is a segment
with the "occ" property. For example:

Scan chain '1' contains 4 cells

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DRC Rule R30

Message Text
Compressor Rule R30 : Nonclock chains <name1> and <name2> are not
independent when clock chain inputs are ignored.

Severity
Warning

Description
The load decompressor must be designed to minimize dependencies between scan chains. At a
minimum, any two non-clock chains must be independent in at least one load mode. Because
clock cells are always “care bits” (they must be set to 0 or 1 in every pattern), non-clock chains
should be independent of each other and of clock chain scan inputs. Failure to satisfy this
requirement will result in additional load decompressor dependencies between non-clock chains.
The clock chain bits is set properly, so this rule violation does not indicate that bad patterns are
generated.

What Next
If this rule fails, during ATPG the results might be a loss of test coverage and pattern inflation due
to the additional load decompressor dependencies.

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DRC Rule R31

Message Text
Compressor Rule R31
Incorrect defined multi chain X-tolerant connection to output N of
unload compressor X using mode L/U.
Incorrect defined X-tolerant connection for chain C to output N of
unload compressor X using mode L/U.

Severity
Error

Description
This rule checks the correctness of the defined connections (if they are defined) between chain
outputs and the outputs of an unload compressor for a given X-tolerant mode, as specified by a
load and unload mode value.
There are two variations of this rule: the first is for modes with a single chain connection to a
compressor output; the second is for modes with multiple chain connections to a chain output.
Note the following:
l C is the name of the chain

l N is the ID number of the output of the unload compressor

l X is the name of the unload compressor

l L is the load mode value

l U is the unload mode value

This rule is checked by simulating the conditions set up by the shift procedure augmented by the
conditioning of a given load and unload mode (including the X-tolerant enable pin set to its active
value) and with the chain outputs set to random values. The simulated value of an output of an
unload compressor is compared with its expected value as determined by its defined connections.
If this rule fails, the connection definition might be incorrect or the conditioning set up by the shift
procedure might be incomplete. There is no automated violation analysis available for this
violation to assist in debug.
This rule can be downgraded to a warning to pass DRC, however there is a high risk that the
patterns might not work at the tester.

What Next
To debug a selected violation, specify the following command before before run_drc:
set_drc -store_unload_mode_data L
In this case, data for up to 32 unload modes is stored for the selected load mode, L. Next, specify
the following:
set_pindata -drcdata {unload_mode U}
At this point, you need to open the GSV and trace back the sensitized (X) path from the output N
of the unload compressor to determine why it does not connect to the expected scan chain output
(s).
For more information, see the -set_unload_mode_ports_to_x option of the set_drc
command.

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DRC Rule R32

Message Text
Compressor Rule R32
Unload compressor <unl_comp_name> had invalid capturing edge on
cell <unl_gate_id> from load compressor cell <load_gate_id>.

Severity
Error

Description
This rule checks the edges of load and unload compressor pipelines for X-tolerant compressors.
A violation occurs if a load compressor cell, indicated by <load_gate_id>, is a leading-edge (LE)
cell and an unload compressor cell, indicated by <unl_gate_id>, is a trailing-edge (TE) cell. The
LE-TE data transfer could occur in a single cycle, thus patterns might fail.
Downgrading this error to pass DRC could result in patterns that fail simulation and on the tester

What Next
The edge of the pipeline cells must be changed, or lockup latches must be inserted to eliminate all
LE-TE paths.

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DRC Rule R33

Message Text
Compressor Rule R33
Unable to find output output_id of unload compressor name.

Severity
Fatal Error

Description
When unload serializers are used, random pattern simulation of the events in the load and shift
procedures is performed to identify unload compressor output nodes. This violation occurs when
there is a failure to identify a DFF (D flip-flop) gate containing data input with the expected value at
the appropriate cycle.

What Next
This violation is a fatal error, and must be corrected to pass DRC. There is no automated violation
analysis for this rule. You can use the report_serializers -all command to display the
serializer data and identify unload serializer outputs. Normally, the problem is due to an incorrect
netlist or test procedure file.
This error can occur if the top-level serializer protocol is generated by the spfgen utility or
manually created, and the ScanEnable signal in not constrained. In this case, you must constrain
the ScanEnable signal to 0 using the add_pi_constraints 0 command.
If both R33 and R35 errors are reported, you should investigate all R35 errors first.
If you encounter only R33 errors, and no R35 errors, you should perform the following steps:
1. Specify the set_drc -store_initial_shifts command.
2. Specify the set_pindata -shift command
3. Execute the run_drc command.
4. Perform the following examinations:
l Use the GSV to make sure the clock behavior is correct by checking clock pins of

unload serializer registers.

l Make sure no unexpected blockage occurs on unload serializer registers that traverse

data paths to scan output ports.

To understand the pindata values, refer to the “Debugging TetraMAX Serializer DRC Errors”
section in the Adaptive Scan with Serializer User Guide.
If there are no problems on the signals, there might be problems on the internal scan chains or
inside the compressor logic.
The following steps enable TetraMAX ATPG to recognize user-provided unload serializer
registers without undergoing the identification process during DRC. This allows you to move on to
subsequent DRC processes.
1. Specify unload serializer register names in the STIL procedure file. For more information,
refer to the “DFTMAX Compression with Serializer” section in the DFT Compiler,
DFTMAX, and DFTMAX Ultra User Guide.
2. Reset the set_drc -nostore_initial_shifts command.

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3. Specify the set_drc –nocheck_user_serializer_bits command.

4. Execute the run_drc command.
By applying these steps, you can move on to subsequent DRC processes in which S and R
violations (other than R33 to R38) might appear. You can usually debug these violations using the
GSV. This enables you to skip serializer-specific DRC and move on to scan DRC and DFTMAX
DRC. You will most likely encounter S or R violations (other than R33 to R38), and you should
debug them.

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DRC Rule R34

Message Text
Compressor Rule R34
Multiple candidates gate_id1, gate_id2 for output output_id of
unload compressor name.

Severity
Error

Description
When unload serializers are used, the unload compressor output nodes are identified via random
pattern simulation of the events in the load and shift procedures. This violation occurs when more
than one D flip-flop (DFF) gate is identified containing a data input with the expected value at the
appropriate cycle.

What Next
You can downgrade the severity of this violation and continue the DRC process. If multiple
candidates are identified for an unload compressor output, the first candidate identified is
selected. Additional DRC failures will occur if you downgrade the severity, and the first candidate
is incorrect.
If you encounter an R34 error, you can edit the STIL procedure file to specify the correct unload
serializer registers, as shown in the following example:

UserKeywords SerializerStructures CompressorStructures;

    }
    UnloadSerializer "abc_top_U_serializer_abc" {
      Length 5;
      ActiveScanChains unload_group;
      ParallelInputs {
        0 "abc_top_U_compressor_abc/serial_reg_0_" no
        1 "abc_top_U_compressor_abc/serial_reg_1_" no
        2 "abc_top_U_compressor_abc/serial_reg_2_" no
        3 "abc_top_U_compressor_abc/serial_reg_3_" no
        4 "abc_top_U_compressor_abc/serial_reg_4_" no
      }
    }

For more information, refer to the “DFTMAX Compression with Serializer” section in the DFT
Compiler, DFTMAX, and DFTMAX Ultra User Guide.

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DRC Rule R35

Message Text
Compressor Rule R35
Unable to find input input_id of load compressor name.

Unable to find xtol-enable input of unload compressor name.

Unable to find mode-port input with serializer connection port_name

position.

Severity
Fatal Error

Description
When load serializers are used, random pattern simulation of the events in the load and shift
procedures is performed to identify the load compressor input nodes, xtol-enable input nodes,
and mode-port input nodes. Failure to identify any D flip-flop (DFF) gates with an output
containing the expected value at the appropriate cycle will result in this violation.

What Next
This violation is a fatal error, and you must fix it to pass DRC. There is no automated violation
analysis for this rule. You can use the report_serializers -all command to display
serializer data and identify load serializer inputs.
If you encounter any R35 errors, you should perform the following steps:
1. Specify the set_drc -store_initial_shifts command.
2. Specify the set_pindata -shift command
3. Execute the run_drc command.
4. Perform the following examinations:
l Use the GSV to make sure the clock behavior is correct by checking clock pins of the

load serializer registers and update stage registers (if they are used).
l Make sure no unexpected blockage occurs on load serializer registers that traverse

data paths to scan input ports.

To understand the pindata values, refer to the “DFTMAX Compression with Serializer” section in
the DFT Compiler, DFTMAX, and DFTMAX Ultra User Guide.
After you finish the debugging process, make sure you reset the set_drc -nostore_
initial_shifts command.

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DRC Rule R36

Message Text
Compressor Rule R36
Multiple candidates gate_id, gate_id for input input_id of load
compressor name.

Multiple candidates gate_id, gate_id for xtol-enable input of

unload compressor name.

Multiple candidates gate_id, gate_id for mode-port input with

serializer connection port_name position.

Severity
Error

Description
When load serializers are used, random pattern simulation of the events in the load and shift
procedures is performed to identify load compressor input nodes, xtol-enable input nodes, and
mode-port input nodes. This violation occurs when more than one D flip-flop (DFF) gate is
identified with an output that has an expected value at the appropriate cycle.

What Next
You can reduce the severity of this violation and continue the DRC process. If multiple candidates
are identified for a load-compressor, xtol-enable, or mode-port input, the first candidate identified
is selected. If you reduce the severity and this candidate is not the correct choice, then other DRC
failures will occur.
If you encounter an R36 error, you can edit the STIL procedure file to specify the correct load
serializer registers, as shown in the following example:

UserKeywords SerializerStructures CompressorStructures;

SerializerStructures {
    InternalShiftStart 6;
    UnloadDataStart 7;
    ExternalCyclesPerShift 5;
    LoadSerializer "abc_top_U_deserializer_abc" {
      Length 5;
      ActiveScanChains load_group;
      ParallelOutputs {
        0 "abc_top_U_compressor_abc/serial_reg_0_" no
        1 "abc_top_U_compressor_abc/serial_reg_1_" no
        2 "abc_top_U_compressor_abc/serial_reg_2_" no
        3 "abc_top_U_compressor_abc/serial_reg_3_" no
        4 "abc_top_U_compressor_abc/serial_reg_4_" no
      }
    }
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UnloadSerializer "abc_top_U_serializer_abc" {
      Length 5;
      ActiveScanChains unload_group;
    }
}

For more information, refer to the “DFTMAX Compression with Serializer” section in the DFT
Compiler, DFTMAX, and DFTMAX Ultra User Guide.

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DRC Rule R37

Message Text
Compressor Rule R37: Scan cell gate_id was clocked during
serializer nonshifting cycle.

Severity
Error

Description
When serializers are used, random pattern simulation of the events in the load and shift
procedures is performed to verify that D flip-flops (DFFs) are not clocked in the same nonshift
cycle. The pattern simulation is done at the same time the load compressor inputs and unload
compressor outputs are identified. An R37 error is issued if the DFFs are clocked during a
nonshift cycle. Later in the DRC process, after the scan cells have been identified, the scan cell
master cells are checked to make sure they are not clocked during nonshift cycles.
When using the set_drc –store_initial_shifts command, the first InternalShiftStart
shift cycles are stored and can be inspected when the pindata is set to shift. However, this applies
strictly to situations when you are debugging R violations that occur before tracing the internal
scan chains (since storing all cycles in the shift will not allow the tracing of internal scan chains).
An M464 warning message is issued in this case.

5. Trace back the clock signal to determine why it is clocked in a nonshift cycle, and identify
any differences from other scan cells without the R37 violations.

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DRC Rule R38

Message Text
Compressor Rule R38
Scan cell gate_id was not clocked during serializer shifting cycle.

Severity
Error

Description
When serializers are used, random pattern simulation of the events in the load and shift
procedures is performed to verify that the D flip-flops (DFFs) are clocked in a shift cycle. This
pattern simulation is performed at the same time the load compressor inputs and unload
compressor outputs are identified. An R38 violation is issued if the DFFs are not clocked in a shift
cycle. Later in the DRC process, after the scan cells have been identified, the scan cell master
cells are checked to make sure they are clocked during shift cycles.
When using the set_drc –store_initial_shifts command, the first InternalShiftStart
shift cycles are stored and can be inspected when the pindata is set to shift. However, this applies
strictly to situations when you are debugging R violations that occur before tracing the internal
scan chains (since storing all cycles in the shift will not allow the tracing of internal scan chains).
An M464 warning message is issued in this case.

What Next
You can downgrade the severity of this violation, and continue the DRC process. If you reduce
the severity, the patterns generated during ATPG will not work at the tester. Normally, the
problem is due to an incorrect netlist or test procedure file.
You can debug an R38 error by performing the following steps:
1. Specify the set_drc -store_initial_shifts command.
2. Specify the set_pindata -shift command
3. Execute the run_drc command.
4. Use the GSV to display the gate ID reported with the R38 violation, and examine the
pindata on the clock line.
5. Trace back the clock signal to determine why it is not clocked in a shift cycle, and identify
any differences from other scan cells without R38 violations.
To understand the pindata values, refer to the “DFTMAX Compression with Serializer” section in
the DFT Compiler, DFTMAX, and DFTMAX Ultra User Guide.
After you finish the debugging process, make sure you reset the set_drc -nostore_
initial_shifts command.

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DRC Rule R39

Message Text
Compressor Rule R39
Unload compressor decompressor failed propagation checking for
chain n in unload mode M.

Severity
Error

Description
During tracing from the ScanOut port, the expected mask bits were not found for the identified
unload mode.

What Next

1. Specify the following:

set_drc -compressor_debug_data
2. Execute the run_drc command to produce verbose output for debugging.

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DRC Rule R40

Message Text
Compressor Rule R40
Could not find flop at index (N) of Load Serializer (M)

Severity
Error

Message Text
Compressor Rule R50
Ignore: Incorrect SPC chain structure at SPC_serial_reg_instance
(gate_id).

Severity
Ignore

Description
TetraMAX ATPG expects a value of 0 in the shift power controller (SPC) register in order to turn
off a group of chains. This rule violation indicates inversions leading up to the SPC control
register. As a result, the register receives a value of 1 instead of 0.

What Next
This is an informational message only. If the violation is not corrected, you can run ATPG and
generate patterns as normal.

Example
TEST-T> report_violation r50_1
Ignore: Incorrect SPC chain structure at OCC_ready_U_DFT_spwr_
cntrl_chain_0/serial_reg_4_ (11408). R50-1
You can use the analyze_violation command to highlight the SPC register that violated the
R50 rule, as shown in the following figure.

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DRC Rule R51

Message Text
Compressor Rule R51
Error: Incorrect SPC update latch asynchronous control in SPC_
update_latch_instance (gate_id).

Severity
Error

Description
This rule checks the clock/set/reset inputs of the shift power controller (SPC) update latches. A
violation indicates any of the following:
l The set input is not off
l The reset input is not off
l The clock/enable input is not OFF during shift procedures
l The clock/enable input is not ON during capture

What Next
This rule can be downgraded to expedite debugging. If the violation is not corrected, you can run
ATPG generate patterns as normal. However, there is a high probability that the resulting
patterns will fail the Verilog resimulation.

Shift pindata is selected bythe analyze_violation command so that violations can be

Severity
Error

Description
This rule applies to Serializer DFTMAX architectures when the shift power controller (SPC)
control chain is an internal chain, with the output of this chain connected to the unload
compressor. It is expected that the input of the chain is always in one to one mode. Downgrading
this rule to warning can result in patterns that will fail simulation and on the tester.

What Next
You must modify the design so the decompressor or compressor have the same head or tail
pipeline stages.

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DRC Rule R56

Message Text
Compressor Rule R56: [Decompressor | Compressor] name has different
[head | tail] pipeline stages pipeline_length and seg_pipeline_
length for its [inputs | outputs].

Severity
Error

Description
Indicates that a particular decompressor or compressor (name) contains different head or tail
pipeline stage lengths for its inputs or outputs. The pipeline length and segment pipeline length
are indicated by the pipeline_length and seg_pipeline_length parameters.

For example, if a decompressor has two inputs, the head pipeline stages for both inputs should be
the same, but different decompressors can have different head pipeline stage lengths.
Compressors can also have different tail pipeline stage lengths.

What Next
Modify your design so the decompressor or compressor has the same head or tail pipeline stage
lengths.

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DRC Rule R57

Message Text
Compressor Rule R57: Compressor Scan <Input | Output> signal_name=#
assignment is missing in the load_unload procedure Shift Vector.

Severity
Error

Description
Indicates the parameters specified in the load_unload procedure are incomplete and cannot
support a call from the patterns. The output pattern data references the signal_name. However,
the pattern data cannot pass into the test without a matching reference to the indicated signal in
the load_unload procedure.

What Next
Review the set of signals in the Shift block vector of the load_unload procedure. Typically, these
signals are referenced by the “_si” or “_so” group. In this case, a group is likely missing the
indicated signal. If this signal is not intended to be included in the passed data, you can use the
set_rules command to downgrade this rule violation to a warning to pass DRC.

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DRC Rule R58

Message Text
Compressor Rule R58: ScanEnable name not constrained to LOGICAL
LOW.

Severity
Warning

Description
If the ScanEnable name is not constrained to "LOGICAL LOW," serial simulation might fail.

What Next
If this warning is unnecessary, you can remove it by adding the add_pi_constraints
command to the script, as shown in the following example:

add_pi_constraints 0 scan_en

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DRC Rule R59

Message Text
Failed to extract SPC register due to incorrect number of pipeline
stages.

Severity
Error

Description
If the number of pipeline stages in the shift power controller (SPC) control chain is different than
the number of internal chains, the SPC registers could be misidentified and incorrectly classified
as pipeline and SPC control registers during scan chain extraction. This can lead to a crash or
incorrect behavior during DRC.

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DRC Rule S5
Message Text
Scan Chain Rule S5: N (G) in chain C previously used in chain
trace.

Severity
Fatal Error

Example
One example, many variations are possible:

Description
A latch or flip-flop gate can only be traced once during the scan chain tracing process. The
indicated cell was either traced twice for the same scan chain or is part of a previously traced scan
chain and marked as part of the other scan chain already.

What Next
This is a fatal error condition that requires either removing the scan chain from the chain list or
changing the chain conditioning. You can analyze a violation using the schematic analysis by
selecting its violation ID number. This sets the gate reporting to the shift procedure simulated data
and displays as a schematic the multiply traced gate.

Message Text
Scan Chain Rule S19: Nonscan Cell I (G) disturbed at time T of P
procedure.

Severity
Warning

Example
One example, many variations are possible:

Description
Nonscan cells must hold their state during the application of the load_unload procedure.
C is the cell type of DFF or DLAT, I is the instance pathname of the affected scan cell, G is its
corresponding gate_ID, P is the name of the procedure, and T is the time within the procedure
when the nonscan cell was disturbed.
Passing this rule allows the fault simulator and test generator to use nonscan cell values that exist
before loading and unloading scan chains to advantage and can increase test coverage. Failing
this rule means the nonscan cells are treated as containing X values, and can't be used to
advantage when creating ATPG patterns. There is no danger of generating patterns which fail
simulation.
This check is performed using the simulated values of each time period of the load_unload test
procedure. A rule violation occurs if any nonscan cell clock/set/reset line becomes potentially
active. For a given nonscan cell, only the first occurrence of a violation is reported.

What Next
It is quite common for designs which contain both scan and nonscan sequential cells to have the
nonscan cells disturbed. This DRC violation should only be of concern if you had expected the
nonscan cells to be stable by design. If this is the case, then further investigation should be
performed.
One common cause of this S19 violation is the DFF devices which form the output registers on
synchronous RAMs. As TetraMAX ATPG creates a derived ATPG model for the RAM it inserts
DFF devices for the RAM data output ports. These devices are nonscan and can trigger the S19
violation.

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You can analyze a violation using the schematic analysis by selecting its violation ID number. This
sets the gate reporting to the failing procedure pattern data and displays all gates in the back trace
cone of the disturbed gate.
It's important to note that the loadable nonscan cells feature is limited in its effectiveness. It will not
be of much benefit if the load_unstable cells form a deep sequential circuit, have sequential loops,
or are fed by X-generators. Since this feature has runtime penalties in DRC, ATPG, and
simulation, you should make sure you are getting a net benefit when using it. You can check its
effectiveness by comparing the number of S19 violations to the following line of run_drc output
(which is only printed when the set_drc -load_nonscan_cells command is specified):
Nonscan load cell identification completed: #load_nonscan_cells=6
(nonx=4)
Note that the loadable nonscan cells feature is beneficial if the #load_nonscan_cells value is
large and/or this value comprises a large percentage of S19s violations.

Message Text
Scan Chain Rule S28: Latch N (G1) not transparent due to connection
to failing TE port (G2).

Severity
Ignored

Example
One example, many variations are possible:

Description
A potential transparent latch gate must not have a path to a trailing edge (TE) cell that can capture
new data.
A violation of this rule introduces no danger of generating bad patterns but is a warning that a
potential reduction of test coverage can result because the latch cannot be made transparent.

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DRC Rule S29

Message Text
Scan Chain Rule S29: Dependent slave I1 (G1) cannot hold same value
as master I2 (G2).

Severity
Warning

Description
A dependent slave device must always carry the same value as its master device. I1 and I2 are
instance pathnames. G1 and G2 are the corresponding gate ID numbers.
If this rule is violated, the dependent slave device might have a value different than its master
device either at the end of the shift procedure or after a capture clock. This might lead to the
generation of ATPG patterns that fail during simulation. However, TetraMAX ATPG takes steps
to avoid a potentially bad patterns as described in the What Next section.
TetraMAX ATPG performs this check using shift data. It considers the first device to be loaded
during shift as the master and the second device loaded during shift as the dependent slave.

What Next
You can continue by changing the severity of this rule to either warning or ignore using the set_
rules command and then repeating the run_drc command. The ATPG algorithm marks the
affected master or slave device as an observe X device to avoid generating patterns that fail in
simulation. However, this observe X condition might result in lower test coverage.
To analyze a violation using the schematic viewer, select its violation ID number from the
ANALYZE button. This changes the pin data reporting to shift data and displays the gates in the
path from the master device to the dependent slave device.
The following are common causes of the S29 scan chain rule violation:
l A dependent slave device does not have exactly the same asynchronous set and reset
controls as its master device. If the dependent slave has different values than its master,
erroneous simulation data is created.
l You are using the wrong polarity for clocks. TetraMAX ATPG classifies a device as master
or dependent slave (DSLAVE) based on which device captures first during a shift
procedure. If you define clocks with the wrong polarity, TetraMAX ATPG classifies a
DSLAVE device as a MASTER device and associates it with a downstream sequential
device instead of the upstream device. You should reverse the polarity of all clocks
associated with the scan chain on which the S29 violation occurs.
l A dependent slave device has a different clock than its master device with the opposite off
state (phase). When this occurs, you might be able to redefine the polarity of a single clock
for one of the devices (usually the dependent slave). When both devices use the same
phase clock you eliminate the dependent slave/master relationship and have two masters
instead. Your scan chain length increases and S22 violations (multiple clocked scan chain)
occur. An S22 violation can also result in patterns that fail simulation, unless you use
techniques such as lockup latches to prevent failures due to clock skew.
You can use the -mask option of the set_rules command to compensate for the DRC
violation. If you set the severity to Warning and enable the -mask option, the ATPG algorithm

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masks the control or observe functions (or both) to ensure that any ATPG pattern generated
passes simulation. However, it reduces test coverage.

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DRC Rule S30

Message Text
Scan Chain Rule S30: RAM I (G) unstable during time T of P
procedure.

Severity
Warning

Description
A RAM must hold state during all test procedure operations, except for the test setup procedure, if
the RAM is to be used in read-only mode. "I" is the instance name of the RAM, "G" is its
corresponding gate ID, "T" is an event time in test procedure "P".
This violation is detected during the simulation of the test procedure file. It indicates one of the
write port controls or perhaps an optional asynchronous set or reset is not at an off state.
A violation of this rule introduces no danger of generating bad patterns but is a warning that a
reduction of test coverage can result. The RAM cannot be used in read-only mode and its
contents is set to all X's. This cannot be important if the RAM had no initialization file, the
initialization file contained all X's, or the RAM is still controllable during Fast-Sequential pattern
generation.

What Next
In general, it is better to have a RAM for which Fast-Sequential patterns can be generated than it
is to have a RAM that operates in read-only mode (behaves like a ROM). If your RAM can be
used during Fast-Sequential pattern generation, then you can change this rule to warning or
ignore and continue.
The report_memory and report_primitives commands can be used to review whether
the RAM is considered controllable during Fast-Sequential ATPG. Check that the RAM is has a
stable clock and is stable during scan chain loads. If the RAM is considered usable during Fast-
Sequential ATPG pattern generation, then test coverage cannot suffer at all, and in fact might be
greater than treating the RAM as a read-only device.
This violation can be analyzed using the schematic viewer by selecting its violation ID number
from the ANALYZE button. This changes the pin data reporting to "pattern data" and displays the
gates in the backward trace cone of the RAM's write, set, or reset control input for which the
violation was reported.
Based upon interactive investigation, the solution to eliminating the violation can involve changing
one of the test procedures such as the load_unload, or shift, or changing logic, or perhaps finding
a control input that can be constrained to avoid the RAM instability.
If no changes to the design or to test procedures are desired you can continue by using the set_
rules command to change the severity of the rule to warning or ignore and the repeating the
run_drc command.

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DRC Rule S32

Message Text
Scan Chain Rule S32: Scancell set to fixed binary value after load
was violated number times

Severity
Error

Description
PLL shift clocks are internal nodes used for shift. These clocks might need to be defined when
scan cells are set to binary values during various test procedures. This might result in incorrect
identification of load0, load1 cells, which might lead to a loss of coverage.
The S32 rule checks for unconstrained scan cells identified as load0, load1. If DRC passes
without defined PLL shift clocks, it implies that the definition of PLL shift clocks is not necessary.
When analyzing an S32 violation, both the value at the end of load_unload and the constrain
value must be inspected for the failing scan cell. An S32 failure will occur if the value at the end of
load is non-X (that is, 0 or 1), and the cause can be traced back in the GSV with pin data set to
load_unload. An S32 failure can also occur when the value at the end of load is X — if the
constrain value is non-X. For example, a D flip-flop (DFF) might have its reset line constrained
active, so the loaded value is immediately replaced at the beginning of the capture cycle. In this
case, you should set the pin data to constrain the value to trace the source of the problem in the
GSV.
The load_unload pindata might show a non-X value at the end of load even though no clock pulse
is displayed. When internal clocks are used, this situation can be caused by a sensitized path from
a PLL clock source. The PLL clock pulses are simulated, but the GSV does not display them. To
verify this, you can identify the clock used for the DFF using the report_scan_cells -
vebose command, then use the report_clocks -intclock command to find the
corresponding PLL source. The analyze_violation s32-1 command displays the DFF
with the load pindata. You can then view the PLL source separately, and use the GSV to see how
they’re connected and determine if the path is sensitized.

The following figure shows an example of this situation:

What Next
S32 violations must be analyzed and fixed. If you downgrade an S32 violation to pass DRC, a loss
of test coverage might result, including increased test data and time. This might also result in
generation of ATPG patterns that fail VCS simulation.

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If the S32 violation is caused by PLL clocks, then removing all PLL clock and PLLSource
definitions will prevent the undesired pulses. TetraMAX DRC only requires these constructs for
OCC controllers that require PLL pulses to enter shift mode. For other types of OCC controllers, it
is safe to remove them.

Category S - Scan Chain Rules 424

What Next
Note the following scenarios:
l The V12 message reports: “Scanport names need to be changed for VCS simulation; use -

Message Text
Vector Rule V17: Line L (filename), clock name should be pulsed,
not forced on.

Severity
Error

Description
DRC procedures must pulse clocks by assigning them the value "P" or hold the clocks off by
assigning them their off state.
TetraMAX ATPG does not support holding a clock to its on state for one or more tester cycles.
The reason is that this would require a tester channel definition that would be RZ(RO) on one
cycle, but then NRZ(NRO) on the next. Very few ASIC vendors or testers like to have the signal
type switch dynamically from cycle to cycle.

What Next
You can downgrade the severity of the violation to warning or ignore to continue, but when you
write patterns you will see inconsistencies across the various pattern formats. Some formats
(Verilog, VHDL, STIL) will support the force "on" across multiple test cycles while others WGL,
FTDL, TDL91, TSTL2 will convert the force on into a pulse in each tester cycle. The suggested
solution is to change the clock forced to its on state of 1/0, into a force to "P" or pulse, or a force to
its off state if that is acceptable. Following are some additional ideas you might want to consider:
Does the clock or asynchronous set/reset need to be applied? Many users feel they should apply
a global reset for good measure or apply at least one clock in the test_setup procedure but ATPG
generally doesn't care if the design is initialized or not unless nonscan cells need to be initialized to
enable other ATPG operations. So you might be able to remove the reset or clock event. Try
replacing the on value with an off value and see if the scan chain check of "run drc" still passes and
what happens to the various contention checks such as Z4.
Another item to review is whether the set, reset, or clock is really used outside of the test_setup
procedure? If you have a PI constraint on the set/rst/clock pin so that it is always off (except for
test_setup), then there is really no reason to declare this pin as a clock and you can remove it from
the defined clock list. After this is done, you are then free to force the value either to 1 or 0 in test_
setup, as long as you restore the PI constraint value by the end of test_setup.
If you have a JTAG design, or for some other reason you are using the set_drc -clock
<some_pin>, then you have the same condition as where a reset declared as a clock will not be
used for patterns. You can then remove the pin from the clock list, and add it to a PI Constraint list
and are then free to force it 0 or 1 in test_setup.
The option set_drc -allow_unstable_set_resets supports asynchronous set/rst pins
without defining them as clocks. By selecting this option you can omit 'rst' from the clock list.
TetraMAX ATPG then creates patterns using this pin as an NRZ/NRO pin and you are free to
force it to 0 or 1 in test_setup.
If the reset is actually used for pattern generation, then another alternative is to use two STIL
timing definitions, one for test_setup and another for all other patterns. Suppose the standard test
cycle is 100ns but you wish to initialize reset for 2000ns. Then define a second timing definition
that is used in the test_setup procedure in which the cycle period is 2100ns and the reset is pulsed

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Message Text
Vector Rule V20: unsupported event (more info here).

Severity
Error

Description
The defined order of events in a capture procedure is not supported or there are extra events in
the procedure.
Failure to pass this rule check indicates that a procedure has defined events in an order which is
not supported by the Basic-Scan or Fast-Sequential ATPG algorithms. Capture procedures must
define events in the following order:

1. force values on inputs

2. measure values on outputs
3. pulse one defined clock and all equivalent ports (optional)
This rule violation occurs if the events have been defined in an order which does not match this
sequence or if extra events (such as explicitly setting a bidirectional control pin) have been defined
which are not expected.
The order of events is defined both by the number of "V{...}" structures used as well as the port
timing defined in the timing section. For forces and measures within the same "V", the port timing
determines the order of events.
Use of Full-Sequential ATPG provides more flexibility in the event order of capture procedures.
When using the Full-Sequential ATPG algorithm you can make use of the Sequential Capture
Procedure.

TetraMAX DRC Rules O-2018.06

DRC Rule V24

Message Text
Vector Rule V24: Time T, PO measures with clocks active not
supported for pattern mapping. (V24)
Time T, PI changes with clocks active not supported for pattern
mapping. (V24)
Time T, Staggered clocks not supported for pattern mapping. (V24)
Time T, Overlapped clocks not supported for pattern mapping. (V24)

Severity
Error

Description
Pattern mapping requires certain restrictions on the input patterns in order for the mapping
algorithm to have the best chance of succeeding. Certain pattern event ordering is not currently
supported:
l output measures with clocks active (fig. 1)
l inputs changing with clocks active (fig. 2)
l staggered clocks (fig 3., fig 5.)
l coincident clocks with different trailing edges (fig 4.)
l overlapped clocks with different durations (fig. 6)

Message Text
Vector Rule V31:
Waveform simulation events (H and L Waveforms across Timing have a
different number of leading Z events(n,n); check consistency)

Waveform simulation events (Both multiple and single-cycle capture

procedures are defined; (name) is [single|multi]-cycle. Affects
bidirectional handling in external simulation

Waveform simulation events (Waveforms [H,L,T,X] need Z event in

single-cycle procedure (name)

Waveform simulation events (Waveforms [H,L,T,X] must not have a Z

event in multiple cycle procedure (name)

Severity
Warning

Message Text
(Version 1) Line N (filename), Invalid internal clock timing: There
is no ClockTiming block named 'string' in ClockStructures 'string'
(V34-1)
(Version 2) Line N (filename), Invalid internal clock timing:
Invalid period for "string" (V34-1)
(Version 3) Line N (filename), Invalid internal clock timing:
Missing period for "string" (V34-1)
(Version 4) Line N (filename), Invalid internal clock timing:
Waveform events must be contained within one period for "string"
(V34-1)
(Version 5) Line N (filename), Invalid internal clock timing:
Waveform events must be monotonically increasing for "string" (V34-
1)
(Version 6) Line N (filename), Invalid internal clock timing:
Inconsistent off_state specification for clock string (V34-1)
(Version 7) Line N (filename), Invalid internal clock timing:
Waveform events must be contained within one period for "string"
(V34-1)
(Version 8) Line N (filename), Invalid internal clock timing:
Cannot slow down capture from 'string' to 'string' beyond 1 cycles.
(V34-1)
(Version 9) Line N (filename), Invalid internal clock timing: Clock
string cannot safely be synchronized in Synchronization Group
string. (V34-2)

Severity
Warning

Description
This violation is reported when you make an incorrect specification in the ClockTiming block of the
STIL procedure file. A clock timing definition with a V34 violation is discarded and the clock’s
timing relationships are not reported by the report_clocks –capture_matrix command.
ATPG will treat the clock as asynchronous to the other clocks, which reduces the test coverage.
The various versions of the V34 message are described as follows:
Version 1 − The specification made by the set_drc –internal_clock_timing command
did not match a named ClockTiming block in the STIL procedure file.

Version 2 − The period for the "string" statement must include a positive integer followed (without
a space) by ns or ps.

Version 3 − The period for the "string" statement is missing or invalid. It must include a positive
integer followed (without a space) by ns or ps.

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Version 4 − The argument for the Period statement is too short to contain both arguments for
Waveform statement.

Version 5 − The first argument for the Waveform statement must be at an earlier time than the
second argument.

Version 6 – The first argument of the Waveform statement must be equal to or greater than 0ns
or 0ps.

Version 7 – The difference between the arguments of the Waveform statement must be less
than the Period argument.

Version 8 – Because a MultiCyclePath is defined between the clocks, the pulses be moved
farther apart. But the set_drc –multiframe_paths command was not set.

Version 9 – This message accompanies one of the other versions of the V34 message. Correct
one or more of the other message(s) first, and this version will no longer print.

What Next
Fix the violated syntax in the STIL procedure file so ATPG can use the clock as an synchronous
clock.

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DRC Rule V35

Message Text
Vector Rule V35:
(Version 1) Line N (filename, Invalid clock constraint: string " is
not a declared constrainable object" (V35-1)
(Version 2) Line N (filename, Invalid clock constraint: Non-clock
entity "string" cannot be pulsed. (V35-1)
(Version 3) Line N (filename, Invalid clock constraint: Constraints
assignment is truncated to the size of "string" (V35-1)
(Version 4) Line N (filename, Invalid clock constraint: Assignment
to InstructionRegister "string" is incomplete; padding with dont_
cares (V35-1)
(Version 5) Line N (filename, Invalid clock constraint "string" is
an unusable constraints assignment (V35-1)
(Version 6) Line N (filename, string is not a constrainable clock
(V35-1)

Severity
Warning

Description
A V35 violation is reported when you make an incorrect specification in the ClockingProcedure
block of the STL procedure file. A clocking procedure with a V35 violation is discarded and is not
reported by the report_clocks -constraints command.
If other ClockingProcedure blocks exist that don’t have V35 violations and are valid, then ATPG
generates patterns. But if the violated clocking procedure represents real clocking behavior, the
test coverage is lower than it should be. In this case, you need to fix the violated syntax so that the
clocking procedure can be used by ATPG.
The various versions of the V35 message are described as follows:
Version 1 − The clocking procedure specified a pin path name that is not specified in the
ClockStructures block as either a clock or a clock instruction register element.
Version 2 − The clocking procedure specified a P in the clock instruction register values.
Version 3 − The clocking procedure specified too many bits for the clock instruction register.
Version 4 − The clocking procedure did not specify enough bits for the clock instruction register.
Version 5 − The clocking procedure specified invalid characters for a clock or in the clock
instruction register.
Version 6 − A reference clock is specified in the ClockingProcedure block.

What Next
You can use the report_feedback_paths command to review the number of gates and
sources in the feedback loop. You can also use it to get a detailed list of instance pathnames of
gates in the loop. The "source" gates of the feedback loop are always listed first. The feedback
path analysis uses test generation, whose parameters are controlled using the set_atpg
command. X1 analysis is affected by the set_atpg -abort_limit switch, since it uses

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ATPG to figure out if the feedback path is sensitizable. The default setting is 10 aborts before the
analysis can complete.
You can analyze an X1 violation using the graphical schematic viewer by selecting the ANALYZE
button on the left, and then choosing the specific occurrence of the X1 violation from the menu.
You can also perform an analysis by manually entering the analyze_violation command
with the -display option. This sets the gate reporting to the pattern data that sets up the
sensitization condition and displays the gates in the failing feedback path along with the net data
that enables that path.
You can find the X1 violation is nothing to worry about due to some controls not considered during
the analysis such as nonscan cells that are constant or PI equivalences. You can then safely
ignore the violation.
If the potential for oscillation is real, you might wish to consider altering your design to eliminate
the feedback loop or at least to prevent the X1 violation, at least in ATPG mode.
You might wish to consider manually breaking the loop for ATPG efforts by disconnecting
selected gates along the way. The add_net_connections command along with the TIEX and
-disconnect options can be used to disconnect all inputs from selected gates in the feedback
path. However, the use of net connections can lead to performance issues during circuit
flattening, so you might want to modify the netlist (used only in the ATPG environment) to break
the loop rather than use the add_net_connections command.

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DRC Rule X2
Message Text
DRC Rule X2: X source T gate G1 is propagatable to N scan cells
(G2).

Severity
Ignored

Description
Note the following definitions:
l T is the gate type of the X-source gate

l G1 is the gate_id of the X-source gate

l N is the number of capturing scan cells of the X-source gate

l G2 is the gate_id of the first capturing scan cell of the X-source gate

This rule checks for gates that are potential sources of X values that can propagate to a scan cell.
The following possible X-source gates are considered:

l Gates with a connection to the global TIEX gate

l Gates (except BUS gates) with a connection to the global TIEZ gate
l TIEX gates
l TIEZ gates, except those that connect directly to a BUS gate
l BUS gates identified as contendable or that can potentially attain a Z state
l TSD or SW gates that do not connect directly to BUS gates
l WIRE gates identified as contendable
l DLAT gates identified as non-hot transparent latches
l DLAT or DFF gates associated with scan cells constrained to X
l DLAT or DFF gates identified as nontransparent nonscan cells
l DLAT or DFF gates with user-selected capture masking
l DLAT or DFF gates with capture masking due to a failing DRC rule
l RAM gates
l ROM gates with memory values that are not fully defined
l Feedback path source gates of sensitizable feedback paths (those that fail Rule X1)
l PI or PIO gates constrained to an X value
Note that constrained values from pin constraints and constant value cells are considered when
determining whether an X-source gate is propagatable to a scan cell. Any X-source gate
considered propagatable to at least one scancell causes a violation of the X2 rule.

What Next
No action is required to correct this problem: ATPG can tolerate captured Xs under normal
conditions. If you want to avoid Xs during ATPG, you can use automated violation analysis to help
debug this problem. To enable this analysis, specify the set_rules X2 warning command,
then run DRC. This analysis displays the failing X-source gate, the capturing scan cell gate, and
all the gates in the paths between them. The pin data is set to the constrain_value option.

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Category Y - PHDS Rules

Y1 - Cell is placed in DEF, but not defined in LEF
Y2 - Cell has DEF-defined DIEAREA mismatch with LEF defined SIZE
Y3 - Cell has DEF-defined DIEAREA offset mismatch with LEF-defined ORIGIN offset
Y4 - Cell has multiple LEF definitions
Y5 - Instance is placed in DEF, but is in the hierarchy of an undefined DESIGN Cell
Y6 - Cell has dimensions less than or equal to zero
Y7 - Cell cell_name is defined in multiple DEF files
Y8 - Instance not placed in DEF
Y9 - Net exceeds maximum size and will be truncated in final PHDS
Y10 - Net has name longer than supported by PHDS
Y11 - Instance has name longer than supported by PHDS
Y12 - Rule is used, but not defined
Y13 - VIA is used, but not defined
Y14 - LEF file in LEF directory is empty
Y15 - DEF file in DEF directory is empty
Y16 - DEF file in DEF directory was not used in PHDS creation
Y17 - DEF file is missing the required DESIGN keyword
Y18 - DEF file does not have corresponding LEF file
Y19 - Cell missing corresponding LEF and DEF files
Y20 - Cell missing corresponding DEF file
Y21 - Less technology LEF files used than specified
Y22 - No layer data found in PHDS
Y23 - No nets, VIAs, instances found in PHDS
Y24 - More nets than net segments in the PHDS
Y25 - Fewer nets than instances found in PHDS

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DRC Rule Y1
Message Text
Cell cell name is placed in DEF, but not defined in LEF (Y1)

Severity
Warning

Description
A cell is included in a DEF file, but is missing from a LEF file.

What Next
When creating the PHDS database, make sure the noted cell is defined in a LEF file.

See Also
Using TetraMAX to Create the PHDS Database

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DRC Rule Y2
Message Text
Cell cell_name has DEF defined DIEAREA mismatch with LEF defined
SIZE. (Y2)

Severity
Warning

Description
There is a size mismatch in the noted cell between the DIEAREA parameters included in the DEF
file and the SIZE parameters defined in the LEF file. In this case, placing a mismatched set of net
geometries and pins can disorient the cell, which leads to incorrect behavior when creating the
PHDS database.

What Next
Correct the DIEAREA parameters in the DEF file so they match the SIZE parameters in the LEF
file. For example:

DEF File:

DIEAREA ( 0 0 ) ( 100 100) ;

Message Text
Cell cell_name has corresponding LEF but is missing corresponding
DEF file. (Y20-1)

Severity
Warning

Description
This message is issued when the set_rules y20 -min_area command is specified, and a
cell with an area greater than the specified area has a corresponding LEF file but not a
corresponding DEF file.

For example, the following command sets the minimum area to 0 to show all cells that have a LEF
file but are missing a DEF file:

Message Text
Error: No nets found in PHDS. (Y23-1)

Error: No VIAs found in PHDS. (Y23-2)

Error: No instances found in PHDS. (Y23-3)

Severity
Error

Description
These message variations indicate that incomplete or incorrect DEF files were read when
creating the PHDS database.

What Next
Check your DEF files and include the missing nets, VIAs, or instances.

See Also
Using TetraMAX to Create the PHDS Database

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DRC Rule Y24

Message Text
More nets than net segments found in PHDS. (nets=A, net segments=B)
(Y24-1)

Severity
Error

Description
This message is reported when the DEF files are missing cell placement or routing information. If
the DEF files have complete routing information, there should be more net segments than nets. If
the DEF files are missing all net placement information, the number of net segments reported is 0.

What Next
Identify the missing cell placement or routing information and include it in the DEF files when
creating the PHDS database.

See Also
Using TetraMAX to Create the PHDS Database

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DRC Rule Y25

Message Text
Fewer nets than instances found in PHDS. (Y25-1).

Severity
Ignore

Description
This message indicates that filler or antenna cells might be included in the PHDS database.

What Next
This is an optional check. The presence of filler or antenna cells are not an issue for the PHDS
database. But these cells are never used by diagnosis and can be filtered out from the LEF/DEF
files to reduce the PHDS size.

See Also
Using TetraMAX to Create the PHDS Database

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Category Z - Tristate Rules

Z1 - bus capable of contention
Z2 - bus capable of holding Z state
Z3 - wire capable of contention
Z4 - bus contention in test procedure
Z5 - BIDI pin not at input mode
Z6 - ATPG constraint violation in test procedure
Z7 - unable to prevent contention for circuit
Z8 - unable to prevent contention for bus
Z9 - bidi bus driver enable affected by scan cell
Z10 - internal bus driver enable affected by scan cell
Z11 - uncontrolled BIDI driver using BIDI control pin
Z12 - BIDI control pin effects capture operation

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DRC Rule Z1
Message Text
Tristate Rule Z1: Bus gate N (G) failed contention ability check
for drivers G1 and G2.

TetraMAX DRC Rules O-2018.06

A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to "pattern data" and a pattern which
causes a contention on the WIRE primitive is selected for display on the schematic. The GSV
displays the gates in the backward trace cones of the contending drivers. Reviewing the gates
displayed can give you some insight as to whether the problem might be overcome by changing a
contention check control or applying some sort of PI constraint or whether the problem is inherent
in the design.

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DRC Rule Z4
Message Text
Tristate Rule Z4: Bus contention on N (G) occurred at time T of X
procedure.

Severity
Warning

Description
A BUS primitive must not be in contention during the simulation of any test procedure.
N is the instance pathname of the BUS primitive, G is its gate_ID number, X is the name of the
procedure, such as shift, test_setup, or load_unload, and T is the simulation time of that
procedure.
Failure to satisfy this rule will not affect test coverage. However, the contention might be harmful
to the device on the tester.
This violation occurs when simulation of the DRC procedures detects any BUS primitive with
inputs in a contending state. A BUS primitive is automatically inserted into the design during
flattening to resolve the driven value on multi driver nets.

What Next
Common causes for this violation include:
l lack of control of internal tristate drivers from a top level port
l forgetting to disable bidi port drive during load_unload and test_setup
l forgetting to force Z on bidi ports during load_unload and test_setup
l disabling Z1 analysis by setting rule Z1 to ignore
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to one of the procedures: shift, test_
setup, load_unload, and so forth., and displays the gates in the backward trace cone of the failing
BUS primitive.
Note that when the violation occurs in the test_setup procedure, only a single simulation value
will appear on the initial schematic display. This corresponds to the time reported in the violation
being analyzed. For example "... occurred at time 200 of test_setup..." would indicate the single
simulation value corresponds to event time 200. You might see all the simulated events of the
test_setup procedure by clicking on the REFRESH button. To return to a single character display,
you will need to repeat the analyze_violation command.
Certain periods of potential contention might be allowable in the test_setup or at the beginning of
the load_unload procedure. However, it is not advisable to continue with potential contention
during the Shift procedure as any patterns produced can lead to device damage when applied on
real silicon.
If this violation is acceptable, you can use the set_rules command to adjust its severity to
ignore.

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DRC Rule Z5
Message Text
Tristate Rule Z5: BIDI port P not set to input mode at time T of X
procedure.

Severity
Ignored

Example
One example, many variations are possible:

Description
Bidirectional ports should be in input mode during the Shift portion of the load_unload procedure
and driven to a non-Z value.
Failure to satisfy this rule will have no affect on test coverage or the accuracy of any patterns
created.

What Next
A violation can be analyzed using the schematic viewer by selecting its violation ID number from
the ANALYZE button. This changes the pin data reporting to the load_unload procedure and
displays the gates in the backward trace cone of the failing PIO primitive (bidirectional port).
Reviewing this displayed data can give insights in how to control the bidirectional port to satisfy
the rule.
To resolve this violation investigate two areas: 1) the bidirectional enable is at an off state, 2) the
bidirectional pin is forced to a 0 or 1 value in the load_unload procedure. If you are unable to
guarantee the bidirectional enable is off during scan chain shifting, then this rule cannot be
satisfied and you should force Z's on the bidi pins involved or a Z4 violation can occur.
Certain test methodologies insist that bidirectional ports which are not scan outputs be in a driven
input mode. This is primarily intended to reduce switching noise on the tester that can occur if the
bidirectional ports are allowed to change direction or state during each shift clock. Your own
specific test methodology cannot have this requirement, if so you might want to set this rule's
severity to ignore using the set_rules command.

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DRC Rule Z6
Message Text
Tristate Rule Z6: ATPG constraint violation on N (G) occurred at
time T of X procedure.

Severity
Warning

Description
Static ATPG constraints must be satisfied during the application of any test procedure.

What Next
You can analyze a violation using the schematic analysis by selecting its violation ID number. This
sets the gate reporting to the procedure pattern data at which the failure occurred and displays
the gates in the backward trace cone of the failing ATPG constraint site.
Note that when the violation occurs in the test_setup procedure, only a single simulation value
will appear on the initial schematic display. This corresponds to the time reported in the violation
being analyzed. For example "... occurred at time 200 of test_setup..." would indicate the single
simulation value corresponds to event time 200. You might see all the simulated events of the
test_setup procedure by clicking on the REFRESH button. To return to a single character display,
you will need to repeat the analyze_violation command.

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DRC Rule Z7
Message Text
Tristate Rule Z7: Cannot set all buses to a noncontending state.

Severity
Error

Description
All BUS primitives must be capable of being simultaneously set to a noncontending state. A BUS
primitive is automatically inserted into the design during flattening to resolve the driven value on
multi driver nets.
Failure to satisfy this rule indicates that test generation cannot find a pattern that will avoid
contention. Depending upon the contention checking conditions controlled by the set_
contention command, any or all patterns generated can end up being discarded due to
contention. This would then contribute to a lower test coverage and increased CPU time.
This check is performed by attempting to find a pattern which simultaneously avoids contention on
all BUS devices in the design. A Z7 violation occurs if a pattern cannot be found.
Z7 checking is not performed if Z1 failures are not present. However, if there are Z1 failures, Z7
checking commences and could fail if ATPG constraints are forcing internal clocks-on in other
than the first cycle.

What Next
This violation has no automated schematic viewing analysis and none is possible.
If Z1 checking has been disabled by changing the severity of Z1 to ignore, then this can contribute
to Z7 violations. Use the report_rules z1 command to determine if Z1 is set to ignore.
If the design has Z8 violations, then investigate these violations first. A Z8 violation is issued for a
single BUS for which no pattern can be found to avoid contention. As long as a single BUS is
failing, there is no point in troubleshooting the Z7 which is a check for all BUSES.
It is important to determine if the contention prevention effort which accompanies a Z1 analysis
had completed or aborted. Follow these steps:

1. Issue the report_buses -summary command to check whether any of the

DRC Rule Z10

Message Text
Tristate Rule Z10: Enable of internal bus driver N (G) connected to
scan cell gate (G).

Severity
Warning

Description
The enable line of an internal three-state driver is controlled by or connected to a scan chain cell.
There is a potential for driver contention between driver devices on the internal multidriver net
both during scan chain shifting and after the application of a capture clock. This check is
performed only for bus gates that fail the contention ability checking (rule Z1).
This rule check is performed using design connectivity plus the affects of any PI constraints, or
constant load cells.

What Next
Use the schematic viewer to analyze the violation ID.
This rule only indicates that there are potential problems. If there are actual problems with scan
chain shifting, Z4 rule violations will occur. All Z4 violations should be corrected, especially those
that occur during the shift procedure as these might be serious.
To avoid contention due to a capture clock changing the contents of controlling scan cells, use the
-capture option of the set_contention command. This causes offending patterns to be
discarded if they are found to cause contention or changed to a force Z if the contention occurs on
a bidirectional port. A message is given indicating the number patterns that were rejected and
there is likely some loss of test coverage due to the pattern rejection.
A general solution to avoid all problems associated with this rule is to modify the design to add
circuitry which prevents the bus from attaining a contention condition. The bus gate will now pass
the Z1 rules check and will not be considered for this Z10 rule checking.

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DRC Rule Z11

Message Text
Tristate Rule Z11: BIDI driver (G1) is not controlled by BIDI
control pin P (G2).

Severity
Error

Example
One example, many variations are possible:

Description
When a bidirectional control pin (BCP) has been specified by the presence of a ReflectIO capture
procedure, then ALL bidirectional pins of the design must be controlled by this BCP.
P is the name of the top level bidi control pin and G2 is its gate ID. G1 is the gate ID of the tristate
driver which is not controlled by P.
The severity of this rule is error because when the ReflectIO protocol is used the avoidance of
contention cannot be guaranteed on a bidi pin if that bidi pin is not controlled by the defined BCP.
Use of a PI Constraint of Z on those bidi pins not controlled by the BCP will not provide a solution
because the ReflectIO protocol reflects back as input the expected output value of the bidi pin and
not the applied input value. A PI constraint affects only input value.

What Next
Use the ANALYZE button to select the violation by its violation ID and to have the violation drawn
in the schematic viewer. This selects a pin data of bidi_control_value and displays the simulated
values on the failing tristate driver gate along with its control logic cone and bidi control pin when
the bidi control pin is at its off value.
If your design OR's the Scan Enable with the BCP control, you should try constraining the scan
enable control to it's off state with an add_pi_constraints command.
Review the control logic of the tristate driver to ensure that an omission has not occurred in the
defined STL procedure file procedure files. If there are no problems found in the procedure files
you have a number of choices:

Category Z - Tristate Rules 513

TetraMAX DRC Rules O-2018.06

l Change the design so that bidi control is achieved.

l Look for an alternative bidi control pin.
l Downgrade the severity to warning or ignore. However, it is likely that the patterns produced
will have contention on the bidi pins not controlled.
l Modify the procedures and command file to eliminate the use of the ReflectIO protocol.
Instead, consider beginning each capture_XXX procedure with a cycle in which the PI's are
forced, but the BIDI's are set to Z. Either later in the same cycle or in a separate cycle the
BIDI's is forced to their intended value.

Category Z - Tristate Rules 514

TetraMAX DRC Rules O-2018.06

DRC Rule Z12

Message Text
Tristate Rule Z12: BIDI control pin P (G1) effects capture
operation of <type> (G2). (Z12-1)

Severity
Error

Example
One example, many variations are possible:

Description
When a bidirectional control pin (BCP) has been specified by either the use of the -bidi_
control_pin option of the set_drc command, or by the ReflectIO capture procedure, then it
must not have a path to a DFF or DLAT state element or RAM.
P is the name of the primary input which has been identified as the BCP, and G1 is its gate ID. The
<type> is the type of device that can capture the BCP's value through a combinational path and
is one of: DFF, DLAT, RAM. G2 is the gate ID of this device.
The severity of this rule is set at error because when using the ReflectIO protocol, any pattern
developed in which the BCP is asserted is changed by the ReflectIO protocol to force BCP off
during the capture clock. The ATPG pattern will have been created assuming the BCP is asserted
during clock capture, but ReflectIO protocol changes this port to be off during all captures. As a
result, the expected value captured into the state element is wrong and will result in a simulation
mismatch reported for every pattern in which the BCP is asserted.

What Next
Use the ANALYZE button to select the violation by its violation ID and to have the associated gates
drawn in the schematic viewer. This selects a pin data of constrain_value and displays the
gates along the combinational gate path from the BCP to the state element which captures this
value. The path drawn displays one unblocked combinational path from the BCP pin to the state
element shown.
Look for a way to block the value from the BCP input point to the state element. This can be done
using an add_capture_masks command or perhaps by locating a primary input that can be
constrained with an add_pi_constraints command to block the path from the BCP to the
state element.

Category Z - Tristate Rules 515

TetraMAX DRC Rules O-2018.06

Use of a PI Constraint to hold the BCP to an off state is possible, but it has a negative affect of
inhibiting all bidirectional ports controlled by this BCP from ever being used in output mode. Test
Coverage might be reduced by this approach.
It is highly suggested that the design be changed to eliminate the path from the BCP to the state
element. If this is not possible, you might want to consider abandoning the use of the ReflectIO
protocol in favor of an end-of-cycle protocol which begins each capture_XXX procedure with a
cycle in which the PI's are forced, but the bidi's are set to Z. Either later in the same cycle or in the
next cycle the bidi's is forced to their desired value (Bidi Dead-Cycle Protocol).

Category Z - Tristate Rules 516

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