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List of Figures I List of Tables II List of Abbrevations III

This document contains a table of contents that outlines 7 chapters covering topics related to digital design including: decode and compare architecture, error correction codes, low-power design methodologies, an introduction to Verilog, an introduction to Xilinx, simulation results, and conclusions. Chapter 3 discusses various low-power design techniques including static and dynamic voltage scaling, clock gating, power gating, parallelization and pipelining. Chapter 4 provides an overview of Verilog, its history and examples of its use. Chapter 5 introduces Xilinx and how to migrate and create projects within it.

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Jaya Swaroop
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66 views

List of Figures I List of Tables II List of Abbrevations III

This document contains a table of contents that outlines 7 chapters covering topics related to digital design including: decode and compare architecture, error correction codes, low-power design methodologies, an introduction to Verilog, an introduction to Xilinx, simulation results, and conclusions. Chapter 3 discusses various low-power design techniques including static and dynamic voltage scaling, clock gating, power gating, parallelization and pipelining. Chapter 4 provides an overview of Verilog, its history and examples of its use. Chapter 5 introduces Xilinx and how to migrate and create projects within it.

Uploaded by

Jaya Swaroop
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CONTENTS

Name of Contents Page No.


LIST OF FIGURES i
LIST OF TABLES ii
LIST OF ABBREVATIONS iii

CHAPTER 1: INTRODUCTION
1.1 Decode and Compare architecture 1
1.2 Decoder 3
1.3 Encoder 4
1.3.1 Octal to binary encoder 5
1.3.2 priority Encoder 6
1.4 Digital Comparator 7
1.4.1 8-Bit Word Comparator 9
1.5 Hamming Distance 9

CHAPTER 2: ERROR CORRECTION CODES


2.1 Data path Design For Systematic Codes 11
2.2 Exclusive-OR Gate Definition 15
2.3 Binary Addition 17
2.4 Half Adder Circuit 19

CHAPTER 3: DESIGNING FOR LOW-POWER CONSUMPTION

3.1 Introduction 21
3.2 Low-Power Design vs. Power-Aware Design 21
3.3 Sources of Power Consumption 22
3.4 Basic Low-Power Design Methodologies 22
3.4.1. Static voltage scaling 23
3.4.2. Frequency Scaling 23
3.4.3. Multi-VDD and CVS 24
3.4.4. Dynamic voltage scaling 24
3.4.5. Voltage dithering 25
3.4.6. Clock gating 27
3.4.7. Power gating 27
3.4.8. Technology scaling 29
3.5 Methodologies at Architectural Level 30
3.5.1. Parallelization 30
3.5.2 Pipelining 30
3.6 Optimizations at Gate Level 31
3.6.1 Path balancing 31
3.6.2. High-Activity Net Remapping 32
3.7 Optimizations at Technology Level 33
3.7.1. Resizing Transistors 33
3.7.2. Optimizing the VDD/VTH Ratio 33
3.8 Different Digital Logic Styles 34
3.8.1 Static Vs Dynamic Logic 34

CHAPTER 4: INTRODUCTION TO VERILOG


4.1 Overview 36
4.2 History 37
4.2.1. Beginning 37
4.2.2. Verilog-95 37
4.2.3 Verilog 2001 38
4.2.4. Verilog 2005 38
4.2.5. SystemVerilog 38
4.3 Examples 39
4.4 Constants 40
4.4.1. Synthesizable Constructs 40
4.5 Initial Vs Always 43
4.6 Race Condition 44
4.7 Operators 45
4.8 System Tasks 45
4.9 Difference Between Verilog and VHDL 46
CHAPTER 5: INTRODUCTION TO XILINX

5.1 Migrating Projects from Previous ISE Software Releases 50


5.1.1 To Migrate A Project 50
5.2 Properties 50
5.2.1 IP Modules 50
5.3 Obsolete Source File Types 51
5.3.1. Using Ise Example Projects 51
5.3.2. Creating A Project 53
5.4 Using The Project Browser 53
5.5 Creating A Project Archive 55

CHAPTER 6: SIMULATION RESULTS

6.1 Simulation 56

CHAPTER 7 CONCLUSION 74

FUTURE WORK 75
REFERENCES 76
PROJECT CODE 77
JOURNAL PAPER

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