ATtiny4 5 9 10 Data Sheet DS40002060A PDF
ATtiny4 5 9 10 Data Sheet DS40002060A PDF
ATtiny4 5 9 10 Data Sheet DS40002060A PDF
The ATtiny4/5/9/10 is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC archi-
tecture. The ATtiny4/5/9/10 is a 6/8-pins device ranging from 512 Bytes to 1024 Bytes Flash, with 32 Bytes
SRAM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching
one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power
consumption versus processing speed.
Features
• Operating Voltage:
– 1.8 – 5.5V
• Programming Voltage:
– 5V
• Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
• Industrial and Extended Temperature Ranges
• Low Power Consumption
– Active Mode:
• 200µA at 1MHz and 1.8V
– Idle Mode:
• 25µA at 1MHz and 1.8V
– Power-down Mode:
• < 0.1µA at 1.8V
Table Of Contents
3 Overview ................................................................................................. 13
3.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 ................................. 14
6 Memories ................................................................................................ 24
6.1 In-System Re-programmable Flash Program Memory .................................... 24
6.2 Data Memory ................................................................................................... 24
6.3 I/O Memory...................................................................................................... 26
10 Interrupts ................................................................................................ 45
10.1 Interrupt Vectors .............................................................................................. 45
10.2 External Interrupts ........................................................................................... 46
10.3 Register Description ........................................................................................ 47
1. Pin Configurations
Figure 1-1. Pinout of ATtiny4/5/9/10
SOT-23
UDFN
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 8 PB2 (T0/CLKO/PCINT2/INT0/ADC2)
NC 2 7 VCC
NC 3 6 PB3 (RESET/PCINT3/ADC3)
GND 4 5 PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 17-4 on page 127.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
2. Ordering Information
2.1 ATtiny4
Supply Voltage Speed(1) Temperature Package(2) Ordering Code(3)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
2.2 ATtiny5
Supply Voltage Speed(1) Temperature Package(2) Ordering Code(3)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
2.3 ATtiny9
Supply Voltage Speed(1) Temperature Package(2) Ordering Code(3)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
2.4 ATtiny10
Supply Voltage Speed(1) Temperature Package(2) Ordering Code(3)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
3. Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per
MHz, allowing the system designer to optimize power consumption versus processing speed.
CONTROL X TIMER/
LINES Y COUNTER0
Z
INTERRUPT
UNIT
ALU
ISP STATUS
INTERFACE REGISTER
DRIVERS
PORT B
PB3:0 GND
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single
instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving through-
puts up to ten times faster than conventional CISC microcontrollers.
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM,
four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, inter-
nal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and
four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to Digital
Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and inter-
rupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by
stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip
functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of
the device is sleeping, allowing very fast start-up combined with low power consumption.
The device is manufactured using high density non-volatile memory technology. The on-chip, in-system programmable
Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer.
The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers
and evaluation kits.
4. General Information
4.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for
download at www.microchip.com
5. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct pro-
gram execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Program Status
Flash
Counter and Control
Program
Memory
16 x 8
Instruction General
Register Purpose Interrupt
Registrers Unit
Instruction Watchdog
Decoder Timer
Indirect Addressing
Direct Addressing
ALU Analog
Control Lines Comparator
ADC
Data Timer/Counter 0
SRAM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instruc-
tions to be executed in every clock cycle. The program memory is In-System reprogrammable Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the
Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables
in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this
section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect informa-
tion about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the
whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The
actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effec-
tively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the usage
of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed).
The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four
different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Sta-
tus Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O func-
tions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
Figure 5-2 below shows the structure of the 16 general purpose working registers in the CPU.
7 0
R16
R17
General R18
Purpose …
Note: A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16
registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle
instructions.
15 XH XL 0
X-register 7 0 7 0
R27 R26
15 YH YL 0
Y-register 7 0 7 0
R29 R28
15 ZH ZL 0
Z-register 7 0 7 0
R31 R30
In different addressing modes these address registers function as automatic increment and automatic decrement (see doc-
ument “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for details).
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the correspond-
ing unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two regis-
ter operands is executed, and the result is stored back to the destination register.
clkCPU
Total Execution Time
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending inter-
rupts, as shown in the following example.
Bit 7 6 5 4 3 2 1 0
0x3C CCP[7:0] CCP
Read/Write W W W W W W W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
7 6 5 4 3 2 1 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Bit 7 6 5 4 3 2 1 0
0x3F I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
6. Memories
This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program
memory space and the data memory space.
clkCPU
Address Compute Address Address valid
Data
Write
WR
Data
Read
RD
7. Clock System
Figure 7-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active
at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using differ-
ent sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 32.
The clock systems is detailed below.
WATCHDOG
CLOCK WATCHDOG
CLOCK
PRESCALER TIMER
CLOCK
SWITCH
See Table 7-3 on page 31 on how to select and change the active clock source.
EXTERNAL
CLOCK CLKI
SIGNAL
GND
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable
operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable
behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency.
7.4 Starting
Table 7-1. Start-up Times when Using the Internal Calibrated Oscillator
Reset Oscillator Configuration Total start-up time
64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles (1)
Notes: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator,
divided by 8
To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the
CLKMS bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the CLKMS bits with the desired value
Bit 7 6 5 4 3 2 1 0
0x39 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS
bits:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a fre-
quency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To
make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings.
Table 8-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
Source Enabled
VLM Interrupt
Pin Change
Main Clock
Watchdog
clkADC (1)
INT0 and
Other I/O
Interrupt
ADC (1)
clkNVM
clkCPU
Idle X X X X X X X X
(2)
ADC Noise Reduction X X X X X X
Standby X X (2) X
(2)
Power-down X X
To enter any of the four sleep modes, the SE bits in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2:0 bits in the SMCR register select which sleep mode (Idle, ADC Noise Reduction, Standby or Power-
down) will be activated by the SLEEP instruction. See Table 8-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the
MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 46 for details.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral
and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See
“Supply Current of I/O Modules” on page 130 for examples. In all other sleep modes, the clock is already stopped.
Note: 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC
PORF
WDRF
EXTRF
Power-on Reset
Circuit
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require
any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to
reach a stable level before normal operation starts. The start up sequence is described in “Starting from Reset” on page 30.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold
voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise. The reset signal is
activated again, without any delay, when VCC decreases below the detection level.
V POT
V CC
V RST
RESET
t TOUT
TIME-OUT
INTERNAL
RESET
V POT
V CC
> t TOUT
V RST
RESET
t TOUT
TIME-OUT
INTERNAL
RESET
When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM can be
shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either flag an inter-
rupt or generate a reset, depending on the configuration.
When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long as VCC
is below the reset level. See Table 9-4 on page 44 for reset level details. If supply voltage rises above the reset level the
condition is removed and the MCU will come out of reset, and initiate the power-up start-up sequence.
If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been restored.
CK
WATCHDOG
RESET
WDP0
WDP1
MUX
WDP2
WDP3
WDE
MCU RESET
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using
the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels
are selected by the fuse WDTON as shown in Table 9-1 on page 41. See “Procedure for Changing the Watchdog Timer
Configuration” on page 41 for details.
Note: 1. WDTON configuration bit set to “0“ means programmed and “1“ means unprogrammed.
Bit 7 6 5 4 3 2 1 0
0x34 VLMF VLMIE – – – VLM2 VLM1 VLM0 VLMCSR
Read/Write R R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
011 VLM2 Triggering sets the VLM Flag (VLMF) and generates a VLM
100 VLM3 interrupt, if enabled
101
110 Not allowed
111
10. Interrupts
This section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a general explanation of the AVR inter-
rupt handling, see “Reset and Interrupt Handling” on page 20.
In case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular
program code can be placed at these locations.
The most typical and general setup for interrupt vector addresses in ATtiny4/5/9/10 is shown in the program example
below.
<continues>
<continued>
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
• Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are
set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10-2. The value on the
INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
11.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direc-
tion of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI
instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resis-
tors. Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is
strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-volt-
age invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 11-1 on page
50. See “Electrical Characteristics” on page 124 for a complete list of parameters.
Rpu
Pxn Logic
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter
for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program,
the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The
physical I/O Registers and bit locations are listed in “Register Description” on page 60.
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction
Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read
only, while the Data Register, the Data Direction Register, and the Pull-up Enable Register are read/write. However, writing
a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 51. Most port pins are multi-
plexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port
pin is described in “Alternate Port Functions” on page 55. Refer to the individual module sections for a full description of the
alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as gen-
eral digital I/O.
REx
Q D
PUExn
Q CLR
RESET WEx
Q D
DDxn
Q CLR
WDx
RESET
RDx
DATA BUS
1
Pxn Q D
PORTxn 0
Q CLR
RESET
WRx WPx
SLEEP RRx
SYNCHRONIZER
RPx
D Q D Q
PINxn
L Q Q
clk I/O
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP are com-
mon to all ports.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an out-
put pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is
written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be written
logic zero.
Table 11-1 summarizes the control signals for the pin value.
Table 11-1. Port Pin Configurations
DDxn PORTxn PUExn I/O Pull-up Comment
0 X 0 Input No Tri-state (hi-Z)
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
SYSTEM CLK
r16 0x02
r17 0x01
PORTx 0x55
Px0 tri-state
SYSTEM CLK
SYNC LATCH
PINxn
t pd, max
t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock
is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The
signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive
clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 11-5 on page
54. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through
the synchronizer is one system clock period.
SYSTEM CLK
r16 0xFF
SYNC LATCH
PINxn
t pd
PUOExn REx
PUOVxn
1
0 Q D
PUExn
Q CLR
DDOExn
RESET WEx
DDOVxn
1
0 Q D
DDxn
Q CLR
WDx
PVOExn RESET
RDx
PVOVxn
DATA BUS
1 1
Pxn
0 Q D 0
PORTxn
PTOExn
Q CLR
DIEOExn
WPx
DIEOVxn RESET
1 WRx
RRx
0 SLEEP
SYNCHRONIZER
RPx
SET
D Q D Q
PINxn
L CLR Q CLR Q
clk I/O
DIxn
AIOxn
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP are com-
mon to all ports. All other signals are unique for each pin.
The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller fam-
ily. Some overriding signals may not be present in all port pins.
Table 11-2 on page 57 summarizes the function of the overriding signals. The pin and port indexes from Figure 11-6 on
page 56 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the
alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the
alternate function. Refer to the alternate function description for further details.
• PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change interrupt
0.
• TPICLK: Serial Programming Clock.
Table 11-4 and Table 11-5 on page 60 relate the alternate functions of Port B to the overriding signals shown in Figure 11-
6 on page 56.
Table 11-4. Overriding Signals for Alternate Functions in PB3..PB2
Signal
Name PB3/ADC3/RESET/PCINT3 PB2/ADC2/INT0/T0/CLKO/PCINT2
PUOE RSTDISBL(1) CKOUT(2)
PUOV 1 0
(1)
DDOE RSTDISBL CKOUT(2)
DDOV 0 1
PVOE 0 CKOUT(2)
PVOV 0 (system clock)
PTOE 0 0
RSTDISBL(1) + (PCINT3 • PCIE0) +
DIEOE (PCINT2 • PCIE0) + ADC2D + INT0
ADC3D
DIEOV RSTDISBL • PCINT3 • PCIE0 (PCINT2 • PCIE0) + INT0
DI PCINT3 Input INT0/T0/PCINT2 Input
AIO ADC3 Input ADC2 Input
12.1 Features
• True 16-bit Design, Including 16-bit PWM
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV0, OCF0A, OCF0B, and ICF0)
12.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal
timing measurement.
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)
Waveform
= Generation
OCnA
OCRnA
Fixed OCnB
TOP (Int.Req.)
DATA BUS
Values
Waveform
= Generation
OCnB
Edge Noise
ICRn
Detector Canceler
ICPn
TCCRnA TCCRnB
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1 on page 62. For actual placement of I/O
pins, refer to “Pinout of ATtiny4/5/9/10” on page 8. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown
in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 81.
Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter
number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in
a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
12.2.1 Registers
The Timer/Counter (TCNT0), Output Compare Registers (OCR0A/B), and Input Capture Register (ICR0) are all 16-bit reg-
isters. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the
section “Accessing 16-bit Registers” on page 79. The Timer/Counter Control Registers (TCCR0A/B) are 8-bit registers and
have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer
Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR
and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock
Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A/B) are compared with the Timer/Counter value at all time. The
result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Out-
put Compare pin (OC0A/B). See “Output Compare Units” on page 68. The compare match event will also set the Compare
Match Flag (OCF0A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the
Input Capture pin (ICP0) or on the Analog Comparator pins (See “Analog Comparator” on page 89). The Input Capture unit
includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR0A Reg-
ister, the ICR0 Register, or by a set of fixed values. When using OCR0A as TOP value in a PWM mode, the OCR0A
Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allow-
ing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR0 Register can be used as an
alternative, freeing the OCR0A to be used as PWM output.
12.2.2 Definitions
The following definitions are used extensively throughout the section:
12.3.1 Prescaler
The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1). This provides the fastest opera-
tion, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four
taps from the prescaler can be used as a clock source.
See Figure 12-2 for an illustration of the prescaler unit.
PSR10
T0
Synchronization
clkT0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 12-3 on page 65.
The prescaled clock has a frequency of fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. See Table 12-6 on page 84
for details.
detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in
the high period of the internal system clock.
The edge detector generates one clkT0 pulse for each positive (CS2:0 = 7) or negative (CS2:0 = 6) edge it detects.
Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE
clk I/O
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been
applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, other-
wise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The
external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50%
duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle
caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of
an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
TEMP (8-bit)
Clock Select
Count Edge
Tn
TCNTnH (8-bit) TCNTnL (8-bit) Clear clkTn Detector
Control Logic
Direction
TCNTn (16-bit Counter)
( From Prescaler )
TOP BOTTOM
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper eight bits
of the counter, and Counter Low (TCNT0L) containing the lower eight bits. The TCNT0H Register can only be indirectly
accessed by the CPU. When the CPU does an access to the TCNT0H I/O location, the CPU accesses the high byte tempo-
rary register (TEMP). The temporary register is updated with the TCNT0H value when the TCNT0L is read, and TCNT0H is
updated with the temporary register value when TCNT0L is written. This allows the CPU to read or write the entire 16-bit
counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to
the TCNT0 Register when the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
The clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no
clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, inde-
pendent of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM03:0) located in the
Timer/Counter Control Registers A and B (TCCR0A and TCCR0B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the Output Compare outputs OC0x. For more details about
advanced counting sequences and waveform generation, see “Modes of Operation” on page 71.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM03:0 bits. TOV0
can be used for generating a CPU interrupt.
TEMP (8-bit)
Analog
Comparator Noise Edge
ICFn (Int.Req.)
Canceler Detector
ICPn
When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively on the Analog Comparator
output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is
triggered, the 16-bit value of the counter (TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag
(ICF0) is set at the same system clock as the TCNT0 value is copied into ICR0 Register. If enabled (ICIE0 = 1), the Input
Capture Flag generates an Input Capture interrupt. The ICF0 flag is automatically cleared when the interrupt is executed.
Alternatively the ICF0 flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR0) is done by first reading the low byte (ICR0L) and then the
high byte (ICR0H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When
the CPU reads the ICR0H I/O location it will access the TEMP Register.
The ICR0 Register can only be written when using a Waveform Generation mode that utilizes the ICR0 Register for defin-
ing the counter’s TOP value. In these cases the Waveform Generation mode (WGM03:0) bits must be set before the TOP
value can be written to the ICR0 Register. When writing the ICR0 Register the high byte must be written to the ICR0H I/O
location before the low byte is written to ICR0L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79.
that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR0 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP0 pin.
TEMP (8-bit)
OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
Waveform Generator OCnx
BOTTOM
WGMn3:0 COMnx1:0
The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Nor-
mal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0x Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. The con-
tent of the OCR0x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update
this register automatically as the TCNT0 and ICR0 Register). Therefore OCR0x is not read via the high byte temporary reg-
ister (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the
OCR0x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte
(OCR0xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated
by the value written. Then when the low byte (OCR0xL) is written to the lower eight bits, the high byte will be copied into the
upper 8-bits of either the OCR0x buffer or OCR0x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79.
COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the
COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register
(DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the
OC0x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode,
but there are some exceptions. See Table 12-2 on page 82, Table 12-3 on page 82 and Table 12-4 on page 82 for details.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that
some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 81
The COM0x1:0 bits have no effect on the Input Capture unit.
TCNTn
OCnA
(COMnA1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF0A or ICF0
flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be
used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running
with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
If the new value written to OCR0A or ICR0 is lower than the current value of TCNT0, the counter will miss the compare
match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the
compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM
mode using OCR0A for defining TOP (WGM03:0 = 15) since the OCR0A then will be double buffered.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare
match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the
port pin unless the data direction for the pin is set to output (DDR_OC0A = 1). The waveform generated will have a maxi-
mum frequency of 0A = fclk_I/O/2 when OCR0A is set to zero (0x0000). The waveform frequency is defined by the following
equation:
f clk_I/O
f OCnA = ---------------------------------------------------
2 N 1 + OCRnA
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX
to 0x0000.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum res-
olution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to
MAX). The PWM resolution in bits can be calculated by using the following equation:
log TOP + 1
R FPWM = -----------------------------------
log 2
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF,
0x01FF, or 0x03FF (WGM03:0 = 5, 6, or 7), the value in ICR0 (WGM03:0 = 14), or the value in OCR0A (WGM03:0 = 15).
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure
12-9 on page 73. The figure shows fast PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in
the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x
and TCNT0. The OC0x interrupt flag will be set when a compare match occurs.
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7 8
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition the OC0A or ICF0 flag is
set at the same timer clock cycle as TOV0 is set when either OCR0A or ICR0 is used for defining the TOP value. If one of
the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur
between the TCNT0 and the OCR0x. Note that when using fixed TOP values the unused bits are masked to zero when any
of the OCR0x Registers are written.
The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0 Register
is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with none or a low
prescaler value, there is a risk that the new ICR0 value written is lower than the current value of TCNT0. The result will then
be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR0A Register however, is dou-
ble buffered. This feature allows the OCR0A I/O location to be written anytime. When the OCR0A I/O location is written the
value written will be put into the OCR0A Buffer Register. The OCR0A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT0 matches TOP. The update is done at the same timer clock
cycle as the TCNT0 is cleared and the TOV0 flag is set.
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is
free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed (by
changing the TOP value), using the OCR0A as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to
two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three
(see Table 12-3 on page 82). The actual OC0x value will only be visible on the port pin if the data direction for the port pin
is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare
match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = -----------------------------------
N 1 + TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the fast
PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock
cycle. Setting the OCR0x equal to TOP will result in a constant high or low output (depending on the polarity of the output
set by the COM0x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its logi-
cal level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f0A = fclk_I/
O/2 when OCR0A is set to zero (0x0000). This feature is similar to the OC0A toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
log TOP + 1
R PCPWM = -----------------------------------
log 2
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 1, 2, or 3), the value in ICR0 (WGM03:0 = 10), or the value in OCR0A (WGM03:0
= 11). The counter has then reached the TOP and changes the count direction. The TCNT0 value will be equal to TOP for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-10 on page 75. The fig-
ure shows phase correct PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and
TCNT0. The OC0x interrupt flag will be set when a compare match occurs.
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. When either OCR0A or ICR0 is
used for defining the TOP value, the OC0A or ICF0 flag is set accordingly at the same timer clock cycle as the OCR0x Reg-
isters are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time
the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur
between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are masked to zero when
any of the OCR0x Registers are written. As the third period shown in Figure 12-10 on page 75 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The rea-
son for this can be found in the time of update of the OCR0x Register. Since the OCR0x update occurs at TOP, the PWM
period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value,
while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the
period will differ in length. The difference in length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the
TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between
the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting the
COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COM0x1:0 to three (See Table 12-4 on page 82). The actual OC0x value will only be visible on the port pin if the data direc-
tion for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x
Register at the compare match between OCR0x and TCNT0 when the counter increments, and clearing (or setting) the
OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = -----------------------------
2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in the
phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to
TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite
logic values.
log TOP + 1
R PFCPWM = -----------------------------------
log 2
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in
ICR0 (WGM03:0 = 8), or the value in OCR0A (WGM03:0 = 9). The counter has then reached the TOP and changes the
count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
and frequency correct PWM mode is shown on Figure 12-11 on page 77. The figure shows phase and frequency correct
PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in the timing diagram shown as a histogram
for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizon-
tal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will
be set when a compare match occurs.
Figure 12-11. Phase and Frequency Correct PWM Mode, Timing Diagram
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4
The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated with the
double buffer value (at BOTTOM). When either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 flag
set when TCNT0 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur
between the TCNT0 and the OCR0x.
As Figure 12-11 on page 77 shows the output generated is, in contrast to the phase correct mode, symmetrical in all peri-
ods. Since the OCR0x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is
free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed by chang-
ing the TOP value, using the OCR0A as TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by set-
ting the COM0x1:0 to three (See Table 12-4 on page 82). The actual OC0x value will only be visible on the port pin if the
data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the
OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and clearing (or setting)
the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase and frequency correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = -----------------------------
2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the
phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to
TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
clkI/O
clkTn
(clkI/O /1)
OCFnx
Figure 12-13 on page 78 shows the same timing data, but with the prescaler enabled.
Figure 12-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCFnx
Figure 12-14 on page 79 shows the count sequence close to TOP in various modes. When using phase and frequency cor-
rect PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be
replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 flag at
BOTTOM.
clkI/O
clkTn
(clkI/O /1)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)
TCNTn
TOP - 1 TOP TOP - 1 TOP - 2
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
Figure 12-15 on page 79 shows the same timing data, but with the prescaler enabled.
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)
TOVn (FPWM)
and ICF n (if used
as TOP)
OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)
the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the
16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR0A/B 16-bit registers does not
involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before
the high byte.
The following code example shows how to access the 16-bit timer registers assuming that no interrupts updates the tempo-
rary register. The same principle can be used directly for accessing the OCR0A/B and ICR0 Registers.
The code example returns the TCNT0 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instruc-
tions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any
other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the
16-bit access.
The following code example shows how to do an atomic read of the TCNT0 Register contents. Reading any of the OCR0A/
B or ICR0 Registers can be done by using the same principle.
The code example returns the TCNT0 value in the r17:r16 register pair.
The following code example shows how to do an atomic write of the TCNT0 Register contents. Writing any of the OCR0A/
B or ICR0 Registers can be done by using the same principle.
The code example requires that the r17:r16 register pair contains the value to be written to TCNT0.
When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on the WGM03:0 bits. Table 12-2
shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to a Normal or CTC (non-PWM) Mode.
Table 12-3 shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to one of the Fast PWM Modes.
Note: 1. A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. In this case the compare match is
ignored, but set or clear is done at BOTTOM. See “Fast PWM Mode” on page 72 for more details.
Table 12-4 shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to the phase correct or the phase and fre-
quency correct, PWM mode.
Table 12-4. Compare Output in Phase Correct and Phase & Frequency Correct PWM Modes
COM0A1/ COM0A0/
COM0B1 COM0B0 Description
0 Normal port operation: OC0A/OC0B disconnected.
0 WGM03 = 0: Normal port operation, OC0A/OC0B disconnected
1
WGM03 = 1: Toggle OC0A on compare match, OC0B reserved
Counting up: Clear OC0A/OC0B on compare match
0
Counting down: Set OC0A/OC0B on compare match
1 (1)
Counting up: Set OC0A/OC0B on compare match
1
Counting down: Clear OC0A/OC0B on compare match
Note: 1. A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. “Phase Correct PWM Mode” on
page 74 for more details.
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse
Width Modulation (PWM) modes. (“Modes of Operation” on page 71).
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is con-
figured as an output. This feature allows software control of the counting.
The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for
write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte regis-
ter (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 79.
Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a compare match between TCNT0
and one of the OCR0x Registers.
Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously
when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This
temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 79.
The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on
the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This tempo-
rary register is shared by all the other 16-bit registers. “Accessing 16-bit Registers” on page 79.
See Figure 1-1 on page 8 for pin use of analog comparator, and Table 11-4 on page 59 and Table 11-5 on page 60 for
alternate pin usage.
When changing the ACIS1/ACIS0 bits, the analog comparator Interrupt must be disabled by clearing its Interrupt Enable bit
in “ACSR – Analog Comparator Control and Status Register”. Otherwise an interrupt can occur when the bits are changed.
14.1 Features
• 8-bit Resolution
• 0.5 LSB Integral Non-linearity
• 1 LSB Absolute Accuracy
• 65µs Conversion Time
• 15 kSPS at Full Resolution
• Four Multiplexed Single Ended Input Channels
• Input Voltage Range: 0 – VCC
• Supply Voltage Range: 2.5V – 5.5V
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
14.2 Overview
ATtiny5/10 feature an 8-bit, successive approximation ADC. The ADC is connected to a 4-channel analog multiplexer
which allows four single-ended voltage inputs constructed from the pins of port B. The single-ended voltage inputs refer to
0V (GND).
The ADC contains a Sample-and-Hold-circuit, which ensures that the input voltage to the ADC is held at a constant level
during conversion. A block diagram of the ADC is shown in Figure 14-1 on page 92.
Internal reference voltage of VCC is provided on-chip.
The ADC is not available in ATtiny4/9.
14.3 Operation
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction Register must be disabled.
This is done by clearing the PRADC bit. See “PRR – Power Reduction Register” on page 36 for more details.
The ADC is enabled by setting the ADC Enable bit, ADEN in “ADCSRA – ADC Control and Status Register A”. Input chan-
nel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC converts an analog input voltage to an 8-bit digital value using successive approximation. The minimum value
represents GND and the maximum value represents the voltage on VCC.
The analog input channel is selected by writing MUX1:0 bits. See “ADMUX – ADC Multiplexer Selection Register” on page
101. Any of the ADC input pins can be selected as single ended inputs to the ADC.
The ADC generates an 8-bit result which is presented in the ADC data register. See “ADCL – ADC Data Register” on page
103.
The ADC has its own interrupt request which can be triggered when a conversion completes.
INTERRUPT FLAGS
ADMUX ADCSRB ADCSRA ADCL
MUX0
MUX1
ADTS2:0
ADSC
ADATE
ADPS2
ADPS1
ADPS0
ADEN
ADIE
TRIGGER ADC IRQ
DECODER
SELECT
CHANNEL
START
PRESCALER
ADC7:0
ADIF
CONVERSION LOGIC
VREF
VCC 8-BIT DAC
-
ADC3 +
SAMPLE & HOLD
ADC2 COMPARATOR
INPUT
MUX
ADC1
ADC0
ADTS[2:0]
PRESCALER
START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR
ADSC
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion
has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC data register. The
first conversion must be started by writing a logical one to bit ADSC bit in ADCSRA. In this mode the ADC will perform suc-
cessive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be
used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of
how the conversion was started.
ADEN
START Reset
7-BIT ADC PRESCALER
CK
CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2
The ADC module contains a prescaler, as illustrated in Figure 14-3 on page 93, which generates an acceptable ADC clock
frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler
starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running
for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising
edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarized in Table 14-1 on page 95. The first conversion after the
ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. See Fig-
ure 14-4.
Figure 14-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion
Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3
ADC Clock
ADEN
ADSC
ADIF
The actual sample-and-hold takes place 3 ADC clock cycles after the start of a normal conversion and 16 ADC clock cycles
after the start of a first conversion. See Figure 14-5. When a conversion is complete, the result is written to the ADC Data
Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC
again, and a new conversion will be initiated on the first rising ADC clock edge.
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3
ADC Clock
ADSC
ADIF
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See Figure 14-6. This assures a fixed
delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles
after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
ADC Clock
Trigger
Source
ADATE
ADIF
In Free Running mode (see Figure 14-7), a new conversion will be started immediately after the conversion completes,
while ADSC remains high.
11 12 13 1 2 3 4
Cycle Number
ADC Clock
ADSC
ADIF
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise
Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power
consumption.
IIH
ADCn
1..100 kohm
CS/H= 14 pF
IIL
VCC/2
The capacitor in Figure 14-8 depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic
capacitance inside the device. The value given is worst case.
The ADC is optimized for analog signals with an output impedance of approximately 10 k, or less. With such sources, the
sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time
the source needs to charge the S/H capacitor. This can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid distortion from unpredictable
signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the sig-
nals as inputs to the ADC.
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in Section 14.7
on page 96. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC
Noise Reduction Mode
• Offset: The deviation of the first transition (0x00 to 0x01) compared to the ideal transition (at 0.5 LSB). Ideal value: 0
LSB.
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF)
compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB
Ideal ADC
Actual ADC
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual
transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Ideal ADC
Actual ADC
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent
transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
1 LSB
DNL
0x00
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1
LSB wide) will code to the same value. Always ± 0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any
code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value:
± 0.5 LSB.
V IN 256
ADCL = -----------------------
V CC
where VIN (see Table 14-2 on page 101) is the voltage on the selected input pin and VCC is the voltage reference. 0x00
represents analog ground, and 0xFF represents the selected reference voltage minus one LSB.
If these bits are changed during a conversion, the change will not go in effect until the conversion is complete (ADIF in
ADCSRA is set)
When an ADC conversion is complete, the result is found in the ADC register.
15.1 Features
• Physical Layer:
– Synchronous Data Transfer
– Bi-directional, Half-duplex Receiver And Transmitter
– Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits
– Parity Error Detection, Frame Error Detection And Break Character Detection
– Parity Generation And Collision Detection
– Automatic Guard Time Insertion Between Data Reception And Transmission
• Access Layer:
– Communication Based On Messages
– Automatic Exception Handling Mechanism
– Compact Instruction Set
– NVM Programming Access Control
– Tiny Programming Interface Control And Status Space Access Control
– Data Space Access Control
15.2 Overview
The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memories (NVM). Memory pro-
gramming is done via the NVM Controller, by executing NVM controller commands as described in “Memory Programming”
on page 115.
The Tiny Programming Interface (TPI) provides access to the programming facilities. The interface consists of two layers:
the access layer and the physical layer. The layers are illustrated in Figure 15-1.
Figure 15-1. The Tiny Programming Interface and Related Internal Interfaces
NVM
TINY PROGRAMMING INTERFACE (TPI) CONTROLLER
RESET
TPICLK PHYSICAL ACCESS
LAYER LAYER NON-VOLATILE
TPIDATA
MEMORIES
DATA BUS
Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET pin as enable, the TPICLK
pin as the clock input, and the TPIDATA pin as data input and output.
NVM can be programmed at 5V, only.
Figure 15-2. Using an External Programmer for In-System Programming via TPI
+5V
ATtiny4/5/9/10
TPI TPIDATA/PB0 PB3/RESET
CONN
GND VCC
TPICLK/PB1 PB2
APPLICATION
NVM can be programmed at 5V, only. In some designs it may be necessary to protect components that can not tolerate 5V
with, for example, series resistors.
15.3.1 Enabling
The following sequence enables the Tiny Programming Interface (see Figure 15-3 for guidance):
• Apply 5V between VCC and GND
• Depending on the method of reset to be used:
– Either: wait tTOUT (see Table 17-4 on page 127) and then set the RESET pin low. This will reset the device and
enable the TPI physical layer. The RESET pin must then be kept low for the entire programming session
– Or: if the RSTDISBL configuration bit has been programmed, apply 12V to the RESET pin. The RESET pin
must be kept at 12V for the entire programming session
• Wait tRST (see Table 17-4 on page 127)
• Keep the TPIDATA pin high for 16 TPICLK cycles
RESET
TPICLK
TPIDATA
15.3.2 Disabling
Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inac-
tive high state or, alternatively, if VHV is no longer applied to the RESET pin.
If the NVM enable bit is not cleared a power down is required to exit TPI programming mode.
See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 114.
TPICLK
BREAK CHARACTER
15.3.6 Operation
The TPI physical layer operates synchronously on the TPICLK provided by the external programmer. The dependency
between the clock edges and data sampling or data change is shown in Figure 15-6. Data is changed at falling edges and
sampled at rising edges.
TPICLK
TPIDATA
SAMPLE
SETUP
The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive mode,
waiting for a start bit. The mode of operation is controlled by the access layer.
The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver is always enabled when a
logical zero is sent. When sending successive logical ones, the output is only driven actively during the first clock cycle.
After this, the output driver is automatically tri-stated and the TPIDATA line is kept high by the internal pull-up. The output is
re-enabled, when the next logical zero is sent.
The collision detection is enabled in transmit mode, when the output driver has been disabled. The data line should now be
kept high by the internal pull-up and it is monitored to see, if it is driven low by the external programmer. If the output is read
low, a collision has been detected.
There are some potential pit-falls related to the way collision detection is performed. For example, collisions cannot be
detected when the TPI physical layer transmits a bit-stream of successive logical zeros, or bit-stream of alternating logical
ones and zeros. This is because the output driver is active all the time, preventing polling of the TPIDATA line. However,
within a single frame the two stop bits should always be transmitted as logical ones, enabling collision detection at least
once per frame (as long as the frame format is not violated regarding the stop bits).
The TPI physical layer will cease transmission when it detects a collision on the TPIDATA line. The collision is signalized to
the TPI access layer, which immediately changes the physical layer to receive mode and goes to the error state. The TPI
access layer can be recovered from the error state only by sending a BREAK character.
• Write messages. A write message is a request to write data. The write message is sent entirely by the external
programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions.
• Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte
operands. This message type is used with the SLDCS, SLD and SIN instructions.
All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY
instruction requires 8 byte operands. For more information, see the TPI instruction set on page 109.
When the TPI physical layer is in transmit mode, the possible exceptions are:
• The TPI physical layer detects a data collision.
All these exceptions are signalized to the TPI access layer. The access layer responds to an exception by aborting any on-
going operation and enters the error state. The access layer will stay in the error state until a BREAK character has been
received, after which it is taken back to its default state. As a consequence, the external programmer can always synchro-
nize the protocol by simply transmitting two successive BREAK characters.
15.5.1 SLD - Serial LoaD from data space using indirect addressing
The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-register for
serial read-out. The data space location is pointed by the Pointer Register (PR), where the address must have been stored
before data is accessed. The Pointer Register is either left unchanged by the operation, or post-incremented, as shown in
Table 15-2.
Table 15-2. The Serial Load from Data Space (SLD) Instruction
Operation Opcode Remarks Register
data DS[PR] 0010 0000 PR PR Unchanged
data DS[PR] 0010 0100 PR PR + 1 Post increment
15.5.6 SLDCS - Serial LoaD data from Control and Status space using direct addressing
The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physical layer shift register for
serial read-out. The SLDCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the
instruction, as shown in Table 15-7.
Table 15-7. The Serial Load Data from Control and Status space (SLDCS) Instruction
Operation Opcode Remarks
data CSS[a] 1000 aaaa Bits marked ‘a’ form the direct, 4-bit addres
15.5.7 SSTCS - Serial STore data to Control and Status space using direct addressing
The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift register to the TPI Control and
Status Space. The SSTCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the
instruction, as shown in Table 15-8.
Table 15-8. The Serial STore data to Control and Status space (SSTCS) Instruction
Operation Opcode Remarks
CSS[a] data 1100 aaaa Bits marked ‘a’ form the direct, 4-bit addres
After the key has been given, the Non-Volatile Memory Enable (NVMEN) bit in the TPI Status Register (TPISR) must be
polled until the Non-Volatile memory has been enabled.
NVM programming is disabled by writing a logical zero to the NVMEN bit in TPISR.
0x0E
... Reserved – – – – – – – –
0x03
0x02 TPIPCR – – – – – GT2 GT1 GT0
0x01 Reserved – – – – – – – –
The default Guard Time is 128 IDLE bits. To speed up the communication, the Guard Time should be set to the shortest
safe value.
16.1 Features
• Two Embedded Non-Volatile Memories:
– Non-Volatile Memory Lock bits (NVM Lock bits)
– Flash Memory
• Four Separate Sections Inside Flash Memory:
– Code Section (Program Memory)
– Signature Section
– Configuration Section
– Calibration Section
• Read Access to All Non-Volatile Memories from Application Software
• Read and Write Access to Non-Volatile Memories from External programmer:
– Read Access to All Non-Volatile Memories
– Write Access to NVM Lock Bits, Flash Code Section and Flash Configuration Section
• External Programming:
– Support for In-System and Mass Production Programming
– Programming Through the Tiny Programming Interface (TPI)
• High Security with NVM Lock Bits
16.2 Overview
The Non-Volatile Memory (NVM) Controller manages all access to the Non-Volatile Memories. The NVM Controller con-
trols all NVM timing and access privileges, and holds the status of the NVM.
During normal execution the CPU will execute code from the code section of the Flash memory (program memory). When
entering sleep and no programming operations are active, the Flash memory is disabled to minimize power consumption.
All NVM are mapped to the data memory. Application software can read the NVM from the mapped locations of data mem-
ory using load instruction with indirect addressing.
The NVM has only one read port and, therefore, the next instruction and the data can not be read simultaneously. When
the application reads data from NVM locations mapped to the data space, the data is read first before the next instruction is
fetched. The CPU execution is here delayed by one system clock cycle.
Internal programming operations to NVM have been disabled and the NVM therefore appears to the application software
as read-only. Internal write or erase operations of the NVM will not be successful.
The method used by the external programmer for writing the Non-Volatile Memories is referred to as external program-
ming. External programming can be done both in-system or in mass production. See Figure 15-2 on page 105. The
external programmer can read and program the NVM via the Tiny Programming Interface (TPI).
In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections
which are read-only.
NVM can be programmed at 5V, only.
The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security shown in Table
16-2. Lock Bits can be erased to "1" with the Chip Erase command, only.
Notes: 1. Program the configuration section bits before programming NVLB1 and NVLB2.
2. "1" means unprogrammed, "0" means programmed
Table 16-6 briefly describes the functionality of all configuration bits and how they are mapped into the configuration byte.
Configuration bits are not affected by a chip erase but they can be cleared using the configuration section erase command
(see “Erasing the Configuration Section” on page 120). Note that configuration bits are locked if Non-Volatile Lock Bit 1
(NVLB1) is programmed.
ATtiny4/5/9/10 have a three-byte signature code, which can be used to identify the device. The three bytes reside in the
signature section, as shown in Table 16-7. The signature data for ATtiny4/5/9/10 is given in Table 16-8.
When the NVM Controller is busy performing an operation it will signal this via the NVM Busy Flag in the NVM Control and
Status Register. See “NVMCSR - Non-Volatile Memory Control and Status Register” on page 123. The NVM Command
Register is blocked for write access as long as the busy flag is active. This is to ensure that the current command is fully
executed before a new command can start.
Programming any part of the NVM will automatically inhibit the following operations:
• All programming to any other part of the NVM
• All reading from any NVM location
ATtiny4/5/9/10 support only external programming. Internal programming operations to NVM have been disabled, which
means any internal attempt to write or erase NVM locations will fail.
LOW/HIGH
BYTE SELECT
FLASH FLASH
SECTION PAGE
00 00
WORD ADDRESS
01 01
WITHIN A FLASH
PAGE
02 ... WORD
... PAGE ...
PAGE ADDRESS
... WITHIN A FLASH ...
SECTION
...
PAGEEND
SECTIONEND
Refer to the Tiny Programming Interface description on page 104 for more detailed information of enabling the TPI and
programming the NVM.
17.2 DC Characteristics
17.3 Speed
The maximum operating frequency of the device depends on VCC . The relationship between supply voltage and maximum
operating frequency is piecewise linear, as shown in Figure 17-1.
12 MHz
8 MHz
4 MHz
Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
V IH1
V IL1
TPIDATA
TPICLK
tCLCH tCHCL
tCLCL
Table 17-9. Serial Programming Characteristics, TA = -40C to 85C, VCC = 5V 5% (Unless Otherwise Noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Clock Frequency 2 MHz
tCLCL Clock Period 500 ns
tCLCH Clock Low Pulse Width 200 ns
tCHCH Clock High Pulse Width 200 ns
tIVCH Data Input to Clock High Setup Time 50 ns
tCHIX Data Input Hold Time After Clock High 100 ns
tCLOV Data Output Valid After Clock Low Time 200 ns
where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin.
Table 18-1. Additional Current Consumption for the different I/O modules (absolute values)
PRR bit Typical numbers
VCC = 2V, f = 1MHz VCC = 3V, f = 4MHz VCC = 5V, f = 8MHz
PRTIM0 6.6 uA 40.0 uA 153.0 uA
PRADC (1) 29.6 uA 88.3 uA 333.3 uA
Table 18-2 below can be used for calculating typical current consumption for other supply voltages and frequencies than
those mentioned in the Table 18-1 above.
Table 18-2. Additional Current Consumption (percentage) in Active and Idle mode
Current consumption additional to Current consumption additional to
active mode with external clock idle mode with external clock
PRR bit (see Figure 18-1 and Figure 18-2) (see Figure 18-7 and Figure 18-8)
PRTIM0 2.3 % 10.4 %
PRADC (1) 6.7 % 28.8 %
Figure 18-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
(PRR=0xFF)
0.7 5.5 V
0.6 5.0 V
0.5 4.5 V
4.0 V
0.4
ICC (mA)
3.3 V
0.3
2.7 V
0.2
1.8 V
0.1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
4.5
5.5 V
4
5.0 V
3.5
4.5 V
3
ICC (mA)
2.5
4.0 V
2
1.5
3.3 V
1
2.7 V
0.5
1.8 V
0
0 2 4 6 8 10 12
Frequency (MHz)
Figure 18-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL OSCILLATOR, 8 MHz
3.5
-40 °C
3 25 °C
85 °C
2.5
2
ICC (mA)
1.5
0.5
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 18-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL OSCILLATOR, 1 MHz
0.9
-40 °C
25 °C
0.8 85 °C
0.7
0.6
ICC (mA)
0.5
0.4
0.3
0.2
0.1
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 18-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL OSCILLATOR, 128 KHz
0.12
-40 °C
25 °C
0.1 85 °C
0.08
ICC (mA)
0.06
0.04
0.02
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 18-6. Active Supply Current vs. VCC (External Clock, 32 kHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL OSCILLATOR, 32 KHz
0.04
-40 °C
85 °C
0.035 25 °C
0.03
0.025
ICC (mA)
0.02
0.015
0.01
0.005
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 18-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
(PRR=0xFF)
0,1
0,09
0,08
5.5 V
0,07 5.0 V
0,06 4.5 V
ICC (mA)
0,05 4.0 V
0,04
3.3 V
0,03
2.7 V
0,02
1.8 V
0,01
0
0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
1
5.5 V
5.0 V
0,8
4.5 V
0,6
ICC (mA)
4.0 V
0,4
3.3 V
0,2
2.7 V
1.8 V
0
0 2 4 6 8 10 12
Frequency (MHz)
Figure 18-9. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
0,7
85 °C
25 °C
-40 °C
0,6
0,5
0,4
ICC (mA)
0,3
0,2
0,1
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-10. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
0,7
0,6
0,5
0,4
ICC (mA)
0,3
85 °C
25 °C
0,2 -40 °C
0,1
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
0.5
85 °C
0.45
0.4
0.35
0.3
ICC (uA)
0.25
0.2
0.15
25 °C
0.1
-40 °C
0.05
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Figure 18-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
9
-40 °C
8 25 °C
85 °C
7
5
ICC (uA)
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-13. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
60
50
40
IOP (uA)
30
20
10
25 °C
85 °C
-40 °C
0
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP (V)
Figure 18-14. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
80
70
60
50
IOP (uA)
40
30
20
10
25 °C
85 °C
0
-40 °C
0 0,5 1 1,5 2 2,5 3
VOP (V)
Figure 18-15. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
160
140
120
100
IOP (uA)
80
60
40
20
25 °C
85 °C
0
-40 °C
0 1 2 3 4 5 6
VOP (V)
Figure 18-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
40
35
30
25
IRESET (uA)
20
15
10
5
25 °C
-40 °C
0 85 °C
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET (V)
Figure 18-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
60
50
40
IRESET (uA)
30
20
10
25 °C
-40 °C
0 85 °C
0 0,5 1 1,5 2 2,5 3
VRESET (V)
Figure 18-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
120
100
80
IRESET (uA)
60
40
20
25 °C
-40 °C
0 85 °C
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5
VRESET (V)
Figure 18-19. I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 1.8V
0.8
0.7 85 °C
0.6
0.5
25 °C
VOL (V)
0.4 -40 °C
0.3
0.2
0.1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IOL (mA)
Figure 18-20. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
0.8
0.7
85 °C
0.6
0.5
25 °C
-40 °C
VOL (V)
0.4
0.3
0.2
0.1
0
0 1 2 3 4 5 6 7 8 9 10
IOL (mA)
Figure 18-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
1
85 °C
0.8
-40 °C
25 °C
0.6
VOL (V)
0.4
0.2
0
0 2 4 6 8 10 12 14 16 18 20
IOL (mA)
Figure 18-22. I/O Pin Output Voltage vs. Source Current (VCC = 1.8V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 1.8V
1.8
1.6
1.4
1.2 -40 °C
VOH (V)
1 25 °C
0.8 85 °C
0.6
0.4
0.2
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IOH (mA)
Figure 18-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
3.1
2.9
2.7
-40 °C
2.5 25 °C
VOH (V)
2.3 85 °C
2.1
1.9
1.7
1.5
0 1 2 3 4 5 6 7 8 9 10
IOH (mA)
Figure 18-24. I/O Pin output Voltage vs. Source Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
5.2
4.8
VOH (V)
4.6
4.4
-40 °C
25 °C
4.2
85 °C
4
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
Figure 18-25. Reset Pin as I/O, Output Voltage vs. Sink Current
OUTPUT VOLTAGE vs. SINK CURRENT
RESET PIN AS I/O
1
1.8 V 3.0 V
0.9
0.8
0.7
5.0 V
0.6
VOL (V)
0.5
0.4
0.3
0.2
0.1
0
0 1 2 3 4
IOL (mA)
Figure 18-26. Reset Pin as I/O, Output Voltage vs. Source Current
OUTPUT VOLTAGE vs. SOURCE CURRENT
RESET PIN AS I/O
3
VOH (V)
5.0 V
1 3.0 V
1.8 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
IOH (mA)
Figure 18-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, I/O PIN READ AS '1'
3,5
3 85 °C
25 °C
-40 °C
2,5
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-28. I/O Pin Input threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, I/O PIN READ AS '0'
85 °C
2,5 25 °C
-40 °C
2
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0,9
0,8
0,7
Input Hysteresis (V)
0,6
-40 °C
0,5
25 °C
0,4
85 °C
0,3
0,2
0,1
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-30. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)
RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC
VIH, RESET READ AS '1'
3
-40 °C
25 °C
85 °C
2,5
2
Threshold (V)
1,5
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-31. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’)
RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC
VIL, RESET READ AS '0'
2,5
85 °C
25 °C
-40 °C
2
1,5
Threshold (V)
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-32. Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O)
RESET PIN AS I/O, INPUT HYSTERESIS vs. VCC
VIL, PIN READ AS "0"
0,9
0,8
-40 °C
0,7
Input Hysteresis (V)
25 °C
0,6
0,5
85 °C
0,4
0,3
0,2
0,1
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-33. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, I/O PIN READ AS '1'
2,5
1,5
Threshold (V)
-40 °C
25 °C
1
85 °C
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-34. Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, I/O PIN READ AS '0'
2,5
85 °C
25 °C
-40 °C
1,5
Threshold (V)
0,5
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0,8
Input Hysteresis (V)
0,6
-40 °C
0,4
25 °C
85 °C
0,2
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0.006
-40
0.004
Offset
25
0.002
85
0
0 1 2 3 4 5
VIN
110
109
108
107 -40 °C
106
Frequency (kHz)
105 25 °C
104
103
102
101
85 °C
100
99
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
110
109
108
107
Frequency (kHz)
106
105
104 1.8 V
103
2.7 V
102
3.3 V
101 4.0 V
5.5 V
100
-60 -40 -20 0 20 40 60 80 100
Temperature
8.4
8.2 -40 °C
25 °C
Frequency (MHz)
8 85 °C
7.8
7.6
7.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
8.3
8.2
8.1
Frequency (MHz)
7.9
5.0 V
7.8
3.0 V
7.7
1.8 V
7.6
-40 -20 0 20 40 60 80 100
Temperature
16
25 °C
85 °C
14 -40 °C
12
Frequency (MHz)
10
0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
1.42
1.41
1.4
1.39
Threshold (V)
1.38
1.37
1.36
1.35
1.34
-40 -20 0 20 40 60 80 100
Temperature (C)
1.7
1.65
1.6
Threshold (V)
1.55
1.5
1.45
1.4
-40 -20 0 20 40 60 80 100
Temperature (C)
2.48
2.47
Threshold (V)
2.46
2.45
2.44
2.43
-40 -20 0 20 40 60 80 100
Temperature (C)
3.9
3.8
Threshold (V)
3.7
3.6
3.5
3.4
-40 -20 0 20 40 60 80 100
Temperature (C)
700
600
500
400
ICC (uA)
300
200
100
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
140
120
100
25 ˚C
ICC (uA)
80
60
40
20
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
0.35
VLM2:0 = 010
VLM2:0 = 011
0.25
VLM2:0 = 100
0.2
ICC (mA)
0.15
0.1
0.05
0 VLM2:0 = 000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
350
-40 °C
300 25 °C
85 °C
250
200
ICC (uA)
150
100
50
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
9
-40 °C
8 25 °C
85 °C
5
ICC (uA)
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Figure 18-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
0,5
0,4
5.5 V
0,3 5.0 V
4.5 V
ICC (mA)
4.0 V
3.3 V
2.7 V
0,2
1.8 V
0,1
0
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
Note: The default clock source for the device is always the internal 8 MHz oscillator. Hence, current consumption in reset remains
unaffected by external clock signals.
2500
2000
Pulsewidth (ns)
1500
1000
500
85 °C
25 °C
-40 °C
0
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. The ADC is available in ATtiny5/10, only.
21.1 6ST1
6 5 4 A
E E1 A2 A
Pin #1 ID 0.10 C
SEATING PLANE
A
1 2 3 A1
C
b e
Side View
Top View
A2 A 0.10 C
SEATING PLANE
0.25 c
A1 C
SEATING PLANE
View A-A
C
O L
SEE VIEW B
View B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.45
A1 0 – 0.15
A2 0.90 – 1.30
D 2.80 2.90 3.00 2
E 2.60 2.80 3.00
E1 1.50 1.60 1.75
Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB L 0.30 0.45 0.55
2. Dimension D does not include mold Flash, protrusions or gate burrs. e 0.95 BSC
Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end.
b 0.30 – 0.50 3
3. Dimension b does not include dambar protrusion. Allowable dambar
protrusion shall not cause the lead width to exceed the maximum c 0.09 – 0.20
b dimension by more than 0.08 mm q 0° – 8°
4. Die is facing down after trim/form.
6/30/08
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22. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device.
22.1 ATtiny4
22.1.1 Rev. E
• Programming Lock Bits
22.1.2 Rev. D
• ESD HBM (ESD STM 5.1) level 1000V
• Programming Lock Bits
22.1.3 Rev. A – C
Not sampled.
22.2 ATtiny5
22.2.1 Rev. E
• Programming Lock Bits
22.2.2 Rev. D
• ESD HBM (ESD STM 5.1) level 1000V
• Programming Lock Bits
22.2.3 Rev. A – C
Not sampled.
22.3 ATtiny9
22.3.1 Rev. E
• Programming Lock Bits
22.3.2 Rev. D
• ESD HBM (ESD STM 5.1) level 1000V
• Programming Lock Bits
22.3.3 Rev. A – C
Not sampled.
22.4 ATtiny10
22.4.1 Rev. E
• Programming Lock Bits
22.4.2 Rev. C – D
• ESD HBM (ESD STM 5.1) level 1000V
• Programming Lock Bits
22.4.3 Rev. A – B
Not sampled.
• Updated “Ordering Information” on page 9. The table below lists new ordering codes and ordering codes not
2.
recommended for new designs
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Customer Support
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
== ISO/TS 16949 ==
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.