MC9S12ZVMRM PDF
MC9S12ZVMRM PDF
MC9S12ZVMRM PDF
S12 MagniV
Microcontrollers
Rev. 2.11
28 OCT 2016
MC9S12ZVMRM
nxp.com
The ZVMC256, ZVML31, ZVM32 and ZVM16 devices are targeted for safety relevant systems and have
been developed using an ISO26262 compliant development system under the NXP SafeAssure program.
For details of device usage in safety relevant systems refer to the MC9S12ZVMB Safety Manual.
The document revision on the Internet is the most current. To verify this is the latest revision, refer to:
nxp.com.
This document contains information for all modules except the CPU. For CPU information please refer to
the CPU S12Z Reference Manual. This revision history table summarizes changes to this document. The
individual module sections contain revision history tables with more detailed information.
NOTE
This reference manual documents the S12ZVM-Family.
It contains a superset of features within the family.
Some module versions differ from one part to another within the family.
Section 1.2.1 MC9S12ZVM-Family Member Comparison provides support to access the
correct information for a particular part within the family.
NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP
data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including
“typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the
rights of others. NXP Semiconductors products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP Semiconductors product
could create a situation where personal injury or death may occur. Should Buyer purchase or use NXP Semiconductors products for any such unintended
or unauthorized application, Buyer shall indemnify and hold NXP Semiconductors and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that NXP Semiconductors was negligent regarding the design or
manufacture of the part.
Table 0-1. Revision History
22 MAY2014 1.4 Updated family derivative table for S12ZVML32, S12ZVM32 and S12ZVM16 devices
Added 64KB, 32KB and 16KB derivative information to flash module chapter
Added pin routing options for S12ZVM32 and S12ZVM16 devices
Added HV Phy information for the S12ZVM32 and S12ZVM16 derivatives
Updated Part ID assignment table and ordering information for S12ZVM32 and S12ZVM16
Corrected PLL VCO maximum frequency specification
Changed VLVLSA maximum from 7V to 6.9V
Added electrical parameter for HD division ratio through the phase multiplexer
Corrected preferred VRL reference from VRL_1 to VRL_0
Included NVM timing parameters for the S12ZVM32 and S12ZVM16 devices
Added GDU S12ZVM32 and S12ZVM16 specific differences and electrical specifications
Added references to fWSTAT
Added VDDX short circuit fall back current and temperature/input dependency specs.
22 APR 2015 2.1 Updated Stop and Wait current parameter values (ISUPS, ISUPW)
Corrected 80LQFP-EP pin name from VSS2 to VSS1
Updated ZVMC256 VDDS regulator parameters.
Changed PL0 ESD specification
Minor corrections to PIM, PMF, SRAM and ADC chapters (see module revision histories)
14 JAN 2016 2.5 Clarified non production mask sets Table 1-4, Table 1-6
Updated ordering information in Appendix L
Changed RESET pin input pulse passed parameter minimum specification value.Table A-13
Replaced Freescale with NXP in logo and page footers
Added maximum value for GDU parameter VBSx current whilst high side inactive Table E-2
07 MAR 2016 2.6 Added 3N95G mask set information Table 1-19, Table 1-4, Table 1-6
Added list of ISO26262 compliant devices
Moved GDU mask set dependent features to device overview section Table 1-19
Added new 64LQFP-EP package diagrams Table K.2
Added minimum value for GDU parameter VBSx current whilst high side inactive Table E-2
Updated VCSAoff parameter limits for GDU V5 and GDU V6 Table E-1, Table E-2
Added ADCCMD1[7:6] device dependencies in register listing Section M.13, Section M.14
Simplified GDU device dependencies in register listing Section M.15
Corrected High Temperature Interrupt spec. (cannot wake up from STOP) Table 1-16
Added footnote to Table A-14
ZVMC256: added typical Run/Wait IDD values, updated 85°C Stop IDD Table A-18, Table A-19
Added bootstrap diode resistance parameter Table E-2
Updated GDU boost coil current limit specification Table E-2, Table E-1
Reverted to original current sense amp. offset values Table E-2, Table E-1
Added package to mask set mapping table Table K-1
08 MAR 2016 2.7 Changed maximum value of VBSTOFF Table E-2, Table E-1
Updated 48LQFP-EP Mechanical Information Diagram Section K.1
19 APR 2016 2.8 Added PAD pin leakage specification at 125C Table A-12
Updated tHGON, tHGOFF parameter values Table E-1
Specified VRH drop when using VDDS1 or VDDS2 as VRH on ZVMC256 Section C.1.1.5
Added min. and max. desaturation comparator filter times to electrical spec. Table E-1
Updated 64LQFP-EP thermal parameters Table A-9, Table A-10
06 JUN 2016 2.9 Fixed corrupted symbol fonts Table A-3, Table A-5
Corrected wrong IFR reference Section 20.3.2.10
Clarified PAD8 leakage better Table A-12
Added ISUPR and ISUPW maximum values at TJ = 175°C for ZVMC256 Table A-18
Added Pseudo STOP maximum current for ZVMC256 Table A-20
Removed bandgap temperature dependency footnote, Table B-1
Changed ZVMC256 SNPS monitor threshold min/max values Table B-2
Changed VLS current limit threshold to 112mA Table E-1, Table E-2
Removed desaturation comparator filter times from GDU chapter.
Added desaturation comparator levels to Table E-1, Table E-2
Added low side desaturation comparator functional range as footnote Table E-1, Table E-2
28 OCT 2016 2.11 Added IOC0 signal mapping to 48LQFP package Figure 1-6
Fixed corrupted symbol fonts in PIM chapter
Added diode to VDDC pin Figure 1-18
Updated Stop mode current ISUPS maximum values Table A-19
Updated tdelon, tdeloff values Table E-1
Chapter 2
Port Integration Module (S12ZVMPIMV3)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.3.2 PIM Registers 0x0200-0x020F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.3.3 PIM Generic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
2.3.4 PIM Generic Register Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 3
Memory Mapping Control (S12ZMMCV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.4.1 Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.4.2 Illegal Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.4.3 Uncorrectable ECC Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Chapter 4
Interrupt (S12ZINTV0)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.4.1 S12Z Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.4.3 Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.4.4 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.4.5 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Chapter 5
Background Debug Controller (S12ZBDCV2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.4.2 Enabling BDC And Entering Active BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.4.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.4.4 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.4.5 BDC Access Of Internal Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.4.6 BDC Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol . . . . . . . . . . . . . . . . . . . . 216
5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.4.10 Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.4.11 Serial Communication Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.5.1 Clock Frequency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 6
S12Z Debug (S12ZDBG) Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.2.1 External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.2.2 Profiling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Chapter 7
ECC Generation Module (SRAM_ECCV1)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.3.1 Non-aligned Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.3.2 Aligned 2 and 4 Byte Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.3 Memory Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.4 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.5 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.3.6 ECC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.3.7 ECC Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Chapter 8
S12 Clock, Reset and Power Management Unit (V10 and V6)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
8.1.1 Differences between S12CPMU_UHV_V10 and S12CPMU_UHV_V6 . . . . . . . . . . . 289
8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
8.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
8.1.4 S12CPMU_UHV_V10_V6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Chapter 9
Analog-to-Digital Converter (ADC12B_LBA)
Chapter 10
Supply Voltage Sensor - (BATSV3)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.2.1 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
10.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Chapter 12
Timer Module (TIM16B2CV3) Block Description
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
12.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
12.2.1 IOC1 - IOC0 — Input Capture and Output Compare Channel 1-0 . . . . . . . . . . . . . . . . 461
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
12.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
12.6.1 Channel [1:0] Interrupt (C[1:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
12.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Chapter 13
Scalable Controller Area Network (S12MSCANV3)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Chapter 14
Programmable Trigger Unit (PTUV3)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2.1 PTUT0 — PTU Trigger 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2.2 PTUT1 — PTU Trigger 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2.3 PTURE — PTUE Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
14.4.2 Memory based trigger event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
14.4.3 Reload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
14.4.4 Async reload event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
14.4.5 Interrupts and error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
14.4.6 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Chapter 16
Serial Communication Interface (S12SCIV6)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Chapter 17
Serial Peripheral Interface (S12SPIV5)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
17.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
17.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
17.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
17.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
17.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
17.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Chapter 18
Gate Drive Unit (GDU)
18.1 Differences GDUV4 vs GDUV5 vs GDUV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.1 HD — High-Side Drain Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.2 VBS[2:0] — Bootstrap Capacitor Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.3 HG[2:0] — High-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.4 HS[2:0] — High-Side Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.5 VLS[2:0] — Voltage Supply for Low-Side Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.6 LG[2:0] — Low-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.2.7 LD[2:0] — Low-Side Gate Pins (only on GDUV6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
18.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
18.4.2 Low-Side FET Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
18.4.3 High-Side FET Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
18.4.4 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.4.5 Desaturation Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
18.4.6 Phase Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
18.4.7 Fault Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
18.4.8 Current Sense Amplifier and Overcurrent Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 738
18.4.9 GDU DC Link Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
18.4.10Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
18.4.11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
18.5.1 FET Pre-Driver Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
18.5.2 GDU Intrinsic Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
18.5.3 Calculation of Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
18.5.4 On Chip GDU tdelon and tdeloff Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Chapter 19
LIN/HV Physical Layer (S12LINPHYV3)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Chapter 20
Flash Module (S12ZFTMRZ)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
20.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
20.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
20.4.3 Flash Block Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
20.4.4 Internal NVM resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
20.4.5 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
20.4.6 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 804
20.4.7 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
20.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
20.4.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
20.4.10Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
20.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
20.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 823
20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 823
20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Chapter 22
Pulse-Width Modulator (S12PWM8B8CV2)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
22.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
22.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
22.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
Appendix A
MCU Electrical Specifications
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
A.2 General Purpose I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
A.3 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
A.4 ADC Calibration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Appendix B
CPMU Electrical Specifications (VREG, OSC, IRC, PLL)
B.1 VREG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
B.2 Reset and Stop Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
B.3 IRC and OSC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
B.4 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
Appendix C
ADC Electrical Specifications
C.1 ADC Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Appendix D
LIN/HV PHY Electrical Specifications
D.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
D.2 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Appendix E
GDU Electrical Specifications
E.1 GDU specifications for devices featuring GDU V4 or V6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
E.2 Preliminary GDU specifications for devices featuring GDU V5 . . . . . . . . . . . . . . . . . . . . . . . . . 914
Appendix F
NVM Electrical Parameters
F.1 NVM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
F.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
F.3 NVM Factory Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Appendix G
BATS Electrical Specifications
G.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
G.2 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Appendix I
SPI Electrical Specifications
I.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Appendix J
MSCAN Electrical Specifications
J.1 MSCAN Wake-up Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Appendix K
Package Information
K.1 48LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
K.2 64LQFP-EP Mechanical Info (all mask sets except 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . 945
K.3 64LQFP-EP Mechanical Information (mask sets 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . . . 949
K.4 80LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Appendix L
Ordering Information
Appendix M
Detailed Register Address Map
M.1 0x0000–0x0003 Part ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
M.2 0x0010–0x001F S12ZINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
M.3 0x0070-0x00FF S12ZMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
M.4 0x0100-0x017F S12ZDBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
M.5 0x0200-0x02FF PIM (See footnotes for part specific information) . . . . . . . . . . . . . . . . . . . . . . . 963
M.6 0x0380-0x039F FTMRZ128K512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
M.7 0x03C0-0x03CF SRAM_ECC_32D7P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
M.8 0x0400-0x042F TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
M.9 0x0480-0x04AF PWM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
M.10 0x0500-x053F PMF15B6C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
M.11 0x0580-0x059F PTU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
M.12 0x05C0-0x05FF TIM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
M.13 0x0600-0x063F ADC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
M.14 0x0640-0x067F ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
M.15 0x06A0-0x06BF GDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
M.16 0x06C0-0x06DF CPMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
M.17 0x06F0-0x06F7 BATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
1.1 Introduction
The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV
technology that offers the capability to integrate 40 V analog components. This family reuses many
features from the existing S12/S12X portfolio. The particular differentiating features of this family are the
enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the
integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit
(GDU), and either Local Interconnect Network (LIN) physical layer or CAN Physical layer. These features
enable a fully integrated single chip solution to drive up to 6 external power MOSFETs for BLDC or
PMSM motor drive applications.
The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM
for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase
locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family allows the
integration of several key system components into a single device, optimizing system architecture and
achieving significant space savings. The MC9S12ZVM-Family delivers all the advantages and
efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size
efficiency advantages currently enjoyed by users of existing S12(X) families. The MC9S12ZVM-Family
is available in different pin-out options, using 80-pin, 64-pin and 48-pin LQFP-EP packages to
accommodate LIN, CAN and external PWM based application interfaces. In addition to the I/O ports
available in each module, further I/O ports are available with interrupt capability allowing wake-up from
stop or wait modes.
The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications,
including:
• 3-phase sensorless BLDC motor control for
— Fuel pump
— Water pump
— Oil pump
— A/C compressor
— HVAC blower
— Engine cooling fan
— Electric vehicle battery cooling fan
• Brush DC motor control requiring driving in 2 directions, along with PWM control for
— Reversible wiper
— Trunk opener
1.2 Features
This section describes the key features of the MC9S12ZVM-Family. It documents the superset of features
within the family. Some module versions differ from one part to another within the family. Section 1.2.1
MC9S12ZVM-Family Member Comparison provides information to help access the correct information
for a particular part within the family.
RAM 32 KB 8 KB 8 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 2 KB 2 KB
Package 80 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 48 pin 64 pin 48 pin 64 pin 48 pin
LINPHY – 1 – 1 – 1 1 1 – – – –
HVPHY – – – – – – – – 1 1 1 1
SCI 2 2 2 2 2 2 2 2 2 2 2 2
SPI 1 1 1 1 1 1 1 0 1 0 1 0
ADC 8+8 4+5 4+5 4+5 4+5 4+5 4+5 1+3 4+5 1+3 4+5 1+3
channels
PMF 6 6 6 6 6 6 6 6 6 6 6 6
channels
TIM 4 TIM0 + 4 4 4 4 4 4 3 4 3 4 3
channels 2 TIM1
PWM 8 – – – – – – – – – – –
channels
MSCAN 1 1 1 1 1 1 – – – – – –
CAN 1 – 1 – 1 – – – – – – –
VREG
CANPHY 1 – – – – – – – – – – –
GDU Needed Needed Needed Needed Needed Needed Not Not Not Not Not Not
external Needed Needed Neede Neede Neede Neede
bootstrap d d d d
diode
Current 2 2 2 2 2 2 2 1 2 1 2 1
sense
op-amps
Auxiliary 2 – – – – – – – – – – –
tracker
VREGs
PIM V3 V2 V2 V2 V2 V2 V2 V2 V2
CPMU_UH V10 V6 V6 V6 V6 V6 V6 V6 V6
V
PMF V4 V3 V3 V3 V3 V3 V4 V4 V4
ADC V3 V1 V1 V1 V1 V1 V1 V1 V1
GDU low side driver state in HD over-voltage case on GOCA1 GOCA1 GOCA1
1.4.2.2 Flash
On-chip flash memory on the MC9S12ZVM-family on the features the following:
• Up to 256KB of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit fault correction
and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
1.4.2.3 EEPROM
• Up to 1K byte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
1.4.2.4 SRAM
• Up to 32 KB of general-purpose RAM with ECC
— Single bit error correction and double bit error detection
ADC0 AN0_[7:0]
5V Analog Supply 12-bit PAD[7:0]
VRH
VDDA/VSSA Analog-Digital Converter VRL
ADC1 AN1_[7:0]
12-bit
PTAD / KWAD
32K, 64K, 128K, 256KB Flash with ECC VRH PAD[15:8]
Analog-Digital Converter VRL
AMPP0
AMPM0
2K, 4K, 8K, 32KB RAM with ECC AMP0
PTP / KWP
PMF PWM1_0 PP0
DBG 15-bit 6 channel PWM1_1 PP1
Interrupt Module Debug Module Pulse Width Modulator PWM1_2
PP2
4 Comparators
BKGD BDC Trace Buffer PWM1_3
Background PWM1_4
Debug Controller PWM1_5
Clock Monitor TIM0 IOC0_0 PT0
PE0 EXTAL COP Watchdog
PTE
PTT
Real Time Interrupt
PE1 XTAL Oscillator IOC0_2 PT2
Auton. Periodic Int. IOC0_3 PT3
PLL with Frequency PTU PTURE
Modulation option Internal RC Oscillator
Programmable Trigger PTUT0
RESET Reset Generation Unit PTUT1
TEST and Test Entry
LINPHY0 (S12ZVML versions only) SCI1 RXD1
OR HV Physical Interface Asynchronous Serial IF TXD1
PTS / KWS
SCI0 RXD0
LIN0 LIN0 Asynchronous Serial IF TXD0
LGND LGND CAN0 RXCAN0 PS0
BCTLC CAN VREG msCAN 2.0B TXCAN0 PS1
VDDC PS2
SPI0 MISO0
CANH0 CANH0 MOSI0 PS3
SPLIT0 SPLIT0 SCK0 PS4
CANL0 CANL0 CANPHY0 Synchronous Serial IF PS5
SS0
VSSC VSSC PWM0 PWM0_[7,5,3,1]
8-bit, 8-channel
PTL/KWL
Size
Address Module
(Bytes)
Size
Address Module
(Bytes)
0x06E0–0x06EF Reserved 16
0x06F0–0x06F7 BATS 8
0x06F8–0x06FF Reserved 8
0x0700–0x0707 SCI0 8
0x0708–0x070F Reserved 8
0x0710–0x0717 SCI1 8
0x0718–0x077F Reserved 104
0x0780–0x0787 SPI0 8
0x0788–0x07FF Reserved 120
0x0800–0x083F CAN0 64
0x0840–0x097F Reserved 320
0x0980–0x0987 LINPHY (S12ZVML derivatives) 8
0x0980–0x0987 HV Physical Interface 8
(S12ZVM32, S12ZVM16 derivatives)
0x0988–0x098F Reserved 8
0x0990–0x0997 CANPHY (ZVMC256 only) 8
0x0998–0x0FFF Reserved 1640
1. Reading from the first 16 locations in this reserved range returns undefined data
NOTE
Reserved register space shown above is not allocated to any module. This
register space is reserved for future use. Writing to these locations has no
effect. Read access to these locations returns zero.
Register Space
0x00_0000
4 KB 0x00_1000
RAM
max. 1 MByte - 4 KB
0x10_0000
EEPROM
max. 1 MByte - 48 KB
Reserved 512 Byte 0x1F_4000
0x20_0000
Unmapped
6 MByte
0x80_0000
Program NVM
max. 8 MB
Unmapped
address range
Figure 1-2. MC9S12ZVM-Family Global Memory Map. (See Table 1-3 for individual device details)
Port L PL[0] — —
sum of ports 29 24 10
NOTE
To avoid current drawn from floating inputs, all non-bonded pins should be
configured as output or configured as input with a pull up or pull down
device enabled
1.7.2.22.2 ECLK
This signal is associated with the output of the bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.25.1 LIN0
On S12ZVML derivatives this pad is connected to the single-wire LIN data bus.
On the S12ZVM32 and S12ZVM16 derivatives this is a single pin bidirectional high voltage physical
interface. It operates in the VSUP voltage range. It can be connected to an external single-wire data bus.
1.7.2.25.2 LP0TXD
This is the LIN physical layer (or HV physical interface) transmitter input signal.
1.7.2.25.3 LP0RXD
This is the LIN physical layer (or HV physical interface) receiver output signal.
1.7.2.25.4 LP0DR1
This is the LIN (or HV physical interface) LP0DR1 register bit, visible at the designated pin for debug
purposes.
1.7.2.26.4 CPTXD0
This is the CAN physical layer transmitter input signal.
1.7.2.26.5 CPRXD0
This is the CAN physical layer receiver output signal.
1.7.2.26.6 CPDR0
This is the CAN physical layer direct control output signal.
1.7.2.26.7 BCTLC
BCTLC provides the base current of an external bipolar that supplies an external CAN physical interface.
This signal is only available on S12ZVMC versions. If not used BCTLC should be left unconnected.
1.7.3.1 VDDX1, VDDX2, VSSX1 — Digital I/O Power and Ground Pins
VDDX1, VDDX2 are voltage regulator outputs to supply the digital I/O drivers.
The VSSX1 pin is the ground pin for the digital I/O drivers.
Bypass requirements on VDDX2, VDDX1, VSSX1 depend on how heavily the MCU pins are loaded.
1.7.3.2 BCTL
BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external
bipolar for the VDDX and VDDA supplies. If not used BCTL should be left unconnected.
VDDX1
RESET
VSSX1
BKGD
VDDF
TEST
VSS1
VDD
PP0
PP1
PS0
PS1
PS2
PS3
PE0
PE1
PT3
PT2
PT1
PT0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSUP 1 60 HS1
VLS_OUT 2 59 HG1
CP 3 58 VBS1
VSSB 4 57 VLS1
BST 5 56 LG1
VCP 6 55 LS1
HD 7 54 LS2
PL0 8 53 LG2
BCTL 9 52 VLS2
SNPS1 10
S12ZVMC256 51 VBS2
BCTLS1 11 80-pin LQFP-EP 50 HG2
VDDS1 12 49 HS2
SNPS2 13 48 HS0
BCTLS2 14 Top view 47 HG0
VDDS2 15 46 VBS0
LD0 16 45 VLS0
LD1 17 44 LG0
LD2 18 43 LS0
PAD0 19 42 SPLIT0
PAD1 20 41 CANL0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BCTLC
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PAD8
VDDC
VSSC
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
VDDA
VSSA
PAD9
CANH0
VDDF
VSS1
HS1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LIN0 1 48 HG1
MODC / BKGD 2 47 VBS1
PTUT0 / (IOC0_1) / (LP0RXD) / RXCAN0 / RXD1 / KWS0 / PS0 3 46 VLS1
PTUT1 / (IOC0_2) / (LP0TXD) / TXCAN0 / TXD1 / KWS1 / PS1 4 45 LG1
MISO0 / (RXD1) / KWS2 / PS2 5 44 LS1
MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3 6 S12ZVML and S12ZVM 43 LS2
PDOCLK / SCK0 / KWS4 / PS4 7 option 42 LG2
PDO / SS0 / KWS5 / PS5 8 41 VLS2
64-pin LQFP-EP VBS2
BCTL 9 40
HD 10 39 HG2
VCP 11 38 HS2
BST 12 37 HS0
VSSB 13 36 HG0
CP 14 35 VBS0
VLS_OUT 15 34 VLS0
VSUP 16 33 LG0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDX2
VSS2
VDD
AN0_0 / AMP0 / KWAD0 / PAD0
VDDA
(SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6
VSSA
LS0
VRH / AN1_3 / KWAD8 / PAD8
TEST
Figure 1-4. S12ZVM and S12ZVML option 64-pin LQFP pin out
HD
BCTLC
VLS_OUT
BST
MODC / BKGD
VSUP
CP
VSSB
VCP
PDO / SS0 / KWS5 / PS5
PDOCLK / SCK0 / KWS4 / PS4
MISO0 / (RXD1) / KWS2 / PS2
PTUT1 / TXCAN0 / TXD1 / KWS1 / PS1
BCTL
MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3
PTUT0 / RXCAN0 / RXD1 / KWS0 / PS0
The exposed pad on the package bottom must be
connected to a grounded contact pad on the PCB.
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDDX2 17 64 VDDC
TEST 18 63 VSSX1
VSS2 19 62 VDDX1
VDD 20 61 PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ
AN0_0 / AMP0 / KWAD0 / PAD0 21 60 PP1 / KWP1 / (PWM0_1) / IRQ
AN0_1 / AMPM0 / KWAD1 / PAD1 22 59 PP2 / KWP2 / (PWM0_2)
AN0_2 / AMPP0 / KWAD2 / PAD2 23 58 VDDF
AN0_3 / KWAD3 / PAD3 24 57 VSS1
AN0_4 / KWAD4 / PAD4 25 56 PE0 / EXTAL
64-pin LQFP-EP
AN1_0 / AMP1 / KWAD5 / PAD5 55 PE1 / XTAL
S12ZVMC Option
26
(SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6 27 54 RESET
AN1_2 / AMPP1 / KWAD7 / PAD7 28 53 PT3 / IOC0_3 / (SS0)
VRH / AN1_3 / KWAD8 / PAD8 29 52 PT2 / IOC0_2 / (PWM0_5) / (SCK0)
VDDA 30 51 PT1 / IOC0_1 / (PWM0_4) / (MOSI0) / (TXD0) / PTURE
LS2
LS1
LG0
LG2
LG1
HS0
HS2
HG0
HG2
HG1
VLS0
VLS2
VLS1
VBS0
VBS2
VBS1
NXP Semiconductors
Chapter 1 Device Overview MC9S12ZVM-Family
RESET
VSSX1
LGND
VDDF
VSS1
HG1
HS1
48
47
46
45
44
43
42
41
40
39
38
37
LIN0 1 36 VBS1
MODC / BKGD 2 35 LG1
PTUT0 / (IOC0_1) / (LP0RXD) / RXD1 / KWS0 / PS0 3 34 LS1
PTUT1 / (IOC0_2) / (LP0TXD) / TXD1 / KWS1 / PS1 4 33 LS2
BCTL 5 S12ZVML and S12ZVM 32 LG2
HD 6 Options 31 VLS2
VCP 7 48-pin LQFP-EP 30 VBS2
BST 8 29 HG2
VSSB 9 28 HS2
CP 10 27 HS0
VLS_OUT 11 26 HG0
VSUP 12 25 VBS0
13
14
15
16
17
18
19
20
21
22
23
24
AN0_1 / AMPM0 / KWAD1 / PAD1
LS0
LG0
TEST
VSS2
VDD
VDDA
VSSA
Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 1 of 4)
Function
Internal Pull
LQFP Option (Priority and device dependencies specified in PIM
Resistor
chapter) Power
Supply
64
64 1st 2nd 3rd 4th 5th Reset
M/ 48 Pin CTRL
MC Func. Func. Func. Func. Func. State
ML
1 — 1 LIN0 — — — — — — — Up
(weak
)
— 1 — BCTLC — — — — — — — —
9 9 5 BCTL — — — — — — — —
10 10 6 HD — — — — — — — —
11 11 7 VCP — — — — — — — —
12 12 8 BST — — — — — — — —
13 13 9 VSSB — — — — — — — —
14 14 10 CP — — — — — — — —
15 15 11 VLS_OU — — — — — — — —
T
16 16 12 VSUP — — — — — VSUP — —
17 17 13 VDDX2 — — — — — VDDX — —
19 19 15 VSS2 — — — — — — — —
Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 2 of 4)
Function
Internal Pull
LQFP Option (Priority and device dependencies specified in PIM
Resistor
chapter) Power
Supply
64
64 1st 2nd 3rd 4th 5th Reset
M/ 48 Pin CTRL
MC Func. Func. Func. Func. Func. State
ML
20 20 16 VDD — — — — — VDD — —
32 32 23 LS0 — — — — — — — —
33 33 24 LG0 — — — — — — — —
34 34 — VLS0 — — — — — — — —
35 35 25 VBS0 — — — — — — — —
Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 3 of 4)
Function
Internal Pull
LQFP Option (Priority and device dependencies specified in PIM
Resistor
chapter) Power
Supply
64
64 1st 2nd 3rd 4th 5th Reset
M/ 48 Pin CTRL
MC Func. Func. Func. Func. Func. State
ML
36 36 26 HG0 — — — — — — — —
37 37 27 HS0 — — — — — — — —
38 38 28 HS2 — — — — — — — —
39 39 29 HG2 — — — — — — — —
40 40 30 VBS2 — — — — — — — —
41 41 31 VLS2 — — — — — — — —
42 42 32 LG2 — — — — — — — —
43 43 33 LS2 — — — — — — — —
44 44 34 LS1 — — — — — — — —
45 45 35 LG1 — — — — — — — —
46 46 — VLS1 — — — — — — — —
47 47 36 VBS1 — — — — — — — —
48 48 37 HG1 — — — — — — — —
49 49 38 HS1 — — — — — — — —
57 57 43 VSS1 — — — — — — — —
58 58 44 VDDF — — — — — VDDF — —
Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 4 of 4)
Function
Internal Pull
LQFP Option (Priority and device dependencies specified in PIM
Resistor
chapter) Power
Supply
64
64 1st 2nd 3rd 4th 5th Reset
M/ 48 Pin CTRL
MC Func. Func. Func. Func. Func. State
ML
62 62 46 VDDX1 — — — — — VDDX — —
63 63 47 VSSX1 — — — — — — — —
64 — 48 LGND — — — — — — — —
— 64 — VDDC — — — — — — — —
1. IOC signal only available on ZVML31, ZVM32 and ZVM16 on this pin.
Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 1 of 5)
1 VSUP — — — — — — VSUP — —
2 VLS_O — — — — — — VSUP — —
UT
3 CP — — — — — — — — —
4 VSSB — — — — — — — — —
5 BST — — — — — — — — —
6 VCP — — — — — — — — —
7 HD — — — — — — — — —
9 BCTL — — — — — — — — —
10 SNPS1 — — — — — — — — —
Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 2 of 5)
11 BCTLS — — — — — — — — —
1
13 SNPS2 — — — — — — — — —
14 BCTLS — — — — — — — — —
2
16 LD0 — — — — — — — — —
17 LD1 — — — — — — — — —
18 LD2 — — — — — — — — —
Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 3 of 5)
37 BCTLC — — — — — — — VDDC — —
38 VDDC — — — — — — — VDDC — —
39 CANH0 — — — — — — — VDDC — —
40 VSSC — — — — — — — VDDC — —
41 CANL0 — — — — — — — VDDC — —
42 SPLIT0 — — — — — — — VDDC — —
43 LS0 — — — — — — — — — —
44 LG0 — — — — — — — — — —
45 VLS0 — — — — — — — — — —
46 VBS0 — — — — — — — — — —
47 HG0 — — — — — — — — — —
Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 4 of 5)
48 HS0 — — — — — — — — — —
49 HS2 — — — — — — — — — —
50 HG2 — — — — — — — — — —
51 VBS2 — — — — — — — — — —
52 VLS2 — — — — — — — — — —
53 LG2 — — — — — — — — — —
54 LS2 — — — — — — — — — —
55 LS1 — — — — — — — — — —
56 LG1 — — — — — — — — — —
57 VLS1 — — — — — — — — — —
58 VBS1 — — — — — — — — — —
59 HG1 — — — — — — — — — —
60 HS1 — — — — — — — — — —
Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 5 of 5)
71 PS1 KWS1 TXD1 SCK0 PTUT1 CPDR0 TXCAN IOC0_2 VDDX PERS/ Up
0 PPSS
73 VDDF — — — — — — — VDDF — —
74 VSS1 — — — — — — — VDD — —
75 VDD — — — — — — — VDD — —
78 VDDX1 — — — — — — — VDDX — —
79 VSSX1 — — — — — — — VDDX — —
GND 2 1 BKGD
RST 4 3 PDO
VDDX 6 5 PDOCLK
the device enters either Stop or Pseudo Stop mode. Further to the general system aspects of Stop
mode discussed here, the motor control loop specific considerations are described in
Section 1.13.3.10.
— Pseudo-stop: In this mode the system clocks are stopped but the oscillator is still running and
the real time interrupt (RTI), watchdog (COP) and Autonomous Periodic Interrupt (API) may
be enabled. Other peripherals are turned off. This mode consumes more current than system
STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode
is significantly shorter.
— Stop: In this mode the oscillator is stopped and clocks are switched off. The counters and
dividers remain frozen. The autonomous periodic interrupt (API) may remain active but has a
very low power consumption. The key pad, SCI and MSCAN transceiver modules can be
configured to wake the device, whereby current consumption is negligible.
If the BDC is enabled in Stop mode, the VREG remains in full performance mode and the
CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all
clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and
BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks are disabled.
With the BDC enabled during Stop, the VREG full performance mode and clock activity lead
to higher current consumption than with BDC disabled. If the BDC is enabled in Stop mode,
then the BATS voltage monitoring remains enabled.
1.10 Security
The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized
that part of the security must lie with the application code. An extreme example would be application code
that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an
application has the capability of downloading code through a serial port and then executing that code (e.g.
an application containing bootloader code), then this capability could potentially be used to read the
EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this
example, the security of the application could be enhanced by requiring a response authentication before
any code can be downloaded.
Device security details are also described in the flash block description.
1.10.1 Features
The security features of the S12Z chip family are:
• Prevent external access of the non-volatile memories (Flash, EEPROM) content
• Restrict execution of NVM commands
This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for
security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a
reset sequence.
The meaning of the security bits SEC[1:0] is shown in Table 1-14. For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 1-14. Security Bits
NOTE
Please refer to the Flash block description for more security byte details.
1.11.1 Reset
Table 1-15. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 8,
“S12 Clock, Reset and Power Management Unit (V10 and V6)”.
CCR
Vector Address Reset Source Local Enable
Mask
Vector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No Yes
Vector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No Yes
Vector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No Yes
Vector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No Yes
Vector base + 0x1BC Reserved
to
Vector base + 0x1B0
Vector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2(TOI) No Yes
Vector base + 0x17C PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes
Vector base + 0x178
to Reserved
Vector base + 0x174
Vector base + 0x170 RAM error I bit EECIE (SBEEIE) No Yes
Vector base + 0x16C
to Reserved
Vector base + 0x168
Vector base + 0x164 FLASH error I bit FERCNFG (SFDIE) No Yes
Vector base + 0x160 FLASH command I bit FCNFG (CCIE) No Yes
Vector base + 0x15C CAN0 wake-up I bit CAN0RIER (WUPIE) Yes Yes
Vector base + 0x158 CAN0 errors I bit CAN0RIER (CSCIE, OVRIE) No Yes
Vector base + 0x154 CAN0 receive I bit CAN0RIER (RXFIE) No Yes
Vector base + 0x150 CAN0 transmit I bit CAN0TIER (TXEIE[2:0]) No Yes
Vector base + 0x14C
to Reserved
Vector base + 0x148
Vector base + 0x144 LINPHY over-current interrupt I bit LPIE (LPDTIE,LPOCIE) No Yes
Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) No Yes
Vector base + 0x13C GDU Desaturation Error I bit GDUIE (GDSEIE) No Yes
Vector base + 0x138 GDU Voltage Limit Detected I bit GDUIE (GOCIE, GHHDIE, No Yes
GLVLSIE)
Vector base + 0x134
to Reserved
Vector base + 0x12C
Vector base + 0x128 CAN Physical Layer I bit CPIE No Yes
(ZVMC256 Only) (CPVFIE, CPOCIE, CPDTIE)
Vector base + 0x124 Port S interrupt I bit PIES[5:0] Yes Yes
Vector base + 0x120 Reserved
Vector base + 0x11C ADC1 Error I bit ADC1EIE (IA_EIE, CMD_EIE, No Yes
EOL_EIE, TRIG_EIE,
RSTAR_EIE, LDOK_EIE)
ADC1IE(CONIF_OIE)
Vector base + 0x118 ADC1 conversion sequence abort I bit ADC1IE(SEQAD_IE) No Yes
Vector base + 0x114 ADC1 conversion complete I bit ADC1CONIE[15:0] No Yes
Vector base + 0x110 Reserved
Vector base + 0x10C Port P interrupt I bit PIEP[2:0] Yes Yes
Vector base + 0x108 EVDD1 over-current interrupt I bit PIEP(OCIE1) No Yes
Vector base + 0x104 Low-voltage interrupt (LVI) I bit CPMULVCTL (LVIE) No Yes
Vector base + 0x100 Autonomous periodical interrupt CPMUAPICTRL (APIE)
I bit Yes Yes
(API)
Vector base + 0xFC High temperature interrupt I bit CPMUHTCTL(HTIE) No Yes
Vector base + 0xF8 VDDS integrity interrupt I bit CPMULVCTL(VDDSIE) No Yes
Vector base + 0xF4 Port AD interrupt I bit PIEADH(PIEADH0) Yes Yes
PIEADL(PIEADL[7:0])
Vector base + 0xF0 PTU Reload Overrun I bit PTUIEH(PTUROIE) No Yes
Vector base + 0xEC PTU Trigger0 Error I bit PTUIEL(TG0AEIE, No Yes
TG0REIE,TG0TEIE)
Vector base + 0xE8 PTU Trigger1 Error I bit PTUIEL(TG1AEIE, TG1REIE, No Yes
TG1TEIE)
Vector base + 0xE4 PTU Trigger0 Done I bit PTUIEL(TG0DIE) No Yes
Vector base + 0xE0 PTU Trigger1 Done I bit PTUIEL(TG1DIE) No Yes
Vector base + 0xDC
to Reserved
Vector base + 0xD4
Vector base + 0xD0 PMF Reload A I bit PMFENCA(PWMRIEA) No Yes
Vector base + 0xCC PMF Reload B I bit PMFENCB(PWMRIEB) No Yes
Vector base + 0xC8 PMF Reload C I bit PMFENCC(PWMRIEC) No Yes
Vector base + 0xC4 PMF Fault I bit PMFFIE(FIE[5:0]) No Yes
Vector base + 0xC0 PMF Reload Overrun I bit PMFROIE(PMFROIEA,PMF No Yes
ROIEB,PMFROIEC)
Vector base + 0xBC Port L interrupt I bit PIEL(PIEL0) Yes Yes
(ZVMC256 Only)
Vector base + 0xB8 Reserved
to
Vector base + 0xB0
Vector base + 0xAC TIM1 timer channel 0 I bit TIM1TIE (C0I) No Yes
(ZVMC256 Only)
Vector base + 0xA8 TIM1 timer channel 1 I bit TIM1TIE (C1I) No Yes
(ZVMC256 Only)
Vector base + 0xA4 Reserved
to
Vector base + 0x90
Vector base + 0x8C TIM1 timer overflow I bit TIM1TSCR2(TOI) No Yes
(ZVMC256 Only)
Vector base + 0x88
to Reserved
Vector base + 0x10
1. 15 bits vector address based
is in progress, that command will be immediately aborted. The state of the word being programmed or the
sector/block being erased is not guaranteed.
The system RAM arrays, including their ECC syndromes, are initialized following a power on reset. All
other RAM arrays are not initialized out of any type of reset. With the exception of a power-on-reset the
RAM content is unaltered by a reset occurrence.
The power on reset sequence including flash and SRAM initialization is shown in Figure 1-8
Figure 1-8. Device Power On Reset Sequence
Vsup
reset sequence. The GSUF bit in the GDUF register is also loaded during the reset sequence. See Table 1-
17, Table 1-18 and Table 1-19.
Table 1-17. Initial COP Rate Configuration
NV[2:0] in CR[2:0] in
FOPT Register CPMUCOP Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
NV[3] in WCOP in
FOPT Register CPMUCOP Register
1 0
0 1
The EPRES bit was only included in early mask sets but was not usable. The implementation of
GDUCTR1 register bits is also mask set dependent as shown in Table 1-19.
StoredReference
V RH = ------------------------------------------------------- 5V
ConvertedReference
StoredReference 5V
Result = ConvertedADInput -----------------------------------------------------------------n-
ConvertedReference 2
With:
ConvertedADInput: Result of the analog to digital conversion of the desired
pin
ConvertedReference: Result of internal channel conversion
TIM0
OC0
GDU
commutation_event zero crossing
comparators
GPHS
SENSOR
PMF
dc_bus_current
async reload
reload
dc_bus_voltage
PHMUX
PTU async reload
ADC0 P1
reload back-EMF P2
P3
If PTU enabled
If PTU enabled
glb_ldok
trigger_0
ADC1
async reload
reload
trigger_1
reload
The control loop consists of the PMF, GDU, ADC and PTU modules. The control loop operates using
either static, dynamic or asynchronous timing. In the following text the event names given in bold type
correspond to those shown in Figure 1-9. The PTU and ADC operate using lists stored in memory. These
lists define trigger points for the PTU, commands for the ADC and results from the ADC. If the PTU is
enabled the reload and async_reload events are immediately passed through to the ADC and GDU
modules.
2. PMF events reloadb and reloadc are not connected at device level
Each control loop cycle is started by a PMF reload event. The PMF reload event restarts the PTU time
base. If the PTU is enabled, the reload is immediately passed through to the ADC and GDU modules.
The PMF generates the reload event at the required PWM reload frequency. The PMF reload event causes
the PTU time base to restart, to acquire the first trigger times from the list and the ADCs to start loading
the ADC conversion command from the Command Sequence List (CSL).
NOTE
In the PTU there is time window after the reload event assertion before the
first trigger is permitted. This time can be up to 10 bus cycles.
Subsequent triggers also require a load time of 6 bus clock cycles (one
trigger generator enabled) or 10 bus clock cycles (both trigger generators
enabled). This defines the minimal spacing between triggers without
causing a PTU trigger generator timing error.
In the ADC there is 10 bus cycle maximum time window after the reload
event assertion to access the first ADC command from the list. In this
window the ADC conversion can not be started. If the measurement is
control loop related these delays are negligible due to much larger delays in
the PWM-GDU-feedback loop.
When the trigger time is encountered the corresponding PTU trigger generates the trigger_x event for the
associated ADC. For simultaneous sampling the PTU generates simultaneous trigger_x events for both
ADCs. At the trigger_x event the ADC starts the first conversion of the next conversion sequence in the
CSL (the first ADC command is already downloaded).
A commutation event is used by the PMF to generate an async_reload event. The async_reload is used by
the PTU to update lists and re-initialize the trigger lists. If the PTU is enabled the async_reload is
immediately passed through to the ADC.
PWM base
PWM with
deadtime
TDEAD_x
GDU
propagation
tdelon
FET
turn on
tHGON
Current sense
settling time
(tcslsst)
ADC delay
The PWM deadtime (TDEAD_X) is an integral number of bus clock cycles, configured by the PMF
deadtime registers.
The GDU propagation delays (tdelon, tdeloff) are specified in the electrical parameter Table E-1.
The FET turn on times (tHGON) are load dependent but are specified for particular loads in the electrical
parameter Table E-1.
The current sense amplifier delay is highly dependent on external components.
The ADC delay until a result is available is specified as the conversion period NCONV in Table C-1.
trigger through the control loop or can prevent propagation so the static timing of the control cycle and
inter-block coherency are not affected by the trigger.
At the end of the conversion sequence the first ADC command from the new sequence is loaded and the
ADCx waits for the next trigger_x. The PTU continues to generate the trigger_x events for each trigger
time from the list until a new reload or async_reload occurs.
Before the upcoming reload event the CPU:
• reads the ADC results from the buffered Conversion Result List
• clears the conversion complete flag
• services the reload by setting new duty cycle values
• sets the PTULDOK bit (corresponding to glb_ldok) to signal the duty cycle coherence
The CPU actions are typically performed in an ISR triggered by the conversion complete flag.
The DC Brushed motor power stage topology is a classical full bridge as shown in Figure 1-11. The DC
Brushed motor is driven by the DC voltage source. A rotational field is created by means of commutator
and brushes on the motor. These drives are still very popular because sophisticated calculations and
algorithms such as commutation, waveform generation, or space vector modulation are not required.
Figure 1-11. DC Brushed Motor External Configuration
+ 1/2 U
PWM PWM
0 2
A B
PWM PWM
1 3
- 1/2 U
Usually the control consists of an outer, speed control loop with inner current (torque) control loop. The
inner loop controls DC voltage applied onto the motor winding. The control loop is calculated regularly
within a given period. In most cases, this period matches the PWM reload period.
Driving the DC motor from a DC voltage source, the motor can work in all four quadrants. The
complementary mode of operation with deadtime insertion is needed for smooth reversal of the motor
current (motor torque), hence smooth full four quadrant control. Usually the center-aligned PWM is
chosen to lower electromagnetic emissions.
Figure 1-12. BDCM Control Loop Configuration
GDU
PMF dc_bus_voltage
M
sine/
cosine
sensor
dc_bus_current0
reloada
reload
glb_ldok
trigger_0
PTU
ADC0
trigger_1
reload
ADC1
The PWM frequency selection is always a compromise between audible noise, electromagnetic emissions,
current ripples and power switching losses.
The BDCM control loop goal is to provide a controlled DC voltage to the motor winding, whereby it is
controlled cycle-by-cycle using a speed, current or torque feedback loop.
The center aligned PWM waveforms generated by the PMF module are applied to the bridge as shown in
Figure 1-13 whereby the base waveform for PWM0_0 and PWM0_1 is depicted at the top and the
complementary PWM0_0 and PWM0_1 waveforms are shown with deadtime insertion depicted by the
gray phases before the switching edges.
PWM0_0 PWM0_2
PWM0_1 PWM0_3
Assuming first quadrant operation, forward accelerating operation, the applied voltage at node A must
exceed the applied voltage at node B (Figure 1-11). Thus the PWM0_0 duty cycle must exceed the
PWM0_2 duty cycle.
The duty cycle of PWM0_0 defines the voltage at the first power stage branch.
The duty cycle of PWM0_2 defines the voltage at the second power stage branch.
Modulating the duty cycle every period using the function FPWM then the duty cycle is expressed as:
PWM0_0 duty-cycle = 0.5 + (0.5 * FPWM); For -1<=FPWM <= 1;
PWM0_2 duty-cycle = 0.5 - (0.5 * FPWM)
reload async_reload
PTU
glb_ldok
trigger_0
dc_bus_current
async_reload
reload ADC0
This BLDC application uses Hall sensor signals to create commutation triggers. The integrated sense
amplifier and an ADC module are used to measure DC bus current, for torque calculation. The DC bus
voltage measurement is used in the control algorithm to counter-modulate the PWM such that the variation
of the DC-bus voltage does not affect the motor current closed loop. The configuration is as follows:
1. Connect the three Hall sensor signals from the motor to input pins PT3-1.
2. Set [T0IC1RR=1] in the register MODRR2 to establish the link from Hall sensor input pins to TIM
input capture channel 1.
3. Setup TIM IC1 for speed measurement of XORed Hall sensor signals. Enable interrupt on both
edges.
4. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=01.
5. Configure PMF for edge-aligned PWM mode with or without restart at commutation:
PMFENCx[RSTRT]. If using the restart option, then select generator A as reload signal source and
keep the following configurations at their default setting: multi timebase generators
(PMFCFG0[MTG]=b0), reload frequency (PMFFQCx[LDFQx]=b0), prescaler
(PMFFQCx[PRSCx]=b00).
6. Enable PMF commutation event input: PMFCFG1[ENCE]=1.
GDU
TIM0 zero crossing
comparators
GPHS
OC0
commutation_event dc_bus_voltage
PMF M
dc_bus_current0
dc_bus_current1
reloada async_reload
reload async_reload
PHMUX
P1
back-EMF P2
glb_ldok P3
trigger_0
PTU
ADC0
trigger_1
async_reload
reload ADC1
To calculate the commutation time in a sensorless motor system the back-EMF zero crossing event of the
currently non-fed phase within an electrical rotation cycle must be determined. For fast motor rotation, the
ADC is used to measure the back-EMF voltage and the DC bus voltage to determine the zero crossing time.
For slow motor rotation the GPHS register can be polled. In either case the zero crossing event is handled
by the CPU monitoring flags or responding to interrupts. The TIM then generates the commutation_event
under CPU control, based on the zero crossing time.
1. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=0b01.
2. Enable PMF commutation event input: PMFCFG1[ENCE]=0b1.
3. Enable internal ADC channel for measuring the phase voltages from the muxed GDU outputs.
4. Align rotor to stator field. Initialize phase MUX using register GDUPHMUX.
5. Startup motor by applying PWM to an arbitrary motor phase.
6. Take samples of the phase voltages periodically based on PWM cycle to detect zero crossing.
7. Calculate the delay to next commutation and store value to output compare register. Update
registers with next values of mask and swap.
8. On next output compare event the buffered mask and swap information are transferred to the active
PMF register to execute the commutation.
dc_bus_current0
dc_bus_current1
reloada
reload
glb_ldok
trigger_0
PTU
ADC0
trigger_1
reload ADC1
dc_bus_current0
dc_bus_current1
sine/cosine
sensor
reload
glb_ldok
trigger_0
PTU
ADC0
trigger_1
reload ADC1
GHHDF INT
VLINSUP
LINPHY BATS
GFDE LDO
BOOST
(OPT L) VCP
LIN ADC INT
(OPT C) LG VRBATP
BCTLC
5V
1.8V 2.8V LS
VDDC (OPT C) GDU
(5V) BCTL
PORF RES
VDD
LVRF RES
VDDF VDDX
VDDA
VDDA
PADS
VRH CORE
PAD8 VRL_SEL RAM’s
ADC FLASH GPIO
VRH_SEL PLL
VRL IRC
VSSA
OSC
VSSA VSSX
VSS
The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected
against reverse battery connections and must not be connected directly to the battery voltage (VBAT).
The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO,
which generates the voltages VDDX, VDD and VDDF. The VDDX domain supplies the device I/O pins,
VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be
connected at board level, they are not connected directly internally. ESD protection diodes exist between
VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal
device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.
The device supports the use of an external PNP to supplement the VDDX supply, for reducing on chip
power dissipation. In this configuration, most of the current flowing from VRBATP to VDDX, flows
through the external PNP. This configuration, using the BCTL pin, can be enabled by register bits
EXTXON and INTXON.
The maximum current that can be sourced by the voltage regulator without the external PNP is specified
as IDDX, for different VSUP ranges, in the electrical parameter appendices. Depending on activity and
external loading, an application current may exceed this specification limit. In such cases the external PNP
configuration must be used.
A supply for an external CANPHY is offered via external device pins BCTLC and VDDC, whereby
BCTLC provides the base current of an external PNP and VDDC is the CANPHY supply (output voltage
of the external PNP). This is only available in the CANPHY package option. This configuration can be
enabled by the register bit EXTCON. An external diode is recommended between VDDC and VDDA.
The LINPHY pull-up resistor is internally connected to VLINSUP.
The ADC register bit VRH_SEL maps the ADC reference VRH to VDDA or to the device pin PAD8.
BCTLC
BATS
GFDE LDO
VDDC BOOST
VRBATP VCP
ADC INT
VSSC
GBOE CPS
CANPHY GCPE CP
INTXON
EXTCON EXTXON VLS_OUT
(11V)
BCTLS1
INT GLVLSF
5V VREG_AUTO VLS
SNPS1
VDDS1 5V LG
VRBATP
5V
1.8V 2.8V LS
GDU VRBATP
BCTLS2
SNPS2
VDDS2 5V
BCTL
VDD RES
PORF RES LVRF
VDDF VDDX
VDDA
VDDA
PADS
VRH CORE
VRL_SEL RAM’s
ADC FLASH GPIO
VRH_SEL PLL
VRL IRC
VSSA
OSC
VSSA VSSX
VSS
The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected
against reverse battery connections and must not be connected directly to the battery voltage (VBAT).
The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO,
which generates the voltages VDDX, VDD and VDDF. The VDDX domain supplies the device I/O pins,
VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be
connected at board level, they are not connected directly internally. ESD protection diodes exist between
VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal
device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.
The device supports the use of an external PNP to supplement the VDDX supply, for reducing on chip
power dissipation. In this configuration, most of the current flowing from VRBATP to VDDX, flows
through the external PNP, using the BCTL pin for PNP base current control. The configuration can be
selected by register bits EXTXON and INTXON.
The maximum current that can be sourced by the voltage regulator without the external PNP is specified
as IDDX, for different VSUP ranges, in the electrical parameter appendices. Depending on activity and
external loading, an application current may exceed this specification limit. In such cases the external PNP
configuration must be used.
A supply for the internal CANPHY is offered via device pins BCTLC and VDDC, whereby BCTLC
provides the base current of an external PNP and VDDC is the CANPHY supply (output voltage of the
external PNP). This configuration can be enabled by the register bit EXTCON.
Two separate 5V range supplies (VDDS1 and VDDS2) are provided for external (sensor) components.
These supplies also use external PNP configurations, whereby the PNP base current is controlled by
BCTLS1 and BCTLS2 for VDDS1 and VDDS2 respectively.
The VDDS1 and VDDS2 supplies feature sense inputs SNPS1 and SNPS2, to detect a short circuit or over
current condition and subsequently limit the current to avoid damage.
For each ADC instantiation, the ADC register bit VRH_SEL maps the ADC reference VRH to VDDA or
to a VDDS of a tracker regulator. The Figure 1-19 example only shows one ADC to VDDS connection.
the capacitor CBS is first charged to VLS_OUT via an external diode (GDUV4) or internal transistor
(GDUV5), when the low side driver is active Figure 1-20. When the high side driver switches on, the
charge on this capacitor, supplies the FET-predriver via the VBSx pin. The CBS capacitor can only be
charged if the low side driver is active, so after a long period of inactivity of the low side driver, the CBS
capacitor becomes discharged. In this case, the low side driver must be switched on to charge CBS before
commencing high side driving. The time it takes to discharge the bootstrap capacitor CBS can be calculated
from the size of the bootstrap capacitor CBS and the current on VBSx pin in the high side inactive phase.
The bootstrap capacitors must be precharged before turning on the high-side drivers for the first time. This
can be done by using the PMF software output control mechanism:
PMFOUTC = 0x3F; // SW control on all outputs
PMFOUTB = 0x2A; // All high-sides off, all low-sides on
The PWM0 signals should be configured to start with turning on the low-side before the high-side drivers
in order to assure precharged bootstraps. Therefore invert the PWM0 signals:
PMFCINV = 0x3F; // Invert all channels to precharge bootstraps
The GDU high side drain voltage, pin HD, is supplied from VBAT through a reverse battery protection
circuit. In a typical application the charge pump is used to switch on an external NMOS, N1, with source
connected to VBAT, by generating a voltage of VBAT+VLS-(2xVdiode). In a reverse battery scenario, the
external bipolar turns on, ensuring that the HD pin is isolated from VBAT by the external NMOS, N1.
VBAT S
N1
D
VLS_OUT (11V)
1nF
10nF
CP
11V
GCPCD 0V
HD
1000F
VBSx (Motor Dependent)
CBS
HGx
HIGH SIDE
HSx
LOW SIDE
V03.18 12 Dec 2015 2.3.2.3/128 • Added bit description for T1IC0RR (MODRR2 register)
2.1 Introduction
2.1.1 Overview
The S12ZVM-family port integration module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
• Port E
External
GPIO Pins
Oscillator
• Port T
LINPHY0/
GPIO PWM01 TIM0 PMF SPI0 SCI0 HVPHY0 PTU Pins
• Port S
GPIO/ LINPHY0/
KWU DBG SCI1 CAN01 CANPHY04 HVPHY0 TIM1 TIM0 PTU SPI0 DBG Pins
1. Only available for ZVMC256, ZVMC128, ZVML128, ZVMC64, ZVML64, and ZVML32
2. Only available for ZVMC128, ZVML128, ZVMC64, ZVML64, and ZVML32
3. Not available for ZVMC256
4. Only available for ZVMC256
5. Only available for ZVML128, ZVML64, ZVML32, ZVML31, ZVM32, and ZVM16
6. Only available for ZVMC256, ZVML31, ZVM32, and ZVM16
• Port P
GPIO/KWU PWM01 PMF ECLK PMF fault IRQ/XIRQ Pins
• Port L
HVI TIM0 Pins
• Port AD
GPIO/KWU ADC1 ADC0 SPI0 GDU PTU DBG Pins
Most I/O pins can be configured by register bits to select data direction and to enable and select pullup or
pulldown devices.
NOTE
This document shows the superset of all available features offered by the
S12ZVM device family. Refer to the package and pinout section in the
device overview for functions not available for a particular device or
package option.
2.1.2 Features
The PIM includes these distinctive registers:
• Data registers and data direction registers for ports E, T, S, P and AD when used as general-purpose
I/O
• Control registers to enable pull devices and select pullups/pulldowns on ports E, T, S, P and AD
• Control register to enable open-drain (wired-or) mode on port S
• Control register to enable digital input buffers on port AD and L1
• Interrupt enable register for pin interrupts and key-wakeup (KWU) on port S, P, AD, and L1
• Interrupt flag register for pin interrupts andkey-wakeup (KWU) on port S, P, AD, and L1
• Control register to configure IRQ pin operation
• Control register to enable ECLK output
• Routing registers to support signal relocation on external pins and control internal routings:
— SPI0 to alternative pins
— Various SCI0-LINPHY0 routing options supporting standalone use and conformance testing2
— Various MSCAN0-CANPHY0 routing options for standalone use and conformance testing1
— Internal RXD0 and RXD1 link to TIM0 input capture channel (IC0_3) for baud rate detection
— Internal ACLK link to TIM0 input capture channel
— 3 pin input mux to one TIM0 IC channel
— 2 TIM0 channels to alternative pins3
— PMF channels to GDU and/or pins
A standard port pin has the following minimum features:
• Input/output selection
• 5V output drive
• 5V digital and analog input
• Input with selectable pullup or pulldown device
Optional features supported on dedicated pins:
• Open drain for wired-or connections
• Interrupt input with glitch filtering
• High current drive strength from VDDX with over-current protection
1. Only available for ZVMC256
2. Only available for ZVML128, ZVML64, ZVML32, and ZVML31
3. Only available for S12ZVMC256, S12ZVML31, S12ZVM32, and S12ZVM16
ZVM32/16
ZVMC256
ZVML31
ZVM32/16
ZVMC256
ZVML31
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVML128/64/32
ZVMC128\64
ZVM32/16
ZVMC256
ZVML31
Pin Pin Function Routing Pin Function
Port I/O Description
Name & Priority1 Register Bit after Reset
ZVM32/16
ZVMC256
ZVML31
R 0 0
0x0200 MODRR0 SPI0SSRR SPI0RR SCI1RR S0L0RR2-01
W
R
0x0201 MODRR1 M0C0RR2-02 PWMPRR1-03 PWM54RR PWM32RR PWM10RR
W
R
0x0202 MODRR2 T0C2RR1-04 T0C1RR4 T1IC0RR2 T0IC3RR1-0 T0IC1RR T0IC1RR0
4
W
0x0203– R 0 0 0 0 0 0 0 0
Reserved
0x0207 W
R 0 0 0 0 0 0 0
0x0208 ECLKCTL NECLK
W
R 0 0 0 0 0 0
0x0209 IRQCR IRQE IRQEN
W
R 0 0 0 0 0 0 0
0x020A PIMMISC OCPE1
W
0x020B– R 0 0 0 0 0 0 0 0
Reserved
0x020C W
R
0x020D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x020E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0210– R 0 0 0 0 0 0 0 0
Reserved
0x025F W
R 0 0 0 0 0 0
0x0260 PTE PTE1 PTE0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R 0 0 0 0 0 0 0 0
0x0261 Reserved
W
R 0 0 0 0 0 0 PTIE1 PTIE0
0x0262 PTIE
W
R 0 0 0 0 0 0 0 0
0x0263 Reserved
W
R 0 0 0 0 0 0
0x0264 DDRE DDRE1 DDRE0
W
R 0 0 0 0 0 0 0 0
0x0265 Reserved
W
R 0 0 0 0 0 0
0x0266 PERE PERE1 PERE0
W
R 0 0 0 0 0 0 0 0
0x0267 Reserved
W
R 0 0 0 0 0 0
0x0268 PPSE PPSE1 PPSE0
W
0x0269– R 0 0 0 0 0 0 0 0
Reserved
0x027F W
R
0x0280 PTADH PTADH72 PTADH62 PTADH52 PTADH42 PTADH32 PTADH22 PTADH12 PTADH0
W
R
0x0281 PTADL PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R
0x0284 DDRADH DDRADH72 DDRADH62 DDRADH52 DDRADH42 DDRADH32 DDRADH22 DDRADL12 DDRADH0
W
R
0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0
W
R
0x0286 PERADH PERADH72 PERADH62 PERADH52 PERADH42 PERADH32 PERADH22 PERADH12 PERADH0
W
R
0x0287 PERADL PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0
W
R
0x0288 PPSADH PPSADH72 PPSADH62 PPSADH52 PPSADH42 PPSADH32 PPSADH22 PPSADH12 PPSADH0
W
R
0x0289 PPSADL PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0
W
0x028A– R 0 0 0 0 0 0 0 0
Reserved
0x028B W
R
0x028C PIEADH PIEADH72 PIEADH62 PIEADH52 PIEADH42 PIEADH32 PIEADH22 PIEADH12 PIEADH0
W
R
0x028D PIEADL PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0
W
R
0x028E PIFADH PIFADH72 PIFADH62 PIFADH52 PIFADH42 PIFADH32 PIFADH22 PIFADH12 PIFADH0
W
R
0x028F PIFADL PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0
W
0x0290– R 0 0 0 0 0 0 0 0
Reserved
0x0297 W
R
0x0298 DIENADH DIENADH72 DIENADH62 DIENADH52 DIENADH42 DIENADH32 DIENADH22 DIENADH12 DIENADH0
W
R
0x0299 DIENADL DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x029A– R 0 0 0 0 0 0 0 0
Reserved
0x02BF W
R 0 0 0 0
0x02C0 PTT PTT3 PTT2 PTT1 PTT0
W
R 0 0 0 0
0x02C2 DDRT DDRT3 DDRT2 DDRT1 DDRT0
W
R 0 0 0 0
0x02C3 PERT PERT3 PERT2 PERT1 PERT0
W
R 0 0 0 0
0x02C4 PPST PPST3 PPST2 PPST1 PPST0
W
0x02C5– R 0 0 0 0 0 0 0 0
Reserved
0x02CF W
R 0 0
0x02D0 PTS PTS55 PTS45 PTS3 PTS2 PTS1 PTS0
W
R 0 0
0x02D2 DDRS DDRS55 DDRS45 DDRS3 DDRS2 DDRS1 DDRS0
W
R 0 0
0x02D3 PERS PERS55 PERS45 PERS3 PERS2 PERS1 PERS0
W
R 0 0
0x02D4 PPSS PPSS55 PPSS45 PPSS3 PPSS2 PPSS1 PPSS0
W
R 0 0 0 0 0 0 0 0
0x02D5 Reserved
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R 0 0
0x02D6 PIES PIES55 PIES45 PIES3 PIES2 PIES1 PIES0
W
R 0 0
0x02D7 PIFS PIFS55 PIFS45 PIFS3 PIFS2 PIFS1 PIFS0
W
0x02D8– R 0 0 0 0 0 0 0 0
Reserved
0x02DE W
R 0 0
0x02DF WOMS WOMS55 WOMS45 WOMS3 WOMS2 WOMS1 WOMS0
W
0x02E0– R 0 0 0 0 0 0 0 0
Reserved
0x02EF W
R 0 0 0 0 0
0x02F0 PTP PTP25 PTP1 PTP0
W
R 0 0 0 0 0
0x02F2 DDRP DDRP25 DDRP1 DDRP0
W
R 0 0 0 0 0
0x02F3 PERP PERP25 PERP1 PERP0
W
R 0 0 0 0 0
0x02F4 PPSP PPSP25 PPSP1 PPSP0
W
R 0 0 0 0 0 0 0 0
0x02F5 Reserved
W
R 0 0 0 0
0x02F6 PIEP OCIE1 PIEP25 PIEP1 PIEP0
W
R 0 0 0 0
0x02F7 PIFP OCIF1 PIFP25 PIFP1 PIFP0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x02F8– R 0 0 0 0 0 0 0 0
Reserved
0x02FC W
R 0 0 0 0 0 0 0
0x02FD RDRP RDRP0
W
0x02FE– R 0 0 0 0 0 0 0 0
Reserved
0x0330 W
R 0 0 0 0 0 0 0 PTIL0
0x0331 PTIL2
W
R 0 0 0 0 0 0 0 0
0x0332 Reserved
W
R 0 0 0 0 0 0 0
0x0333 PTPSL2 PTPSL0
W
R 0 0 0 0 0 0 0
0x0334 PPSL2 PPSL0
W
R 0 0 0 0 0 0 0 0
0x0335 Reserved
W
R 0 0 0 0 0 0 0
0x0336 PIEL2 PIEL0
W
R 0 0 0 0 0 0 0
0x0337 PIFL2 PIFL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x0338– R 0 0 0 0 0 0 0 0
Reserved
0x0339 W
R 0 0 0 0 0 0 0
0x033A PTABYPL2 PTABYPL0
W
R 0 0 0 0 0 0 0
0x033B PTADIRL2 PTADIRL0
W
R 0 0 0 0 0 0 0
0x033C DIENL2 DIENL0
W
R 0 0 0 0 0 0 0
0x033D PTAENL2 PTAENL0
W
R 0 0 0 0 0 0 0
0x033E PIRL2 PIRL0
W
R 0 0 0 0 0 0 0
0x033F PTTEL2 PTTEL0
W
7 6 5 4 3 2 1 0
R 0 0
SPI0SSRR SPI0RR SCI1RR S0L0RR2-02
W
Reset 0 0 0 0 0 0 0 0
Field Description
1 SS0 on PAD6
0 SS0 based on SPI0RR
PS1 / LPTXD0
LINPHY0/
SCI0 HVPHY0
1
0 0
TXD0 LPTXD0
1
LPDR1
LIN
0
RXD0 LPRXD0
1
0
T0IC3RR1-0
1
01 PS0 / LPRXD0
10 RXD1
11 ACLK
TIM0 input PT0 / RXD0
capture 00 PT3
channel 3
NOTE
For standalone usage of SCI0 on external pins set
[S0L0RR2:S0L0RR0]=0b110 and disable the LINPHY0/HVPHY0
(LPCR[LPE]=0). This releases PS0 and PS1 to other associated functions
and maintains TXD0 and RXD0 signals on PT1 and PT0, respectively, if no
other function with higher priority takes precedence.
7 6 5 4 3 2 1 0
R
M0C0RR2-02 PWMPRR1-03 PWM54RR PWM32RR PWM10RR
W
Reset 0 0 0 0 0 0 0 0
Field Description
11 PMF channels 1, 3, 5 connected to related PWM1_x pins (only available for ZVMC256)
10 PMF channels 0, 2, 4 connected to related PWM1_x pins (only available for ZVMC256)
01 All PMF channels connected to related PWM1_x pins
00 No PMF channels connected to related PWM1_x pins
0
1
TXCAN0/CPDR1
CPTXD0
1
0 0
TXCAN CPTXD
1
CPDR1 CANH
CANL
0
RXCAN CPRXD
1
0
1 CPRXD0
RXCAN0
M0C0RR[2:0] Description
NOTE
For standalone usage of MSCAN0 on external pins set
M0C0RR[2:0]=0b110 and disable CANPHY0 (CPCR[CPE]=0). This
releases the CANPHY0 associated pins to other shared functions.
7 6 5 4 3 2 1 0
R
T0C2RR1-02 T0C1RR2 T1IC0RR3 T0IC3RR1-0 T0IC1RR T0IC1RR02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7-6 Module Routing Register — TIM0 IOC0_2 routing (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
T0C2RR1-0
11 reserved
101 TIM0 IC0_2 is routed to the HVI, OC0_2 is disconnected from GPIO
01 TIM0 IOC0_2 is routed to PS1
00 TIM0 IOC0_2 is routed to PT2
5 Module Routing Register — TIM0 IOC0_1 routing (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
T0C1RR
1 TIM0 IOC0_1 is routed to PS0
0 TIM0 IOC0_1 is routed to PT1
Field Description
1 TIM0 input capture channel 1 is connected to logically XORed input signals of pins PT3-1
0 TIM0 input capture channel 1 is connected to PT1 or to pin selected by T0C1RR0 (if available)
0 Module Routing Register — TIM0 IC1 routing option 0 (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
T0IC1RR0
Timer input capture channel 1 can be used to determine the asynchronous commutation event in BLDC motor
applications with Hall sensors. An integrated XOR gate supports direct connection of the three sensor inputs to
the device.
Note: This bit takes precedence over T0C1RR and T0IC1RR.
1 TIM0 input capture channel 1 is connected to logically XORed input signals of pins PT0, PS0 and PS1
0 TIM0 input capture channel 1 is connected to pin selected by T0IC1RR
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
NECLK
W
Reset: 1 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
IRQE IRQEN
W
Reset 0 0 0 0 0 0 0 0
Field Description
6 IRQ enable —
IRQEN
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
OCPE1
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
1. Read: Anytime
Write: Only in special mode.
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
: 7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
NOTE
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
7 6 5 4 3 2 1 0
R
PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard port data registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Table 2-17. Port Data Register Field Descriptions
Field Description
7 6 5 4 3 2 1 0
Reset - - - - - - - -
This is a generic description of the standard port input registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Table 2-18. Port Input Register Field Descriptions
Field Description
7 6 5 4 3 2 1 0
R
DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard data direction registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Field Description
Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct
value is read on port data and port input registers, when changing the data direction register.Eqn. 0-1
7 6 5 4 3 2 1 0
R
PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0
W
Reset
Ports E: 0 0 0 0 0 0 1 1
Ports S: 0 0 12 12 1 1 1 1
Others: 0 0 0 0 0 0 0 0
This is a generic description of the standard pull device enable registers. Refer to Table 2-39 to determine
the implemented bits in the respective register. Unimplemented bits read zero.
Field Description
7 6 5 4 3 2 1 0
R
PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0
W
Reset
Ports E: 0 0 0 0 0 0 1 1
Others: 0 0 0 0 0 0 0 0
This is a generic description of the standard polarity select registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Table 2-21. Polarity Select Register Field Descriptions
Field Description
7-0 Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin
PPSx7-0
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
If a port has interrupt functionality this bit also selects the polarity of the active edge.
If MSCAN is active a pullup device can be activated on the RXCAN input; attempting to select a pulldown disables
the pull-device.
7 6 5 4 3 2 1 0
R
PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard port interrupt enable registers. Refer to Table 2-39 to
determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-22. Port Interrupt Enable Register Field Descriptions
Field Description
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
7 6 5 4 3 2 1 0
R
PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard port interrupt flag registers. Refer to Table 2-39 to determine
the implemented bits in the respective register. Unimplemented bits read zero.
Field Description
Writing a logic “1” to the corresponding bit field clears the flag.
7 6 5 4 3 2 1 0
R
DIENx7 DIENx6 DIENx5 DIENx4 DIENx3 DIENx2 DIENx1 DIENx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard digital input enable registers. Refer to Table 2-39 to determine
the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-24. Digital Input Enable Register Field Descriptions
Field Description
7 6 5 4 3 2 1 0
R
RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard reduced drive registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Table 2-25. Reduced Drive Register Field Descriptions
Field Description
7-0 Reduced Drive Register — Select reduced drive for output pin
RDRx7-0 This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
7 6 5 4 3 2 1 0
R
WOMx7 WOMx6 WOMx5 WOMx4 WOMx3 WOMx2 WOMx1 WOMx0
W
Reset 0 0 0 0 0 0 0 0
This is a generic description of the standard wired-or registers. Refer to Table 2-39 to determine the
implemented bits in the respective register. Unimplemented bits read zero.
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PPSP2 PPS1P PPSP0
W
Reset 0 0 0 0 0 0 0 0
Field Description
0 Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin
PPSP
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active interrupt edge.
This bit selects if a high or a low level on FAULT5 generates a fault event in PMF.
1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input
0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input
7 6 5 4 3 2 1 0
R 0 0 0 0
OCIE1 PIEP2 PIEP1 PIEP0
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0
OCIF1 PIFP2 PIFP1 PIFP0
W
Reset 0 0 0 0 0 0 0 0
Field Description
Writing a logic “1” to the corresponding bit field clears the flag.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 PTIL02
W
Reset 0 0 0 0 0 0 0 -
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTPSL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PPSL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTABYPL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTADIRL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
DIENL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTAENL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PIRL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
2.3.4.12 Port L Test Enable Register (PTTEL)Port L Input Divider Ratio Selection
Address 0x033F Access: User read/write1
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTTEL02
W
Reset 0 0 0 0 0 0 0 0
Field Description
2.4.1 General
Each pin except BKGD can act as general-purpose I/O. In addition each pin can act as an output or input
of a peripheral module.
2.4.2 Registers
Table 2-39 lists the implemented configuration bits which are available on each port. These registers
except the pin input registers can be written at any time, however a specific configuration might not
become active. For example a pullup device does not become active while the port is used as a push-pull
output.
Unimplemented bits read zero.
Port PT PTI DDR PER PPS PIE PIF DIE RDR WOM
E 1-0 1-0 1-0 1-0 1-0 - - - - -
Table 2-40 shows the effect of enabled peripheral features on I/O state and enabled pull devices.
SPI0 MISO0, MOSI0, SCK0, SS0 Controlled input/output Forced off if output
SCIx transmitter TXDx Forced output Forced off
VRH, VRL
PTIx synch.
PIN
PTx 0
DDRx 0
1
data out
output enable
Periph. port enable
Module
data in
CAUTIONInterrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses
and interrupt priorities are defined at MCU level.
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
uncertain
Valid pulse, interrupt flag set
tP_MASK tP_PASS
Figure 2-36. Interrupt Glitch Filter (here: active low level selected)
VHVI REXT_HVI
10K PL (HVI)
40K
Input Buffer
PTIL
(DIENL & (PTAENL | STOP))
500K | (PTAENL & PTADIRL & PTTEL & STOP)
PTAENL VDDX
PTAENL & PTTEL
& STOP & PTPSL
& PTADIRL & STOP PTAENL Impedance
& STOP & PTADIRL Converter
ADC
PTAENL
& STOP & PTADIRL
110K
PTAENL
PIRL & PTADIRL
440K & PTABYPL
Voltages up to VHVI can be applied to the HVI pin. Internal voltage dividers scale the input signals down
to logic level. There are two modes, digital and analog, where these signals can be processed.
input or the voltage divider can be bypassed (PTADIRL=1). Additionally in latter case the impedance
converter in the ADC signal path can be used or bypassed in direct input mode (PTABYPL).
Out of reset the digital input buffer of the selected pin is disabled to avoid shoot-through current. Thus pin
interrupts can only be generated if DIENL=1.
In stop mode (RPM) the digital input buffer is enabled only if DIENL=1 to support wakeup functionality.
Table 2-42 shows the HVI input configuration depending on register bits and operation mode.
NOTE
An external resistor REXT_HVI must always be connected to the high-
voltage input to protect the device pins from fast transients and to achieve
the specified pin input divider ratios when using the HVI in analog mode.
VDDX
500K
min. 1/10 * VDDX
110K / 550K Digital in
40K
PIRL=0 / PIRL=1
HVI
10K
HV Supply
HV Supply
10K
HVI
Digital in
610K / 1050K
PIRL=0 / PIRL=1
Revision Sections
Revision Date Description of Changes
Number Affected
3.1 Introduction
The S12ZMMC module controls the access to all internal memories and peripherals for the S12ZCPU, and
the S12ZBDC module. It also provides access to the RAM for ADCs and the PTU module. The S12ZMMC
determines the address mapping of the on-chip resources, regulates access priorities and enforces memory
protection. Figure 3-1 shows a block diagram of the S12ZMMC module.
3.1.1 Glossary
Table 3-2. Glossary Of Terms
Term Definition
unmapped
Address space that is not assigned to a memory
address range
reserved address
Address space that is reserved for future use cases
range
illegal access Memory access, that is not supported or prohibited by the S12ZMMC, e.g. a data store to NVM
3.1.2 Overview
The S12ZMMC provides access to on-chip memories and peripherals for the S12ZCPU, the S12ZBDC,
the PTU, and the ADC. It arbitrates memory accesses and determines all of the MCU memory maps.
Furthermore, the S12ZMMC is responsible for selecting the MCUs functional mode.
3.1.3 Features
• S12ZMMC mode operation control
• Memory mapping for S12ZCPU and S12ZBDC, PTU and ADCs
— Maps peripherals and memories into a 16 MByte address space for the S12ZCPU, the
S12ZBDC, the PTU, and the ADCs
— Handles simultaneous accesses to different on-chip resources (NVM, RAM, and peripherals)
• Access violation detection and logging
— Triggers S12ZCPU machine exceptions upon detection of illegal memory accesses and
uncorrectable ECC errors
— Logs the state of the S12ZCPU and the cause of the access error
Memory Protection
Register
Block
Crossbar Switch
0x0071- Reserved R 0 0 0 0 0 0 0 0
0x007F W
0x0080 MMCECH R
ITR[3:0] TGT[3:0]
W
0x0081 MMCECL R
ACC[3:0] ERR[3:0]
W
0x0084 Reserved R 0 0 0 0 0 0 0 0
W
0x0088- Reserved R 0 0 0 0 0 0 0 0
0x00FF W
= Unimplemented or Reserved
Read: Anytime.
Write: Only if a transition is allowed (see Figure 3-4).
The MODE register determines the operating mode of the MCU.
CAUTION
Table 3-4. MODE Field Descriptions
Field Description
7 Mode Select Bit — This bit determines the current operating mode of the MCU. Its reset value is captured from
MODC the MODC pin at the rising edge of the RESET pin. Figure 3-4 illustrates the only valid mode transition from
special single-chip mode to normal single chip mode.
Normal Special
Single-Chip Single-Chip
Mode (NS) write access to Mode (SS)
MODE:
1 MODC bit
Read: Anytime
Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000
Table 3-5. MMCECH and MMCECL Field Descriptions
Field Description
7-4 (MMCECH) Initiator Field — The ITR[3:0] bits capture the initiator which caused the access violation. The initiator is
ITR[3:0] captured in form of a 4 bit value which is assigned as follows:
0: none (no error condition detected)
1: S12ZCPU
2: reserved
3: ADC0
4: ADC1
5: PTU
6-15: reserved
3-0 (MMCECH) Target Field — The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a
TGT[3:0] 4 bit value which is assigned as follows:
0: none
1: register space
2: RAM
3: EEPROM
4: program flash
5: IFR
6-15: reserved
Field Description
7-4 (MMCECL) Access Type Field — The ACC[3:0] bits capture the type of memory access, which caused the access
ACC[3:0] violation. The access type is captured in form of a 4 bit value which is assigned as follows:
0: none (no error condition detected)
1: opcode fetch
2: vector fetch
3: data load
4: data store
5-15: reserved
3-0 (MMCECL) Error Type Field — The EC[3:0] bits capture the type of the access violation. The type is captured in form of
ERR[3:0] a 4 bit value which is assigned as follows:
0: none (no error condition detected)
1: access to an illegal access
2: uncorrectable ECC error
3-15:reserved
The MMCEC register captures debug information about access violations. It is set to a non-zero value if
a S12ZCPU access violation or an uncorrectable ECC error has occurred. At the same time this register is
set to a non-zero value, access information is captured in the MMCPCn and MMCCCRn registers. The
MMCECn, the MMCPCn and the MMCCCRn registers are not updated if the MMCECn registers contain
a non-zero value. The MMCECn registers are cleared by writing the value 0xFFFF.
Read: Anytime
Write: Never
Field Description
7 (MMCCCRH) S12ZCPU User State Flag — This bit shows the state of the user/supervisor mode bit in the S12ZCPU’s CCR
CPUU at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically
updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error
code registers (MMCECn) are cleared.
6 (MMCCCRL) S12ZCPU X-Interrupt Mask— This bit shows the state of the X-interrupt mask in the S12ZCPU’s CCR at the
CPUX time the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automatically
updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error
code registers (MMCECn) are cleared.
4 (MMCCCRL) S12ZCPU I-Interrupt Mask— This bit shows the state of the I-interrupt mask in the CPU’s CCR at the time the
CPUI access violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updated
when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code
registers (MMCECn) are cleared.
Read: Anytime
Write: Never
Field Description
7–0 (MMCPCH) S12ZCPU Program Counter Value— The CPUPC[23:0] stores the CPU’s program counter value at the time
7–0 (MMCPCM) the access violation occurred. CPUPC[23:0] always points to the instruction which triggered the violation. These
7–0 (MMCPCL) bits are undefined if the error code registers (MMCECn) are cleared.
CPUPC[23:0]
Register Space
0x00_0000
4 KB 0x00_1000
RAM
max. 1 MByte - 4 KB
0x10_0000
EEPROM
max. 1 MByte - 48 KB
Reserved 512 Byte 0x1F_4000
0x20_0000
Unmapped
6 MByte
0x80_0000
Program NVM
max. 8 MByte
Unmapped
address range
Write access ok ok ok
Code execution ok
1. Unsupported NVM accesses during NVM command execution (“collisions”), are treated as illegal accesses.
• All illegal accesses performed by an ADC or PTU module trigger error interrupts. See ADC and
PTU section for details.
NOTE
Illegal accesses caused by S12ZCPU opcode prefetches will also trigger
machine exceptions, even if those opcodes might not be executed in the
program flow. To avoid these machine exceptions, S12ZCPU instructions
must not be executed from the last (high addresses) 8 bytes of RAM,
EEPROM, and Flash.
4.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
• I-bit and X-bit maskable interrupt requests
• One non-maskable unimplemented page1 op-code trap
4.1.1 Glossary
The following terms and abbreviations are used in the document.
Table 4-2. Terminology
Term Meaning
CCW Condition Code Register (in the S12Z CPU)
DMA Direct Memory Access
INT Interrupt
IPL Interrupt Processing Level
ISR Interrupt Service Routine
MCU Micro-Controller Unit
IRQ refers to the interrupt request associated with the IRQ pin
XIRQ refers to the interrupt request associated with the XIRQ pin
4.1.2 Features
• Interrupt vector base register (IVBR)
• One system reset vector (at address 0xFFFFFC).
• One non-maskable unimplemented page1 op-code trap (SPARE) vector (at address vector base1 +
0x0001F8).
• One non-maskable unimplemented page2 op-code trap (TRAP) vector (at address vector base1 +
0x0001F4).
• One non-maskable software interrupt request (SWI) vector (at address vector base1 + 0x0001F0).
• One non-maskable system call interrupt request (SYS) vector (at address vector base1 +
0x00001EC).
• One non-maskable machine exception vector request (at address vector base1 + 0x0001E8.
• One spurious interrupt vector (at address vector base1 + 0x0001DC).
• One X-bit maskable interrupt vector request associated with XIRQ (at address vector base1 +
0x0001D8).
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address).
• One I-bit maskable interrupt vector request associated with IRQ (at address vector base1 +
0x0001D4).
• up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base1 + 0x000010
.. vector base + 0x0001D0).
• Each I-bit maskable interrupt request has a configurable priority level.
• I-bit maskable interrupts can be nested, depending on their priority levels.
• Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
Peripheral Wake Up
Interrupt Requests CPU
Vector
Address
Non I Bit Maskable
Channels
Decoder
Priority
To CPU
IVBR
Interrupt
Requests
New
Priority IPL
PRIOLVL2 Level
One Set Per Channel PRIOLVL1 Filter
(Up to 117 Channels) PRIOLVL0
Current
Highest Pending IPL
IPL
PRIOLVLnPriority Level
= configuration bits from the associated
channel configuration register
IVBR = Interrupt Vector Base
IPL = Interrupt Processing Level
Register
Address Bit 7 6 5 4 3 2 1 Bit 0
Name
0x000010 IVBR R
IVB_ADDR[15:8]
W
0x000011 R 0
IVB_ADDR[7:1]
W
0x000017 INT_CFADDR R 0 0 0 0
INT_CFADDR[6:3]
W
0x000018 INT_CFDATA0 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x000019 INT_CFDATA1 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001A INT_CFDATA2 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001B INT_CFDATA3 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001C INT_CFDATA4 R 0 0 0 0 0
PRIOLVL[2:0]
W
= Unimplemented or Reserved
Register
Address Bit 7 6 5 4 3 2 1 Bit 0
Name
0x00001D INT_CFDATA5 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001E INT_CFDATA6 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001F INT_CFDATA7 R 0 0 0 0 0
PRIOLVL[2:0]
W
= Unimplemented or Reserved
Address: 0x000010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
IVB_ADDR[15:1]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Figure 4-3. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Table 4-4. IVBR Field Descriptions
Field Description
15–1 Interrupt Vector Base Address Bits — These bits represent the upper 15 bits of all vector addresses. Out
IVB_ADDR of reset these bits are set to 0xFFFE (i.e., vectors are located at 0xFFFE00–0xFFFFFF).
[15:1] Note: A system reset will initialize the interrupt vector base register with “0xFFFE” before it is used to
determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the
reset vector (0xFFFFFC–0xFFFFFF).
Address: 0x000017
7 6 5 4 3 2 1 0
R 0 0 0 0
INT_CFADDR[6:3]
W
Reset 0 0 0 0 1 0 0 0
= Unimplemented or Reserved
Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
Table 4-5. INT_CFADDR Field Descriptions
Field Description
6–3 Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
INT_CFADDR[6:3] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7.
The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number
(multiply with 4 to get the vector address offset).
If, for example, the value 0x70 is written to this register, the configuration data register block for the 8
interrupt vector requests starting with vector at address (vector base + (0x70*4 = 0x0001C0)) is selected
and can be accessed as INT_CFDATA0–7.
Address: 0x000018
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-5. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x000019
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001A
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001B
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-8. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001C
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-9. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001D
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-10. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001E
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x00001F
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PRIOLVL[2:0]
W
Reset 0 0 0 0 0 0 0 1(1)
= Unimplemented or Reserved
Figure 4-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime
Write: Anytime
Table 4-6. INT_CFDATA0–7 Field Descriptions
Field Description
2–0 Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of
PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”).
Please also refer to Table 4-7 for available interrupt request priority levels.
Note: Write accesses to configuration data registers of unused interrupt channels are ignored and read
accesses return all 0s. For information about what interrupt channels are used in a specific MCU, please
refer to the Device Reference Manual for that MCU.
Note: When non I-bit maskable request vectors are selected, writes to the corresponding INT_CFDATA
registers are ignored and read accesses return all 0s. The corresponding vectors do not have
configuration data registers associated with them.
Note: Write accesses to the configuration register for the spurious interrupt vector request
(vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU,
PRIOLVL = 7).
NOTE
All non I-bit maskable interrupt requests always have higher priority than I-
bit maskable interrupt requests. If an I-bit maskable interrupt request is
interrupted by a non I-bit maskable interrupt request, the currently active
interrupt processing level (IPL) remains unaffected. It is possible to nest
non I-bit maskable interrupt requests, e.g., by nesting SWI, SYS or TRAP
calls.
4.5.1 Initialization
After system reset, software should:
• Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFFFE00–0xFFFFFB).
Stacked IPL 0 4 0 0 0
IPL in CCW 0 4 7 4 3 1 0
6
RTI
L7
5
4
Processing Levels RTI
3
L3 (Pending)
2 RTI
L4
1
L1 (Pending) RTI
0
Reset
Figure 4-14. Interrupt Processing Example
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is
shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU
reference manual for details.
5.1 Introduction
The background debug controller (BDC) is a single-wire, background debug system implemented in on-
chip hardware for minimal CPU intervention. The device BKGD pin interfaces directly to the BDC.
The S12ZBDC maintains the standard S12 serial interface protocol but introduces an enhanced handshake
protocol and enhanced BDC command set to support the linear instruction set family of S12Z devices and
offer easier, more flexible internal resource access over the BDC serial interface.
5.1.1 Glossary
Table 5-2. Glossary Of Terms
Term Definition
BDCSI Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface.
EWAIT Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT
5.1.2 Features
The BDC includes these distinctive features:
• Single-wire communication with host development system
• SYNC command to determine communication rate
• Genuine non-intrusive handshake protocol
• Enhanced handshake protocol for error detection and stop mode recognition
• Active out of reset in special single chip mode
• Most commands not requiring active BDM, for minimal CPU intervention
• Full global memory map access without paging
• Simple flash mass erase capability
A disabled BDC has no influence on stop mode operation. In this case the BDCSI clock is disabled in stop
mode thus it is not possible to enable the BDC from within stop mode.
INSTRUCTION
DECODE AND
FSM
ADDRESS
BUS INTERFACE
AND DATA
CONTROL LOGIC BUS CONTROL
CPU CONTROL
BDCCSR REGISTER ERASE FLASH
AND DATAPATH
CONTROL FLASH ERASED
FLASH SECURE
Size
Global Address Module
(Bytes)
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
Not BDCCSRH R BDMACT 0 UNSEC ERASE
Applicable ENBDC BDCCIS STEAL CLKSW
W
Not BDCCSRL R
Applicable WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD
W
7 6 5 4 3 2 1 0
R BDMACT 0 UNSEC ERASE
ENBDC BDCCIS STEAL CLKSW
W
Reset
Secure AND SSC-Mode 1 1 0 0 0 0 0 0
Unsecure AND SSC-Mode 1 1 0 0 0 0 1 0
Secure AND NSC-Mode 0 0 0 0 0 0 0 0
Unsecure AND NSC-Mode 0 0 0 0 0 0 1 0
= Unimplemented, Reserved
Field Description
7 Enable BDC — This bit controls whether the BDC is enabled or disabled. When enabled, active BDM can be
ENBDC entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the
valid command set is restricted. Further information is provided in Table 5-7.
0 BDC disabled
1 BDC enabled
Note: ENBDC is set out of reset in special single chip mode.
6 BDM Active Status — This bit becomes set upon entering active BDM. BDMACT is cleared as part of the active
BDMACT BDM exit sequence.
0 BDM not active
1 BDM active
Note: BDMACT is set out of reset in special single chip mode.
5 BDC Continue In Stop — If ENBDC is set then BDCCIS selects the type of BDC operation in stop mode (as
BDCCIS shown in Table 5-3). If ENBDC is clear, then the BDC has no effect on stop mode and no BDC communication
is possible.If ACK pulse handshaking is enabled, then the first ACK pulse following stop mode entry is a long
ACK. This bit cannot be written when the device is in stop mode.
0 Only the BDCCLK clock continues in stop mode
1 All clocks continue in stop mode
3 Steal enabled with ACK— This bit forces immediate internal accesses with the ACK handshaking protocol
STEAL enabled. If ACK handshaking is disabled then BDC accesses steal the next bus cycle.
0 If ACK is enabled then BDC accesses await a free cycle, with a timeout of 512 cycles
1 If ACK is enabled then BDC accesses are carried out in the next bus cycle
2 Clock Switch — The CLKSW bit controls the BDCSI clock source. This bit is initialized to “0” by each reset and
CLKSW can be written to “1”. Once it has been set, it can only be cleared by a reset. When setting CLKSW a minimum
delay of 150 cycles at the initial clock speed must elapse before the next command can be sent. This guarantees
that the start of the next BDC command uses the new clock for timing subsequent BDC communications.
0 BDCCLK used as BDCSI clock source
1 Device fast clock used as BDCSI clock source
Note: Refer to the device specification to determine which clock connects to the BDCCLK and fast clock inputs.
1 Unsecure — If the device is unsecure, the UNSEC bit is set automatically.
UNSEC 0 Device is secure.
1 Device is unsecure.
Note: When UNSEC is set, the device is unsecure and the state of the secure bits in the on-chip Flash EEPROM
can be changed.
0 Erase Flash — This bit can only be set by the dedicated ERASE_FLASH command. ERASE is unaffected by
ERASE write accesses to BDCCSR. ERASE is cleared either when the mass erase sequence is completed, independent
of the actual status of the flash array or by a soft reset.
Reading this bit indicates the status of the requested mass erase sequence.
0 No flash mass erase sequence pending completion
1 Flash mass erase sequence pending completion.
7 6 5 4 3 2 1 0
R
WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD
W
Reset 0 0 0 0 0 0 0 0
Field Description
7 WAIT Indicator Flag — Indicates that the device entered wait mode. Writing a “1” to this bit whilst in wait mode
WAIT has no effect. Writing a “1” after exiting wait mode, clears the bit.
0 Device did not enter wait mode
1 Device entered wait mode.
6 STOP Indicator Flag — Indicates that the CPU requested stop mode following a STOP instruction. Writing a
STOP “1” to this bit whilst not in stop mode clears the bit. Writing a “1” to this bit whilst in stop mode has no effect.
This bit can only be set when the BDC is enabled.
0 Device did not enter stop mode
1 Device entered stop mode.
5 RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM.
RAMWF Writing a “1” to this bit, clears the bit.
0 No RAM write double fault detected.
1 RAM write double fault detected.
Field Description
When NORESP is set a value of 0xEE is returned for each data byte associated with the current access.
Writing a “1” to this bit, clears the bit.
0 Internal action or data access completed.
1 Internal action or data access did not complete.
2 Read Data Invalid Flag — Indicates invalid read data due to an ECC error during a BDC initiated read access.
RDINV The access returns the actual data read from the location.
Writing a “1” to this bit, clears the bit.
0 No invalid read data detected.
1 Invalid data returned during a BDC read access.
1 Illegal Access Flag — Indicates an attempted illegal access. This is set in the following cases:
ILLACC When the attempted access addresses unimplemented memory
When the access attempts to write to the flash array
When a CPU register access is attempted with an invalid CRN (Section 5.4.5.1).
Illegal accesses return a value of 0xEE for each data byte
Writing a “1” to this bit, clears the bit.
0 No illegal access detected.
1 Illegal BDC access detected.
Field Description
0 Illegal Command Flag — Indicates an illegal BDC command. This bit is set in the following cases:
ILLCMD When an unimplemented BDC command opcode is received.
When a DUMP_MEM{_WS}, FILL_MEM{_WS} or READ_SAME{_WS} is attempted in an illegal sequence.
When an active BDM command is received whilst BDM is not active
When a non Always-available command is received whilst the BDC is disabled or a flash mass erase is ongoing.
When a non Always-available command is received whilst the device is secure
Read commands return a value of 0xEE for each data byte
Writing a “1” to this bit, clears the bit.
0 No illegal command detected.
1 Illegal BDC command detected.
5.4.1 Security
If the device resets with the system secured, the device clears the BDCCSR UNSEC bit. In the secure state
BDC access is restricted to the BDCCSR register. A mass erase can be requested using the
ERASE_FLASH command. If the mass erase is completed successfully, the device programs the security
bits to the unsecure state and sets the BDC UNSEC bit. If the mass erase is unsuccessful, the device
remains secure and the UNSEC bit is not set.
For more information regarding security, please refer to device specific security information.
When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC
commands can affect CPU register contents until the BDC GO command returns from active BDM to user
code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used
determines if BDM becomes active before or after execution of the next instruction.
NOTE
Attempting to activate BDM using a BGND instruction whilst the BDC is
disabled, the CPU requires clock cycles for the attempted BGND execution.
However BACKGROUND commands issued whilst the BDC is disabled
are ignored by the BDC and the CPU execution is not delayed.
Secure BDC
Command Type CPU Status Command Set
Status Status
Non-intrusive commands are used to read and write target system memory locations and to enter active
BDM. Target system memory includes all memory and registers within the global memory map, including
external memory.
Active background commands are used to read and write all memory locations and CPU resources.
Furthermore they allow single stepping through application code and to exit from active BDM.
Non-intrusive commands can only be executed when the BDC is enabled and the device unsecure. Active
background commands can only be executed when the system is not secure and is in active BDM.
Non-intrusive commands do not require the system to be in active BDM for execution, although, they can
still be executed in this mode. When executing a non-intrusive command with the ACK pulse handshake
protocol disabled, the BDC steals the next bus cycle for the access. If an operation requires multiple cycles,
then multiple cycles can be stolen. Thus if stolen cycles are not free cycles, the application code execution
is delayed. The delay is negligible because the BDC serial transfer rate dictates that such accesses occur
infrequently.
For data read commands, the external host must wait at least 16 BDCSI clock cycles after sending the
address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDC shift register, ready to be shifted out. For write commands, the external host must wait 16 bdcsi
cycles after sending the data to be written before attempting to send a new command. This is to avoid
disturbing the BDC shift register before the write has been completed. The external host must wait at least
for 16 bdcsi cycles after a control command before starting any new serial command.
If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first
free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then
the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition
to the host.
Table 5-8 summarizes the BDC command set. The subsequent sections describe each command in detail
and illustrate the command structure in a series of packets, each consisting of eight bit times starting with
a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The
time for an 8-bit command is 8 16 target BDCSI clock cycles.
The nomenclature below is used to describe the structure of the BDC commands. Commands begin with
an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDCSI clock cycles (DLY)
dack = delay (16 cycles) no ACK; or delay (=> 32 cycles) then ACK.(DACK)
ad24 = 24-bit memory address in the host-to-target direction
rd8 = 8 bits of read data in the target-to-host direction
rd16 = 16 bits of read data in the target-to-host direction
rd24 = 24 bits of read data in the target-to-host direction
rd32 = 32 bits of read data in the target-to-host direction
rd64 = 64 bits of read data in the target-to-host direction
rd.sz = read data, size defined by sz, in the target-to-host direction
wd8 = 8 bits of write data in the host-to-target direction
wd16 = 16 bits of write data in the host-to-target direction
wd32 = 32 bits of write data in the host-to-target direction
wd.sz = write data, size defined by sz, in the host-to-target direction
ss = the contents of BDCCSRL in the target-to-host direction
sz = memory operand size (00 = byte, 01 = word, 10 = long)
(sz = 11 is reserved and currently defaults to long)
crn = core register number, 32-bit data width
WS = command suffix signaling the operation is with status
Table 5-8. BDC Command Summary
DUMP_MEM.sz Non-Intrusive Yes (0x32+4 x sz)/dack/rd.sz Dump (read) memory based on operand
size (sz). Used with READ_MEM to dump
large blocks of memory. An initial
READ_MEM is executed to set up the
starting address of the block and to retrieve
the first result. Subsequent DUMP_MEM
commands retrieve sequential operands.
DUMP_MEM.sz_WS Non-Intrusive No (0x33+4 x sz)/d/ss/rd.sz Dump (read) memory based on operand
size (sz) and report status. Used with
READ_MEM{_WS} to dump large blocks of
memory. An initial READ_MEM{_WS} is
executed to set up the starting address of
the block and to retrieve the first result.
Subsequent DUMP_MEM{_WS}
commands retrieve sequential operands.
FILL_MEM.sz Non-Intrusive Yes (0x12+4 x sz)/wd.sz/dack Fill (write) memory based on operand size
(sz). Used with WRITE_MEM to fill large
blocks of memory. An initial WRITE_MEM
is executed to set up the starting address of
the block and to write the first operand.
Subsequent FILL_MEM commands write
sequential operands.
FILL_MEM.sz_WS Non-Intrusive No (0x13+4 x sz)/wd.sz/d/ss Fill (write) memory based on operand size
(sz) and report status. Used with
WRITE_MEM{_WS} to fill large blocks of
memory. An initial WRITE_MEM{_WS} is
executed to set up the starting address of
the block and to write the first operand.
Subsequent FILL_MEM{_WS} commands
write sequential operands.
GO Active Yes 0x08/dack Resume CPU user code execution
Background
GO_UNTIL(2) Active Yes 0x0C/dack Go to user program. ACK is driven upon
Background returning to active background mode.
NOP Non-Intrusive Yes 0x00/dack No operation
READ_Rn Active Yes (0x60+CRN)/dack/rd32 Read the requested CPU register
Background
READ_MEM.sz Non-Intrusive Yes (0x30+4 x sz)/ad24/dack/rd.sz Read the appropriately-sized (sz) memory
value from the location specified by the 24-
bit address
READ_MEM.sz_WS Non-Intrusive No (0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory
value from the location specified by the 24-
bit address and report status
READ_DBGTB Non-Intrusive Yes (0x07)/dack/rd32/dack/rd32 Read 64-bits of DBG trace buffer
READ_SAME.sz Non-Intrusive Yes (0x50+4 x sz)/dack/rd.sz Read from location. An initial READ_MEM
defines the address, subsequent
READ_SAME reads return content of
same address
READ_SAME.sz_WS Non-Intrusive No (0x51+4 x sz)/d/ss/rd.sz Read from location. An initial READ_MEM
defines the address, subsequent
READ_SAME reads return content of
same address
READ_BDCCSR Always No 0x2D/rd16 Read the BDCCSR register
Available
SYNC_PC Non-Intrusive Yes 0x01/dack/rd24 Read current PC
WRITE_MEM.sz Non-Intrusive Yes (0x10+4 x Write the appropriately-sized (sz) memory
sz)/ad24/wd.sz/dack value to the location specified by the 24-bit
address
WRITE_MEM.sz_WS Non-Intrusive No (0x11+4 x sz)/ad24/wd.sz/d/ss Write the appropriately-sized (sz) memory
value to the location specified by the 24-bit
address and report status
WRITE_Rn Active Yes (0x40+CRN)/wd32/dack Write the requested CPU register
Background
WRITE_BDCCSR Always No 0x0D/wd16 Write the BDCCSR register
Available
ERASE_FLASH Always No 0x95/d Mass erase internal flash
Available
STEP1 (TRACE1) Active Yes 0x09/dack Execute one CPU command.
Background
1. The SYNC command is a special operation which does not have a command code.
5.4.4.1 SYNC
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct speed to use for serial communications until after it has analyzed the response to the SYNC
command.
To issue a SYNC command, the host:
1. Ensures that the BKGD pin is high for at least 4 cycles of the slowest possible BDCSI clock
without reset asserted.
2. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDCSI clock.
3. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically
one cycle of the host clock which is as fast as the maximum target BDCSI clock).
4. Removes all drive to the BKGD pin so it reverts to high impedance.
5.4.4.2 ACK_DISABLE
Disable host/target handshake protocol Always Available
0x03
D
host
L
target
Y
Disables the serial communication handshake protocol. The subsequent commands, issued after the
ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not
followed by an ACK pulse.
5.4.4.3 ACK_ENABLE
Enable host/target handshake protocol Always Available
0x02
D
host A
target C
K
Enables the hardware handshake protocol in the serial communication. The hardware handshake is
implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command.
The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface
with the CPU. An ACK pulse is issued by the target device after this command is executed. This command
can be used by the host to evaluate if the target supports the hardware handshake protocol. If the target
supports the hardware handshake protocol, subsequent commands are enabled to execute the hardware
handshake protocol, otherwise this command is ignored by the target. Table 5-8 indicates which
commands support the ACK hardware handshake protocol.
For additional information about the hardware handshake protocol, refer to Section 5.4.7,” and
Section 5.4.8.”
5.4.4.4 BACKGROUND
Enter active background mode (if enabled) Non-intrusive
0x04
D
host A
target C
K
Provided ENBDC is set, the BACKGROUND command causes the target MCU to enter active BDM as
soon as the current CPU instruction finishes. If ENBDC is cleared, the BACKGROUND command is
ignored.
A delay of 16 BDCSI clock cycles is required after the BACKGROUND command to allow the target
MCU to finish its current CPU instruction and enter active background mode before a new BDC command
can be accepted.
The host debugger must set ENBDC before attempting to send the BACKGROUND command the first
time. Normally the host sets ENBDC once at the beginning of a debug session or after a target system reset.
During debugging, the host uses GO commands to move from active BDM to application program
execution and uses the BACKGROUND command or DBG breakpoints to return to active BDM.
A BACKGROUND command issued during stop or wait modes cannot immediately force active BDM
because the WAI instruction does not end until an interrupt occurs. For the detailed mode dependency
description refer to Section 5.1.3.3.
The host can recognize this pending BDM request condition because both NORESP and WAIT are set, but
BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands
are allowed.
DUMP_MEM.sz
0x32 Data[7-0]
D
host A target
target C host
K
D
host A target target
target C host host
K
D
host A target target target target
target C host host host host
K
DUMP_MEM.sz_WS
D
host target target
L
target host host
Y
D
host target target target
L
target host host host
Y
D
host target target target target target
L
target host host host host host
Y
DUMP_MEM{_WS} is used with the READ_MEM{_WS} command to access large blocks of memory.
An initial READ_MEM{_WS} is executed to set-up the starting address of the block and to retrieve the
first result. The DUMP_MEM{_WS} command retrieves subsequent operands. The initial address is
incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent
DUMP_MEM{_WS} commands use this address, perform the memory read, increment it by the current
operand size, and store the updated address in the temporary register. If the with-status option is specified,
the BDCCSRL status byte is returned before the read data. This status byte reflects the state after the
memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The
effect of the access size and alignment on the next address to be accessed is explained in more detail in
Section 5.4.5.2”.
NOTE
DUMP_MEM{_WS} is a valid command only when preceded by SYNC,
NOP, READ_MEM{_WS}, or another DUMP_MEM{_WS} command.
Otherwise, an illegal command response is returned, setting the ILLCMD
bit. NOP can be used for inter-command padding without corrupting the
address pointer.
The size field (sz) is examined each time a DUMP_MEM{_WS} command is processed, allowing the
operand size to be dynamically altered. The examples show the DUMP_MEM.B{_WS},
DUMP_MEM.W{_WS} and DUMP_MEM.L{_WS} commands.
FILL_MEM.sz
0x12 Data[7-0]
D
host host A
target target C
K
D
host host host A
target target target C
K
D
host host host host host A
target target target target target C
K
FILL_MEM.sz_WS
FILL_MEM.sz_WS
D
host host target
L
target target host
Y
D
host host host target
L
target target target host
Y
D
host host host host host target
L
target target target target target host
Y
FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory.
An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first
datum. If an initial WRITE_MEM{_WS} is not executed before the first FILL_MEM{_WS}, an illegal
command response is returned. The FILL_MEM{_WS} command stores subsequent operands. The initial
address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent
FILL_MEM{_WS} commands use this address, perform the memory write, increment it by the current
operand size, and store the updated address in the temporary register. If the with-status option is specified,
the BDCCSRL status byte is returned after the write data. This status byte reflects the state after the
memory write was performed. If enabled an ACK pulse is generated after the internal write access has been
completed or aborted. The effect of the access size and alignment on the next address to be accessed is
explained in more detail in Section 5.4.5.2”
NOTE
FILL_MEM{_WS} is a valid command only when preceded by SYNC,
NOP, WRITE_MEM{_WS}, or another FILL_MEM{_WS} command.
Otherwise, an illegal command response is returned, setting the ILLCMD
bit. NOP can be used for inter command padding without corrupting the
address pointer.
The size field (sz) is examined each time a FILL_MEM{_WS} command is processed, allowing the
operand size to be dynamically altered. The examples show the FILL_MEM.B{_WS},
FILL_MEM.W{_WS} and FILL_MEM.L{_WS} commands.
5.4.4.7 GO
Go Non-intrusive
0x08
D
host A
target C
K
This command is used to exit active BDM and begin (or resume) execution of CPU application code. The
CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at
the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM,
the updated value is used when prefetching resumes. If enabled, an ACK is driven on exiting active BDM.
If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the
ILLCMD bit is set.
5.4.4.8 GO_UNTIL
Go Until Active Background
0x0C
D
host A
target C
K
This command is used to exit active BDM and begin (or resume) execution of application code. The CPU
pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the
current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM,
the updated value is used when prefetching resumes.
After resuming application code execution, if ACK is enabled, the BDC awaits a return to active BDM
before driving an ACK pulse. timeouts do not apply when awaiting a GO_UNTIL command ACK.
If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending
GO_UNTIL.
If a GO_UNTIL command is issued whilst BDM is inactive, an illegal command response is returned and
the ILLCMD bit is set.
If ACK handshaking is disabled, the GO_UNTIL command is identical to the GO command.
5.4.4.9 NOP
No operation Active Background
0x00
D
host A
target C
K
NOP performs no operation and may be used as a null command where required.
5.4.4.10 READ_Rn
Read CPU register Active Background
D
host A target target target target
target C host host host host
K
This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers
are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return
zero. The register is addressed through the CPU register number (CRN). See Section 5.4.5.1 for the CRN
address decoding. If enabled, an ACK pulse is driven before the data bytes are transmitted.
If the device is not in active BDM, this command is illegal, the ILLCMD bit is set and no access is
performed.
READ_MEM.sz
D
host host A target
target target C host
K
D
host host A target target
target target C host host
K
D
host host A target target target target
target target C host host host host
K
READ_MEM.sz_WS
D
host host target target
L
target target host host
Y
D
host host target target target
L
target target host host host
Y
D
host host target target target target target
L
target target host host host host host
Y
Read data at the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb)
immediately after the command.
The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0-
modulo-size alignments. Byte alignment details are described in Section 5.4.5.2”. If the with-status option
is specified, the BDCCSR status byte is returned before the read data. This status byte reflects the state
after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are
transmitted.
The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS}
commands.
5.4.4.12 READ_DBGTB
Read DBG trace buffer Non-intrusive
TB Line [31- TB Line [23- TB Line [15- TB Line [7- TB Line [63- TB Line [55- TB Line [47- TB Line [39-
0x07
24] 16] 8] 0] 56] 48] 40] 32]
D D
host A target target target target A target target target target
target C host host host host C host host host host
K K
This command is only available on devices, where the DBG module includes a trace buffer. Attempted use
of this command on devices without a traace buffer return 0x00.
Read 64 bits from the DBG trace buffer. Refer to the DBG module description for more detailed
information. If enabled an ACK pulse is generated before each 32-bit longword is ready to be read by the
host. After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword,
since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line
bits[31:0]; the second to trace buffer line bits[63:32]. If ACK handshaking is disabled, the host must wait
16 clock cycles (DLY) after completing the first 32-bit read before starting the second 32-bit read.
READ_SAME
D
host A target target
target C host host
K
READ_SAME_WS
D
host target target target
L
target host host host
Y
Read from location defined by the previous READ_MEM. The previous READ_MEM command defines
the address, subsequent READ_SAME commands return contents of same address. The example shows
the sequence for reading a 16-bit word size. Byte alignment details are described in Section 5.4.5.2”. If
enabled, an ACK pulse is driven before the data bytes are transmitted.
NOTE
READ_SAME{_WS} is a valid command only when preceded by SYNC,
NOP, READ_MEM{_WS}, or another READ_SAME{_WS} command.
Otherwise, an illegal command response is returned, setting the ILLCMD
bit. NOP can be used for inter-command padding without corrupting the
address pointer.
5.4.4.14 READ_BDCCSR
Read BDCCSR Status Register Always Available
BDCCSR BDCCSR
0x2D
[15:8] [7-0]
D
host target target
L
target host host
Y
Read the BDCCSR status register. This command can be executed in any mode.
5.4.4.15 SYNC_PC
Sample current PC Non-intrusive
PC PC PC
0x01
data[23–16] data[15–8] data[7–0]
D
host A target target target
target C host host host
K
This command returns the 24-bit CPU PC value to the host. Unsuccessful SYNC_PC accesses return 0xEE
for each byte. If enabled, an ACK pulse is driven before the data bytes are transmitted. The value of 0xEE
is returned if a timeout occurs, whereby NORESP is set. This can occur if the CPU is executing the WAI
instruction, or the STOP instruction with BDCCIS clear, or if a CPU access is delayed by EWAIT. If the
CPU is executing the STOP instruction and BDCCIS is set, then SYNC_PC returns the PC address of the
instruction following STOP in the code listing.
This command can be used to dynamically access the PC for performance monitoring as the execution of
this command is considerably less intrusive to the real-time operation of an application than a
BACKGROUND/read-PC/GO command sequence. Whilst the BDC is not in active BDM, SYNC_PC
returns the PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC
returns the address of the next instruction to be executed on returning from active BDM. Thus following
a write to the PC in active BDM, a SYNC_PC returns that written value.
WRITE_MEM.sz
D
host host host A
host target
target target target C
K
D
host host host host host A
host target
target target target target target C
K
WRITE_MEM.sz_WS
D
host host host target
L
target target target host
Y
D
host host host host target
L
target target target target host
Y
D
host host host host host host target
L
target target target target target target host
Y
Write data to the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb)
immediately after the command.
If the with-status option is specified, the status byte contained in BDCCSRL is returned after the write data.
This status byte reflects the state after the memory write was performed. The examples show the
WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled
an ACK pulse is generated after the internal write access has been completed or aborted.
The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0-
modulo-size alignments. Byte alignment details are described in Section 5.4.5.2”.
5.4.4.17 WRITE_Rn
Write general-purpose CPU register Active Background
If the device is in active BDM, this command writes the 32-bit operand to the selected CPU general-
purpose register. See Section 5.4.5.1 for the CRN details. Accesses to CPU registers are always 32-bits
wide, regardless of implemented register width. If enabled an ACK pulse is generated after the internal
write access has been completed or aborted.
If the device is not in active BDM, this command is rejected as an illegal operation, the ILLCMD bit is set
and no operation is performed.
5.4.4.18 WRITE_BDCCSR
Write BDCCSR Always Available
BDCCSR BDCCSR
0x0D
Data [15-8] Data [7-0]
D
host host host
L
target target target
Y
16-bit write to the BDCCSR register. No ACK pulse is generated. Writing to this register can be used to
configure control bits or clear flag bits. Refer to the register bit descriptions.
5.4.4.19 ERASE_FLASH
Erase FLASH Always Available
0x95
D
host
L
target
Y
Mass erase the internal flash. This command can always be issued. On receiving this command twice in
succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC
command following a single ERASE_FLASH initializes the sequence, such that thereafter the
ERASE_FLASH must be applied twice in succession to request a mass erase. If 512 BDCSI clock cycles
elapse between the consecutive ERASE_FLASH commands then a timeout occurs, which forces a soft
reset and initializes the sequence. The ERASE bit is cleared when the mass erase sequence has been
completed. No ACK is driven.
During the mass erase operation, which takes many clock cycles, the command status is indicated by the
ERASE bit in BDCCSR. Whilst a mass erase operation is ongoing, Always-available commands can be
issued. This allows the status of the erase operation to be polled by reading BDCCSR to determine when
the operation is finished.
The status of the flash array can be verified by subsequently reading the flash error flags to determine if
the erase completed successfully.
ERASE_FLASH can be aborted by a SYNC pulse forcing a soft reset.
NOTE: Device Bus Frequency Considerations
The ERASE_FLASH command requires the default device bus clock
frequency after reset. Thus the bus clock frequency must not be changed
following reset before issuing an ERASE_FLASH command.
5.4.4.20 STEP1
Step1 Active Background
0x09
D
host A
target C
K
This command is used to step through application code. In active BDM this command executes the next
CPU instruction in application code. If enabled an ACK is driven.
If a STEP1 command is issued and the CPU is not halted, the command is ignored.
Using STEP1 to step through a CPU WAI instruction is explained in Section 5.1.3.3.2.
to start the bit up to one target clock cycle earlier. Synchronization between the host and target is
established in this manner at the start of every bit time.
Figure 5-6 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later than eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
BDCSI clock
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
10 CYCLES
EARLIEST START
OF NEXT BIT
SYNCHRONIZATION TARGET SENSES BIT LEVEL
UNCERTAINTY
PERCEIVED START
OF BIT TIME
Figure 5-7 shows the host receiving a logic 1 from the target system. The host holds the BKGD pin low
long enough for the target to recognize it (at least two target clock cycles). The host must release the low
drive at the latest after 6 clock cycles, before the target drives a brief high speedup pulse seven target clock
cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock
cycles after it started the bit time.
BDCSI clock
(TARGET MCU)
HOST DRIVE
TO BKGD PIN HIGH-IMPEDANCE
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES
Figure 5-8 shows the host receiving a logic 0 from the target. The host initiates the bit time but the target
finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target
clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10
target clock cycles after starting the bit time.
BDCSI clock
(TARGET MCU)
HOST DRIVE
TO BKGD PIN HIGH-IMPEDANCE
SPEEDUP
TARGET MCU PULSE
DRIVE AND
SPEED-UP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
10 CYCLES
EARLIEST START
10 CYCLES OF NEXT BIT
BKGD PIN
EARLIEST
16th CYCLE OF THE START OF
LAST COMMAND BIT NEXT BIT
The handshake protocol is enabled by the ACK_ENABLE command. The BDC sends an ACK pulse when
the ACK_ENABLE command has been completed. This feature can be used by the host to evaluate if the
target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command,
the host knows that the target supports the hardware handshake protocol.
Unlike the normal bit transfer, where the host initiates the transmission by issuing a negative edge on the
BKGD pin, the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative
edge on the BKGD pin. Figure 5-9 specifies the timing when the BKGD pin is being driven. The host must
follow this timing constraint in order to avoid the risk of an electrical conflict at the BKGD pin.
When the handshake protocol is enabled, the STEAL bit in BDCCSR selects if bus cycle stealing is used
to gain immediate access. If STEAL is cleared, the BDC is configured for low priority bus access using
free cycles, without stealing cycles. This guarantees that BDC accesses remain truly non-intrusive to not
affect the system timing during debugging. If STEAL is set, the BDC gains immediate access, if necessary
stealing an internal bus cycle.
NOTE
If bus steals are disabled then a loop with no free cycles cannot allow access.
In this case the host must recognize repeated NORESP messages and then
issue a BACKGROUND command to stop the target and access the data.
Figure 5-10 shows the ACK handshake protocol without steal in a command level timing diagram. The
READ_MEM.B command is used as an example. First, the 8-bit command code is sent by the host,
followed by the address of the memory location to be read. The target BDC decodes the command. Then
an internal access is requested by the BDC. When a free bus cycle occurs the READ_MEM.B operation
is carried out. If no free cycle occurs within 512 core clock cycles then the access is aborted, the NORESP
flag is set and the target generates a Long-ACK pulse.
Having retrieved the data, the BDC issues an ACK pulse to the host controller, indicating that the
addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the data read part
of the command.
TARGET HOST
Alternatively, setting the STEAL bit configures the handshake protocol to make an immediate internal
access, independent of free bus cycles.
The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not
acknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDC command. The host can decide to abort any possible pending ACK pulse in order to be
sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command,
and its corresponding ACK, can be aborted.
Commands With-Status do not generate an ACK, thus if ACK is enabled and a With-Status command is
issued, the host must use the 512 cycle timeout to calculate when the data is ready for retrieval.
Following a STOP or WAI instruction, if the BDC is enabled, the first ACK, following stop or wait mode
entry is a long ACK to indicate an exception.
Figure 5-12 shows a conflict between the ACK pulse and the SYNC request pulse. The target is executing
a pending BDC command at the exact moment the host is being connected to the BKGD pin. In this case,
an ACK pulse is issued simultaneously to the SYNC command. Thus there is an electrical conflict between
the ACK speedup pulse and the SYNC pulse. As this is not a probable situation, the protocol does not
prevent this conflict from happening.
BDCSI clock
(TARGET MCU)
ACK PULSE
TARGET MCU
DRIVES TO HIGH-IMPEDANCE
BKGD PIN
ELECTRICAL CONFLICT
SPEEDUP PULSE
HOST AND TARGET
HOST DRIVE TO BKGD PIN
DRIVES SYNC
TO BKGD PIN
BKGD PIN
16 CYCLES
at the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDC
command, or the start of a SYNC request pulse.
2.10 28.JUN.2013 General Emphasized need to set TSOURCE for tracing or profiling
Section 6.3.2.21 Corrected DBGCDM write access dependency
Section 6.3.2.1 Corrrected ARM versus PTACT dependency
Section 6.3.2.5 Modified DBGTBH read access dependencies
2.11 15.JUL.2013 Section 6.3.2 Added explicit names to state control register bit fields
4.00 18.SEP.2013 General Added PREND bit to improve usability of profiling format for debugging
4.01 18.OCT.2013 Section 6.4.5.4 Removed trace buffer read dependence on PROFILE bit
Section 6.4.6.3 Corrected reference to timestamp clock source in profiling mode
4.02 03.FEB.2015 Section 6.1 Updated Table 6-2 and preceding NOTE to support V2, V3 and V4
6.1 Introduction
NOTE
Device reference manuals specify which S12Z Debug module version is
integrated on the device. Some reference manuals support families of
devices, with device dependent Debug module versions. This chapter
describes the superset. The feature differences are listed in Table 6-2.
Table 6-2. Comparison of S12Z Debug Module Versions
Match 2 trigger included Match 2 trigger included Match 2 trigger not included
PREND bit not included PREND bit included PREND bit not included
The DBG module provides on-chip breakpoints and trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The DBG module is optimized for the S12Z architecture and
allows debugging of CPU module operations.
Typically the DBG module is used in conjunction with the BDC module, whereby the user configures the
DBG module for a debugging session over the BDC interface. Once configured the DBG module is armed
and the device leaves active BDM returning control to the user program, which is then monitored by the
DBG module. Alternatively the DBG module can be configured over a serial interface using SWI routines.
6.1.1 Glossary
Table 6-3. Glossary Of Terms
Term Definition
PC Program Counter
Trigger A trace buffer input that triggers tracing start, end or mid point
6.1.2 Overview
The comparators monitor the bus activity of the CPU. A single comparator match or a series of matches
can trigger bus tracing and/or generate breakpoints. A state sequencer determines if the correct series of
matches occurs. Similarly an external event can trigger bus tracing and/or generate breakpoints.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
6.1.3 Features
• Four comparators (A, B, C, and D)
— Comparators A and C compare the full address bus and full 32-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor PC addresses or addresses of data accesses
— Each comparator can select either read or write access cycles
— Comparator matches can force state sequencer state transitions
EXTERNAL EVENT
TRIG
REGISTERS
MATCH0
COMPARATOR A STATE SEQUENCER
MATCH CONTROL
CPU BUS
BUS INTERFACE
AND
COMPARATOR
MATCH1 EVENT CONTROL
COMPARATOR B
BREAKPOINT
COMPARATOR C MATCH2 REQUESTS
COMPARATOR D MATCH3
TRACE
CONTROL
TRIGGER
PROFILE
OUTPUT
TRACE BUFFER
READ TRACE DATA (DBG READ DATA BUS)
R 0 0 0 0
0x0101 DBGC2 CDCM ABCM
W
R
0x0102 DBGTCRH reserved TSOURCE TRANGE TRCMOD TALIGN
W
R 0 0 0
0x0103 DBGTCRL PREND DSTAMP PDOE PROFILE STAMP
W
R 0 CNT
0x0106 DBGCNT
W
R
0x0107 DBGSCR1 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0
W
R
0x0108 DBGSCR2 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0
W
R
0x0109 DBGSCR3 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0
W
R 0 0
0x0110 DBGACTL NDB INST RW RWE reserved COMPE
W
0x0111- R 0 0 0 0 0 0 0 0
Reserved
0x0114 W
R
0x0115 DBGAAH DBGAA[23:16]
W
R
0x0116 DBGAAM DBGAA[15:8]
W
R
0x0117 DBGAAL DBGAA[7:0]
W
R
0x0118 DBGAD0 Bit 31 30 29 28 27 26 25 Bit 24
W
R
0x0119 DBGAD1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x011A DBGAD2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x011B DBGAD3 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x011C DBGADM0 Bit 31 30 29 28 27 26 25 Bit 24
W
R
0x011D DBGADM1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x011E DBGADM2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x011F DBGADM3 Bit 7 6 5 4 3 2 1 Bit 0
W
R 0 0 0
0x0120 DBGBCTL INST RW RWE reserved COMPE
W
0x0121- R 0 0 0 0 0 0 0 0
Reserved
0x0124 W
R
0x0125 DBGBAH DBGBA[23:16]
W
R
0x0126 DBGBAM DBGBA[15:8]
W
R
0x0127 DBGBAL DBGBA[7:0]
W
R 0 0
0x0130 DBGCCTL NDB INST RW RWE reserved COMPE
W
0x0131- R 0 0 0 0 0 0 0 0
Reserved
0x0134 W
R
0x0135 DBGCAH DBGCA[23:16]
W
R
0x0136 DBGCAM DBGCA[15:8]
W
R
0x0137 DBGCAL DBGCA[7:0]
W
R
0x0138 DBGCD0 Bit 31 30 29 28 27 26 25 Bit 24
W
R
0x0139 DBGCD1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x013A DBGCD2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x013B DBGCD3 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x013C DBGCDM0 Bit 31 30 29 28 27 26 25 Bit 24
W
R
0x013D DBGCDM1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x013E DBGCDM2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x013F DBGCDM3 Bit 7 6 5 4 3 2 1 Bit 0
W
R 0 0 0
0x0140 DBGDCTL INST RW RWE reserved COMPE
W
0x0141- R 0 0 0 0 0 0 0 0
Reserved
0x0144 W
R
0x0145 DBGDAH DBGDA[23:16]
W
R
0x0146 DBGDAM DBGDA[15:8]
W
0x0148- R 0 0 0 0 0 0 0 0
Reserved
0x017F W
Read: Anytime
Write: Bit 7 Anytime with the exception that it cannot be set if PTACT is set. An ongoing profiling session
must be finished before DBG can be armed again.
Bit 6 can be written anytime but always reads back as 0.
Bits 5:0 anytime DBG is not armed and PTACT is clear.
NOTE
On a write access to DBGC1 and simultaneous hardware disarm from an
internal event, the hardware disarm has highest priority, clearing the ARM
bit and generating a breakpoint, if enabled.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[5:0] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
Field Description
7 Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by register
ARM writes and is automatically cleared when the state sequencer returns to State0 on completing a debugging
session. On setting this bit the state sequencer enters State1.
0 Debugger disarmed. No breakpoint is generated when clearing this bit by software register writes.
1 Debugger armed
6 Immediate Trigger Request Bit — This bit when written to 1 requests an immediate transition to final state
TRIG independent of comparator status. This bit always reads back a 0. Writing a 0 to this bit has no effect.
0 No effect.
1 Force state sequencer immediately to final state.
4 Background Debug Mode Enable — This bit determines if a CPU breakpoint causes the system to enter
BDMBP Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDC is not enabled,
then no breakpoints are generated.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDC enabled. Otherwise no breakpoint.
3 CPU Breakpoint Enable — The BRKCPU bit controls whether the debugger requests a breakpoint to CPU upon
BRKCPU transitions to State0. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If
tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 6.4.7 for further details.
0 Breakpoints disabled
1 Breakpoints enabled
1–0 External Event Enable — The EEVE bits configure the external event function. Table 6-5 explains the bit
EEVE encoding.
EEVE Description
00 External event function disabled
01 External event forces a trace buffer entry if tracing is enabled
10 External event is mapped to the state sequencer, replacing comparator channel 3
11 External event pin gates trace buffer entries
Read: Anytime.
Write: Anytime the module is disarmed and PTACT is clear.
This register configures the comparators for range matching.
Field Description
3–2 C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
CDCM[1:0] described in Table 6-7.
1–0 A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 6-8.
CDCM Description
00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
01 Match2 mapped to comparator C/D inside range....... Match3 disabled.
10 Match2 mapped to comparator C/D outside range....... Match3 disabled.
11 Reserved(1)
1. Currently defaults to Match2 mapped to inside range: Match3 disabled.
ABCM Description
00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
01 Match0 mapped to comparator A/B inside range....... Match1 disabled.
10 Match0 mapped to comparator A/B outside range....... Match1 disabled.
11 Reserved(1)
1. Currently defaults to Match0 mapped to inside range: Match1 disabled
Read: Anytime.
Write: Anytime the module is disarmed and PTACT is clear.
WARNING
DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.
This register configures the trace buffer for tracing and profiling.
Field Description
TRCMOD Description
00 Normal
01 Loop1
10 Detail
11 Pure PC
TALIGN Description
00 Trigger ends data trace
01 Trigger starts data trace
10 32 lines of data trace follow trigger
11(1) Reserved
1. Tracing/Profiling disabled.
Read: Anytime.
Write: Anytime the module is disarmed and PTACT is clear.
This register configures the profiling and timestamp features
Table 6-13. DBGTCRL Field Descriptions
Field Description
4 Profiling End — This bit, when set, forces the profiling session to end when the trace buffer has been filled. This
PREND prevents a rollover of the trace buffer from overwriting the initial entry containing the start address
0 Trace buffer rollover is enabled during profiling. After the last line has been filled, the entries continue, starting
at line0 and overwriting the older data
1 Trace buffer rollover is disabled during profiling. When the trace buffer is full, the profilling session ends, the
PTBOVF bit is set and the ARM bit is cleared.
3 Comparator D Timestamp Enable — This bit, when set, enables Comparator D matches to generate
DSTAMP timestamps in Detail, Normal and Loop1 trace modes.
0 Comparator D match does not generate timestamp
1 Comparator D match generates timestamp if timestamp function is enabled
2 Profile Data Out Enable — This bit, when set, configures the device profiling pins for profiling.
PDOE 0 Device pins not configured for profiling
1 Device pins configured for profiling
1 Profile Enable — This bit, when set, enables the profile function, whereby a subsequent arming of the DBG
PROFILE activates profiling.
When PROFILE is set, the TRCMOD bits are ignored.
0 Profile function disabled
1 Profile function enabled
0 Timestamp Enable — This bit, when set, enables the timestamp function. The timestamp function adds a
STAMP timestamp to each trace buffer entry in Detail, Normal and Loop1 trace modes.
0 Timestamp function disabled
1 Timestamp function enabled
Read: Only when unlocked AND not armed and the TSOURCE bit is set, otherwise an error code (0xEE)
is returned. Only aligned word read operations are supported. Misaligned word reads or byte reads return
the error code 0xEE for each byte.
Write: Aligned word writes when the DBG is disarmed and the PTACT is clear unlock the trace buffer for
reading but do not affect trace buffer contents.
Table 6-14. DBGTB Field Descriptions
Field Description
15–0 Trace Buffer Data Bits — The Trace Buffer Register is a window through which the lines of the trace buffer may
Bit[15:0] be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to
the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The
trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module
is disarmed. The DBGTB register can be read only as an aligned word. Byte reads or misaligned access of these
registers returns 0xEE and does not increment the trace buffer pointer. Similarly word reads while the debugger
is armed or trace buffer is locked return 0xEEEE. The POR state is undefined Other resets do not affect the trace
buffer contents.
Read: Anytime.
Write: Never.
Field Description
6–0 Count Value — The CNT bits [6:0] indicate the number of valid data lines stored in the trace buffer. Table 6-16
CNT[6:0] shows the correlation between the CNT bits and the number of valid data lines in the trace buffer. When the CNT
rolls over to zero, the TBF bit in DBGSR is set. Thereafter incrementing of CNT continues if configured for end-
alignment or mid-alignment.
The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by
power-on-reset initialization but is not cleared by other system resets. If a reset occurs during a debug session,
the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset
occurred. The DBGCNT register is not decremented when reading from the trace buffer.
Read: Anytime.
Write: If DBG is not armed and PTACT is clear.
The state control register 1 selects the targeted next state whilst in State1. The matches refer to the outputs
of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12”.
Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control
register.
Field Description
CxSC[1:0] Function
00 Match has no effect
01 Match forces sequencer to State2
10 Match forces sequencer to State3
11 Match forces sequencer to Final State
In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.
Read: Anytime.
Write: If DBG is not armed and PTACT is clear.
The state control register 2 selects the targeted next state whilst in State2. The matches refer to the outputs
of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12”.
Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control
register.
Table 6-19. DBGSCR2 Field Descriptions
Field Description
Field Description
CxSC[1:0] Function
00 Match has no effect
01 Match forces sequencer to State1
10 Match forces sequencer to State3
11 Match forces sequencer to Final State
In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.
Read: Anytime.
Write: If DBG is not armed and PTACT is clear.
The state control register three selects the targeted next state whilst in State3. The matches refer to the
outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12”.
Comparators must be enabled by setting the comparator enable bit in the associated DBGxCTL control
register.
Table 6-21. DBGSCR3 Field Descriptions
Field Description
Field Description
CxSC[1:0] Function
00 Match has no effect
01 Match forces sequencer to State1
10 Match forces sequencer to State2
11 Match forces sequencer to Final State
In the case of simultaneous matches, the match on the higher channel number (3....0) has priority.
Read: Anytime.
Write: Never
DBGEFR contains flag bits each mapped to events whilst armed. Should an event occur, then the
corresponding flag is set. With the exception of TRIGF, the bits can only be set when the ARM bit is set.
The TRIGF bit is set if a TRIG event occurs when ARM is already set, or if the TRIG event occurs
simultaneous to setting the ARM bit.All other flags can only be cleared by arming the DBG module. Thus
the contents are retained after a debug session for evaluation purposes.
A set flag does not inhibit the setting of other flags.
Table 6-23. DBGEFR Field Descriptions
Field Description
7 Profiling Trace Buffer Overflow Flag — Indicates the occurrence of a trace buffer overflow event during a
PTBOVF profiling session.
0 No trace buffer overflow event
1 Trace buffer overflow event
6 TRIG Flag — Indicates the occurrence of a TRIG event during the debug session.
TRIGF 0 No TRIG event
1 TRIG event
Field Description
4 External Event Flag — Indicates the occurrence of an external event during the debug session.
EEVF 0 No external event
1 External event
3–0 Match Event[3:0]— Indicates a comparator match event on the corresponding comparator channel.
ME[3:0]
Read: Anytime.
Write: Never.
Table 6-24. DBGSR Field Descriptions
Field Description
7 Trace Buffer Full — The TBF bit indicates that the trace buffer has been filled with data since it was last armed.
TBF If this bit is set, then all trace buffer lines contain valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
4 Profiling Transmission Active — The PTACT bit, when set, indicates that the profiling transmission is still
PTACT active. When clear, PTACT then profiling transmission is not active. The PTACT bit is set when profiling begins
with the first PTS format entry to the trace buffer. The PTACT bit is cleared when the profiling transmission ends.
2–0 State Sequencer Flag Bits — The SSF bits indicate the current State Sequencer state. During a debug session
SSF[2:0] on each transition to a new state these bits are updated. If the debug session is ended by software clearing the
ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a
debug session is ended by an internal event, then the state sequencer returns to State0 and these bits are
cleared to indicate that State0 was entered during the session. On arming the module the state sequencer enters
State1 and these bits are forced to SSF[2:0] = 001. See Table 6-25.
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-26. DBGACTL Field Descriptions
Field Description
6 Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
NDB register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the
same register is set.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
5 Instruction Select — This bit configures the comparator to compare PC or data access addresses.
INST 0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3 Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
RW associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
RWE associated comparator. This bit is ignored when INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0 Enable Bit — Determines if comparator is enabled
COMPE 0 The comparator is not enabled
1 The comparator is enabled
Table 6-27 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-28. DBGAAH, DBGAAM, DBGAAL Field Descriptions
Field Description
23–16 Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares
DBGAA the address bus bits [23:16] to a logic one or logic zero.
[23:16] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
15–0 Comparator Address Bits [15:0]— These comparator address bits control whether the comparator compares
DBGAA the address bus bits [15:0] to a logic one or logic zero.
[15:0] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
This register can be accessed with a byte resolution, whereby DBGAD0, DBGAD1, DBGAD2, DBGAD3
map to DBGAD[31:0] respectively.
Field Description
31–16 Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one
Bits[31:16] or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1.
(DBGAD0, 0 Compare corresponding data bit to a logic zero
DBGAD1) 1 Compare corresponding data bit to a logic one
15–0 Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one
Bits[15:0] or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1.
(DBGAD2, 0 Compare corresponding data bit to a logic zero
DBGAD3) 1 Compare corresponding data bit to a logic one
Read: Anytime.
Field Description
31–16 Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the
Bits[31:16] corresponding comparator data compare bits.
(DBGADM0, 0 Do not compare corresponding data bit
DBGADM1) 1 Compare corresponding data bit
15-0 Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the
Bits[15:0] corresponding comparator data compare bits.
(DBGADM2, 0 Do not compare corresponding data bit
DBGADM3) 1 Compare corresponding data bit
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-31. DBGBCTL Field Descriptions
Field(1) Description
5 Instruction Select — This bit configures the comparator to compare PC or data access addresses.
INST 0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3 Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
RW associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
RWE associated comparator. This bit is ignored when INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0 Enable Bit — Determines if comparator is enabled
COMPE 0 The comparator is not enabled
1 The comparator is enabled
1. If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored.
Table 6-32 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, as matches based on instructions reaching the execution stage are data independent.
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-33. DBGBAH, DBGBAM, DBGBAL Field Descriptions
Field Description
23–16 Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares
DBGBA the address bus bits [23:16] to a logic one or logic zero.
[23:16] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
15–0 Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares
DBGBA the address bus bits [15:0] to a logic one or logic zero.
[15:0] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-34. DBGCCTL Field Descriptions
Field Description
6 Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
NDB register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the
same register is set.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
5 Instruction Select — This bit configures the comparator to compare PC or data access addresses.
INST 0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3 Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
RW associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
RWE associated comparator. This bit is not used if INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0 Enable Bit — Determines if comparator is enabled
COMPE 0 The comparator is not enabled
1 The comparator is enabled
Table 6-35 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-36. DBGCAH, DBGCAM, DBGCAL Field Descriptions
Field Description
23–16 Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares
DBGCA the address bus bits [23:16] to a logic one or logic zero.
[23:16] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
15–0 Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares
DBGCA the address bus bits [15:0] to a logic one or logic zero.
[15:0] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
This register can be accessed with a byte resolution, whereby DBGCD0, DBGCD1, DBGCD2, DBGCD3
map to DBGCD[31:0] respectively.
XGATE data accesses have a maximum width of 16-bits and are mapped to DBGCD[15:0].
Table 6-37. DBGCD Field Descriptions
Field Description
31–16 Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one
Bits[31:16] or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1.
(DBGCD0, 0 Compare corresponding data bit to a logic zero
DBGCD1) 1 Compare corresponding data bit to a logic one
15–0 Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one
Bits[15:0] or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1.
(DBGCD2, 0 Compare corresponding data bit to a logic zero
DBGCD3) 1 Compare corresponding data bit to a logic one
Read: Anytime.
Field Description
31–16 Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the
Bits[31:16] corresponding comparator data compare bits.
(DBGCDM0, 0 Do not compare corresponding data bit
DBGCDM1) 1 Compare corresponding data bit
15–0 Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the
Bits[15:0] corresponding comparator data compare bits.
(DBGCDM2, 0 Do not compare corresponding data bit
DBGCDM3) 1 Compare corresponding data bit
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-39. DBGDCTL Field Descriptions
Field(1) Description
5 Instruction Select — This bit configures the comparator to compare PC or data access addresses.
INST 0 Comparator compares addresses of data accesses
1 Comparator compares PC address
3 Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
RW associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
2 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
RWE associated comparator. This bit is ignored if INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
0 Enable Bit — Determines if comparator is enabled
COMPE 0 The comparator is not enabled
1 The comparator is enabled
1. If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored.
Table 6-40 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-41. DBGDAH, DBGDAM, DBGDAL Field Descriptions
Field Description
23–16 Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares
DBGDA the address bus bits [23:16] to a logic one or logic zero.
[23:16] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Field Description
15–0 Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares
DBGDA the address bus bits [15:0] to a logic one or logic zero.
[15:0] 0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
accesses). Furthermore, comparators A and C can compare the data buses to values stored in DBGXD3-0
and allow data bit masking.
The comparators can monitor the buses for an exact address or an address range. The comparator
configuration is controlled by the control register contents and the range control by the DBGC2 contents.
The comparator control register also allows the type of data access to be included in the comparison
through the use of the RWE and RW bits. The RWE bit controls whether the access type is compared for
the associated comparator and the RW bit selects either a read or write access for a valid match.
The INST bit in each comparator control register is used to determine the matching condition. By setting
INST, the comparator matches opcode addresses, whereby the databus, data mask, RW and RWE bits are
ignored. The comparator register must be loaded with the exact opcode address.
The comparator can be configured to match memory access addresses by clearing the INST bit.
Each comparator match can force a transition to another state sequencer state (see Section 6.4.3”).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is matched at a given address, this
address may not contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from, when tracing CPU accesses
in Detail mode. This is determined by the TRANGE bits in the DBGTCRH register. The TRANGE
encoding is shown in Table 6-10. If the TRANGE bits select a range definition using comparator D and
the COMPE bit is clear, then comparator D is configured for trace range definition. By setting the COMPE
bit the comparator is configured for address bus comparisons, the TRANGE bits are ignored and the
tracing range function is disabled. Similarly if the TRANGE bits select a range definition using comparator
C and the COMPE bit is clear, then comparator C is configured for trace range definition.
Match[0, 1, 2, 3] map directly to Comparators [A, B, C, D] respectively, except in range modes (see
Section 6.3.2.2”). Comparator priority rules are described in the event priority section (Section 6.4.3.5”).
If the comparator INST bit is set, the comparator address register contents are compared with the PC, the
data register contents and access type bits are ignored. The comparator address register must be loaded
with the address of the first opcode byte.
The fixed mapping of data comparator bytes to addresses within a 32-bit data field ensures data matches
independent of access size. To compare a single data byte within the 32-bit field, the other bytes within
that field must be masked using the corresponding data mask registers. This ensures that any access of that
byte (32-bit,16-bit or 8-bit) with matching data causes a match. If no bytes are masked then the data
comparator always compares all 32-bits and can only generate a match on a 32-bit access with correct 32-
bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even if
the contents of the addressed bytes match because all 32-bits must match. In Table 6-44 the Access
Address column refers to the address bits[1:0] of the lowest accessed address (most significant data byte).
Table 6-44. Data Register Use Dependency On CPU Access Type
Memory Address[2:0]
Access Access
Case 000 001 010 011 100 101 110
Address Size
1 00 32-bit DBGxD0 DBGxD1 DBGxD2 DBGxD3
2 01 32-bit DBGxD1 DBGxD2 DBGxD3 DBGxD0
3 10 32-bit DBGxD2 DBGxD3 DBGxD0 DBGxD1
4 11 32-bit DBGxD3 DBGxD0 DBGxD1 DBGxD2
5 00 16-bit DBGxD0 DBGxD1
6 01 16-bit DBGxD1 DBGxD2
7 10 16-bit DBGxD2 DBGxD3
Memory Address[2:0]
Access Access
Case 000 001 010 011 100 101 110
Address Size
8 11 16-bit DBGxD3 DBGxD0
9 00 8-bit DBGxD0
10 01 8-bit DBGxD1
11 10 8-bit DBGxD2
12 11 8-bit DBGxD3
13 00 8-bit DBGxD0
Denotes byte that is not accessed.
For a match of a 32-bit access with data compare, the address comparator must be loaded with the address
of the lowest accessed byte. For Case1 Table 6-44 this corresponds to 000, for Case2 it corresponds to 001.
To compare all 32-bits, it is required that no bits are masked.
When using the AB comparator pair for a range comparison, the data bus can be used for qualification by
using the comparator A data and data mask registers. Similarly when using the CD comparator pair for a
range comparison, the data bus can be used for qualification by using the comparator C data and data mask
registers. The DBGACTL/DBGCCTL RW and RWE bits can be used to qualify the range comparison on
either a read or a write access. The corresponding DBGBCTL/DBGDCTL bits are ignored. The
DBGACTL/DBGCCTL COMPE/INST bits are used for range comparisons. The DBGBCTL/DBGDCTL
COMPE/INST bits are ignored in range modes.
6.4.3 Events
Events are used as qualifiers for a state sequencer change of state. The state control register for the current
state determines the next state for each event. An event can immediately initiate a transition to the next
state sequencer state whereby the corresponding flag in DBGSR is set.
State 0 ARM = 1
(Disarmed) State1 State2
The state sequencer allows a defined sequence of events to provide a breakpoint and/or a trigger point for
tracing of data in the trace buffer. When the DBG module is armed by setting the ARM bit in the DBGC1
register, the state sequencer enters State1. Further transitions between the states are controlled by the state
control registers and depend upon event occurrences (see Section 6.4.3). From Final State the only
permitted transition is back to the disarmed State0. Transition between the states 1 to 3 is not restricted.
Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. If
breakpoints are enabled, then an event based transition to State0 generates the breakpoint request. A
transition to State0 resulting from writing “0” to the ARM bit does not generate a breakpoint request.
Using Begin-Alignment together with opcode address comparisons, if the instruction is about to be
executed then the trace is started. If the trigger is at the address of a COF instruction, whilst tracing COF
addresses, then that COF address is stored to the trace buffer. If breakpoints are enabled, the breakpoint is
generated upon entry into State0 on completion of the tracing session; thus the breakpoint does not occur
at the instruction boundary.
NOTE
When a CPU indexed jump instruction is executed, the destination address
is stored to the trace buffer on instruction completion, indicating the COF
has taken place. If an interrupt occurs simultaneously then the next
instruction carried out is actually from the interrupt service routine. The
instruction at the destination address of the original program flow gets
executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The NOP at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LD X,#SUB_1
MARK1: JMP (0,X) ; IRQ interrupt occurs during execution of this
MARK2: NOP ;
The Normal Mode trace buffer format is shown in the following tables. Whilst tracing in Normal or Loop1
modes each array line contains 2 data entries, thus in this case the DBGCNT[0] is incremented after each
separate entry. Information byte bits indicate if an entry is a source, destination or vector address.
The external event input can force trace buffer entries independent of COF occurrences, in which case the
EEVI bit is set and the PC value of the last instruction is stored to the trace buffer. If the external event
coincides with a COF buffer entry a single entry is made with the EEVI bit set.
Normal mode profiling with timestamp is possible when tracing from a single source by setting the
STAMP bit in DBGTCRL. This results in a different format (see Table 6-49).
Table 6-48. Normal and Loop1 Mode Trace Buffer Format without Timestamp
Table 6-48. Normal and Loop1 Mode Trace Buffer Format without Timestamp
CPU CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0
CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2
Table 6-49. Normal and Loop1 Mode Trace Buffer Format with Timestamp
Field Description
7–6 CPU Entry Type Field — Indicates the type of stored address of the trace buffer entry as described in Table 6-51
CET
3 Comparator Timestamp Indicator — This bit indicates if the trace buffer entry corresponds to a comparator
CTI timestamp.
0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow
1 Trace buffer entry initiated by comparator D match
2 External Event Indicator — This bit indicates if the trace buffer entry corresponds to an external event.
EEVI 0 Trace buffer entry not initiated by an external event
1 Trace buffer entry initiated by an external event
0 Timestamp Overflow Indicator — Indicates if the trace buffer entry corresponds to a timestamp overflow
TOVF 0 Trace buffer entry not initiated by a timestamp overflow
1 Trace buffer entry initiated by a timestamp overflow
Detail Mode data entries store the bytes aligned to the address of the MSB accessed (Byte1 Table 6-54).
Thus accesses split across 32-bit boundaries are wrapped around.
Table 6-54. Detail Mode Data Byte Alignment
Access Access
CDATA31 CDATA21 CDATA11 CDATA01
Address Size
00 32-bit Byte1 Byte2 Byte3 Byte4
01 32-bit Byte4 Byte1 Byte2 Byte3
10 32-bit Byte3 Byte4 Byte1 Byte2
11 32-bit Byte2 Byte3 Byte4 Byte1
00 24-bit Byte1 Byte2 Byte3
01 24-bit Byte1 Byte2 Byte3
10 24-bit Byte3 Byte1 Byte2
11 24-bit Byte2 Byte3 Byte1
00 16-bit Byte1 Byte2
01 16-bit Byte1 Byte2
10 16-bit Byte1 Byte2
11 16-bit Byte2 Byte1
00 8-bit Byte1
01 8-bit Byte1
10 8-bit Byte1
11 8-bit Byte1
Denotes byte that is not accessed.
Information Bytes
When tracing in Detail Mode, CINF provides information about the type of CPU access being made.
TSINF provides information about a timestamp. Bit1 indicates if the byte is a TSINF byte.
Table 6-55. CINF Field Descriptions
Field Description
7–6 Access Type Indicator — This field indicates the CPU access size.
CSZ 00 8-bit Access
0116-bit Access
10 24-bit Access
11 32-bit Access
5 Read/Write Indicator — Indicates if the corresponding stored address corresponds to a read or write access.
CRW 0 Write Access
1 Read Access
Field Description
3 Comparator Timestamp Indicator — This bit indicates if the trace buffer entry corresponds to a comparator
CTI timestamp.
0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow
1 Trace buffer entry initiated by comparator D match
2 Program Counter Valid Indicator — Indicates if the PC entry is valid on the timestamp line.
PC 0 Trace buffer entry does not include PC value
1 Trace buffer entry includes PC value
0 Timestamp Overflow Indicator — Indicates if the trace buffer entry corresponds to a timestamp overflow
TOVF 0 Trace buffer entry not initiated by a timestamp overflow
1 Trace buffer entry initiated by a timestamp overflow
in bytes[6:4], the other payload bytes may be compressed or complete addresses as indicated by the info
byte bits.
Table 6-57. Pure PC Mode Trace Buffer Format Single Source
If the info bit for byte3 indicates a full CPU PC address, whereby bytes[5:3] are used, then the info bit
mapped to byte[4] is redundant and the byte[6] is unused because a line overflow has occurred. Similarly
a base address stored in bytes[4:2] causes line overflow, so bytes[6:5] are unused.
CXINF[6:4] indicate how many bytes in a line contain valid data, since tracing may terminate before a
complete line has been filled.
7 6 5 4 3 2 1 0
CXINF MAT PLEC NB3 NB2 NB1 NB0
Figure 6-29. Pure PC Mode CXINF
Field Description
MAT Mid Aligned Trigger— This bit indicates a mid aligned trigger position. When a mid aligned trigger occurs, the
next trace buffer entry is a base address and the counter is incremented to a new line, independent of the number
of bytes used on the current line. The MAT bit is set on the current line, to indicate the position of the trigger.
When configured for begin or end aligned trigger, this bit has no meaning.
NOTE: In the case when ARM and TRIG are simultaneously set together in the same cycle that a new PC value
is registered, then this PC is stored to the same trace buffer line and MAT set.
0 Line filled without mid aligned trigger occurrence
1 Line last entry is the last PC entry before a mid aligned trigger
PLEC[2:0] Payload Entry Count— This field indicates the number of valid bytes in the trace buffer line
Binary encoding is used to indicate up to 7 valid bytes.
NBx Payload Compression Indicator— This field indicates if the corresponding payload byte is the lowest byte of a
base PC entry
0 Corresponding payload byte is a not the lowest byte of a base PC entry
1 Corresponding payload byte is the lowest byte of a base PC entry
Pure PC mode tracing does not support timestamps or external event entries.
6.4.5.3 Timestamp
When set, the STAMP bit in DBGTCRL configures the DBG to add a timestamp to trace buffer entries in
Normal, Loop1 and Detail trace buffer modes. The timestamp is generated from a 16-bit counter and is
stored to the trace buffer line each time a trace buffer entry is made.
The number of core clock cycles since the last entry equals the timestamp + 1. The core clock runs at twice
the frequency of the bus clock. The timestamp of the first trace buffer entry is 0x0000. With timestamps
enabled trace buffer entries are initiated in the following ways:
• according to the trace mode specification, for example COF PC addresses in Normal mode
• on a timestamp counter overflow
If the timestamp counter reaches 0xFFFF then a trace buffer entry is made, with timestamp=
0xFFFF and the timestamp overflow bit TOVF is set.
• on a match of comparator D
If STAMP and DSTAMP are set then comparator D is used for forcing trace buffer entries with
timestamps. The state control register settings determine if comparator D is also used to trigger the
state sequencer. Thus if the state control register configuration does not use comparator D, then it
is used solely for the timestamp function. If comparator D initiates a timestamp then the CTI bit is
set in the INFO byte. This can be used in Normal/Loop1 mode to indicate when a particular data
access occurs relative to the PC flow. For example when the timing of an access may be unclear
due to the use of indexes.
NOTE
If comparator D is configured to match a PC address then associated
timestamps trigger a trace buffer entry during execution of the previous
instruction. Thus the PC stored to the trace buffer is that of the previous
instruction.The comparator must contain the PC address of the instruction’s
first opcode byte
Timestamps are disabled in Pure PC mode.
pointer is initialized by each aligned write to DBGTB to point to the oldest data again. This enables an
interrupted trace buffer read sequence to be easily restarted from the oldest data entry. After reading all
trace buffer lines, the next read wraps around and returns the contents of line0.
The least significant word of each 64-bit wide array line is read out first. All bytes, including those
containing invalid information are read out.
CLOCK
PDOCLK
DATA
TBUF PDO
DEV TOOL
DBG
MCU
Figure 6-31 shows the profiling clock, PDOCLK, whose edges are offset from the bus clock, to ease setup
and hold time requirements relative to PDO, which is synchronous to the bus clock.
Figure 6-31. PDO Profiling Clock Control
STROBE
BUS CLOCK
PDO
CLOCK ENABLE
PDOCLK
The trace buffer is used as a temporary storage medium to store COF information before it is transmitted.
COF information can be transmitted whilst new information is written to the trace buffer. The trace buffer
data is transmitted at PDO least significant bit first. After the first trace buffer entry is made, transmission
begins in the first clock period in which no further data is written to the trace buffer.
If a trace buffer line transmission completes before the next trace buffer line is ready, then the clock output
is held at a constant level until the line is ready for transfer.
When the DBG module is disarmed but profiling transmission is ongoing, register write accesses are
suppressed and reading from the DBGTB returns the code 0xEEEE.
7 6 5 4 3 2 1 0
The INFO byte indicates the line format used. Up to 4 bytes of each line are dedicated to branch COFs.
Further bytes are used for storing indirect COF information (indexed jumps and interrupt vectors).
Indexed jumps force a full line entry with the PTIB format and require 3-bytes for the full 24-bit
destination address. Interrupts force a full line entry with the PTVB format, whereby vectors are stored as
a single byte and a 16-bit timestamp value is stored simultaneously to indicate the number of core clock
cycles relative to the previous COF. At each trace buffer entry the 16-bit timestamp counter is cleared. The
device vectors use address[8:0] whereby address[1:0] are constant zero for vectors. Thus the value stored
to the PTVB vector byte is equivalent to (Vector Address[8:1]).
After the PTS entry, the pointer increments and the DBG begins to fill the next line with direct COF
information. This continues until the direct COF field is full or an indirect COF occurs, then the INFO byte
and, if needed, indirect COF information are entered on that line and the pointer increments to the next line.
If a timestamp overflow occurs, indicating a 65536 bus clock cycles without COF, then an entry is made
with the TSOVF bit set, INFO[6] (Table 6-60) and profiling continues.
If a trace buffer overflow occurs, a final entry is made with the TBOVF bit set, profiling is terminated and
the DBG is disarmed. Trace buffer overflow occurs when the trace buffer contains 64 lines pending
transmission.
Whenever the DBG is disarmed during profiling, a final entry is made with the TERM bit set to indicate
the final entry.
When a final entry is made then by default the PTW line format is used, except if a COF occurs in the same
cycle in which case the corresponding PTIB/PTVB/PTHF format is used. Since the development tool
receives the INFO byte first, it can determine in advance the format of data it is about to receive. The
transmission of the INFO byte starts when a line is complete. Whole bytes are always transmitted. The
grey shaded bytes of Table 6-59 are not transmitted.
Figure 6-32. INFO byte encoding
7 6 5 4 3 2 1 0
0 TSOVF TBOVF TERM Line Format
Line0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0
Line1 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0
Line2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1
6.4.7 Breakpoints
Breakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced by
the following events
• Through comparator matches via Final State.
• Through software writing to the TRIG bit in the DBGC1 register via Final State.
• Through the external event input (DBGEEV) via Final State.
• Through a profiling trace buffer overflow event.
Breakpoints are not generated by software writes to DBGC1 that clear the ARM bit.
• When a reset occurs the debugger pulls BKGD low until the reset ends, forcing SSC mode entry.
• Then the debugger reads the reset flags to determine the cause of reset.
• If required, the debugger can read the trace buffer to see what happened just before reset. Since the
trace buffer and DBGCNT register are not affected by resets other than POR.
• The debugger configures and arms the DBG to start tracing on returning to application code.
• The debugger then sets the PC according to the reset flags.
• Then the debugger returns to user code with GO or STEP1.
V01.10 19-March-15 7.3.1 add feature description for S12ZVMC256 in case of non-aligned write to
memory data word containing a double bit ECC error
7.1 Introduction
The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft
errors, mainly generated by alpha radiation, can occur randomly during operation. "Soft error" means that
only the information inside the memory cell is corrupt; the memory cell itself is not damaged. A write
access with correct data solves the issue. If the ECC algorithm is able to correct the data, then the system
can use this corrected data without any issues. If the ECC algorithm is able to detect, but not correct the
error, then the system is able to ignore the memory read data to avoid system malfunction.
The ECC value is calculated based on an aligned 2 byte memory data word. The ECC algorithm is able to
detect and correct single bit ECC errors. Double bit ECC errors will be detected but the system is not able
to correct these errors. This kind of ECC code is called SECDED code. This ECC code requires 6
additional parity bits for each 2 byte data word.
7.1.1 Features
The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm.
The SRAM_ECC module includes the following features:
• SECDED ECC code
– Single bit error detection and correction per 2 byte data word
– Double bit error detection per 2 byte data word
• Memory initialization function
• Byte wide system memory write access
• Automatic single bit ECC error correction for read and write accesses
• Debug logic to read and write raw use data and ECC values
NOTE
Register Address = Module Base Address + Address Offset, where the
Module Base Address is defined at the MCU level and the Address Offset
is defined at the module level.
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0000 R 0 0 0 0 0 0 0 RDY
ECCSTAT W
0x0001 R 0 0 0 0 0 0 0
ECCIE SBEEIE
W
0x0002 R 0 0 0 0 0 0 0
ECCIF SBEEIF
W
0x0003 - 0x0006 R 0 0 0 0 0 0 0 0
Reserved W
0x0007 R
ECCDPTRH DPTR[23:16]
W
0x0008 R
ECCDPTRM DPTR[15:8]
W
0x0009 R 0
ECCDPTRL DPTR[7:1]
W
0x000A - 0x000B R 0 0 0 0 0 0 0 0
Reserved W
0x000C R
ECCDDH DDATA[15:8]
W
0x000D R
ECCDDL DDATA[7:0]
W
0x000E R 0 0
ECCDE DECC[5:0]
W
0x000F R 0 0 0 0 0
ECCDCMD ECCDRR ECCDW ECCDR
W
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 RDY
Reset 0 0 0 0 0 0 0 0
1. Read: Anytime
Write: Never
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
SBEEIE
W
Reset 0 0 0 0 0 0 0 0
1. Read: Anytime
Write: Anytime
Field Description
0 Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt.
SBEEIE 0 Interrupt request is disabled
1 Interrupt will be requested whenever SBEEIF is set
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
SBEEIF
W
Reset 0 0 0 0 0 0 0 0
1. Read: Anytime
Write: Anytime, write 1 to clear
Field Description
0 Single bit ECC Error Interrupt Flag — The flag is set to 1 when a single bit ECC error occurs.
SBEEIF 0 No occurrences of single bit ECC error since the last clearing of the flag
1 Single bit ECC error has occured since the last clearing of the flag
7 6 5 4 3 2 1 0
R
DPTR[23:16]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
DPTR[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R 0
DPTR[7:1]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
DPTR ECC Debug Pointer — This register contains the system memory address which will be used for a debug
[23:0] access. Address bits not relevant for SRAM address space are not writeable, so the software should read back
the pointer value to make sure the register contains the intended memory address. It is possible to write an
address value to this register which points outside the system memory. There is no additional monitoring of the
register content; therefore, the software must make sure that the address value points to the system memory
space.
7 6 5 4 3 2 1 0
R
DDATA[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
DDATA[7:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
DDATA ECC Debug Raw Data — This register contains the raw data which will be written into the system memory
[23:0] during a debug write command or the read data from the debug read command.
7 6 5 4 3 2 1 0
R 0 0
DECC[5:0]
W
Reset 0 0 0 0 0 0 0 0
1. Read: Anytime
Write: Anytime
Field Description
5:0 ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory
DECC[5:0] during a debug write command or the ECC read value from the debug read command.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
ECCDRR ECCDW ECCDR
W
Reset 0 0 0 0 0 0 0 0
1. Read: Anytime
Write: Anytime, in special mode only
Field Description
7 ECC Disable Read Repair Function— Writing one to this register bit will disable the automatic single bit ECC
ECCDRR error repair function during read access; see also chapter 7.3.7, “ECC Debug Behavior”.
0 Automatic single ECC error repair function is enabled
1 Automatic single ECC error repair function is disabled
1 ECC Debug Write Command — Writing one to this register bit will perform a debug write access, to the system
ECCDW memory. During this access the debug data word (DDATA) and the debug ECC value (DECC) will be written to
the system memory address defined by DPTR. If the debug write access is done, this bit is cleared. Writing 0
has no effect. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set).
0 ECC Debug Read Command — Writing one to this register bit will perform a debug read access from the system
ECCDR memory address defined by DPTR. If the debug read access is done, this bit is cleared and the raw memory read
data are available in register DDATA and the raw ECC value is available in register DECC. Writing 0 has no
effect. If the ECCDW and ECCDR bit are set at the same time, then only the ECCDW bit is set and the Debug
Write Command is performed. It is not possible to set this bit if the previous debug access is ongoing (ECCDW
or ECCDR bit set).
The single bit ECC error generates an interrupt when enabled. The double bit ECC errors are reported by
the SRAM_ECC module, but handled at MCU level. For more information, see the MMC description.
1. On S12ZVMC256 device only, the data are written into the memory even if a double bit ECC error was detected. The data
word written to the memory is undefined due to the correction based on a double bit ECC error signature. The written data word
is ECC clean.
2 byte use data ECC 2 byte use data ECC 4 byte read data from system memory
8.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit
(S12_CPMU_UHV_V10 and S12CPMU_UHV_V6).
• The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical crystal oscillators.
• The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the
required chip internal voltages and voltage monitors.
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
• The Internal Reference Clock (IRC1M) provides a 1MHz internal clock.
8.1.2 Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
• Supports crystals or resonators from 4MHz to 20MHz.
• High noise immunity due to input hysteresis and spike filtering.
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical crystals
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor
• Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
• Optional oscillator clock monitor reset
• Optional full swing mode for higher immunity against noise injection on the cost of higher power
consumption and increased emission
The Voltage Regulator (VREGAUTO) has the following features:
• Input voltage range from 6 to 18V (nominal operating range)
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR)
• Low-voltage reset (LVR)
• On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel.
• Voltage Regulator providing Full Performance Mode (FPM) and Reduced Performance Mode
(RPM)
• External ballast device support to reduce internal power dissipation
• Capable of supplying both the MCU internally plus external components
• Over-temperature interrupt
The Phase Locked Loop (PLL) has the following features:
• Highly accurate and phase locked frequency multiplier
• Configurable internal filter for best stability and lock time
• Frequency modulation for defined jitter and reduced emission
• Automatic frequency lock detector
• Interrupt request on entry or exit from locked condition
• PLL clock monitor reset
• Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
• PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference
clock
The Internal Reference Clock (IRC1M) has the following features:
• Frequency trimming
(A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after
reset, which can be overwritten by application if required)
• Temperature Coefficient (TC) trimming.
(A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC
trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM
register).
NOTE
The voltage regulator is active, providing the nominal supply voltages with
full current sourcing capability (see also Appendix for VREG electrical
parameters). The features ACLK clock source, Low Voltage Interrupt (LVI),
Low Voltage Reset (LVR) and Power-On Reset (POR) are available.
– Make sure the PLL configuration is valid for the selected oscillator frequency.
– Enable the external oscillator (OSCE bit).
– Wait for oscillator to start up (UPOSC=1).
– Select the Oscillator Clock (OSCCLK) as source of the Bus Clock (PLLSEL=0).
— The PLLCLK is on and used to qualify the external oscillator clock.
COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop
Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer
to CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode.
When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode and
COP is operating.
During Full Stop Mode the RTI counter halts.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0,
RTIOSCSEL=0).
• Pseudo Stop Mode (PSTP = 1 and OSCE=1)
External oscillator (XOSCLCP) continues to run.
— If COPOSCSEL1=0:
If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run
with a clock derived from the oscillator clock.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
— If COPOSCSEL1=1:
If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock
derived from the oscillator clock.
The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During
Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)
depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped
during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode.
For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to
CSAD bit description for details) occurs when entering or exiting (Pseudo, Full) Stop Mode.
When bit CSAD is clear the ACLK clock source is on for the COP during Pseudo Stop Mode
and COP is operating.
The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit
to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software
must wait for a minimum time equivalent to the startup-time of the external
oscillator tUPOSC before entering Pseudo Stop Mode.
Peak + OSCCLK
Detector Gain Control _
VDD=1.8V
VSS
Rf
C1 C2
VSS VSS
Figure 8-2. XOSCLCP Block Diagram
8.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
1K
Voltage BCTL E
Regulator B
C
VDDX
8.2.10 BCTLC — Base Control Pin for external PNP for VDDC power
domain
BCTLC is the ballast connection for the on chip voltage regulator for the VDDC power domain. It provides
the base current of an external BJT (PNP) of the VDDC supply. An additional 1K resistor between
emitter and base of the BJT is required.
8.2.11 BCTLS1 — Base Control Pin for external PNP for VDDS1 power
domain
BCTLS1 is the ballast connection for the on chip voltage regulator for the VDDS1 power domain. It
provides the base current of an external BJT (PNP) of the VDDS1 supply. An additional 1K resistor
between emitter and base of the BJT is required.
Figure 8-4 shows an application example for the external BCTLS1 pin.
1K
Voltage BCTLS1 E
Regulator B
C
SNPS1
8.2.12 BCTLS2 — Base Control Pin for external PNP for VDDS2 power
domain
BCTLS2 is the ballast connection for the on chip voltage regulator for the VDDS2 power domain. It
provides the base current of an external BJT (PNP) of the VDDS2 supply. An additional 1K resistor
between emitter and base of the BJT is required.
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
CPMU R 0 0 0 0 0 0 0 0
0x0000
RESERVED00 W
RESERVED R 0 0 0 0 U U U U
0x0001 CPMU W
VREGTRIM0
RESERVED R 0 0 U U U 0 0 0
0x0002 CPMU W
VREGTRIM1
R 0 0 0
0x0003 CPMURFLG PORF LVRF COPRF OMRF PMRF
W
CPMU R
0x0004 VCOFRQ[1:0] SYNDIV[5:0]
SYNR W
CPMU R 0 0
0x0005 REFFRQ[1:0] REFDIV[3:0]
REFDIV W
CPMU R 0 0 0
0x0006 POSTDIV[4:0]
POSTDIV W
R 0 0 LOCK 0 UPOSC
0x0007 CPMUIFLG RTIF LOCKIF OSCIF
W
R 0 0 0 0 0
0x0008 CPMUINT RTIE LOCKIE OSCIE
W
R COP RTI COP
0x0009 CPMUCLKS PLLSEL PSTP CSAD PRE PCE
W OSCSEL1 OSCSEL OSCSEL0
R 0 0 0 0 0 0
0x000A CPMUPLL FM1 FM0
W
R
0x000B CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
R 0 0 0
0x000C CPMUCOP WCOP RSBCK CR2 CR1 CR0
W WRTMASK
RESERVED R 0 0 0 0 0 0 0 0
0x000D
CPMUTEST0 W
= Unimplemented or Reserved
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
RESERVED R 0 0 0 0 0 0 0 0
0x000E
CPMUTEST1 W
CPMU R 0 0 0 0 0 0 0 0
0x000F
ARMCOP W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPMU R Reserved 0 0 HTDS
0x0010 VSEL HTE HTIE HTIF
HTCTL W
CPMU R 0 0 0 0 LVDS
0x0011 VDDSIE LVIE LVIF
LVCTL W
CPMU R 0 0
0x0012 APICLK APIES APIEA APIFE APIE APIF
APICTL W
R 0 0
0x0013 CPMUACLKTR ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0
W
R
0x0014 CPMUAPIRH APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
R
0x0015 CPMUAPIRL APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
RESERVED R 0 0 0 0 0 0 0 0
0x0016
CPMUTEST3 W
R 0 0 0
0x0017 CPMUHTTR HTOE HTTR3 HTTR2 HTTR1 HTTR0
W
CPMU R 0
0x0018 TCTRIM[4:0] IRCTRIM[9:8]
IRCTRIMH W
CPMU R
0x0019 IRCTRIM[7:0]
IRCTRIML W
R 0 0 0 0 0 0 0
0x001A CPMUOSC OSCE
W
R 0 0 0 0 0 0 0
0x001B CPMUPROT PROT
W
RESERVED R 0 0 0 0 0
0x001C 0 0 0
CPMUTEST2 W
CPMU R 0
0x001D VRH2EN VRH1EN EXTS2ON EXTS1ON EXTCON EXTXON INTXON
VREGCTL W
R 0 0 0 0 0 0
0x001E CPMUOSC2 OMRE OSCMOD
W
R SCS2 SCS1 LVDS2 LVDS1
0x001F CPMUVDDS SCS2IF SCS1IF LVS2IF LVS1IF
W
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special Mode
Read: Anytime
Write: Only in Special Mode
7 6 5 4 3 2 1 0
R 0 0 0
PORF LVRF COPRF OMRF PMRF
W
Read: Anytime
Write: Refer to each bit for individual write conditions
Field Description
6 Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
PORF a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5 Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs on the VDD, VDDF or VDDX
LVRF domain. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
3 COP Reset Flag — COPRF is set to 1 when a COP (Computer Operating Properly) reset occurs. Refer to 8.5.5,
COPRF “Computer Operating Properly Watchdog (COP) Reset and 8.3.2.12, “S12CPMU_UHV_V10_V6 COP Control
Register (CPMUCOP) for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 COP reset has not occurred.
1 COP reset has occurred.
1 Oscillator Clock Monitor Reset Flag — OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer
OMRF to8.5.3, “Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1. Writing a 0 has
no effect.
0 Loss of oscillator clock reset has not occurred.
1 Loss of oscillator clock reset has occurred.
0 PLL Clock Monitor Reset Flag — PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be
PMRF cleared by writing a 1. Writing a 0 has no effect.
0 Loss of PLL clock reset has not occurred.
1 Loss of PLL clock reset has occurred.
7 6 5 4 3 2 1 0
R
VCOFRQ[1:0] SYNDIV[5:0]
W
Reset 0 1 0 1 1 0 0 0
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
NOTE
fVCO must be within the specified VCO frequency lock range. Bus
frequency fbus must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 8-3. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
Table 8-3. VCO Clock Frequency Selection
7 6 5 4 3 2 1 0
R 0 0
REFFRQ[1:0] REFDIV[3:0]
W
Reset 0 0 0 0 1 1 1 1
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
f OSC
If XOSCLCP is enabled (OSCE=1) f REF = -------------------------------------
REFDIV + 1
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 8-4.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= fREF <=
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
7 6 5 4 3 2 1 0
R 0 0 0
POSTDIV[4:0]
W
Reset 0 0 0 0 0 0 1 1
= Unimplemented or Reserved
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect
f VCO
If PLL is locked (LOCK=1) f PLL = -----------------------------------------
POSTDIV + 1
f VCO
If PLL is not locked (LOCK=0) f PLL = ---------------
4
f PLL
If PLL is selected (PLLSEL=1) f bus = -------------
2
When changing the POSTDIV[4:0] value or PLL transitions to locked stated (lock=1), it takes up to 32
Bus Clock cycles until fPLL is at the desired target frequency. This is because the post divider gradually
changes (increases or decreases) fPLL in order to avoid sudden load changes for the on-chip voltage
regulator.
7 6 5 4 3 2 1 0
R 0 0 LOCK 0 UPOSC
RTIF LOCKIF OSCIF
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 8-5. CPMUIFLG Field Descriptions
Field Description
7 Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
RTIF a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
4 PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
LOCKIF writing a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3 Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is
LOCK unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL
stabilization time tlock.
0 VCOCLK is not within the desired tolerance of the target frequency.
fPLL = fVCO/4.
1 VCOCLK is within the desired tolerance of the target frequency.
fPLL = fVCO/(POSTDIV+1).
1 Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
OSCIF by writing a 1. Writing a 0 has no effect. If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
0 Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop
UPOSC Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
1 The oscillator is qualified by the PLL.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
RTIE LOCKIE OSCIE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Field Description
7 6 5 4 3 2 1 0
Reset 1 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write:
• Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
• All bits in Special Mode (if PROT=0).
• PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
• CSAD: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
• COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or
insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
• COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1
or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for
instance core clock etc.).
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL and COPOSCSEL was successful. This is because under
certain circumstances writes have no effect or bits are automatically
changed (see CPMUCLKS register and bit descriptions).
NOTE
When using the oscillator clock as system clock (write PLLSEL = 0) it is
highly recommended to enable the oscillator clock monitor reset feature
(write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset
feature is disabled (OMRE = 0) and the oscillator clock is used as system
clock, the system will stall in case of loss of oscillation.
Field Description
7 PLL Select Bit
PLLSEL This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
Entering Full Stop Mode sets the PLLSEL bit.
0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2).
1 System clocks are derived from PLLCLK, fbus = fPLL / 2.
6 Pseudo Stop Bit
PSTP This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode (Full Stop Mode).
1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator tUPOSC before entering Pseudo Stop Mode.
5 COP in Stop Mode ACLK Disable — If this bit is set the ACLK for the COP in Stop Mode is disabled. Hence the
CSAD COP is static while in Stop Mode and continues to operate after exit from Stop Mode.
For CSAD = 1 and COP is running on ACLK (COPOSCSEL1 = 1) the following applies:
Due to clock domain crossing synchronization there is a latency time of 2 ACLK cycles to enter Stop Mode.
After exit from STOP mode (when interrupt service routine is entered) the software has to wait for 2 ACLK cycles
before it is allowed to enter Stop mode again (STOP instruction). It is absolutely forbidden to enter Stop Mode
before this time of 2 ACLK cycles has elapsed.
0 COP running in Stop Mode (ACLK for COP enabled in Stop Mode).
1 COP stopped in Stop Mode (ACLK for COP disabled in Stop Mode)
4 COP Clock Select 1 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
COP (see also Table 8-8).
OSCSEL1 If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
COPOSCSEL1 selects the clock source to the COP to be either ACLK (derived from trimmable internal RC-
Oscillator) or clock selected via COPOSCSEL0 (IRCCLK or OSCCLK).
Changing the COPOSCSEL1 bit re-starts the COP time-out period.
COPOSCSEL1 can be set independent from value of UPOSC.
UPOSC= 0 does not clear the COPOSCSEL1 bit.
0 COP clock source defined by COPOSCSEL0
1 COP clock source is ACLK derived from a trimmable internal RC-Oscillator
3 RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
PRE 0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1.
Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not
be reset.
2 COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
PCE 0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will
not be reset.
Field Description
1 RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
0 COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
COP (see also Table 8-8)
OSCSEL0 If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK.
Changing the COPOSCSEL0 bit re-starts the COP time-out period.
COPOSCSEL0 can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL0 bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
0 0 IRCCLK
0 1 OSCCLK
1 x ACLK
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
FM1 FM0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Field Description
5, 4 PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
FM1, FM0 is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 8-10 for coding.
FM Amplitude /
FM1 FM0
fVCO Variation
0 0 FM off
0 1 1%
1 0 2%
1 1 4%
7 6 5 4 3 2 1 0
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status) re-
starts the RTI time-out period.
Field Description
7 Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
RTDEC 0 Binary based divider value. See Table 8-12
1 Decimal based divider value. See Table 8-13
6–4 Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See Table 8-
RTR[6:4] 12 and Table 8-13.
3–0 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
RTR[3:0] provide additional granularity.Table 8-12 and Table 8-13 show all possible divide values selectable by the
CPMURTI register.
RTR[6:4] =
RTR[3:0]
000 001 010 011 100 101 110 111
(OFF) (210) (211) (212) (213) (214) (215) (216)
0000 (1) OFF(1) 210 211 212 213 214 215 216
0001 (2) OFF 2x210 2x211 2x212 2x213 2x214 2x215 2x216
0010 (3) OFF 3x210 3x211 3x212 3x213 3x214 3x215 3x216
0011 (4) OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216
0100 (5) OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216
0101 (6) OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216
0110 (7) OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216
0111 (8) OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216
1000 (9) OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216
1001 (10) OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216
1010 (11) OFF 11x210 11x211 11x212 11x213 11x214 11x215 11x216
1011 (12) OFF 12x210 12x211 12x212 12x213 12x214 12x215 12x216
1100 (13) OFF 13x210 13x211 13x212 13x213 13x214 13x215 13x216
1101 (14) OFF 14x210 14x211 14x212 14x213 14x214 14x215 14x216
1110 (15) OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216
1111 (16) OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216
1. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
RTR[6:4] =
RTR[3:0]
000 001 010 011 100 101 110 111
(1x103) (2x103) (5x103) (10x103) (20x103) (50x103) (100x103) (200x103)
0000 (1) 1x103 2x103 5x103 10x103 20x103 50x103 100x103 200x103
0001 (2) 2x103 4x103 10x103 20x103 40x103 100x103 200x103 400x103
0010 (3) 3x103 6x103 15x103 30x103 60x103 150x103 300x103 600x103
0011 (4) 4x103 8x103 20x103 40x103 80x103 200x103 400x103 800x103
0100 (5) 5x103 10x103 25x103 50x103 100x103 250x103 500x103 1x106
0101 (6) 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1.2x106
0110 (7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106
0111 (8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106
1000 (9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.8x106
1001 (10) 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106
1010 (11) 11 x103 22x103 55x103 110x103 220x103 550x103 1.1x106 2.2x106
1011 (12) 12x103 24x103 60x103 120x103 240x103 600x103 1.2x106 2.4x106
1100 (13) 13x103 26x103 65x103 130x103 260x103 650x103 1.3x106 2.6x106
1101 (14) 14x103 28x103 70x103 140x103 280x103 700x103 1.4x106 2.8x106
1110 (15) 15x103 30x103 75x103 150x103 300x103 750x103 1.5x106 3x106
1111 (16) 16x103 32x103 80x103 160x103 320x103 800x103 1.6x106 3.2x106
7 6 5 4 3 2 1 0
R 0 0 0
WCOP RSBCK CR2 CR1 CR0
W WRTMASK
Reset F 0 0 0 0 F F F
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Read: Anytime
Write:
1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode
2. WCOP, CR2, CR1, CR0:
— Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect
— Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPOSCSEL1 bit (writing a different value) or loosing UPOSC status
while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
WRTMASK = 0.
2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.
Field Description
7 Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the
WCOP selected period. A write during the first 75% of the selected period generates a COP reset. As long as all writes
occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out
logic restarts and the user must wait until the next window before writing to CPMUARMCOP. Table 8-15 shows
the duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6 COP and RTI Stop in Active BDM Mode Bit
RSBCK 0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
5 Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
WRTMASK while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP.
(Does not count for “write once”.)
2–0 COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 8-15 and Table 8-16).
CR[2:0] Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-
out causes a System Reset. This can be avoided by periodically (before time-out) initializing the COP counter
via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special Mode
COPCLK
Cycles to time-out
CR2 CR1 CR0 (COPCLK is either IRCCLK or
OSCCLK depending on the
COPOSCSEL0 bit)
0 0 0 COP disabled
0 0 1 2 14
0 1 0 2 16
0 1 1 2 18
1 0 0 2 20
1 0 1 2 22
1 1 0 2 23
1 1 1 2 24
COPCLK
CR2 CR1 CR0 Cycles to time-out
(COPCLK is ACLK divided by 2)
0 0 0 COP disabled
0 0 1 27
0 1 0 29
0 1 1 2 11
1 0 0 2 13
1 0 1 2 15
1 1 0 2 16
1 1 1 2 17
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special Mode
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Only in Special Mode
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
Field Description
5 Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.
VSEL multiplexed to an internal Analog to Digital Converter channel). If not set, the die temperature proportional
voltage VHT of the temperature sensor can be accessed internally. See device level specification for connectivity.
For any of these access the HTE bit must be set.
0 An internal temperature proportional voltage VHT can be accessed internally.
1 Bandgap reference voltage VBG can be accessed internally.
3 High Temperature Sensor/Bandgap Voltage Enable Bit — This bit enables the high temperature sensor and
HTE bandgap voltage amplifier.
0 The temperature sensor and bandgap voltage amplifier is disabled.
1 The temperature sensor and bandgap voltage amplifier is enabled.
2 High Temperature Detect Status Bit — This read-only status bit reflects the temperature status. Writes have
HTDS no effect.
0 Junction Temperature is below level THTID or RPM.
1 Junction Temperature is above level THTIA and FPM.
1 High Temperature Interrupt Enable Bit
HTIE 0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0 High Temperature Interrupt Flag — HTIF is set to 1 when HTDS status bit changes. This flag can only be
HTIF cleared by writing a 1.
Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
NOTE
The voltage at the temperature sensor can be computed as follows:
VHT(temp) = VHT(150) - (150 - temp) * dVHT
VBG
Ref
TEMPSENSE ADC
VSEL Channel
C
HTD
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Field Description
Read: Anytime
Write: Anytime
Table 8-19. CPMUAPICTL Field Descriptions
Field Description
7 Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APICLK APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous Clock (ACLK) used as source.
1 Bus Clock used as source.
4 Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin
APIES API_EXTCLK as shown in Figure 8-25. See device level specification for connectivity of API_EXTCLK pin.
0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
every selected period with the size of half of the minimum period (APIR=0x0000 in Table 8-23).
1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Period.
3 Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
APIEA can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
2 Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
APIFE when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
1 Autonomous Periodical Interrupt Enable Bit
APIE 0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
0 Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
APIF This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an
interrupt request.
0 API time-out has not yet occurred.
1 API time-out has occurred.
APIES=0
API period
APIES=1
Read: Anytime
Write: Anytime
Table 8-20. CPMUACLKTR Field Descriptions
Field Description
7–2 Autonomous Clock Period Trimming Bits — See Table 8-21 for trimming effects. The ACLKTR[5:0] value
ACLKTR[5:0] represents a signed number influencing the ACLK period time.
111111 -1
000000 0 mid
000001 +1
.... increasing
011110 +30
011111 +31 highest
Read: Anytime
Write: Anytime if APIFE=0, Else writes have no effect.
Table 8-22. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field Description
15-0 Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See Table 8-
APIR[15:0] 23 for details of the effect of the autonomous periodical interrupt rate bits.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2)
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period
NOTE
For APICLK bit clear the first time-out period of the API will show a
latency time between two to three fACLK cycles due to synchronous clock
gate release when the API feature gets enabled (APIFE bit set).
Read: Anytime
Write: Only in Special Mode
Read: Anytime
Write: Anytime
Table 8-25. CPMUHTTR Field Descriptions
Field Description
7 High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
HTOE 0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
3–0 High Temperature Trimming Bits — See Table 8-26 for trimming effects.
HTTR[3:0]
1110
1111 highest lowest
15 14 13 12 11 10 9 8
R 0
TCTRIM[4:0] IRCTRIM[9:8]
W
Reset F F F F F 0 F F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency fIRC1M_TRIM.
7 6 5 4 3 2 1 0
R
IRCTRIM[7:0]
W
Reset F F F F F F F F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency fIRC1M_TRIM.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect
NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
Table 8-27. CPMUIRCTRIMH/L Field Descriptions
Field Description
IRCTRIM[5:0]
......
1MHz
600KHz
IRCTRIM[9:0]
$000 $3FF
frequency
111 0x11111
0 x11
] = ...
M[4:0 0x10101
RI 0x10100
T CT TC increases
0x10011
0x10010
0x10001
TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC)
0x00001
0x00010
0x00011
0x00100 TC decreases
TCT
R IM[ 0x00101
4:0 ]=0 ...
x01 0x01111
111
NOTE
The frequency is not necessarily linear with the temperature (in most cases
it will not be). The above diagram is meant only to give the direction
(positive or negative) of the variation of the TC, relative to the nominal TC.
Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the
temperature coefficient will be zero. These two combinations basically
switch off the TC compensation module, which results in the nominal TC of
the IRC1M.
NOTE
Since the IRC1M frequency is not a linear function of the temperature, but
more like a parabola, the above relative variation is only an indication and
should be considered with care.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
OSCE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
NOTE.
Write to this register clears the LOCK and UPOSC status bits.
Field Description
7 Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the
OSCE CPMIUFLG register indicates when the oscillation is stable and when OSCCLK can be selected as source of the
Bus Clock or source of the COP or RTI.If the oscillator clock monitor reset is enabled (OMRE = 1 in
CPMUOSC2 register), then a loss of oscillation will lead to an oscillator clock monitor reset.
0 External oscillator is disabled.
REFCLK for PLL is IRCCLK.
1 External oscillator is enabled.
Oscillator clock monitor is enabled.
External oscillator is qualified by PLLCLK.
REFCLK for PLL is the external oscillator clock divided by REFDIV.
If OSCE bit has been set (write “1”) the EXTAL and XTAL pins are exclusively reserved for the oscillator and they
can not be used anymore as general purpose I/O until the next system reset.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator tUPOSC before entering Pseudo Stop Mode.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PROT
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Field Description
PROT Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from
accidental overwrite (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the
PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. (see list of protected registers above).
Read: Anytime
Write: Only in Special Mode
Read: Anytime
Write: VRH2EN, VRH1EN, EXTS2ON, EXTS1ON anytime
Write: EXTCON, EXTXON, INTXON once in normal modes, anytime in special modes
Table 8-30. Effects of writing the EXTXON and INTXON bits
value of value of
EXTXON INTXON Write Access
to be written to be written
0 0 blocked, no effect
0 1 legal access
1 0 legal access
1 1 blocked, no effect
Field Description
7 VRH2 Enable Bit — This bits switches VDDS2 pin to VRH2 of ADC.
VRH2EN 0 VRH2 of ADC disconnected (open)
1 VRH2 of ADC connected to VDDS2.
In RPM VRH2 is always disconnected from VDDS2 regardless of the value of the VRH2EN bit.
6 VRH1 Enable Bit — This bits switches VDDS1 pin to VRH1 of ADC.
VRH1EN 0 VRH1 of ADC disconnected (open)
1 VRH1 of ADC connected to VDDS1.
In RPM VRH1 is always disconnected from VDDS1 regardless of the value of the VRH1EN bit.
5 External voltage regulator Enable Bit for VDDS2 domain — Should be enabled after system startup if VDDS2
EXTS2ON is used.
0 VDDS2 domain disabled
1 VDDS2 domain enabled. BCTLS2 pin is active.
Field Description
4 External voltage regulator Enable Bit for VDDS1 domain — Should be enabled after system startup if VDDS1
EXTS1ON is used.
0 VDDS1 domain disabled
1 VDDS1 domain enabled. BCTLS1 pin is active.
2 External voltage regulator Enable Bit for VDDC domain — Should be disabled after system startup if VDDC
EXTCON domain is not used. Must be kept set, if an internal or external CANPHY is present in the application.
0 VDDC domain disabled
1 VDDC domain enabled. BCTLC pin is active.
1 External voltage regulator Enable Bit for VDDX domain — Should be set to 1 if external BJT is present on
EXTXON the PCB, cleared otherwise.
0 VDDX control loop does not use external BJT
1 VDDX control loop uses external BJT
0 Internal voltage regulator Enable Bit for VDDX domain— Should be set to 1 if no external BJT is present on
INTXON the PCB, cleared otherwise.
0 VDDX control loop does not use internal power transistor
1 VDDX control loop uses internal power transistor
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
OMRE OSCMOD
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
Field Description
1 This bit enables the oscillator clock monitor reset. If OSCE bit in CPMUOSC register is 1, then the OMRE bit can
OMRE not be changed (writes will have no effect).
0 Oscillator clock monitor reset is disabled
1 Oscillator clock monitor reset is enabled
0 This bit selects the mode of the external oscillator (XOSCLCP)
OSCMOD If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect).
0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL))
1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL)
Read: Anytime
Write: SCS2IF, SCS1IF, LVS2IF and LVS1IF are write anytime,
SCS2, SCS, LVS2 and LVS1 are read only
Field Description
7 Short circuit on VDDS2 Status Bit —This read-only status bit reflects short circuit status on VDDS2 supply. This
SCS2 feature only makes sense if the VDDS2 supply is enabled (EXT2SON=1).
0 VRH2EN=0 or RPM or VDDS2 voltage level is less than or equal to VDDA supply.
1 VRH2EN=1and FPM and the voltage level on VDDS2 is greater than on VDDA supply.
6 Short circuit on VDDS1 Status Bit —This read-only status bit reflects short circuit status on VDDS1 supply. This
SCS1 feature only makes sense if the VDDS1 supply is enabled (EXT1SON=1).
0 VRH1EN=0 or RPM or VDDS1 voltage level is less than or equal to VDDA supply.
1 VRH1EN=1and FPM and the voltage level on VDDS1 is greater than on VDDA supply.
5 Low Voltage on VDDS2 Status Bit —This read-only status bit reflects the voltage level on VDDS2 supply.
LVDS2 If VDDS2 is enabled (EXTS2ON=1 in CPMUVREGCTL register), it is monitored that VDDS2 does not drop
below a voltage threshold VDDSM.
0 VDDS2 voltage is above VDDSM threshold or VDDS2 is disabled or RPM.
1 EXTS2ON =1 and VDDS2 voltage is below VDDSM threshold and FPM.
4 Low Voltage on VDDS1 Status Bit —This read-only status bit reflects the voltage level on VDDS1 supply.
LVDS1 If VDDS1 is enabled (EXTS1ON=1 in CPMUVREGCTL register), it is monitored that VDDS1 does not drop
below a voltage threshold VDDSM.
0 VDDS1 voltage is above VDDSM threshold or VDDS1 is disabled or RPM.
1 EXTS1ON =1 and VDDS1 voltage is below VDDSM threshold and FPM.
Field Description
3 Short circuit VDDS2 Interrupt Flag — SCS2IF is set to 1 when SCS2 status bit changes. This flag can only be
SCS2IF cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), SCS2IF causes an interrupt request.
0 No change in SCS2 bit.
1 SCS2 bit has changed.
2 Short circuit VDDS1 Interrupt Flag — SCS1IF is set to 1 when SCS1 status bit changes. This flag can only be
SCS1IF cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), SCS1IF causes an interrupt request.
0 No change in SCS1 bit.
1 SCS1 bit has changed.
1 Low-Voltage VDDS2 Interrupt Flag — LVS2IF is set to 1 when LVDS2 status bit changes. This flag can only
LVS2IF be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), LVS2IF causes an interrupt request.
0 No change in LVDS2 bit.
1 LVDS2 bit has changed.
0 Low-Voltage VDDS1 Interrupt Flag — LVS1IF is set to 1 when LVDS1 status bit changes. This flag can only
LVS1IF be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), LVS1IF causes an interrupt request.
0 No change in LVDS1 bit.
1 LVDS1 bit has changed.
f OSC
If oscillator is enabled (OSCE=1) f REF = -------------------------------------
REFDIV + 1
f VCO
If PLL is locked (LOCK=1) f PLL = -----------------------------------------
POSTDIV + 1
f VCO
If PLL is not locked (LOCK=0) f PLL = ---------------
4
f PLL
If PLL is selected (PLLSEL=1) f bus = -------------
2
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
Several examples of PLL divider settings are shown in Table 8-34. The following rules help to achieve
optimum stability and shortest lock time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
Table 8-34. Examples of PLL Divider Settings
fosc REFDIV[3:0] fREF REFFRQ[1:0] SYNDIV[5:0] fVCO VCOFRQ[1:0] POSTDIV[4:0] fPLL fbus
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with
the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated
based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal
filter capacitor, based on the width and direction of the correction pulse which leads to a higher or lower
VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the
VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison. So e.g. a failure in the reference clock will cause the PLL not to lock.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance
check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously
(during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK
will have stabilized to the programmed frequency.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within the tolerance, Lock, and is cleared when
the VCO frequency is out of the tolerance, unl.
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the
LOCK bit.In case of loss of reference clock (e.g. IRCCLK) the PLL will not lock or if already locked, then
it will unlock. The frequency of the VCOCLK will be very low and will depend on the value of the
VCOFRQ[1:0] bits.
256 cycles
fVCORST
tlock
LOCK
tSTP_REC
PLLCLK
tlock
LOCK
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for
details).
8.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in Figure 8-43.
Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going
into Full Stop Mode.
Figure 8-43. Full Stop Mode using Oscillator Clock as source of the Bus Clock
wake up
Core tSTP_REC
Clock
tlock
PLLCLK
tUPOSC
UPOSC
PLLSEL
automatically set when going into Full Stop Mode
Depending on the COP configuration there might be a significant latency time until COP is active again
after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP
clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).
OSCE
UPOSC
tUPOSC
select OSCCLK as Core/Bus Clock by writing PLLSEL to zero
PLLSEL
8.5 Resets
8.5.1 General
All reset sources are listed in Table 8-35. There is only one reset vector for all these reset sources. Refer
to MCU specification for reset vector address.
Table 8-35. Reset Summary
RESET
1 0 x x x x x Run (ACLK)
1 1 x x x x x Static (ACLK)
0 x 1 1 1 1 1 Run (OSCCLK)
0 x 1 1 0 0 x Static (IRCCLK)
0 x 1 1 0 1 x Static (IRCCLK)
0 x 1 0 0 x x Static (IRCCLK)
0 x 1 0 1 1 1 Static (OSCCLK)
0 x 0 1 1 1 1 Static (OSCCLK)
0 x 0 1 0 1 x Static (IRCCLK)
0 x 0 1 0 0 0 Static (IRCCLK)
0 x 0 0 1 1 1 Satic (OSCCLK)
0 x 0 0 0 1 1 Static (IRCCLK)
0 x 0 0 0 1 0 Static (IRCCLK)
0 x 0 0 0 0 0 Static (IRCCLK)
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
In MCU Normal Mode the COP time-out period (CR[2:0]) and COP window (WCOP) setting can be
automatically pre-loaded at reset release from NVM memory (if values are defined in the NVM by the
application). By default the COP is off and no window COP feature is enabled after reset release via NVM
memory. The COP control register CPMUCOP can be written once in an application in MCU Normal
Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM
memory at reset release. Any value for the new COP time-out period and COP window setting is allowed
except COP off value if the COP was enabled during pre-load via NVM memory.
The COP clock source select bits can not be pre-loaded via NVM memory at reset release. The IRC clock
is the default COP clock source out of reset.
The COP clock source select bits (COPOSCSEL0/1) and ACLK clock control bit in Stop Mode (CSAD)
can be modified until the CPMUCOP register write once has taken place. Therefore these control bits
should be modified before the final COP time-out period and window COP setting is written.
The CPMUCOP register access to modify the COP time-out period and window COP setting in MCU
Normal Mode after reset release must be done with the WRTMASK bit cleared otherwise the update is
ignored and this access does not count as the write once.
8.6 Interrupts
The interrupt vectors requested by the S12CPMU_UHV_V10_V6 are listed in Table 8-37. Refer to MCU
specification for related vector addresses and priorities.
CCR
Interrupt Source Local Enable
Mask
Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling
the oscillator can also cause a status change of UPOSC.
Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads
to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE
Loosing the oscillator status (UPOSC=0) affects the clock configuration of
the system1. This needs to be dealt with in application software.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable
frequency is desired.
See Table 8-21 for the trimming effect of ACLKTR[5:0].
NOTE
The first period after enabling the counter by APIFE might be reduced by
API start up delay tsdel.
It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and
enabling the external access with setting APIEA.
/* Initialize */
/* PLL Clock = 50 MHz, divide by one */
CPMUPOSTDIV = 0x00;
/* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */
/* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */
/* maximum frequency of the MCU */
CPMUSYNR = 0x00;
/* put your code to loop and wait for the LOCKIF and OSCIF or */
/* poll CPMUIFLG register until both UPOSC and LOCK status are “1” */
/* that is CPMUIFLG == 0x1B */
/* in case later in your code you want to disable the Oscillator and use the */
/* 1MHz IRCCLK as PLL reference clock */
/* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */
/* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */
/* maximum frequency of the MCU */
CPMUSYNR = 0x00;
Revision Revision
Sections Affected Description of Changes
Number Date
V1.37 19. Apr 2013 - Updates from review of reference manual to fix typos etc.
Provided more detailed information regarding captured information in
V1.38 30. Apr 2013 9.5.2.13/9-389 bits RIDX_IMD[5:0] for different scenarios of Sequence Abort Event
execution.
V1.39 02. Jul 2013 9.5.2.6/9-378 Update of: Timing considerations for Restart Mode
Feature V1 V2 V3
9.2 Introduction
The ADC12B_LBA is an n-channel multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ADC parameters and accuracy.
The List Based Architecture (LBA) provides flexible conversion sequence definition as well as flexible
oversampling. The order of channels to be converted can be freely defined. Also, multiple instantiations
of the module can be triggered simultaneously (matching sampling point across multiple module
instantiations).
There are four register bits which control the conversion flow (please refer to the description of register
ADCFLWCTL).
The four conversion flow control bits of register ADCFLWCTL can be modified in two different ways:
• Via data bus accesses
• Via internal interface Signals (Trigger, Restart, LoadOK, and Seq_Abort; see also Figure 9-2).
Each Interface Signal is associated with one conversion flow control bit.
For information regarding internal interface connectivity related to the conversion flow control please
refer to the device overview of the reference manual.
The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both
depending on the register access configuration bits ACC_CFG[1:0].
The four bits of register ADCFLWCTL reflect the captured request and status of the four internal interface
Signals (LoadOK, Trigger, Restart, and Seq_abort; see also Figure 9-2) if access configuration is set
accordingly and indicate event progress (when an event is processed and when it is finished).
Conversion flow error situations are captured by corresponding interrupt flags in the ADCEIF register.
There are two conversion flow control modes (Restart Mode, Trigger Mode). Each mode causes a certain
behavior of the conversion flow control bits which can be selected according to the application needs.
Please refer to Section 9.5.2.1, “ADC Control Register 0 (ADCCTL_0) and Section 9.6.3.2.4, “The two
conversion flow control Mode Configurations for more information regarding conversion flow control.
Because internal components of the ADC are turned on/off with bit ADC_EN, the ADC requires a
recovery time period (tREC) after ADC is enabled until the first conversion can be launched via a trigger.
When bit ADC_EN gets cleared (transition from 1’b1 to 1’b0) any ongoing conversion sequence will be
aborted and pending results, or the result of current conversion, gets discarded (not stored). The ADC
cannot be re-enabled before any pending action or action in process is finished respectively aborted, which
could take up to a maximum latency time of tDISABLE (see device level specification for more details).
After exiting MCU Stop Mode, the following happens in the order given with expected event(s)
depending on the conversion flow control mode:
— In ADC conversion flow control mode “Trigger Mode” a Restart Event is expected to
simultaneously set bits TRIG and RSTA, causing the ADC to execute the Restart Event
(CMD_IDX and RVL_IDX cleared) followed by the Trigger Event. The Restart Event can be
generated automatically after exit from MCU Stop Mode if bit AUT_RSTA is set.
— In ADC conversion flow control mode “Restart Mode”, a Restart Event is expected to set bit
RSTA only (ADC already aborted at MCU Stop Mode entry hence bit SEQA must not be set
simultaneously) causing the ADC to execute the Restart Event (CDM_IDX and RVL_IDX
cleared). The Restart Event can be generated automatically after exit from MCU Stop Mode if
bit AUT_RSTA is set.
— The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Stop Mode
request. Hence the same buffer will be used after exit from Stop Mode that was used when the
Stop Mode request occurred.
NOTE
In principle, the MCU could stay in Wait Mode for a shorter period of time
than the ADC needs to abort an ongoing conversion (range of µµµµs).
Therefore in case a Sequence Abort Event is issued automatically due to
MCU Wait Mode request a following Restart Event after exit from MCU
Wait Mode can not be executed before ADC has finished this Sequence
Abort Event. The Restart Event is detected but it is pending.
This applies in case MCU Wait Mode is exited before ADC has finished the
Sequence Abort Event and a Restart Event is issued immediately after exit
from MCU Wait Mode. Bit READY can be used by software to detect when
the Restart Event can be issued without latency time in processing the event
(see also Figure 9-1).
AN3 AN1 AN4 IN5 AN6 AN1 AN3 AN1 AN4 AN5 AN2 AN0
Sequence_n Sequence_0 Sequence_1
Wait Mode READY=1’b1 EOS
entry Earliest point of time to issue
Abort Restart Event without latency
CSL_0 Active Idle Active
t
Figure 9-1. Conversion Flow Control Diagram - Wait Mode (SWAI=1’b1, AUT_RSTA=1’b0)
see reference
manual for
connectivity DMA access
information ADC Comm_0
regarding ADC
internal interface Temperature Comm_1
Sense ..........
Internal_7 ..........
Idle/
........... Active
Internal_6
.......... Command
Internal_5 ........... Sequence Alternative-
Internal_4 ........... List Command
int. ........... (RAM/
Internal_3 Sequence
Channel NVM)
........... List
Internal_2 MUX ........... (RAM/
VREG_sense Comm 63 NVM)
DMA access
VRH_2 (V3) Result_0
Result_1
VRH_1 .......... active
VRH_0 .......... Conversion
Successive ........... Result List
VRL_1 (V1, V2) Approximation .......... (RAM)
...........
VRL_0 Register (SAR) ...........
and C-DAC ........... Alternative
........... Result
VDDA ........... List
Result 63 (RAM)
VSSA
Final +
ANx
..... + Buffer -
ext.
Buffer Comparator
AN2 Channel AMP
MUX -
AN1
PIM ADC12B_LBA
R 0 0 RIDX_IMD[5:0]
0x000F ADCIMDRI_1
W
= Unimplemented or Reserved
Figure 9-3. ADC12B_LBA Register Summary (Sheet 1 of 3)
= Unimplemented or Reserved
Figure 9-3. ADC12B_LBA Register Summary (Sheet 2 of 3)
= Unimplemented or Reserved
Figure 9-3. ADC12B_LBA Register Summary (Sheet 3 of 3)
Field Description
15 ADC Enable Bit — This bit enables the ADC (e.g. sample buffer amplifier etc.) and controls accessibility of ADC
ADC_EN register bits. When this bit gets cleared any ongoing conversion sequence will be aborted and pending results
or the result of current conversion gets discarded (not stored). The ADC cannot be re-enabled before any
pending action or action in process is finished or aborted, which could take up to a maximum latency time of
tDISABLE (see device reference manual for more details).
Because internal components of the ADC are turned on/off with this bit, the ADC requires a recovery time period
(tREC) after ADC is enabled until the first conversion can be launched via a trigger.
0 ADC disabled.
1 ADC enabled.
14 ADC Soft-Reset — This bit causes an ADC Soft-Reset if set after a severe error occurred (see list of severe
ADC_SR errors in Section 9.5.2.9, “ADC Error Interrupt Flag Register (ADCEIF) that causes the ADC to cease operation).
It clears all overrun flags and error flags and forces the ADC state machine to its idle state. It also clears the
Command Index Register, the Result Index Register, and the CSL_SEL and RVL_SEL bits (to be ready for a new
control sequence to load new command and start execution again from top of selected CSL).
A severe error occurs if an error flag is set which cause the ADC to cease operation.
In order to make the ADC operational again an ADC Soft-Reset must be issued.
Once this bit is set it can not be cleared by writing any value. It is cleared only by ADC hardware after the Soft-
Reset has been executed.
0 No ADC Soft-Reset issued.
1 Issue ADC Soft-Reset.
13 Freeze Mode Configuration — This bit influences conversion flow during Freeze Mode.
FRZ_MOD 0 ADC continues conversion in Freeze Mode.
1 ADC freezes the conversion at next conversion boundary at Freeze Mode entry.
12 Wait Mode Configuration — This bit influences conversion flow during Wait Mode.
SWAI 0 ADC continues conversion in Wait Mode.
1 ADC halts the conversion at next conversion boundary at Wait Mode entry.
Field Description
11-10 ADCFLWCTL Register Access Configuration — These bits define if the register ADCFLWCTL is controlled via
ACC_CFG[1:0] internal interface only or data bus only or both. See Table 9-4. for more details.
9 Control Of Conversion Result Storage and RSTAR_EIF flag setting at Sequence Abort or Restart Event — This
STR_SEQA bit controls conversion result storage and RSTAR_EIF flag setting when a Sequence Abort Event or Restart
Event occurs as follows:
If STR_SEQA = 1’b0 and if a:
• Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is not stored
and the respective conversion complete flag is not set
• Restart Event only is issued before the last conversion of a CSL is finished and no Sequence Abort Event is
in process (SEQA clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware
If STR_SEQA = 1’b1 and if a:
• Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and
the respective conversion complete flag is set and Intermediate Result Information Register is updated.
• Restart Event only occurs during the last conversion of a CSL and no Sequence Abort Event is in process
(SEQA clear) does not set the RSTA_EIF error flag
• Restart Event only is issued before the CSL is finished and no Sequence Abort Event is in process (SEQA
clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware
8 (Conversion Flow Control) Mode Configuration — This bit defines the conversion flow control after a Restart
MOD_CFG Event and after execution of the “End Of List” command type:
- Restart Mode
- Trigger Mode
(For more details please see also section Section 9.6.3.2, “Introduction of the Programmer’s Model and
following.)
0 “Restart Mode” selected.
1 “Trigger Mode” selected.
NOTE
Each conversion flow control bit (SEQA, RSTA, TRIG, LDOK) must be
controlled by software or internal interface according to the requirements
described in Section 9.6.3.2.4, “The two conversion flow control Mode
Configurations and overview summary in Table 9-11.
Field Description
7 CSL Buffer Mode Select Bit — This bit defines the CSL buffer mode. This bit is only writable if ADC_EN is clear.
CSL_BMOD 0 CSL single buffer mode.
1 CSL double buffer mode.
6 RVL Buffer Mode Select Bit — This bit defines the RVL buffer mode.
RVL_BMOD 0 RVL single buffer mode
1 RVL double buffer mode
5 Special Mode Access Control Bit — This bit controls register access rights in MCU Special Mode. This bit is
SMOD_ACC automatically cleared when leaving MCU Special Mode.
Note: When this bit is set also the ADCCMD register is writeable via the data bus to allow modification of the
current command for debugging purpose. But this is only possible if the current command is not already
processed (conversion not started).
Please see access details given for each register.
Care must be taken when modifying ADC registers while bit SMOD_ACC is set to not corrupt a possible ongoing
conversion.
0 Normal user access - Register write restrictions exist as specified for each bit.
1 Special access - Register write restrictions are lifted.
4 Automatic Restart Event after exit from MCU Stop and Wait Mode (SWAI set) — This bit controls if a Restart
AUT_RSTA Event is automatically generated after exit from MCU Stop Mode or Wait Mode with bit SWAI set. It can be
configured for ADC conversion flow control mode “Trigger Mode” and “Restart Mode” (anytime during application
runtime).
0 No automatic Restart Event after exit from MCU Stop Mode.
1 Automatic Restart Event occurs after exit from MCU Stop Mode.
Field Description
7 Command Sequence List Select bit — This bit controls and indicates which ADC Command List is active. This
CSL_SEL bit can only be written if ADC_EN bit is clear. This bit toggles in CSL double buffer mode when no conversion or
conversion sequence is ongoing and bit LDOK is set and bit RSTA is set. In CSL single buffer mode this bit is
forced to 1’b0 by bit CSL_BMOD.
0 ADC Command List 0 is active.
1 ADC Command List 1 is active.
6 Result Value List Select Bit — This bit controls and indicates which ADC Result List is active. This bit can only
RVL_SEL be written if bit ADC_EN is clear. After storage of the initial Result Value List this bit toggles in RVL double buffer
mode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted.
In RVL single buffer mode this bit is forced to 1’b0 by bit RVL_BMOD.
Please see also Section 9.3.1.2, “MCU Operating Modes for information regarding Result List usage in case of
Stop or Wait Mode.
0 ADC Result List 0 is active.
1 ADC Result List 1 is active.
5 Double Bit ECC Error Flag — This flag indicates that a double bit ECC error occurred during conversion
DBECC_ERR command load or result storage and ADC ceases operation.
In order to make the ADC operational again an ADC Soft-Reset must be issued.
This bit is cleared if bit ADC_EN is clear.
0 No double bit ECC error occurred.
1 A double bit ECC error occurred.
3 Ready For Restart Event Flag — This flag indicates that ADC is in its idle state and ready for a Restart Event.
READY It can be used to verify after exit from Wait Mode if a Restart Event can be issued and processed immediately
without any latency time due to an ongoing Sequence Abort Event after exit from MCU Wait Mode (see also the
Note in Section 9.3.1.2, “MCU Operating Modes).
0 ADC not in idle state.
1 ADC is in idle state.
Field Description
6-0 ADC Clock Prescaler — These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency
PRS[6:0] is calculated as follows:
f BUS
f A TD CLK = ------------------------------------
2x PRS + 1
Refer to Device Specification for allowed frequency range of fATDCLK.
Field Description
7 Result Register Data Justification — Conversion result data format is always unsigned. This bit controls
DJM justification of conversion result data in the conversion result list.
0 Left justified data in the conversion result list.
1 Right justified data in the conversion result list.
2-0 ADC Resolution Select — These bits select the resolution of conversion results. See Table 9-9 for coding.
SRES[2:0]
0 0 0 8-bit data
1.
0 0 1 Reserved
0 1 0 10-bit data
1.
0 1 1 Reserved
1 0 0 12-bit data
(1)
1 x x Reserved
Timing considerations (Trigger Event - channel sample start) depending on ADC mode configuration:
• Restart Mode
When the Restart Event has been processed (initial command of current CSL is loaded) it takes two
Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from the Trigger Event (bit
TRIG set) until the select channel starts to sample.
During a conversion sequence (back to back conversions) it takes five Bus Clock cycles plus two
ADC conversion clock cycles (pump phase) from current conversion period end until the newly
selected channel is sampled in the following conversion period.
• Trigger Mode
When a Restart Event occurs a Trigger Event is issued simultaneously. The time required to process
the Restart Event is mainly defined by the internal read data bus availability and therefore can vary.
In this mode the Trigger Event is processed immediately after the Restart Event is finished and both
conversion flow control bits are cleared simultaneously. From de-assert of bit TRIG until sampling
begins five Bus Clock cycles are required. Hence from occurrence of a Restart Event until channel
sampling it takes five Bus Clock cycles plus an uncertainty of a few Bus Clock cycles.
For more details regarding the sample phase please refer to Section 9.6.2.2, “Sample and Hold Machine with Sample Buffer
Amplifier.
Field Description
7 Conversion Sequence Abort Event — This bit indicates that a conversion sequence abort event is in progress.
SEQA When this bit is set the ongoing conversion sequence and current CSL will be aborted at the next conversion
boundary. This bit gets cleared when the ongoing conversion sequence is aborted and ADC is idle.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See
Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for more
details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “Seq_Abort” if access control is configured accordingly
via ACC_CFG[1:0]. After being set an additional request via the internal interface Signal “Seq_Abort” causes an
overrun. See also conversion flow control in case of overrun situations.
General:
In both conversion flow control modes (Restart Mode and Trigger Mode) when bit RSTA gets set automatically
bit SEQA gets set when the ADC has not reached one of the following scenarios:
- A Sequence Abort request is about to be executed or has been executed.
- “End Of List” command type has been executed or is about to be executed
In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart
Request.
0 No conversion sequence abort request.
1 Conversion sequence abort request.
6 Conversion Sequence Trigger Bit — This bit starts a conversion sequence if set and no conversion or
TRIG conversion sequence is ongoing. This bit is cleared when the first conversion of a sequence starts to sample.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
After being set this bit can not be cleared by writing a value of 1’b1 instead the error flag TRIG_EIF is set. See
also Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for
more details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “Trigger” if access control is configured accordingly via
ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the flag
TRIG_EIF to be set.
0 No conversion sequence trigger.
1 Trigger to start conversion sequence.
Field Description
5 Restart Event (Restart from Top of Command Sequence List) — This bit indicates that a Restart Event is
RSTA executed. The ADC loads the conversion command from top of the active Sequence Command List when no
conversion or conversion sequence is ongoing. This bit is cleared when the first conversion command of the
sequence from top of active Sequence Command List has been loaded into the ADCCMD register.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See also
Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for more
details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “Restart” if access control is configured accordingly via
ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Restart“ causes an overrun.
See conversion flow control in case of overrun situations for more details.
General:
In conversion flow control mode “Trigger Mode” when bit RSTA gets set bit TRIG is set simultaneously if one of
the following has been executed:
- “End Of List” command type has been executed or is about to be executed
- Sequence Abort Event
0 Continue with commands from active Sequence Command List.
1 Restart from top of active Sequence Command List.
4 Load OK for alternative Command Sequence List — This bit indicates if the preparation of the alternative
LDOK Sequence Command List is done and Command Sequence List must be swapped with the Restart Event. This
bit is cleared when bit RSTA is set (Restart Event executed) and the Command Sequence List got swapped.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
This bit is forced to zero if bit CSL_BMOD is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
To set bit LDOK the bits LDOK and RSTA must be written simultaneously.
After being set this bit can not be cleared by writing a value of 1’b1. See also Section 9.6.3.2.6, “Conversion flow
control in case of conversion sequence control bit overrun scenarios for more details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “LoadOK” and “Restart” if access control is configured
accordingly via ACC_CFG[1:0]. With the assertion of Interface Signal “Restart” the interface Signal “LoadOK” is
evaluated and bit LDOK set accordingly (bit LDOK set if Interface Signal “LoadOK” asserted when Interface
Signal “Restart” asserts).
General:
Only in “Restart Mode” if a Restart Event occurs without bit LDOK being set the error flag LDOK_EIF is set except
when the respective Restart Request occurred after or simultaneously with a Sequence Abort Request.
The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after:
- ADC got enabled
- Exit from Stop Mode
- ADC Soft-Reset
0 Load of alternative list done.
1 Load alternative list.
RSTA TRIG SEQA LDOK Conversion Flow Control Conversion Flow Control
Mode Scenario
For a detailed description of all conversion flow control bit scenarios please see also Section 9.6.3.2.4,
“The two conversion flow control Mode Configurations, Section 9.6.3.2.5, “The four ADC conversion
flow control bits and Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control
bit overrun scenarios
Field Description
7 Illegal Access Error Interrupt Enable Bit — This bit enables the illegal access error interrupt.
IA_EIE 0 Illegal access error interrupt disabled.
1 Illegal access error interrupt enabled.
6 Command Value Error Interrupt Enable Bit — This bit enables the command value error interrupt.
CMD_EIE 0 Command value interrupt disabled.
1 Command value interrupt enabled.
5 ”End Of List” Error Interrupt Enable Bit — This bit enables the “End Of List” error interrupt.
EOL_EIE 0 “End Of List” error interrupt disabled.
1 “End Of List” error interrupt enabled.
3 Conversion Sequence Trigger Error Interrupt Enable Bit — This bit enables the conversion sequence trigger
TRIG_EIE error interrupt.
0 Conversion sequence trigger error interrupt disabled.
1 Conversion sequence trigger error interrupt enabled.
2 Restart Request Error Interrupt Enable Bit— This bit enables the restart request error interrupt.
RSTAR_EIE 0 Restart Request error interrupt disabled.
1 Restart Request error interrupt enabled.
1 Load OK Error Interrupt Enable Bit — This bit enables the Load OK error interrupt.
LDOK_EIE 0 Load OK error interrupt disabled.
1 Load OK error interrupt enabled.
Field Description
7 Conversion Sequence Abort Done Interrupt Enable Bit — This bit enables the conversion sequence abort
SEQAD_IE event done interrupt.
0 Conversion sequence abort event done interrupt disabled.
1 Conversion sequence abort event done interrupt enabled.
6 ADCCONIF Register Flags Overrun Interrupt Enable — This bit enables the flag which indicates if an overrun
CONIF_OIE situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag.
0 No ADCCONIF Register Flag overrun occurred.
1 ADCCONIF Register Flag overrun occurred.
Field Description
7 Illegal Access Error Interrupt Flag — This flag indicates that storing the conversion result caused an illegal
IA_EIF access error or conversion command loading from outside system RAM or NVM area occurred.
The ADC ceases operation if this error flag is set (issue of type severe).
0 No illegal access error occurred.
1 An illegal access error occurred.
6 Command Value Error Interrupt Flag — This flag indicates that an invalid command is loaded (Any command
CMD_EIF that contains reserved bit settings) or illegal format setting selected (reserved SRES[2:0] bit settings).
The ADC ceases operation if this error flag is set (issue of type severe).
0 Valid conversion command loaded.
1 Invalid conversion command loaded.
5 “End Of List” Error Interrupt Flag — This flag indicates a missing “End Of List” command type in current
EOL_EIF executed CSL.
The ADC ceases operation if this error flag is set (issue of type severe).
0 No “End Of List” error.
1 “End Of List” command type missing in current executed CSL.
Field Description
3 Trigger Error Interrupt Flag — This flag indicates that a trigger error occurred.
TRIG_EIF This flag is set in “Restart” Mode when a conversion sequence got aborted and no Restart Event occurred before
the Trigger Event or if the Trigger Event occurred before the Restart Event was finished (conversion command
has been loaded).
This flag is set in “Trigger” Mode when a Trigger Event occurs before the Restart Event is issued to start
conversion of the initial Command Sequence List. In “Trigger” Mode only a Restart Event is required to start
conversion of the initial Command Sequence List.
This flag is set when a Trigger Event occurs before a conversion sequence got finished.
This flag is also set if a Trigger occurs while a Trigger Event is just processed - first conversion command of a
sequence is beginning to sample (see also Section 9.6.3.2.6, “Conversion flow control in case of conversion
sequence control bit overrun scenarios).
This flag is also set if the Trigger Event occurs automatically generated by hardware in “Trigger Mode” due to a
Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface.
The ADC ceases operation if this error flag is set (issue of type severe).
0 No trigger error occurred.
1 A trigger error occurred.
2 Restart Request Error Interrupt Flag — This flag indicates a flow control issue. It is set when a Restart Request
RSTAR_EIF occurs after a Trigger Event and before one of the following conditions was reached:
- The “End Of List” command type has been executed
- Depending on bit STR_SEQA if the “End Of List” command type is about to be executed
- The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request.
The ADC continues operation if this error flag is set.
This flag is not set for Restart Request overrun scenarios (see also Section 9.6.3.2.6, “Conversion flow control
in case of conversion sequence control bit overrun scenarios).
0 No Restart request error situation occurred.
1 Restart request error situation occurred.
1 Load OK Error Interrupt Flag — This flag can only be set in “Restart Mode”. It indicates that a Restart Request
LDOK_EIF occurred without LDOK. This flag is not set if a Sequence Abort Event is already in process (bit SEQA set)
when the Restart Request occurs or a Sequence Abort Request occurs simultaneously with the Restart
Request.
The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after:
- ADC got enabled
- Exit from Stop Mode
- ADC Soft-Reset
- ADC used in CSL single buffer mode
The ADC continues operation if this error flag is set.
0 No Load OK error situation occurred.
1 Load OK error situation occurred.
Field Description
7 Conversion Sequence Abort Done Interrupt Flag — This flag is set when the Sequence Abort Event has been
SEQAD_IF executed except the Sequence Abort Event occurred by hardware in order to be able to enter MCU Stop Mode
or Wait Mode with bit SWAI set.This flag is also not set if the Sequence Abort request occurs during execution
of the last conversion command of a CSL and bit STR_SEQA being set.
0 No conversion sequence abort request occurred.
1 A conversion sequence abort request occurred.
6 ADCCONIF Register Flags Overrun Interrupt Flag — This flag indicates if an overrun situation occurred for
CONIF_OIF one of the CON_IF[15:1] flags or for the EOL_IF flag. In RVL single buffer mode (RVL_BMOD clear) an overrun
of the EOL_IF flag is not indicated (For more information please see Note below).
0 No ADCCONIF Register Flag overrun occurred.
1 ADCCONIF Register Flag overrun occurred.
NOTE
In RVL double buffer mode a conversion interrupt flag (CON_IF[15:1]) or
End Of List interrupt flag (EOL_IF) overrun is detected if one of these bits
is set when it should be set again due to conversion command execution.
In RVL single buffer mode a conversion interrupt flag (CON_IF[15:1])
overrun is detected only. The overrun is detected if any of the conversion
interrupt flags (CON_IF[15:1]) is set while the first conversion result of a
CSL is stored (result of first conversion from top of CSL is stored).
Read: Anytime
Write: Anytime
Table 9-16. ADCCONIE Field Descriptions
Field Description
15-1 Conversion Interrupt Enable Bits — These bits enable the individual interrupts which can be triggered via
CON_IE[15:1] interrupt flags CON_IF[15:1].
0 ADC conversion interrupt disabled.
1 ADC conversion interrupt enabled.
0 End Of List Interrupt Enable Bit — This bit enables the end of conversion sequence list interrupt.
EOL_IE 0 End of list interrupt disabled.
1 End of list interrupt enabled.
Read: Anytime
Write: Anytime
Table 9-17. ADCCONIF Field Descriptions
Field Description
15-1 Conversion Interrupt Flags — These bits could be set by the binary coded interrupt select bits
CON_IF[15:1] INTFLG_SEL[3:0] when the corresponding conversion command has been processed and related data has
been stored to RAM.
See also notes below.
0 End Of List Interrupt Flag — This bit is set by the binary coded conversion command type select bits
EOL_IF CMD_SEL[1:0] for “end of list” type of commands and after such a command has been processed and the
related data has been stored RAM.
See also second note below
NOTE
These bits can be used to indicate if a certain packet of conversion results is
available. Clearing a flag indicates that conversion results have been
retrieved by software and the flag can be used again (see also Section 9.9.6,
“RVL swapping in RVL double buffer mode and related registers
ADCIMDRI and ADCEOLRI.
NOTE
Overrun situation of a flag CON_IF[15:1] and EOL_IF are indicated by flag
CONIF_OIF.
Read: Anytime
Write: Never
Table 9-18. ADCIMDRI Field Descriptions
Field Description
15 Active CSL At Intermediate Event — This bit indicates the active (used) CSL at the occurrence of a conversion
CSL_IMD interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort
Event gets executed.
0 CSL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
1 CSL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
14 Active RVL At Intermediate Event — This bit indicates the active (used) RVL buffer at the occurrence of a
RVL_IMD conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a
Sequence Abort Event gets executed.
0 RVL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
1 RVL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.
5-0 RES_IDX Value At Intermediate Event — These bits indicate the result index (RES_IDX) value at the
RIDX_IMD[5:0] occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event)
or occurrence of EOL_IF flag or when a Sequence Abort Event gets executed to abort an ongoing conversion
(the result index RES_IDX is captured at the occurrence of a result data store).
When a Sequence Abort Event has been processed flag SEQAD_IF is set and the RES_IDX value of the last
stored result is provided. Hence in case an ongoing conversion is aborted the RES_IDX value captured in
RIDX_IMD bits depends on bit STORE_SEQA:
- STORE_SEQA =1: The result index of the aborted conversion is provided
- STORE_SEQA =0: The result index of the last stored result at abort execution time is provided
In case a CSL is aborted while no conversion is ongoing (ADC waiting for a Trigger Event) the last captured result
index is provided.
In case a Sequence Abort Event was initiated by hardware due to MCU entering Stop Mode or Wait Mode with
bit SWAI set, the result index of the last stored result is captured by bits RIDX_IMD but flag SEQAD_IF is not
set.
NOTE
The register ADCIMDRI is updated and simultaneously a conversion
interrupt flag CON_IF[15:1] occurs when the corresponding conversion
command (conversion command with INTFLG_SEL[3:0] set) has been
processed and related data has been stored to RAM.
Field Description
7 Active CSL When “End Of List” Command Type Executed — This bit indicates the active (used) CSL when
CSL_EOL a “End Of List” command type has been executed and related data has been stored to RAM.
0 CSL_0 active when “End Of List” command type executed.
1 CSL_1 active when “End Of List” command type executed.
6 Active RVL When “End Of List” Command Type Executed — This bit indicates the active (used) RVL when
RVL_EOL a “End Of List” command type has been executed and related data has been stored to RAM.
0 RVL_0 active when “End Of List” command type executed.
1 RVL_1 active when “End Of List” command type executed.
NOTE
The conversion interrupt EOL_IF occurs and simultaneously the register
ADCEOLRI is updated when the “End Of List” conversion command type
has been processed and related data has been stored to RAM.
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more
details)
Table 9-20. ADCCMD_0 Field Descriptions
Field Description
31-30 Conversion Command Select Bits — These bits define the type of current conversion described in Table 9-21.
CMD_SEL[1:0]
ADC12B_LBA V2 and V3 (includes OPT[1:0])
29-28 Option Bits — These two option bits can be used to control a SoC level feature/function. These bits are used
OPT[1:0] together with Option bits OPT[2:3]. Please refer to the device reference manual for details of the
feature/functionality controlled by these bits
27-24 Conversion Interrupt Flag Select Bits — These bits define which interrupt flag is set in the ADCIFH/L register
INTFLG_SEL[ at the end of current conversion.The interrupt flags ADCIF[15:1] are selected via binary coded bits
3:0] INTFLG_SEL[3:0]. See also Table 9-22
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
0 0 Normal Conversion
0 1 End Of Sequence
(Wait for Trigger to execute next sequence or for a Restart)
1 0 End Of List
(Automatic wrap to top of CSL
and Continue Conversion)
1 1 End Of List
(Wrap to top of CSL and:
- In “Restart Mode” wait for Restart Event followed by a Trigger
- In “Trigger Mode” wait for Trigger or Restart Event)
0x0008 0 1 0 0
0x0010 0 1 0 1
0x0800 1 1 0 0
0x1000 1 1 0 1
0x2000 1 1 1 0
0x4000 1 1 1 1
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more
details)
Table 9-23. ADCCMD_1 Field Descriptions
Field Description
21-16 ADC Input Channel Select Bits — These bits select the input channel for the current conversion. See Table 9-
CH_SEL[5:0] 24 for channel coding information.
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
0 0 0 0 1 1 Reserved
0 0 0 1 0 0 Reserved
0 0 0 1 0 1 Reserved
0 0 0 1 1 0 Reserved
0 0 0 1 1 1 Reserved
0 0 1 0 0 0 Internal_0
(ADC temperature sense)
0 0 1 0 0 1 Internal_1
0 0 1 0 1 0 Internal_2
0 0 1 0 1 1 Internal_3
0 0 1 1 0 0 Internal_4
0 0 1 1 0 1 Internal_5
0 0 1 1 1 0 Internal_6
0 0 1 1 1 1 Internal_7
0 1 0 0 0 0 AN0
0 1 0 0 0 1 AN1
0 1 0 0 1 0 AN2
0 1 0 0 1 1 AN3
0 1 0 1 0 0 AN4
0 1 x x x x ANx
1 x x x x x Reserved
NOTE
ANx in Table 9-24 is the maximum number of implemented analog input
channels on the device. Please refer to the device overview of the reference
manual for details regarding number of analog input channels.
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more
details)
Table 9-25. ADCCMD_2 Field Descriptions
Field Description
15-11 Sample Time Select Bits — These four bits select the length of the sample time in units of ADC conversion
SMP[4:0] clock cycles. Note that the ADC conversion clock period is itself a function of the prescaler value (bits PRS[6:0]).
Table 9-26 lists the available sample time lengths.
ADC12B_LBA V2 and V3 (includes OPT[3:2])
10-9 Option Bits — These two option bits can be used to control a SoC level feature/function. These bits are used
OPT[3:2] together with Option bits OPT[1:0]. Please refer to the device reference manual for details of the
feature/functionality controlled by these bits.
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
0 0 0 0 0 4
0 0 0 0 1 5
0 0 0 1 0 6
0 0 0 1 1 7
0 0 1 0 0 8
0 0 1 0 1 9
0 0 1 1 0 10
0 0 1 1 1 11
0 1 0 0 0 12
0 1 0 0 1 13
0 1 0 1 0 14
0 1 0 1 1 15
0 1 1 0 0 16
0 1 1 0 1 17
0 1 1 1 0 18
0 1 1 1 1 19
1 0 0 0 0 20
1 0 0 0 1 21
1 0 0 1 0 22
1 0 0 1 1 23
1 0 1 0 0 24
1 0 1 0 1 Reserved
1 0 1 1 0 Reserved
1 0 1 1 1 Reserved
1 1 x x x Reserved
Field Description
5-0 ADC Command Index Bits — These bits represent the command index value for the conversion commands
CMD_IDX relative to the two CSL start addresses in the memory map. These bits do not represent absolute addresses
[5:0] instead it is a sample index (object size 32bit). See also Section 9.6.3.2.2, “Introduction of the two Command
Sequence Lists (CSLs) for more details.
23 22 21 20 19 18 17 16
R
CMD_PTR[23:16]
W
Reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
R
CMD_PTR[15:8]
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Bits CMD_PTR[23:2] writable if bit ADC_EN clear or bit SMOD_ACC set
Table 9-28. ADCCBP Field Descriptions
Field Description
23-2 ADC Command Base Pointer Address — These bits define the base address of the two CSL areas inside the
CMD_PTR system RAM or NVM of the memory map. They are used to calculate the final address from which the
[23:2] conversion commands will be loaded depending on which list is active. For more details see Section 9.6.3.2.2,
“Introduction of the two Command Sequence Lists (CSLs).
Field Description
5-0 ADC Result Index Bits — These read only bits represent the index value for the conversion results relative to
RES_IDX[5:0] the two RVL start addresses in the memory map. These bits do not represent absolute addresses instead it
is a sample index (object size 16bit). See also Section 9.6.3.2.3, “Introduction of the two Result Value Lists
(RVLs) for more details.
23 22 21 20 19 18 17 16
R 0 0 0 0
RES_PTR[19:16]
W
Reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
R
RES_PTR[15:8]
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Bits RES_PTR[19:2] writeable if bit ADC_EN clear or bit SMOD_ACC set
Table 9-30. ADCRBP Field Descriptions
Field Description
19-2 ADC Result Base Pointer Address — These bits define the base address of the list areas inside the system
RES_PTR[19:2] RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits
can only be written if bit ADC_EN is clear. See also Section 9.6.3.2.3, “Introduction of the two Result Value
Lists (RVLs).
Field Description
6-0 ADC Command and Result Offset Value — These read only bits represent the conversion command and result
CMDRES_OFF0 offset value relative to the conversion command base pointer address and result base pointer address in the
[6:0] memory map to refer to CSL_0 and RVL_0. It is used to calculate the address inside the system RAM to which
the result at the end of the current conversion is stored to and the area (RAM or NVM) from which the
conversion commands are loaded from. This is a zero offset (null offset) which can not be modified. These bits
do not represent absolute addresses instead it is a sample offset (object size 16bit for RVL, object size 32bit
for CSL). See also Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) and
Section 9.6.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details.
Field Description
6-0 ADC Result Address Offset Value — These bits represent the conversion command and result offset value
CMDRES_OFF1 relative to the conversion command base pointer address and result base pointer address in the memory map
[6:0] to refer to CSL_1 and RVL_1. It is used to calculate the address inside the system RAM to which the result at
the end of the current conversion is stored to and the area (RAM or NVM) from which the conversion
commands are loaded from. These bits do not represent absolute addresses instead it is an sample offset
(object size 16bit for RVL, object size 32bit for CSL).,These bits can only be modified if bit ADC_EN is clear.
See also Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) and Section 9.6.3.2.3,
“Introduction of the two Result Value Lists (RVLs) for more details.
9.6.1 Overview
The ADC12B_LBA consists of an analog sub-block and a digital sub-block. It is a successive
approximation analog-to-digital converter including a sample-and-hold mechanism and an internal charge
scaled C-DAC (switched capacitor scaled digital-to-analog converter) with a comparator to realize the
successive approximation algorithm.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Total Sample Time SAR Sequence
(N = SMP[4:0]) (Resolution Dependent Length: SRES[2:0])
"Buffer" "Final" Sample CAP hold phase
Sample Time Sample Time
(2 cycles) (N - 2 cycles)
ADC_CLK
Figure 9-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling)
Please note that there is always a pump phase of two ADC_CLK cycles before the sample phase begins,
hence glitches during the pump phase could impact the conversion accuracy for short sample times.
}
Command_2 normal conversion 0 0
Command_3 normal conversion 0 0
Command_4 normal conversion Sequence_1 0 0
Command_5 normal conversion 0 0
Command_6 normal conversion 0 0
Command_7 End Of Sequence 0 1
Waiting for trigger
to proceed
Figure 9-29. Example CSL with sequences and an “End Of List” command type identifier
ADCCBP+(ADCCROFF_0) ADCCBP+(ADCCROFF_0)
CSL_0 (active) CSL_0 (alternative)
ADCCBP+(ADCCROFF_0+ ADCCBP+(ADCCROFF_0+
ADCCIDX(max)) ADCCIDX(max))
ADCCBP+(ADCCROFF_1) ADCCBP+(ADCCROFF_1)
CSL_1 (alternative) CSL_1 (active)
ADCCBP+(ADCCROFF_1+ ADCCMDP+(ADCCROFF_1+
ADCCIDX(max)) ADCCIDX(max))
Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Memory Map
0x00_0000
Register Space
ADCCBP+(ADCCROFF_0)
CSL_0 (active)
ADCCBP+(ADCCROFF_0+
ADCCIDX(max))
Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
While the ADC is enabled, one CSL is active (indicated by bit CSL_SEL) and the corresponding list
should not be modified anymore. At the same time the alternative CSL can be modified to prepare the ADC
for new conversion sequences in CSL double buffered mode. When the ADC is enabled, the command
address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under
control of the ADC.
ADCRBP+(ADCCROFF_0) ADCRBP+(ADCCROFF_0)
RVL_0 (active) RVL_0 (alternative)
ADCRBP+(ADCCROFF_0+ ADCRBP+(ADCCROFF_0+
ADCRIDX(max)) ADCRIDX(max))
ADCRBP+(ADCCROFF_1) ADCRBP+(ADCCROFF_1)
RVL_1 (alternative) RVL_1 (active)
ADCRBP+(ADCCROFF_1+ ADCRBP+(ADCCROFF_1+
ADCRIDX(max)) ADCRIDX(max))
Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Memory Map
0x00_0000
Register Space
ADCRBP+(ADCCROFF_0)
RVL_0 (active)
ADCRBP+(ADCCROFF_0+
ADCRIDX(max))
Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
While ADC is enabled, one Result Value List is active (indicated by bit RVL_SEL). The conversion Result
Value List can be read anytime. When the ADC is enabled the conversion result address registers
(ADCRBP, ADCCROFF_0/1, ADCRIDX) are read only and register ADCRIDX is under control of the
ADC.
A conversion result is always stored as 16bit entity in unsigned data representation. Left and right
justification inside the entity is selected via the DJM control bit. Unused bits inside an entity are stored
zero.
Table 9-33. Conversion Result Justification Overview
• Trigger Event
Internal Interface Signal: Trigger
Corresponding Bit Name: TRIG
– Function:
Start the first conversion of a conversion sequence which is defined in the active Command
Sequence List
– Requested by:
- Positive edge of internal interface signal Trigger
- Write Access via data bus to set control bit TRIG
– When finished:
This bit is cleared by the ADC when the first conversion of the sequence is beginning to
sample
– Mandatory Requirements:
- In all ADC conversion flow control modes bit TRIG is only set (Trigger Event executed)
if the Trigger Event occurs while no conversion or conversion sequence is ongoing (ADC
idle)
- In ADC conversion flow control mode “Restart Mode” with a Restart Event in progress it
is not allowed that a Trigger Event occurs before the background command load phase has
finished (Restart Event has been executed) else the error flag TRIG_EIF is set
- In ADC conversion flow control mode “Trigger Mode” a Restart Event causes bit TRIG
being set automatically. Bit TRIG is set when no conversion or conversion sequence is
ongoing (ADC idle) and the RVL done condition is reached by one of the following:
* A “End Of List” command type has been executed
* A Sequence Abort Event is in progress or has been executed
The ADC executes the Restart Event followed by the Trigger Event.
- In ADC conversion flow control mode “Trigger Mode” a Restart Event and a simultaneous
Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC
cease operation.
– When finished:
This bit is cleared when the first conversion command of the sequence from top of active
Sequence Command List is loaded
– Mandatory Requirement:
- In all ADC conversion flow control modes a Restart Event causes bit RSTA to be set. Bit
SEQA is set simultaneously by ADC hardware if:
* ADC not idle (a conversion or conversion sequence is ongoing and current CSL not
finished) and no Sequence Abort Event in progress (bit SEQA not already set or set
simultaneously via internal interface or data bus)
* ADC idle but RVL done condition not reached
The RVL done condition is reached by one of the following:
* A “End Of List” command type has been executed
* A Sequence Abort Event is in progress or has been executed (bit SEQA already set or set
simultaneously via internal interface or data bus)
The ADC executes the Sequence Abort Event followed by the Restart Event for the
conditions described before or only a Restart Event.
- In ADC conversion flow control mode “Trigger Mode” a Restart Event causes bit TRIG
being set automatically. Bit TRIG is set when no conversion or conversion sequence is
ongoing (ADC idle) and the RVL done condition is reached by one of the following:
* A “End Of List” command type has been executed
* A Sequence Abort Event is in progress or has been executed
The ADC executes the Restart Event followed by the Trigger Event.
- In ADC conversion flow control mode “Trigger Mode” a Restart Event and a simultaneous
Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC
cease operation.
If signal Restart is asserted before signal LoadOK is set the conversion starts from top of
currently active CSL at the next Trigger Event (no exchange of CSL list).
If signal Restart is asserted after or simultaneously with signal LoadOK the conversion
starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is
configured for double buffer mode.
9.6.3.2.6 Conversion flow control in case of conversion sequence control bit overrun
scenarios
Restart Request Overrun:
If a legal Restart Request is detected and no Restart Event is in progress, the RSTA bit is set due to the
request. The set RSTA bit indicates that a Restart Request was detected and the Restart Event is in process.
In case further Restart Requests occur while the RSTA bit is set, this is defined a overrun situation. This
scenario is likely to occur when bit STR_SEQA is set or when a Restart Event causes a Sequence Abort
Event. The request overrun is captured in a background register that always stores the last detected overrun
request. Hence if the overrun situation occurs more than once while a Restart Event is in progress, only
the latest overrun request is pending. When the RSTA bit is cleared, the latest overrun request is processed
and RSTA is set again one cycle later.
LoadOK Overrun:
Simultaneously at any Restart Request overrun situation the LoadOK input is evaluated and the status is
captured in a background register which is alternated anytime a Restart Request Overrun occurs while
Load OK Request is asserted. The Load OK background register is cleared as soon as the pending Restart
Request gets processed.
Trigger Overrun:
If a Trigger occurs whilst bit TRIG is already set, this is defined as a Trigger overrun situation and causes
the ADC to cease conversion at the next conversion boundary and to set bit TRIG_EIF. A overrun is also
detected if the Trigger Event occurs automatically generated by hardware in “Trigger Mode” due to a
Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface. In this
case the ADC ceases operation before conversion begins to sample. In “Trigger Mode” a Restart Request
Overrun does not cause a Trigger Overrun (bit TRIG_EIF not set).
Sequence Abort Request Overrun:
If a Sequence Abort Request occurs whilst bit SEQA is already set, this is defined as a Sequence Abort
Request Overrun situation and the overrun request is ignored.
9.7 Resets
At reset the ADC12B_LBA is disabled and in a power down state. The reset state of each individual bit is
listed within Section 9.5.2, “Register Descriptions” which details the registers and their bit-fields.
9.8 Interrupts
The ADC supports three types of interrupts:
• Conversion Interrupt
• Sequence Abort Interrupt
• Error and Conversion Flow Control Issue Interrupt
Each of the interrupt types is associated with individual interrupt enable bits and interrupt flags.
Remaining error interrupt flags cause an error interrupt if enabled, but ADC continues operation. The
related interrupt flags are:
• RSTAR_EIF
• LDOK_EIF
• CONIF_OIF
9.9.1 List Usage — CSL single buffer mode and RVL single buffer mode
In this use case both list types are configured for single buffer mode (CSL_BMOD=1’b0 and
RVL_BMOD=1’b0, CSL_SEL and RVL_SEL are forced to 1’b0). The index register for the CSL and RVL
are cleared to start from the top of the list with next conversion command and result storage in the
following cases:
• The conversion flow reaches the command containing the “End-of-List” command type identifier
• A Restart Request occurs at a sequence boundary
• After an aborted conversion or conversion sequence
CSL_0 RVL_0
CSL_1 RVL_1
(unused) (unused)
Figure 9-35. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram
9.9.2 List Usage — CSL single buffer mode and RVL double buffer mode
In this use case the CSL is configured for single buffer mode (CSL_BMOD=1’b0) and the RVL is
configured for double buffer mode (RVL_BMOD=1’b1). In this buffer configuration only the result list
RVL is switched when the first conversion result of a CSL is stored after a CSL was successfully finished
or a CSL got aborted.
CSL_0 RVL_0
CSL_1 RVL_1
(unused)
Figure 9-36. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram
The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the “End
Of List “ command type) is shown by register ADCEOLRI.
The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0.
9.9.3 List Usage — CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1 and
RVL_BMOD=1’b1) and whenever a Command Sequence List (CSL) is finished or aborted the command
Sequence List is swapped by the simultaneous assertion of bits LDOK and RSTA.
CSL_0 RVL_0
CSL_1 RVL_1
Figure 9-37. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram
This use case can be used if the channel order or CSL length varies very frequently in an application.
9.9.4 List Usage — CSL double buffer mode and RVL single buffer mode
In this use case the CSL is configured for double buffer mode (CSL_BMOD=1’b1) and the RVL is
configured for single buffer mode (RVL_BMOD=1’b0).
The two command lists can be different sizes and the allocated result list memory area in the RAM must
be able to hold as many entries as the larger of the two command lists. Each time when the end of a
Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped.
CSL_0 RVL_0
CSL_1 RVL_1
(unused)
Figure 9-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram
9.9.5 List Usage — CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1) and
RVL_BMOD=1’b1).
This setup is the same as Section 9.9.3, “List Usage — CSL double buffer mode and RVL double buffer
mode but at the end of a CSL the CSL is not always swapped (bit LDOK not always set with bit RSTA).
The Result Value List is swapped whenever a CSL is finished or a CSL got aborted.
CSL_0 RVL_0
CSL_1 RVL_1
Figure 9-39. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram
9.9.6 RVL swapping in RVL double buffer mode and related registers
ADCIMDRI and ADCEOLRI
When using the RVL in double buffer mode, the registers ADCIMDRI and ADCEOLRI can be used by
the application software to identify which RVL holds relevant and latest data and which CSL is related to
this data. These registers are updated at the setting of one of the CON_IF[15:1] or the EOL_IF interrupt
flags. As described in the register description Section 9.5.2.13, “ADC Intermediate Result Information
Register (ADCIMDRI) and Section 9.5.2.14, “ADC End Of List Result Information Register
(ADCEOLRI), the register ADCIMDRI, for instance, is always updated at the occurrence of a
CON_IF[15:1] interrupt flag amongst other cases. Also each time the last conversion command of a CSL
is finished and the corresponding result is stored, the related EOL_IF flag is set and register ADCEOLRI
is updated. Hence application software can pick up conversion results, or groups of results, or an entire
result list driven fully by interrupts. A use case example diagram is shown in Figure 9-40.
t
Comments:
EOL: ”End Of List” command type processed
INT_x: One of the CON_IF interrupt flags occurs
tdelay: Delay can vary depending on the DMA performance, and ADC configuration (conversion
flow using the Trigger to proceed through the CSL)
mode “Trigger Mode” only a Restart Event is necessary if ADC is idle to restart Conversion Sequence List
execution (the Trigger Event occurs automatically).
It is possible to set bit RSTA and SEQA simultaneously, causing a Sequence Abort Event followed by a
Restart Event. In this case the error flags behave differently depending on the selected conversion flow
control mode:
• Setting both flow control bits simultaneously in conversion flow control mode “Restart Mode”
prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
• Setting both flow control bits simultaneously in conversion flow control mode “Trigger Mode”
prevents the error flag RSTA_EIF from occurring.
If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort
Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
Please see also the detailed conversion flow control bit mandatory requirements and execution information
for bit RSTA and SEQA described in Section 9.6.3.2.5, “The four ADC conversion flow control bits.
9.9.7.3 Restart CSL execution with new/other CSL (alternative CSL becomes
active CSL) — CSL swapping
After all alternative conversion command list entries are finished the bit LDOK can be set simultaneously
with the next Restart Event to swap command buffers.
To start conversion command list execution it is mandatory that the ADC is idle (no conversion or
conversion sequence is ongoing).
If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting
bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted
and the ADC is idle (no conversion sequence or conversion ongoing).
After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set)
and simultaneously set bit LDOK to swap the CSL buffer. After the Restart Event is finished (bit RSTA
and LDOK are cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion
from the top of the newly selected CSL buffer. In conversion flow control mode “Trigger Mode” only a
Restart Event (simultaneously with bit LDOK being set) is necessary to restart conversion command list
execution with the newly selected CSL buffer (the Trigger Event occurs automatically).
It is possible to set bits RSTA, LDOK and SEQA simultaneously, causing a Sequence Abort Event
followed by a Restart Event. In this case the error flags behave differently depending on the selected
conversion flow control mode:
• Setting these three flow control bits simultaneously in “Restart Mode” prevents the error flags
RSTA_EIF and LDOK_EIF from occurring.
• Setting these three flow control bits simultaneously in “Trigger Mode” prevents the error flag
RSTA_EIF from occurring.
If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort
Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
Please see also the detailed conversion flow control bit mandatory requirements and execution information
for bit RSTA and SEQA described in Section 9.6.3.2.5, “The four ADC conversion flow control bits.
AN3 AN1 AN4 IN5 AN3 AN1 AN4 IN5 AN3 AN1 AN3 AN1 AN4
Figure 9-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode)
Initial
Restart Repetition of CSL_0
Event Trigger Trigger Trigger
AN3 AN1 AN4 IN5 AN2 AN0 AN4 IN3 AN6 AN1 IN1 AN3 AN1 AN4
Sequence_0 Sequence_1 Sequence_2 Sequence_0
EOS EOS EOL
CSL_0 Active
t
Figure 9-42. Conversion Flow Control Diagram — Triggered Conversion (CSL Repetition)
AN3 AN1 AN4 IN5 AN21AN0 AN4 IN3 AN6 AN1 AN3 AN1 AN4 AN5 AN2 AN0
Sequence_2
Sequence_0 Sequence_1 Sequence_0 Sequence_1
EOS EOS Stop Mode EOS
entry
Abort
CSL_0 Active Idle Idle Active
t
Figure 9-43. Conversion Flow Control Diagram — Triggered Conversion (with Stop Mode)
AN3 AN1 AN4 IN5 AN21AN0 AN4 IN3 AN6 AN1 AN3 AN1 AN4 AN5 AN2 AN0
Sequence_2
Sequence_0 Sequence_1 Sequence_0 Sequence_1
EOS EOS Stop Mode EOS
conversion command entry
load phase
Abort
CSL_0 Active Idle Idle Active
t
Figure 9-44. Conversion Flow Control Diagram — Fully Timing Controlled Conversion (with Stop Mode)
Unlike the Stop Mode entry shown in Figure 9-43 and Figure 9-44 it is recommended to issue the Stop
Mode at sequence boundaries (when ADC is idle and no conversion/conversion sequence is ongoing).
Any of the Conversion flow control application use cases described above (Continuous, Triggered, or
Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer
mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit
LDOK set.
V02.00 16 Mar 2011 10.3.2.1 - added BVLS[1] to support four voltage level
10.4.2.1 - moved BVHS to register bit 6
10.1 Introduction
The BATS module provides the functionality to measure the voltage of the chip supply pin VSUP.
10.1.1 Features
The VSUP pin can be routed via an internal divider to the internal Analog to Digital Converter.
Independent of the routing to the Analog to Digital Converter, it is possible to route this voltage to a
comparator to generate a low or a high voltage interrupt to alert the MCU.
VSUP
BVLS[1:0]
Comparator
BVHS
BSUSE
1
to ADC
BSUAE
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0000 R 0 0 0
BATE BVHS BVLS[1:0] BSUAE BSUSE
W
0x0002 R 0 0 0 0 0 0
BATIE BVHIE BVLIE
W
0x0003 R 0 0 0 0 0 0
BATIF BVHIF BVLIF
W
0x0004 - 0x0005 R 0 0 0 0 0 0 0 0
Reserved
W
0x0006 - 0x0007 R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
= Unimplemented
7 6 5 4 3 2 1 0
R 0 0 0
BVHS BVLS[1:0] BSUAE BSUSE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6 BATS Voltage High Select — This bit selects the trigger level for the Voltage Level High Condition (BVHC).
BVHS
0 Voltage level VHBI1 is selected
1 Voltage level VHBI2 is selected
5:4 BATS Voltage Low Select — This bit selects the trigger level for the Voltage Level Low Condition (BVLC).
BVLS[1:0]
00 Voltage level VLBI1 is selected
01 Voltage level VLBI2 is selected
10 Voltage level VLBI3 is selected
11 Voltage level VLBI4 is selected
3 BATS VSUP ADC Connection Enable — This bit connects the VSUP pin through the resistor chain to ground and
BSUAE connects the ADC channel to the divided down voltage.
0 ADC Channel is disconnected
1 ADC Channel is connected
2 BATS VSUP Level Sense Enable — This bit connects the VSUP pin through the resistor chain to ground and
BSUSE enables the Voltage Level Sense features measuring BVLC and BVHC.
NOTE
When opening the resistors path to ground by changing BSUSE or BSUAE
then for a time TEN_UNC + two bus cycles the measured value is invalid.
This is to let internal nodes be charged to correct value. BVHIE, BVLIE
might be cleared for this time period to avoid false interrupts.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 BVHC BVLC
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
1 BATS Voltage Sense High Condition Bit — This status bit indicates that a high voltage at VSUP, depending on
BVHC selection, is present.
0 BATS Voltage Sense Low Condition Bit — This status bit indicates that a low voltage at VSUP, depending on
BVLC selection, is present.
V
VHBI_A
VHBI_D
VLBI_D
VLBI_A
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
BVHIE BVLIE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
BVHIF BVLIF
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
1 BATS Interrupt Flag High Detect — The flag is set to 1 when BVHC status bit changes.
BVHIF
0 No change of the BVHC status bit since the last clearing of the flag.
1 BVHC status bit has changed since the last clearing of the flag.
0 BATS Interrupt Flag Low Detect — The flag is set to 1 when BVLC status bit changes.
BVLIF
0 No change of the BVLC status bit since the last clearing of the flag.
1 BVLC status bit has changed since the last clearing of the flag.
7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
NOTE
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special mode can alter the module’s functionality.
10.4.1 General
The BATS module allows measuring the voltage on the VSUP pin. The voltage at the VSUP pin can be
routed via an internal voltage divider to an internal Analog to Digital Converter Channel. Also the BATS
module can be configured to generate a low and high voltage interrupt based on VSUP. The trigger level
of the high and low interrupt are selectable.
10.4.2 Interrupts
This section describes the interrupt generated by the BATS module. The interrupt is only available in CPU
run mode. Entering and exiting CPU stop mode has no effect on the interrupt flags.
To make sure the interrupt generation works properly the bus clock frequency must be higher than the
Voltage Warning Low Pass Filter frequency (fVWLP_filter).
The comparator outputs BVLC and BVHC are forced to zero if the comparator is disabled (configuration
bit BSUSE is cleared). If the software disables the comparator during a high or low Voltage condition
(BVHC or BVLC active), then an additional interrupt is generated. To avoid this behavior the software
must disable the interrupt generation before disabling the comparator.
The BATS interrupt vector is named in Table 10-6. Vector addresses and interrupt priorities are defined at
MCU level.
The module internal interrupt sources are combined into one module interrupt signal.
then BVLC is set. BVLC status bit indicates that a low voltage at pin VSUP is present. The Low Voltage
Interrupt flag (BVLIF) is set to 1 when the Voltage Low Condition (BVLC) changes state . The Interrupt
flag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests
an interrupt to MCU (BATI).
If measured when
a) VHBI1 selected with BVHS = 0
Vmeasure VHBI1_A (rising edge) or Vmeasure VHBI1_D (falling edge)
or when
a) VHBI2 selected with BVHS = 1
Vmeasure VHBI2_A (rising edge) or Vmeasure VHBI2_D (falling edge)
then BVHC is set. BVHC status bit indicates that a high voltage at pin VSUP is present. The High Voltage
Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt
flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module
requests an interrupt to MCU (BATI).
V03.03 Jan,14,2013
-single source generate different channel guide
11.1 Introduction
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible
programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform.
This timer could contain up to 4 input capture/output compare channels . The input capture function is used
to detect a selected transition edge and record the time. The output compare function is used for generating
output signals or for timer software delays.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
11.1.1 Features
The TIM16B4CV3 includes these distinctive features:
• Up to 4 channels available. (refer to device specification for exact number)
• All channels have same input capture/output compare functionality.
• Clock prescaling.
• 16-bit counter.
Channel 0
Input capture
Bus clock Prescaler IOC0
Output compare
Timer channel 3
interrupt
11.2.1 IOC3 - IOC0 — Input Capture and Output Compare Channel 3-0
Those pins serve as input capture or output compare for TIM16B4CV3 channel .
NOTE
For the description of interrupts see Section 11.6, “Interrupts”.
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0009 R
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
TCTL2 W
0x000A R RESERV RESERV RESERV RESERV RESERV RESERV RESERV RESERV
TCTL3 W ED ED ED ED ED ED ED ED
0x000B R
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
TCTL4 W
0x000C R RESERV RESERV RESERV RESERV
C3I C2I C1I C0I
TIE W ED ED ED ED
0x000D R 0 0 0 RESERV
TOI PR2 PR1 PR0
TSCR2 W ED
0x000E R RESERV RESERV RESERV RESERV
TFLG1 C3F C2F C1F C0F
W ED ED ED ED
0x000F R 0 0 0 0 0 0 0
TOF
TFLG2 W
0x0010–0x001F R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
TCxH–TCxL(1) W
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0024–0x002B R
Reserved W
0x002C R RESERV RESERV RESERV RESERV
OCPD3 OCPD2 OCPD1 OCPD0
OCPD W ED ED ED ED
0x002D R
Reserved
0x002E R
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
PTPSR W
0x002F R
Reserved W
Figure 11-3. TIM16B4CV3 Register Summary (Sheet 2 of 2)
1. The register is available only if corresponding channel exists.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED IOS3 IOS2 IOS1 IOS0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0
Field Description
3:0 Note: Force Output Compare Action for Channel 3:0 — A write to this register with the corresponding data
FOC[3:0] bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
15 14 13 12 11 10 9 9
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R 0 0 0
TEN TSWAI TSFRZ TFFCA PRNT
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Table 11-4. TSCR1 Field Descriptions
Field Description
7 Timer Enable
TEN 0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is
generated by the timer prescaler.
Field Description
3 Precision Timer
PRNT 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED TOV3 TOV2 TOV1 TOV0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Table 11-5. TTOV Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
3:0 Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
TOV[3:0] in output compare mode. When set, it takes precedence over forced output compare
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Table 11-6. TCTL1/TCTL2 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field Description
3:0 Output Mode — These four pairs of control bits are encoded to specify the output action to be taken as a result
OMx of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
3:0 Output Level — These fourpairs of control bits are encoded to specify the output action to be taken as a result
OLx of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
11.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Module Base + 0x000A
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime.
Table 11-8. TCTL3/TCTL4 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
3:0 Input Capture Edge Control — These four pairs of control bits configure the input capture edge detector
EDGnB circuits.
EDGnA
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED C3I C2I C1I C0I
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime.
Table 11-10. TIE Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field Description
3:0 Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
C3I:C0I the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
7 6 5 4 3 2 1 0
R 0 0 0
TOI RESERVED PR2 PR1 PR0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime.
Table 11-11. TSCR2 Field Descriptions
Field Description
2:0 Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
PR[2:0] Bus Clock as shown in Table 11-12.
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED C3F C2F C1F C0F
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will
not affect current status of the bit.
Table 11-13. TRLG1 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
3:0 Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
C[3:0]F compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
TOF
W
Reset 0 0 0 0 0 0 0 0
Unimplemented or Reserved
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 .
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 11-14. TRLG2 Field Descriptions
Field Description
7 Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
TOF requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one .
15 14 13 12 11 10 9 0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should take place before low
byte otherwise it will give a different result.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED OCPD3 OCPD2 OCPD1 OCPD0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 11-15. OCPD Field Description
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
7 6 5 4 3 2 1 0
R
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
All bits reset to zero.
...
Field Description
7:0 Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 11-17 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:
PRNT = 1 : Prescaler = PTPS[7:0] + 1
Prescale
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
Factor
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 2
0 0 0 0 0 0 1 0 3
0 0 0 0 0 0 1 1 4
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
0 0 0 1 0 0 1 1 20
0 0 0 1 0 1 0 0 21
0 0 0 1 0 1 0 1 22
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
1 1 1 1 1 1 0 0 253
1 1 1 1 1 1 0 1 254
1 1 1 1 1 1 1 0 255
1 1 1 1 1 1 1 1 256
PTPSR[7:0]
tim source Clock
PRE-PRESCALER
PRNT
PR[2:1:0]
1
PRESCALER MUX
0
CxI
TCNT(hi):TCNT(lo)
CxF
CHANNEL 0
16-BIT COMPARATOR C0F C0F
CH. 0 CAPTURE
OM:OL0
TC0 IOC0 PIN
TOV0 IOC0 PIN
LOGIC CH. 0COMPARE
EDGE
EDG0A EDG0B DETECT IOC0
CHANNEL 1
16-BIT COMPARATOR C1F C1F CH. 1 CAPTURE
OM:OL1
TC1 IOC1 PIN
LOGIC CH. 1 COMPARE IOC1 PIN
TOV1
EDG1A EDG1B EDGE
DETECT
CHANNEL2 IOC1
CHANNELn-1
16-BIT COMPARATOR Cn-1F Cn-1F CH.n-1 CAPTURE
TCn-1 OM:OLn-1 IOCn-1 PIN
LOGIC CH. n-1COMPAREIOCn-1 PIN
EDG(n-1)A TOVn-1
EDGE
EDG(n-1)B DETECT
IOCn-1
n is channels number.
11.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter in the present timer by
using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a
glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.
11.5 Resets
The reset state of each individual bit is listed within Section 11.3, “Memory Map and Register Definition”
which details the registers and their bit fields
11.6 Interrupts
This section describes interrupts originated by the TIM16B4CV3 block. Table 11-18 lists the interrupts
generated by the TIM16B4CV3 to communicate with the MCU.
Table 11-18. TIM16B4CV3 Interrupts
C[3:0]F — — — Timer Channel 3–0 Active high timer channel interrupts 3–0
TOF — — — Timer Overflow Timer Overflow interrupt
The TIM16B4CV3 could use up to 5 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
V03.03 Jan,14,2013
-single source generate different channel guide
12.1 Introduction
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible
programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform.
This timer could contain up to 2 input capture/output compare channels . The input capture function is used
to detect a selected transition edge and record the time. The output compare function is used for generating
output signals or for timer software delays.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
12.1.1 Features
The TIM16B2CV3 includes these distinctive features:
• Up to 2 channels available. (refer to device specification for exact number)
• All channels have same input capture/output compare functionality.
• Clock prescaling.
• 16-bit counter.
Channel 0
Input capture
Bus clock Prescaler IOC0
Output compare
Channel 1
Timer overflow
Input capture
interrupt 16-bit Counter IOC1
Output compare
Timer channel 0
interrupt
Registers
Timer channel 1
interrupt
12.2.1 IOC1 - IOC0 — Input Capture and Output Compare Channel 1-0
Those pins serve as input capture or output compare for TIM16B2CV3 channel .
NOTE
For the description of interrupts see Section 12.6, “Interrupts”.
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x000C R RESERV RESERV RESERV RESERV RESERV RESERV
TIE C1I C0I
W ED ED ED ED ED ED
0x000D R 0 0 0 RESERV
TOI PR2 PR1 PR0
TSCR2 W ED
0x000E R RESERV RESERV RESERV RESERV RESERV RESERV
TFLG1 C1F C0F
W ED ED ED ED ED ED
0x000F R 0 0 0 0 0 0 0
TOF
TFLG2 W
0x0010–0x001F R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
TCxH–TCxL(1) W
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0024–0x002B R
Reserved W
0x002C R RESERV RESERV RESERV RESERV RESERV RESERV
OCPD1 OCPD0
OCPD W ED ED ED ED ED ED
0x002D R
Reserved
0x002E R
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
PTPSR W
0x002F R
Reserved W
Figure 12-3. TIM16B2CV3 Register Summary (Sheet 2 of 2)
1. The register is available only if corresponding channel exists.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED IOS1 IOS0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0
Field Description
1:0 Note: Force Output Compare Action for Channel 1:0 — A write to this register with the corresponding data
FOC[1:0] bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
15 14 13 12 11 10 9 9
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R 0 0 0
TEN TSWAI TSFRZ TFFCA PRNT
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Table 12-4. TSCR1 Field Descriptions
Field Description
7 Timer Enable
TEN 0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is
generated by the timer prescaler.
Field Description
3 Precision Timer
PRNT 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TOV1 TOV0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Table 12-5. TTOV Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
1:0 Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
TOV[1:0] in output compare mode. When set, it takes precedence over forced output compare
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED OM1 OL1 OM0 OL0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
Table 12-6. TCTL1/TCTL2 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field Description
1:0 Output Mode — These two pairs of control bits are encoded to specify the output action to be taken as a result
OMx of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
1:0 Output Level — These two pairs of control bits are encoded to specify the output action to be taken as a result
OLx of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
12.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Module Base + 0x000A
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED EDG1B EDG1A EDG0B EDG0A
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime.
Table 12-8. TCTL3/TCTL4 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
1:0 Input Capture Edge Control — These two pairs of control bits configure the input capture edge detector
EDGnB circuits.
EDGnA
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED C1I C0I
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime.
Table 12-10. TIE Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field Description
1:0 Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
C1I:C0I the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
7 6 5 4 3 2 1 0
R 0 0 0
TOI RESERVED PR2 PR1 PR0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Read: Anytime
Write: Anytime.
Table 12-11. TSCR2 Field Descriptions
Field Description
2:0 Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
PR[2:0] Bus Clock as shown in Table 12-12.
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED C1F C0F
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will
not affect current status of the bit.
Table 12-13. TRLG1 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
1:0 Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
C[1:0]F compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
TOF
W
Reset 0 0 0 0 0 0 0 0
Unimplemented or Reserved
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 .
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 12-14. TRLG2 Field Descriptions
Field Description
7 Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
TOF requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one .
15 14 13 12 11 10 9 0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should take place before low
byte otherwise it will give a different result.
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED OCPD1 OCPD0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 12-15. OCPD Field Description
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
7 6 5 4 3 2 1 0
R
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
W
Reset 0 0 0 0 0 0 0 0
Read: Anytime
Write: Anytime
All bits reset to zero.
...
Field Description
7:0 Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 12-17 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:
PRNT = 1 : Prescaler = PTPS[7:0] + 1
Prescale
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
Factor
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 2
0 0 0 0 0 0 1 0 3
0 0 0 0 0 0 1 1 4
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
0 0 0 1 0 0 1 1 20
0 0 0 1 0 1 0 0 21
0 0 0 1 0 1 0 1 22
- - - - - - - - -
- - - - - - - - -
- - - - - - - - -
1 1 1 1 1 1 0 0 253
1 1 1 1 1 1 0 1 254
1 1 1 1 1 1 1 0 255
1 1 1 1 1 1 1 1 256
PTPSR[7:0]
tim source Clock
PRE-PRESCALER
PRNT
PR[2:1:0]
1
PRESCALER MUX
0
CxI
TCNT(hi):TCNT(lo)
CxF
CHANNEL 0
16-BIT COMPARATOR C0F C0F
CH. 0 CAPTURE
OM:OL0
TC0 IOC0 PIN
TOV0 IOC0 PIN
LOGIC CH. 0COMPARE
EDGE
EDG0A EDG0B DETECT IOC0
CHANNEL 1
16-BIT COMPARATOR C1F C1F CH. 1 CAPTURE
OM:OL1
TC1 IOC1 PIN
LOGIC CH. 1 COMPARE IOC1 PIN
TOV1
EDG1A EDG1B EDGE
DETECT
CHANNEL2 IOC1
CHANNELn-1
16-BIT COMPARATOR Cn-1F Cn-1F CH.n-1 CAPTURE
TCn-1 OM:OLn-1 IOCn-1 PIN
LOGIC CH. n-1COMPAREIOCn-1 PIN
EDG(n-1)A TOVn-1
EDGE
EDG(n-1)B DETECT
IOCn-1
n is channels number.
12.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter in the present timer by
using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a
glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.
12.5 Resets
The reset state of each individual bit is listed within Section 12.3, “Memory Map and Register Definition”
which details the registers and their bit fields
12.6 Interrupts
This section describes interrupts originated by the TIM16B2CV3 block. Table 12-18 lists the interrupts
generated by the TIM16B2CV3 to communicate with the MCU.
Table 12-18. TIM16B2CV3 Interrupts
C[1:0]F — — — Timer Channel 1–0 Active high timer channel interrupts 1–0
TOF — — — Timer Overflow Timer Overflow interrupt
The TIM16B2CV3 could use up to 3 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
Revision History
Revision Sections
Revision Date Description of Changes
Number Affected
V03.14 12 Nov 2012 Table 13-10 • Corrected RxWRN and TxWRN threshold values
13.1 Introduction
Scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which
is the specific implementation of the MSCAN concept targeted for the S12, S12X and S12Z
microcontroller families.
The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the
Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is
recommended that the Bosch specification be read first to familiarize the reader with the terms and
concepts contained within this document.
Though not exclusively intended for automotive applications, CAN protocol is designed to meet the
specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI
environment of a vehicle, cost-effectiveness, and required bandwidth.
MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified
application software.
13.1.1 Glossary
Table 13-1. Terminology
ACK Acknowledge of CAN message
CAN Controller Area Network
CRC Cyclic Redundancy Code
EOF End of Frame
FIFO First-In-First-Out Memory
IFS Inter-Frame Sequence
SOF Start of Frame
CPU bus CPU related read/write data bus
CAN bus CAN protocol related serial bus
oscillator clock Direct clock from external oscillator
bus clock CPU bus related clock
CAN clock CAN protocol related clock
MSCAN
Oscillator Clock CANCLK Tq Clk
MUX Presc.
Bus Clock RXCAN
Receive/
Transmit
Engine
TXCAN
Configuration
Registers Wake-Up
Low Pass Filter
13.1.3 Features
The basic features of the MSCAN are as follows:
• Implementation of the CAN protocol — Version 2.0A/B
— Standard and extended data frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbps1
— Support for remote frames
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization using a “local priority” concept
• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or eight 8-bit filters
• Programmable wake-up functionality with integrated low-pass filter
• Programmable loopback mode supports self-test operation
• Programmable listen-only mode for monitoring of CAN bus
• Programmable bus-off recovery functionality
• Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
• Programmable MSCAN clock source either bus clock or oscillator clock
• Internal timer for time-stamping of received and transmitted messages
• Three low-power modes: sleep, power down, and MSCAN enable
• Global initialization of configuration registers
1. Depending on the actual bit timing and the clock jitter of the PLL.
MCU
CAN Controller
(MSCAN)
TXCAN RXCAN
Transceiver
CANH CANL
CAN Bus
The detailed register descriptions follow in the order they appear in the register map.
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0002 R
CANBTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
0x0003 R
CANBTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
0x0005 R
CANRIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
0x0006 R 0 0 0 0 0
CANTFLG TXE2 TXE1 TXE0
W
0x0007 R 0 0 0 0 0
CANTIER TXEIE2 TXEIE1 TXEIE0
W
0x0008 R 0 0 0 0 0
CANTARQ ABTRQ2 ABTRQ1 ABTRQ0
W
0x000A R 0 0 0 0 0
CANTBSEL TX2 TX1 TX0
W
0x000C R 0 0 0 0 0 0 0 0
Reserved W
0x000D R 0 0 0 0 0 0 0
CANMISC BOHOLD
W
= Unimplemented or Reserved
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x000E R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CANRXERR W
0x0010–0x0013 R
CANIDAR0–3 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0014–0x0017 R
CANIDMRx AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0018–0x001B R
CANIDAR4–7 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x001C–0x001F R
CANIDMR4–7 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0020–0x002F R
CANRXFG See Section 13.3.3, “Programmer’s Model of Message Storage”
W
0x0030–0x003F R
CANTXFG See Section 13.3.3, “Programmer’s Model of Message Storage”
W
= Unimplemented or Reserved
7 6 5 4 3 2 1 0
R RXACT SYNCH
RXFRM CSWAI TIME WUPE SLPRQ INITRQ
W
Reset: 0 0 0 0 0 0 0 1
= Unimplemented
NOTE
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
Field Description
7 Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message
RXFRM correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset.
Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.
0 No valid message was received since last clearing this flag
1 A valid message was received since last clearing of this flag
6 Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message(1). The flag is
RXACT controlled by the receiver front end. This bit is not valid in loopback mode.
0 MSCAN is transmitting or idle
1 MSCAN is receiving a message (including when arbitration is lost)
5 CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all
CSWAI(2) the clocks at the CPU bus interface to the MSCAN module.
0 The module is not affected during wait mode
1 The module ceases to be clocked during wait mode
4 Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and
SYNCH able to participate in the communication process. It is set and cleared by the MSCAN.
0 MSCAN is not synchronized to the CAN bus
1 MSCAN is synchronized to the CAN bus
3 Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.
TIME If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the
active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the
highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 13.3.3, “Programmer’s Model of Message
Storage”). In loopback mode no receive timestamp is generated. The internal timer is reset (all bits set to 0) when
disabled. This bit is held low in initialization mode.
0 Disable internal MSCAN timer
1 Enable internal MSCAN timer
Field Description
2 Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode or from power down
WUPE(3) mode (entered from sleep) when traffic on CAN is detected (see Section 13.4.5.5, “MSCAN Sleep Mode”). This
bit must be configured before sleep mode entry for the selected function to take effect.
0 Wake-up disabled — The MSCAN ignores traffic on CAN
1 Wake-up enabled — The MSCAN is able to restart
1 Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
SLPRQ(4) mode (see Section 13.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see Section 13.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ
cannot be set while the WUPIF flag is set (see Section 13.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
0 Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
INITRQ(5),(6) Section 13.4.4.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 13.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).
The following registers enter their hard reset state and restore their default values: CANCTL0(7), CANRFLG(8),
CANRIER(9), CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
1. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
2. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
CPU enters wait (CSWAI = 1) or stop mode (see Section 13.4.5.2, “Operation in Wait Mode” and Section 13.4.5.3, “Operation
in Stop Mode”).
3. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 13.3.2.6,
“MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
4. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
5. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
6. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
7 6 5 4 3 2 1 0
R SLPAK INITAK
CANE CLKSRC LOOPB LISTEN BORM WUPM
W
Reset: 0 0 0 1 0 0 0 1
= Unimplemented
Field Description
7 MSCAN Enable
CANE 0 MSCAN module is disabled
1 MSCAN module is enabled
6 MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock
CLKSRC generation module; Section 13.4.3.2, “Clock System,” and Section Figure 13-43., “MSCAN Clocking Scheme,”).
0 MSCAN clock source is the oscillator clock
1 MSCAN clock source is the bus clock
5 Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used
LOOPB for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN
input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does
normally when transmitting and treats its own transmitted message as a message received from a remote node.
In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure
proper reception of its own message. Both transmit and receive interrupts are generated.
0 Loopback self test disabled
1 Loopback self test enabled
4 Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN
LISTEN messages with matching ID are received, but no acknowledgement or error frames are sent out (see
Section 13.4.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports
applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any
messages when listen only mode is active.
0 Normal operation
1 Listen only mode activated
3 Bus-Off Recovery Mode — This bit configures the bus-off state recovery mode of the MSCAN. Refer to
BORM Section 13.5.2, “Bus-Off Recovery,” for details.
0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification)
1 Bus-off recovery upon user request
Field Description
2 Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is
WUPM applied to protect the MSCAN from spurious wake-up (see Section 13.4.5.5, “MSCAN Sleep Mode”).
0 MSCAN wakes up on any dominant level on the CAN bus
1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup
1 Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
SLPAK Section 13.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
0 Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
INITAK (see Section 13.4.4.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN has entered initialization mode
7 6 5 4 3 2 1 0
R
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
Reset: 0 0 0 0 0 0 0 0
Field Description
7-6 Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
SJW[1:0] (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 13-5).
5-0 Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
BRP[5:0] (see Table 13-6).
0 0 1 Tq clock cycle
0 1 2 Tq clock cycles
1 0 3 Tq clock cycles
1 1 4 Tq clock cycles
0 0 0 0 0 0 1
0 0 0 0 0 1 2
0 0 0 0 1 0 3
0 0 0 0 1 1 4
: : : : : : :
1 1 1 1 1 1 64
7 6 5 4 3 2 1 0
R
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
Reset: 0 0 0 0 0 0 0 0
Field Description
7 Sampling — This bit determines the number of CAN bus samples taken per bit time.
SAMP 0 One sample per bit.
1 Three samples per bit(1).
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Field Description
6-4 Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG2[2:0] of the sample point (see Figure 13-44). Time segment 2 (TSEG2) values are programmable as shown in
Table 13-8.
3-0 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG1[3:0] of the sample point (see Figure 13-44). Time segment 1 (TSEG1) values are programmable as shown in
Table 13-9.
0 0 0 1 Tq clock cycle(1)
0 0 1 2 Tq clock cycles
: : : :
1 1 0 7 Tq clock cycles
1 1 1 8 Tq clock cycles
1. This setting is not valid. Please refer to Table 13-36 for valid settings.
0 0 0 0 1 Tq clock cycle(1)
0 0 0 1 2 Tq clock cycles1
0 0 1 0 3 Tq clock cycles1
0 0 1 1 4 Tq clock cycles
: : : : :
1 1 1 0 15 Tq clock cycles
1 1 1 1 16 Tq clock cycles
1. This setting is not valid. Please refer to Table 13-36 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 13-8 and Table 13-9).
Eqn. 13-1
Prescaler Þ value
Bit Þ Time = ---------------------------------------------------------- 1 + TimeSegment1 + TimeSegment2
f CANCLK
7 6 5 4 3 2 1 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
The CANRFLG register is held in the reset state1 when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable
again as soon as the initialization mode is exited (INITRQ = 0 and INITAK
= 0).
Field Description
7 Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 13.4.5.5,
WUPIF “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 13.3.2.1, “MSCAN Control Register 0
(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0 No wake-up activity observed while in sleep mode
1 MSCAN detected activity on the CAN bus and requested wake-up
6 CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status
CSCIF due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-
bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see Section 13.3.2.6, “MSCAN Receiver Interrupt Enable Register
(CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0 No change in CAN bus status occurred since last interrupt
1 MSCAN changed current CAN bus status
Field Description
5-4 Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As
RSTAT[1:0] soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00 RxOK: 0 receive error counter 96
01 RxWRN: 96 receive error counter 128
10 RxERR: 128 receive error counter
11 Bus-off(1): 256transmit error counter
3-2 Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.
TSTAT[1:0] As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00 TxOK: 0 transmit error counter 96
01 TxWRN: 96 transmit error counter 128
10 TxERR: 128 transmit error counter 256
11 Bus-Off: 256 transmit error counter
1 Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
OVRIF is pending while this flag is set.
0 No data overrun condition
1 A data overrun detected
0 Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
RXF(2) This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0 No new message available within the RxFG
1 The receiver FIFO is not empty. A new message is available in the RxFG
1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
7 6 5 4 3 2 1 0
R
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
Reset: 0 0 0 0 0 0 0 0
NOTE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
Field Description
5-4 Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state
RSTATE[1:0 changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to
] indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state
changes for generating CSCIF interrupt.
10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”(2) state. Discard other
receiver state changes for generating CSCIF interrupt.
11 Generate CSCIF interrupt on all state changes.
3-2 Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter
TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter
state changes for generating CSCIF interrupt.
10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other
transmitter state changes for generating CSCIF interrupt.
11 Generate CSCIF interrupt on all state changes.
1. WUPIE and WUPE (see Section 13.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery
mechanism from stop or wait is required.
2. Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 13.3.2.5, “MSCAN Receiver
Flag Register (CANRFLG)”).
7 6 5 4 3 2 1 0
R 0 0 0 0 0
TXE2 TXE1 TXE0
W
Reset: 0 0 0 0 0 1 1 1
= Unimplemented
NOTE
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable
when not in initialization mode (INITRQ = 0 and INITAK = 0).
Field Description
2-0 Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
TXE[2:0] not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 13.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 13.3.2.10, “MSCAN Transmitter
Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
is cleared (see Section 13.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”).
When listen-mode is active (see Section 13.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
7 6 5 4 3 2 1 0
R 0 0 0 0 0
TXEIE2 TXEIE1 TXEIE0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
The CANTIER register is held in the reset state when the initialization mode
is active (INITRQ = 1 and INITAK = 1). This register is writable when not
in initialization mode (INITRQ = 0 and INITAK = 0).
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0
ABTRQ2 ABTRQ1 ABTRQ0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
The CANTARQ register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable
when not in initialization mode (INITRQ = 0 and INITAK = 0).
Field Description
2-0 Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be
ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see
Section 13.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see
Section 13.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a
transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated
TXE flag is set.
0 No abort request
1 Abort request pending
7 6 5 4 3 2 1 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
The CANTAAK register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1).
Field Description
2-0 Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending abort request
ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application
software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is
cleared whenever the corresponding TXE flag is cleared.
0 The message was not aborted.
1 The message was aborted.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
TX2 TX1 TX0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
The CANTBSEL register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK=1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Field Description
2-0 Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG
TX[2:0] register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer
TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is
cleared and the buffer is scheduled for transmission (see Section 13.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”).
0 The associated message buffer is deselected
1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register:
To get the next available transmit buffer, application software must read the CANTFLG register and write
this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The
value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the
Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.
Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered
bit position set to 1 is presented. This mechanism eases the application software’s selection of the next
available Tx buffer.
• LDAA CANTFLG; value read is 0b0000_0110
• STAA CANTBSEL; value written is 0b0000_0110
• LDAA CANTBSEL; value read is 0b0000_0010
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
7 6 5 4 3 2 1 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
5-4 Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
IDAM[1:0] (see Section 13.4.3, “Identifier Acceptance Filter”). Table 13-18 summarizes the different settings. In filter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
2-0 Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
IDHIT[2:0] Section 13.4.3, “Identifier Acceptance Filter”). Table 13-19 summarizes the different settings.
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
Writing to this register when in special system operating modes can alter the
MSCAN functionality.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
BOHOLD
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
0 Bus-off State Hold Until User Request — If BORM is set in MSCAN Control Register 1 (CANCTL1), this bit
BOHOLD indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off.
Refer to Section 13.5.2, “Bus-Off Recovery,” for details.
0 Module is not bus-off or recovery has been requested by user in bus-off state
1 Module is bus-off and holds this state until user request
7 6 5 4 3 2 1 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
7 6 5 4 3 2 1 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
7 6 5 4 3 2 1 0
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 0 0 0 0 0 0 0 0
Field Description
7-0 Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
AC[7:0] of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
7 6 5 4 3 2 1 0
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 0 0 0 0 0 0 0 0
Field Description
7-0 Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
AC[7:0] of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
7 6 5 4 3 2 1 0
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 0 0 0 0 0 0 0 0
Field Description
7-0 Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
AM[7:0] the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
7 6 5 4 3 2 1 0
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 0 0 0 0 0 0 0 0
Field Description
7-0 Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
AM[7:0] the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Offset
Register Access
Address
Figure 13-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 13-25.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
Register
Bit 7 6 5 4 3 2 1 Bit0
Name
0x00X0 R
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
IDR0 W
0x00X1 R
ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15
IDR1 W
0x00X2 R
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
IDR2 W
0x00X3 R
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
IDR3 W
0x00X4 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR0 W
0x00X5 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR1 W
0x00X6 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR2 W
0x00X7 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR3 W
0x00X8 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR4 W
0x00X9 R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR5 W
0x00XA R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR6 W
0x00XB R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DSR7 W
0x00XC R
DLC3 DLC2 DLC1 DLC0
DLR W
Register
Bit 7 6 5 4 3 2 1 Bit0
Name
Read:
• For transmit buffers, anytime when TXEx flag is set (see Section 13.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 13.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• For receive buffers, only when RXF flag is set (see Section 13.3.2.5, “MSCAN Receiver Flag
Register (CANRFLG)”).
Write:
• For transmit buffers, anytime when TXEx flag is set (see Section 13.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 13.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
Figure 13-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
IDR0 R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
0x00X0 W
IDR1 R
ID2 ID1 ID0 RTR IDE (=0)
0x00X1 W
IDR2 R
0x00X2 W
IDR3 R
0x00X3 W
7 6 5 4 3 2 1 0
R
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
W
Reset: x x x x x x x x
Field Description
7-0 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
ID[28:21] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
7 6 5 4 3 2 1 0
R
ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15
W
Reset: x x x x x x x x
Field Description
7-5 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
ID[20:18] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
4 Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by
SRR the user for transmission buffers and is stored as received on the CAN bus for receive buffers.
3 ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In
IDE the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.
0 Standard format (11 bit)
1 Extended format (29 bit)
2-0 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
ID[17:15] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
7 6 5 4 3 2 1 0
R
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
W
Reset: x x x x x x x x
Field Description
7-0 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
ID[14:7] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
7 6 5 4 3 2 1 0
R
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
W
Reset: x x x x x x x x
Field Description
7-1 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
ID[6:0] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
0 Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the CAN
RTR frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission
of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to
be sent.
0 Data frame
1 Remote frame
7 6 5 4 3 2 1 0
R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
Reset: x x x x x x x x
Field Description
7-0 Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the
ID[10:3] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number. See also ID bits in Table 13-31.
7 6 5 4 3 2 1 0
R
ID2 ID1 ID0 RTR IDE (=0)
W
Reset: x x x x x x x x
Field Description
7-5 Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the
ID[2:0] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number. See also ID bits in Table 13-30.
4 Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the
RTR CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the
transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of
the RTR bit to be sent.
0 Data frame
1 Remote frame
3 ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In
IDE the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.
0 Standard format (11 bit)
1 Extended format (29 bit)
7 6 5 4 3 2 1 0
R
W
Reset: x x x x x x x x
7 6 5 4 3 2 1 0
Reset: x x x x x x x x
7 6 5 4 3 2 1 0
R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
Reset: x x x x x x x x
Field Description
7 6 5 4 3 2 1 0
R
DLC3 DLC2 DLC1 DLC0
W
Reset: x x x x x x x x
Field Description
3-0 Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective
DLC[3:0] message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 13-34 shows the effect of setting the DLC bits.
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
• The transmission buffer with the lowest local priority field wins the prioritization.
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
7 6 5 4 3 2 1 0
R
PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
W
Reset: 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Reset: x x x x x x x x
7 6 5 4 3 2 1 0
Reset: x x x x x x x x
13.4.1 General
This section provides a complete functional description of the MSCAN.
Rx0
Rx1
Rx2
MSCAN RxBG
Rx3
Rx4
RXF
Tx0 TXE0
TxBG
PRIO
Tx1 TXE1
CPU bus
MSCAN
TxFG
PRIO
Tx2 TXE2
TxBG
Transmitter PRIO
The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a
broad range of network applications.
software simpler because only one address area is applicable for the transmit process, and the required
address space is minimized.
The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers.
Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
The MSCAN then schedules the message for transmission and signals the successful transmission of the
buffer by setting the associated TXE flag. A transmit interrupt (see Section 13.4.7.2, “Transmit Interrupt”)
is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,
the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this
purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs
this field when the message is set up. The local priority reflects the priority of this particular message
relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field
is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN
arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message in one of the three transmit buffers. Because messages that are already in
transmission cannot be aborted, the user must request the abort by setting the corresponding abort request
bit (ABTRQ) (see Section 13.3.2.9, “MSCAN Transmitter Message Abort Request Register
(CANTARQ)”.) The MSCAN then grants the request, if possible, by:
1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register.
2. Setting the associated TXE flag to release the buffer.
3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
generates a receive interrupt1 (see Section 13.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive
handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be
over-written by the next message. The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the
background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt,
or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see
Section 13.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages
exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event
that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly
received messages with accepted identifiers and another message is correctly received from the CAN bus
with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication
is generated if enabled (see Section 13.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit
messages while the receiver FIFO is being filled, but all incoming messages are discarded. As soon as a
receive buffer in the FIFO is available again, new valid messages will be accepted.
Figure 13-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3,
CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank
(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit.
• Four identifier acceptance filters, each to be applied to:
— The 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B
messages.
— The 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages.
Figure 13-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3,
CANIDMR0–CANIDMR3) produces filter 0 and 1 hits. Similarly, the second filter bank
(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits.
• Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode
implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard
identifier or a CAN 2.0B compliant extended identifier.
Figure 13-42 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3,
CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank
(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to 7 hits.
• Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is
never set.
CAN 2.0B
Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR
CAN 2.0A/B
Standard Identifier ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3
AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0
AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0
CAN 2.0B
Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR
CAN 2.0A/B ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3
Standard Identifier
CAN 2.0B
Extended Identifier ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR
CAN 2.0A/B
Standard Identifier ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID3 ID10 IDR3 ID3
MSCAN
Bus Clock
CLKSRC
Oscillator Clock
The clock source bit (CLKSRC) in the CANCTL1 register (13.3.2.2/13-486) defines whether the internal
CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the
CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the
clock is required.
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the
bus clock due to jitter considerations, especially at the faster CAN bus rates.
For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal
oscillator (oscillator clock).
A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the
atomic unit of time handled by the MSCAN.
Eqn. 13-2
f CANCLK
= --------------------------------------------------------
Tq Prescaler Þ value
A bit time is subdivided into three segments as described in the Bosch CAN 2.0A/B specification. (see
Figure 13-44):
• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
• Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
• Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be
programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Eqn. 13-3
f Tq
Bit Þ Rate = --------------------------------------------------------------------------------------------
-
number Þ of Þ Time Þ Quanta
NRZ Signal
1 4 ... 16 2 ... 8
Syntax Description
A node in receive mode samples the CAN bus at this point. If the
Sample Point three samples per bit option is selected, then this point marks the
position of the third sample.
The synchronization jump width (see the Bosch CAN 2.0A/B specification for details) can be programmed
in a range of 1 to 4 time quanta by setting the SJW parameter.
The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing
registers (CANBTR0, CANBTR1) (see Section 13.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)”
and Section 13.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”).
Table 13-36 gives an overview of the Bosch CAN 2.0A/B specification compliant segment settings and
the related parameter values.
NOTE
It is the user’s responsibility to ensure the bit time settings are in compliance
with the CAN standard.
Table 13-36. Bosch CAN 2.0A/B Compliant Bit Time Segment Settings
Synchronization
Time Segment 1 TSEG1 Time Segment 2 TSEG2 SJW
Jump Width
5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1
4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2
5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3
6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3
7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3
8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3
9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3
INIT
INITRQ SYNC
sync. Flag
CPU INITRQ
Init Request
INITAK sync.
Flag
SYNC INITAK
INITAK
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Figure 13-45).
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
NOTE
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
MSCAN Mode
SLPRQ
SLPRQ SYNC
sync. Flag
CPU SLPRQ
Sleep Request
SLPAK sync.
Flag
SYNC SLPAK
SLPAK MSCAN
in Sleep Mode
NOTE
The application software must avoid setting up a transmission (by clearing
one or more TXEx flag(s)) and immediately request sleep mode (by setting
SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode
directly depends on the exact sequence of operations.
If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 13-46). The application software must
use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.
When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks
that allow register accesses from the CPU side continue to run.
If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits
due to the stopped clocks. TXCAN remains in a recessive state. If RXF = 1, the message can be read and
RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does
not take place while in sleep mode.
It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes
place while in sleep mode.
If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN.
RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE
must be set before entering sleep mode to take effect.
The MSCAN is able to leave sleep mode (wake up) only when:
• CAN bus activity occurs and WUPE = 1
or
• the CPU clears the SLPRQ bit
NOTE
The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and
SLPAK = 1) is active.
After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode
was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message
aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it
continues counting the 128 occurrences of 11 consecutive recessive bits.
13.4.7 Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated
flags. Each interrupt is listed and described separately.
02.00 22. Mar. 2012 14.3.2.1, - removed PTUWP bit (now: PTUPTR is write protected if both
14.3.2.7, TGs are disabled, TGxLxIDX is write protected if the associated
14.3.2.10, TG is disabled)
14.3.2.14 - - TGxLIST bits are writeable if associated TG is disabled
14.3.2.17 - PTULDOK bit is writable if both TGs are disabled
- TGxLIST swap at every reload with LDOK set
Term Meaning
TG Trigger Generator
14.1 Introduction
In PWM driven systems it is important to schedule the acquisition of the state variables with respect to
PWM cycle.
The Programmable Trigger Unit (PTU) is intended to completely avoid CPU involvement in the time
acquisitions of state variables during the control cycle that can be half, full, multiple PWM cycles.
All acquisition time values are stored inside the global memory map, basically inside the system memory;
see the MMC section for the supported memory area. In such cases the pre-setting of the acquisition times
needs to be completed during the previous control cycle to where the actual acquisitions are to be made.
14.1.1 Features
The PTU module includes these distinctive features:
• One 16 bit counter as time base for all trigger events
• Two independent trigger generators (TG0 and TG1)
• Up to 32 trigger events per trigger generator
• Global Load OK support, to guarantee coherent update of all control loop modules
• Trigger values stored inside the global memory map, basically inside system memory
• Software generated reload event and Trigger event generation for debugging
Module A
Module B
reload_is_async
Control Logic ptu_reload_is_async
reload PTURE
ptu_reload
PTU glb_ldok
0x0000 R 0 0 0 0 0
PTUE PTUFRZ TG1EN TG0EN
W
0x0001 R 0 0 0 0 0 0 0
PTUC PTULDOK
W
0x0002 R 0 0 0 0 0 0 0
PTUIEH PTUROIE
W
0x0003 R
PTUIEL TG1AEIE TG1REIE TG1TEIE TG1DIE TG0AEIE TG0REIE TG0TEIE TG0DIE
W
0x0004 R 0 0 0 0 0 0
PTUIFH PTUDEEF PTUROIF
W
0x0005 R
PTUIFL TG1AEIF TG1REIF TG1TEIF TG1DIF TG0AEIF TG0REIF TG0TEIF TG0DIF
W
0x0006 R 0 0 0 0 0 0 0
TG0LIST TG0LIST
W
0x0007 R 0 0 0 TG0TNUM[4:0]
TG0TNUM W
0x0008 R TG0TV[15:8]
TG0TVH W
= Unimplemented
Figure 14-2. PTU Register Summary
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0009 R TG0TV[7:0]
TG0TVL W
0x000A R 0 0 0 0 0 0 0
TG1LIST TG1LIST
W
0x000B R 0 0 0 TG1TNUM[4:0]
TG1TNUM W
0x000C R TG1TV[15:8]
TG1TVH W
0x000D R TG1TV[7:0]
TG1TVL W
0x000E R PTUCNT[15:8]
PTUCNTH W
0x000F R PTUCNT[7:0]
PTUCNTL W
0x0010 R 0 0 0 0 0 0 0 0
Reserved W
0x0011 R
PTUPTRH PTUPTR[23:16]
W
0x0012 R
PTUPTRM PTUPTR[15:8]
W
0x0013 R 0
PTUPTRL PTUPTR[7:1]
W
0x0014 R 0 TG0L10DX[6:0]
TG0L0IDX W
0x0015 R 0
TG0L1IDX TG0L1IDX[6:0]
W
0x0016 R 0
TG1L0IDX TG1L0IDX[6:0]
W
0x0017 R 0
TG1L1IDX TG1L1IDX[6:0]
W
= Unimplemented
Figure 14-2. PTU Register Summary
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0018 - 0x001E R 0 0 0 0 0 0 0 0
Reserved W
0x001F R 0 0 0 0 0
PTUDEBUG PTUREPE PTUT1PE PTUT0PE
W PTUFRE TG1FTE TG0FTE
= Unimplemented
Figure 14-2. PTU Register Summary
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PTUFRZ TG1EN TG0EN
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6 PTU Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the PTU time base
PTUFRZ counter. If this bit is set, whenever the MCU is in freeze mode, the input clock to the time base counter is disabled.
In this way, the counters can be stopped while in freeze mode so that once normal program flow is continued, the
counter is re-enabled.
0 Allow time base counter to continue while in freeze mode
1 Disable time base counter clock whenever the part is in freeze mode
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTULDOK
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
0 Load Okay — When this bit is set by the software, this allows the trigger generator to switch to the alternative
PTULDOK list and load the trigger time values at the next reload event from the new list. If the reload event occurs when
the PTULDOK bit is not set then the trigger generator generates a reload overrun event and uses the previously
used list. At the next reload event this bit is cleared by control logic. Write 0 is only possible if TG0EN and
TG1EN is cleared.
The PTULDOK can be used by other module as global load OK (glb_ldok).
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
PTUROIE
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
0 PTU Reload Overrun Interrupt Enable — Enables PTU reload overrun interrupt.
PTUROIE 0 No interrupt will be requested whenever PTUROIF is set
1 Interrupt will be requested whenever PTUROIF is set
7 6 5 4 3 2 1 0
R
TG1AEIE TG1REIE TG1TEIE TG1DIE TG0AEIE TG0REIE TG0TEIE TG0DIE
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 Trigger Generator 1 Memory Access Error Interrupt Enable — Enables trigger generator memory access error
TG1AEIE interrupt.
0 No interrupt will be requested whenever TG1AEIF is set
1 Interrupt will be requested whenever TG1AEIF is set
6 Trigger Generator 1 Reload Error Interrupt Enable — Enables trigger generator reload error interrupt.
TG1REIE 0 No interrupt will be requested whenever TG1REIF is set
1 Interrupt will be requested whenever TG1REIF is set
Field Description
5 Trigger Generator 1 Timing Error Interrupt Enable — Enables trigger generator timing error interrupt.
TG1TEIE 0 No interrupt will be requested whenever TG1TEIF is set
1 Interrupt will be requested whenever TG1TEIF is set
4 Trigger Generator 1 Done Interrupt Enable — Enables trigger generator done interrupt.
TG1DIE 0 No interrupt will be requested whenever TG1DIF is set
1 Interrupt will be requested whenever TG1DIF is set
3 Trigger Generator 0 Memory Access Error Interrupt Enable — Enables trigger generator memory access error
TG0AEIE interrupt.
0 No interrupt will be requested whenever TG0AEIF is set
1 Interrupt will be requested whenever TG0AEIF is set
2 Trigger Generator 0 Reload Error Interrupt Enable — Enables trigger generator reload error interrupt.
TG0REIE 0 No interrupt will be requested whenever TG0REIF is set
1 Interrupt will be requested whenever TG0REIF is set
1 Trigger Generator 0 Timing Error Interrupt Enable — Enables trigger generator timing error interrupt.
TG0TEIE 0 No interrupt will be requested whenever TG0TEIF is set
1 Interrupt will be requested whenever TG0TEIF is set
0 Trigger Generator 0 Done Interrupt Enable — Enables trigger generator done interrupt.
TG0DIE 0 No interrupt will be requested whenever TG0DIF is set
1 Interrupt will be requested whenever TG0DIF is set
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
PTUDEEF PTUROIF
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
1 PTU Double bit ECC Error Flag — This bit is set if the read data from the memory contains double bit ECC
PTUDEEF errors. While this bit is set the trigger generation of both trigger generators stops.
0 No double bit ECC error occurs
1 Double bit ECC error occurs
0 PTU Reload Overrun Interrupt Flag — If reload event occurs when the PTULDOK bit is not set then this bit will
PTUROIF be set. This bit is not set if the reload event was forced by an asynchronous commutation event.
0 No reload overrun occurs
1 Reload overrun occurs
7 6 5 4 3 2 1 0
R
TG1AEIF TG1REIF TG1EIF TG1DIF TG0AEIF TG0REIF TG0EIF TG0DIF
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 Trigger Generator 1 Memory Access Error Interrupt Flag — This bit is set if trigger generator 1 uses a read
TG1AEIF address outside the memory address range, see the MMC section for the supported memory area.
0 No trigger generator 1 memory access error occurs
1 Trigger generator 1 memory access error occurs
6 Trigger Generator 1 Reload Error Interrupt Flag — This bit is set if a new reload event occurs when the trigger
TG1REIF generator has neither reached the end of list symbol nor the maximum possible triggers. This bit is not set if the
reload event was forced by an asynchronous commutation event.
0 No trigger generator 1 reload error occurs
1 Trigger generator 1 reload error occurs
5 Trigger Generator 1 Timing Error Interrupt Flag — This bit is set if the trigger generator receives a time value
TG1TEIF which is below the current counter value.
0 No trigger generator 1 error occurs
1 Trigger generator 1 error occurs
4 Trigger Generator 1 Done Interrupt Flag —This bit is set if the trigger generator receives the end of list symbol
TG1DIF or the maximum number of generated trigger events was reached.
0 Trigger generator 1 is running
1 Trigger generator 1 is done
3 Trigger Generator 0 Memory Access Error Interrupt Flag — This bit is set if trigger generator 0 uses a read
TG0AEIF address outside the memory address range, see the MMC section for the supported memory area.
0 No trigger generator 0 memory access error occurred
1 Trigger generator 0 memory access error occurred
2 Trigger Generator 0 Reload Error Interrupt Flag — This bit is set if a new reload event occurs when the trigger
TG0REIF generator has neither reached the end of list symbol nor the maximum possible triggers. This bit is not set if the
reload event was forced by an asynchronous commutation event.
0 No trigger generator 0 reload error occurs
1 Trigger generator 0 reload error occurs
1 Trigger Generator 0 Timing Error Interrupt Flag — This bit is set if the trigger generator receives a time value
TG0TEIF which is below the current counter value.
0 No trigger generator 0 error occurs
1 Trigger generator 0 error occurs
0 Trigger Generator 0 Done Interrupt Flag —This bit is set if the trigger generator receives the end of list symbol
TG0DIF or the maximum number of generated trigger events was reached.
0 Trigger generator 0 is running
1 Trigger generator 0 is done
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
TG0LIST
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
0 Trigger Generator 0 List — This bit shows the number of the current used list.
TG0LIST 0 Trigger generator 0 is using list 0
1 Trigger generator 0 is using list 1
7 6 5 4 3 2 1 0
R 0 0 0 TG0TNUM[4:0]
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
4:0 Trigger Generator 0 Trigger Number — This register shows the number of generated triggers since the last
TG0TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this
register. See also Figure 14-22.
7 6 5 4 3 2 1 0
R TG0TV[15:8]
Reset
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R TG0TV[7:0]
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
TG0TV[15:0] Trigger Generator 0 Trigger Value — This register contains the trigger value to generate the next trigger. If
the time base counter reach this value the next trigger event is generated. If the trigger generator reached the
end of list (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger
number 32 then the last used trigger value is visible inside this register. See also Figure 14-22.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
TG1LIST
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
0 Trigger Generator 1 List — This bit shows the number of the current used list.
TG1LIST 0 Trigger generator 1 is using list 0
1 Trigger generator 1 is using list 1
7 6 5 4 3 2 1 0
R 0 0 0 TG1TNUM[4:0]
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
4:0 Trigger Generator 1 Trigger Number — This register shows the number of generated triggers since the last
TG1TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this
register. See also Figure 14-22.
7 6 5 4 3 2 1 0
R TG1TV[15:8]
Reset
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R TG1TV[7:0]
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
TG1TV[15:0] Trigger Generator 1 Next Trigger Value — This register contains the currently used trigger value to generate
the next trigger. If the time base counter reach this value the next trigger event is generated. If the trigger
generator reached the end of list (EOL) symbol then this value is visible inside this register. If the last generated
trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 14-
22.
7 6 5 4 3 2 1 0
R PTUCNT[15:8]
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R PTUCNT[7:0]
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
PTUCNT[15:0] PTU Time Base Counter value — This register contains the current status of the internal time base counter. If
both TG are done with the execution of the trigger list then the counter also stops. The counter is restarted by
the next reload event.
7 6 5 4 3 2 1 0
R
PTUPTR[23:16]
W
Reset
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
PTUPTR[15:8]
W
Reset
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R 0
PTUPTR[7:1]
W
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
PTUPTR PTU Pointer — This register cannot be modified if TG0EN or TG1EN bit is set. This register defines the start
[23:0] address of the used list area inside the global memory map. For more information see Section 14.4.2, “Memory
based trigger event list”.
7 6 5 4 3 2 1 0
R 0 TG0L0IDX[6:0]
Reset
0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6:0 Trigger Generator 0 List 0 Index Register — This register defines offset of the start point for the trigger event
TG0L0IDX list 0 used by trigger generator 0. This register is read only, so the list 0 for trigger generator 0 will start at the
[6:0] PTUPTR address. For more information see Section 14.4.2, “Memory based trigger event list”.
7 6 5 4 3 2 1 0
R 0
TG0L1IDX[6:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6:0 Trigger Generator 0 List 1 Index Register — This register cannot be modified after the TG0EN bit is set. This
TG0L1IDX register defines offset of the start point for the trigger event list 1 used by trigger generator 0. For more
[6:0] information see Section 14.4.2, “Memory based trigger event list”.
7 6 5 4 3 2 1 0
R 0
TG1L0IDX[6:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6:0 Trigger Generator 1 List 0 Index Register — This register cannot be modified after the TG1EN bit is set. This
TG1L0IDX register defines offset of the start point for the trigger event list 0 used by trigger generator 1. For more
[6:0] information see Section 14.4.2, “Memory based trigger event list”.
7 6 5 4 3 2 1 0
R 0
TG1L1IDX[6:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6:0 Trigger Generator 1 List 1 Index Register — This register cannot be modified after the TG1EN bit is set. This
TG1L1IDX register defines offset of the start point for the trigger event list 1 used by trigger generator 1. For more
[6:0] information see Section 14.4.2, “Memory based trigger event list”.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PTUREPE PTUT1PE PTUT0PE
W PTUFRE TG1FTE TG0FTE
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6 PTURE Pin Enable — This bit enables the output port for pin PTURE.
PTUREPE 0 PTURE output port are disabled
1 PTURE output port are enabled
5 PTU PTUT1 Pin Enable — This bit enables the output port for pin PTUT1.
PTUT1PE 0 PTUT1 output port are disabled
1 PTUT1 output port are enabled
4 PTU PTUT0 Pin Enable — This bit enables the output port for pin PTUT0.
PTUT0PE 0 PTUT0 output port are disabled
1 PTUT0 output port are enabled
2 Force Reload event generation — If one of the TGs is enabled then writing 1 to this bit will generate a reload
PTUFRE event. The reload event forced by PTUFRE does not set the PTUROIF interrupt flag. Also the ptu_reload signal
asserts for one bus clock cyclet. Writing 0 to this bit has no effect. Always reads back as 0. This behavior is not
available during stop or freeze mode.
1 Trigger Generator 1 Force Trigger Event — If TG1 is enabled then writing 1 to this bit will generate a trigger
TG1FTE event independent on the list based trigger generation. Writing 0 to this bit has no effect. Always reads back as
0.This behavior is not available during stop or freeze mode.
0 Trigger Generator 0 Force Trigger Event — If TG0 is enabled then writing 1 to this bit will generate a trigger
TG0FTE event independent on the list based trigger generation. Writing 0 to this bit has no effect. Always reads back as
0. This behavior is not available during stop or freeze mode.
14.4.1 General
The PTU module consists of two trigger generators (TG0 and TG1). For each TG a separate enable bit is
available, so that both TGs can be enabled independently.
If both trigger generators are disabled then the PTU is disabled, the trigger generation stops and the
memory accesses are disabled.
The trigger generation of the PTU module is synchronized to the incoming reload event. This reload event
resets and restarts the internal time base counter and makes sure that the first trigger value from the actual
trigger list is loaded. Furthermore the corresponding module is informed that a new control cycle has
started.
If the counter value matches the current trigger value then a trigger event is generated. In this way, the
reload event is delayed by the number of bus clock cycles defined by the current trigger value. After this,
a new trigger value is loaded from the memory and the TG waits for the next match. So up to 32 trigger
events per control cycle can be generated. If the trigger value is 0x0000 or 32 trigger events have been
generated during this control cycle, the TGxDIF bit is set and the TG waits for the next reload event.
Figure 14-22 shows an example of the trigger generation using the trigger values shown in Figure 14-23.
Figure 14-22. TG0 trigger generation example
Control Cycle
Delay T1
Delay T0
t
outgoing trigger events
PTUCNT
TG0LIST
TG0TV T0 T1 T2 0x0000 T0
TG0TNUM 0 1 2 3 0
TG0DIF
NOTE
If the trigger list contains less than 32 trigger values a delay between the
generation of the last trigger and the assertion of the done interrupt flag will
be visible. During this time the PTU loads the next trigger value from the
memory to evaluate the EOL symbol.
reload event
PTULDOK
TG0LIST
TG0DIF TG0DIF
mechanism” above. The only difference is, that during an async reload event the error interrupt flags
PTUROIF and TGxREIF are not generated.
error condition the trigger generator reloads the new data from the trigger list and starts to generate the
trigger. During an async reload event the TGxREIF interrupt flag is not set.
If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then
the data is ignored and the trigger generator reload error flag (TGxREIF) is not set.
14.4.6 Debugging
To see the internal status of the trigger generator the register TGxLIST, TGxTNUM, and TGxTV can be
used. The TGxLIST register shows the number of currently used list. The TGxTNUM shows the number
of generated triggers since the last reload event. If the maximum number of triggers was generated then
this register shows zero. The trigger value loaded from the memory to generate the next trigger event is
visible inside the TGxTV register. If the execution of the trigger list is done then these registers are
unchanged until the next reload event. The next PWM reload event clears the TGxTNUM register and
toggles the used trigger list if PTULDOK was set.
To generate a reload event or trigger event independent from the PWM status the debug register bits
PTUFRE or TGxFTE can be used. A write one to this bits will generate the associated event.This behavior
is not available during stop or freeze mode.
V04.00 03 Dec 2013 15.3.2.3/15-573 • Added write protection to REV1-0 bits (WP)
15.3.2.11/15-579 • Added PWM read through PMFOUTB (generator output read option)
15.3.2.18/15-585 • Updated note at CINVn bits
V04.1 05 Nov 2015 Figure 15-51./15- • correct figure Figure 15-51./15-606, Figure 15-52./15-607,Figure 15-
606 53./15-607
Figure 15-52./15- • update DMPx register description
607Figure 15-
53./15-607
Glossary
Table 15-2. Glossary of Terms
Term Definition
Term Definition
PWM active state PWM logic level high causing external power device to conduct
Normal output
Positive polarity
PWM inactive PWM logic level low causing external power device not to conduct
or disabled state
Inverted output
Negative polarity
PWM clock Clock supplied to PWM and deadtime generators. Based on core clock. Rate depends on prescaler setting.
PWM cycle PWM period determined by modulus register and PWM clock rate. Note the differences in edge- or center-
aligned mode.
PWM reload cycle A.k.a. control cycle. Determined by load frequency which is 1 to n-times the PWM cycle. PWM reload cycle
triggered double-buffered registers take effect at the next PWM reload event.
Commutation cycle For 6-step motor control only. Started by an event external to the PMF module (async_event). This may be
a delayed Hall effect or back-EMF zero crossing event determining the rotor position. Commutation cycle
triggered double-buffered registers take effect at the next commutation event and optionally the PWM
counters are restarted.
15.1 Introduction
NOTE
Device reference manuals specify which module version is integrated on the
device. Some reference manuals support families of devices, with device
dependent module versions. This chapter describes the superset. The feature
differences are listed in Table 15-3.
Feature V3 V4
Ability to read the PWM output value through PMFOUTB not available available
register
The Pulse width Modulator with Fault protection (PMF) module can be configured for one, two, or three
complementary pairs. For example:
• One complementary pair and four independent PWM outputs
• Two complementary pairs and two independent PWM outputs
15.1.1 Features
• Three complementary PWM signal pairs, or six independent PWM signals
• Edge-aligned or center-aligned mode
• Features of complementary channel operation:
— Deadtime insertion
— Separate top and bottom pulse width correction via current status inputs or software
— Three variants of PWM output:
– Asymmetric in center-aligned mode
– Variable edge placement in edge-aligned mode
– Double switching in center-aligned mode
• Three 15-bit counters based on core clock
• Separate top and bottom polarity control
• Half-cycle reload capability
• Integral reload rates from 1 to 16
• Programmable fault protection
• Link to timer output compare for 6-step BLDC commutation support with optional counter restart
Reload overrun interrupt
• PWM compare output polarity control Software-controlled PWM outputs, complementary or
independent
Mode Description
STOP PWM outputs are disabled
WAIT PWM outputs are disabled as a function of the PMFWAI bit
FREEZE PWM outputs are disabled as a function of the PMFFRZ bit
CORE
CLOCK MTG MULTIPLE REGISTERS OR BITS
FOR TIMEBASE A, B, OR C
PRSC PRESCALER Single-underline denotes buffered registers taking effect at PWM reload (pmf_reloada,b,c)
Double-underline denotes buffered registers taking effect at commutation event (async_event)
DEADTIME PMFDTM
MUX, REGISTER
SWAP & INSERTION
CURRENT
SENSE TOPNEG
TOP/BOTTOM
GENERATION
BOTNEG
6
buffered mode. In addition, if restart is enabled (RSTRTx=1), the commutation event generates both
“PWM reload event” and “PWM reload-is-asynchronous event” simultaneously.
00 direct input
01 rising edge
10 falling edge
11 both edges
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R
0x0000 PMFCFG0 WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA
W
R 0
0x0001 PMFCFG1 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA
W
R
0x0002 PMFCFG2 REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
W
R 0
0x0003 PMFCFG3 PMFWAI PMFFRZ VLMODE PINVC PINVB PINVA
W
R 0 0
0x0004 PMFFEN FEN5 FEN4 FEN3 FEN2 FEN1 FEN0
W
R 0 0
0x0005 PMFFMOD FMOD5 FMOD4 FMOD3 FMOD2 FMOD1 FMOD0
W
R 0 0
0x0006 PMFFIE FIE5 FIE4 FIE3 FIE2 FIE1 FIE0
W
R 0 0
0x0007 PMFFIF FIF5 FIF4 FIF3 FIF2 FIF1 FIF0
W
R 0 0 0 0
0x0008 PMFQSMP0 QSMP5 QSMP4
W
R
0x0009 PMFQSMP1 QSMP3 QSMP2 QSMP1 QSMP0
W
0x000A- R 0 0 0 0 0 0 0 0
Reserved
0x000B W
= Unimplemented or Reserved
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R 0 0
0x000C PMFOUTC OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0
W
R 0 0
0x000D PMFOUTB OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
W
R 0 0 0
0x000F PMFCCTL ISENS IPOLC IPOLB IPOLA
W
R
0x0010 PMFVAL0 PMFVAL0
W
R
0x0011 PMFVAL0 PMFVAL0
W
R
0x0012 PMFVAL1 PMFVAL1
W
R
0x0013 PMFVAL1 PMFVAL1
W
R
0x0014 PMFVAL2 PMFVAL2
W
R
0x0015 PMFVAL2 PMFVAL2
W
R
0x0016 PMFVAL3 PMFVAL3
W
R
0x0017 PMFVAL3 PMFVAL3
W
R
0x0018 PMFVAL4 PMFVAL4
W
R
0x0019 PMFVAL4 PMFVAL4
W
R
0x001A PMFVAL5 PMFVAL5
W
= Unimplemented or Reserved
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R
0x001B PMFVAL5 PMFVAL5
W
R 0 0
0x001E PMFICCTL PECC PECB PECA ICCC ICCB ICCA
W
R 0 0
0x001F PMFCINV CINV5 CINV4 CINV3 CINV2 CINV1 CINV0
W
R 0 0 0
0x0020 PMFENCA PWMENA GLDOKA RSTRTA LDOKA PWMRIEA
W
R
0x0021 PMFFQCA LDFQA HALFA PRSCA PWMRFA
W
R 0 PMFCNTA
0x0022 PMFCNTA
W
R PMFCNTA
0x0023 PMFCNTA
W
R 0
0x0024 PMFMODA PMFMODA
W
R
0x0025 PMFMODA PMFMODA
W
R 0 0 0 0
0x0026 PMFDTMA PMFDTMA
W
R
0x0027 PMFDTMA PMFDTMA
W
R 0 0 0
0x0028 PMFENCB PWMENB GLDOKB RSTRTB LDOKB PWMRIEB
W
R
0x0029 PMFFQCB LDFQB HALFB PRSCB PWMRFB
W
= Unimplemented or Reserved
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R 0 PMFCNTB
0x002A PMFCNTB
W
R PMFCNTB
0x002B PMFCNTB
W
R 0
0x002C PMFMODB PMFMODB
W
R
0x002D PMFMODB PMFMODB
W
R 0 0 0 0
0x002E PMFDTMB PMFDTMB
W
R
0x002F PMFDTMB PMFDTMB
W
R 0 0 0
0x0030 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC
W
R
0x0031 PMFFQCC LDFQC HALFC PRSCC PWMRFC
W
= Unimplemented or Reserved
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R 0 PMFCNTC
0x0032 PMFCNTC
W
R PMFCNTC
0x0033 PMFCNTC
W
R 0
0x0034 PMFMODC PMFMODC
W
R
0x0035 PMFMODC PMFMODC
W
R 0 0 0 0
0x0036 PMFDTMC PMFDTMC
W
R
0x0037 PMFDTMC PMFDTMC
W
R
0x0038 PMFDMP0 DMP05 DMP04 DMP03 DMP02 DMP01 DMP00
W
R
0x0039 PMFDMP1 DMP15 DMP14 DMP13 DMP12 DMP11 DMP10
W
R
0x003A PMFDMP2 DMP25 DMP24 DMP23 DMP22 DMP21 DMP20
W
R
0x003B PMFDMP3 DMP35 DMP34 DMP33 DMP32 DMP31 DMP30
W
R
0x003C PMFDMP4 DMP45 DMP44 DMP43 DMP42 DMP41 DMP40
W
R
0x003D PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50
W
R 0 0
0x003E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0
W
R 0 0 0 0 0 0 0 0
0x003F Reserved
W
= Unimplemented or Reserved
Field Description
7 Write Protect— This bit enables write protection to be used for all write-protectable registers. While clear, WP
WP allows write-protected registers to be written. When set, WP prevents any further writes to write-protected
registers. Once set, WP can be cleared only by reset.
0 Write-protectable registers may be written
1 Write-protectable registers are write-protected
6 Multiple Timebase Generators — This bit determines the number of timebase counters used. This bit cannot
MTG be modified after the WP bit is set.
If MTG is set, PWM generators B and C and registers 0x0028 – 0x0037 are availabled.The three generators have
their own variable frequencies and are not synchronized.
If MTG is cleared, PMF registers from 0x0028 – 0x0037 can not be written and read zeroes, and bits EDGEC
and EDGEB are ignored. Pair A, Pair B, and Pair C PWMs are synchronized to PWM generator A and use
registers from 0x0020 – 0x0027.
0 Single timebase generator
1 Multiple timebase generators
5 Edge-Aligned or Center-Aligned PWM for Pair C — This bit determines whether PWM4 and PWM5 channels
EDGEC will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be
modified after the WP bit is set.
0 PWM4 and PWM5 are center-aligned PWMs
1 PWM4 and PWM5 are edge-aligned PWMs
4 Edge-Aligned or Center-Aligned PWM for Pair B — This bit determines whether PWM2 and PWM3 channels
EDGEB will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be
modified after the WP bit is set.
0 PWM2 and PWM3 are center-aligned PWMs
1 PWM2 and PWM3 are edge-aligned PWMs
3 Edge-Aligned or Center-Aligned PWM for Pair A— This bit determines whether PWM0 and PWM1 channels
EDGEA will use edge-aligned or center-aligned waveforms. It determines waveforms for Pair B and Pair C if the MTG bit
is cleared. This bit cannot be modified after the WP bit is set.
0 PWM0 and PWM1 are center-aligned PWMs
1 PWM0 and PWM1 are edge-aligned PWMs
2 Independent or Complementary Operation for Pair C— This bit determines if the PWM channels 4 and 5 will
INDEPC be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM4 and PWM5 are complementary PWM pair
1 PWM4 and PWM5 are independent PWMs
Field Description
1 Independent or Complementary Operation for Pair B— This bit determines if the PWM channels 2 and 3 will
INDEPB be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM2 and PWM3 are complementary PWM pair
1 PWM2 and PWM3 are independent PWMs
0 Independent or Complementary Operation for Pair A— This bit determines if the PWM channels 0 and 1 will
INDEPA be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM0 and PWM1 are complementary PWM pair
1 PWM0 and PWM1 are independent PWMs
A normal PWM output or positive polarity means that the PWM channel outputs high when the counter
value is smaller than or equal to the pulse width value and outputs low otherwise. An inverted output or
negative polarity means that the PWM channel outputs low when the counter value is smaller than or equal
to the pulse width value and outputs high otherwise.
NOTE
The TOPNEGx and BOTNEGx are intended for adapting to the polarity of
external predrivers on devices driving the PWM output directly to pins. If
an integrated GDU is driven it must be made sure to keep the reset values of
these bits in order not to violate the deadtime insertion.
Table 15-7. PMFCFG1 Field Descriptions
Field Description
6 Enable Commutation Event — This bit enables the commutation event input and activates buffering of registers
ENCE PMFOUTC and PMFOUTB and MSKx bits.This bit cannot be modified after the WP bit is set.If set to zero the
commutation event input is ignored and writes to the above registers and bits will take effect immediately. If set
to one, the commutation event input is enabled and the value written to the above registers and bits does not
take effect until the next commutation event occurs.
0 Commutation event input disabled and PMFOUTC, PMFOUTB and MSKn not buffered
1 Commutation event input enabled and PMFOUTC, PMFOUTB and MSKn buffered
5 Pair C Bottom-Side PWM Polarity — This bit determines the polarity for Pair C bottom-side PWM (PWM5). This
BOTNEGC bit cannot be modified after the WP bit is set.
0 Positive PWM5 polarity
1 Negative PWM5 polarity
Field Description
4 Pair C Top-Side PWM Polarity — This bit determines the polarity for Pair C top-side PWM (PWM4). This bit
TOPNEGC cannot be modified after the WP bit is set.
0 Positive PWM4 polarity
1 Negative PWM4 polarity
3 Pair B Bottom-Side PWM Polarity — This bit determines the polarity for Pair B bottom-side PWM (PWM3). This
BOTNEGB bit cannot be modified after the WP bit is set.
0 Positive PWM3 polarity
1 Negative PWM3 polarity
2 Pair B Top-Side PWM Polarity — This bit determines the polarity for Pair B top-side PWM (PWM2). This bit
TOPNEGB cannot be modified after the WP bit is set.
0 Positive PWM2 polarity
1 Negative PWM2 polarity
1 Pair A Bottom-Side PWM Polarity — This bit determines the polarity for Pair A bottom-side PWM (PWM1). This
BOTNEGA bit cannot be modified after the WP bit is set.
0 Positive PWM1 polarity
1 Negative PWM1 polarity
0 Pair A Top-Side PWM Polarity — This bit determines the polarity for Pair A top-side PWM (PWM0). This bit
TOPNEGA cannot be modified after the WP bit is set.
0 Positive PWM0 polarity
1 Negative PWM0 polarity
Field Description
Field Description
WARNING
When using the TOPNEG/BOTNEG bits and the MSKn bits at the same
time, when in complementary mode, it is possible to have both PMF channel
outputs of a channel pair set to one.
Field Description
7 PMF Stops While in WAIT Mode — When set to zero, the PWM generators will continue to run while the chip
PMFWAI is in WAIT mode. In this mode, the peripheral clock continues to run but the CPU clock does not. If the device
enters WAIT mode and this bit is one, then the PWM outputs will be switched to their inactive state until WAIT
mode is exited. At that point the PWM outputs will resume operation as programmed in the PWM registers. This
bit cannot be modified after the WP bit is set.
0 PMF continues to run in WAIT mode
1 PMF is disabled in WAIT mode
6 PMF Stops While in FREEZE Mode — When set to zero, the PWM generators will continue to run while the
PMFFRZ chip is in FREEZE mode. If the device enters FREEZE mode and this bit is one, then the PWM outputs will be
switched to their inactive state until FREEZE mode is exited. At that point the PWM outputs will resume operation
as programmed in the PWM registers. This bit cannot be modified after the WP bit is set.
0 PMF continues to run in FREEZE mode
1 PMF is disabled in FREEZE mode
Field Description
4–3 Value Register Load Mode — This field determines the way the value registers are being loaded. This register
VLMODE cannot be modified after the WP bit is set.
[1:0] 00 Each value register is accessed independently
01 Writing to value register zero also writes to value registers one to five
10 Writing to value register zero also writes to value registers one to three
11 Reserved (defaults to independent access)
2 PWM Invert Complement Source Pair C — This bit controls PWM4/PWM5 pair. When set, this bit inverts the
PINVC COMPSRCC signal. This bit has no effect in independent mode.
Note: PINVC is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVC returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCC inverted only in complementary mode
1 PWM Invert Complement Source Pair B — This bit controls PWM2/PWM3 pair. When set, this bit inverts the
PINVB COMPSRCB signal. This bit has no effect in independent mode.
Note: PINVB is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVB returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCB inverted only in complementary mode
0 PWM Invert Complement Source Pair A — This bit controls PWM0/PWM1 pair. When set, this bit inverts the
PINVA COMPSRCA signal. This bit has no effect on in independent mode.
Note: PINVA is buffered. The value written does not take effect until the LDOKA bit or global load OK is set and
the next PWM load cycle begins. Reading PINVA returns the value in the buffer and not necessarily the
value in use.
0 No inversion
1 COMPSRCA inverted only in complementary mode
Field Description
Field Description
6,4-0 Fault m Pin Recovery Mode — This bit selects automatic or manual recovery of FAULTm input faults. See
FMOD[5:0] Section 15.4.13.2, “Automatic Fault Recovery” and Section 15.4.13.3, “Manual Fault Recovery” for more details.
0 Manual fault recovery of FAULTm input faults
1 Automatic fault recovery of FAULTm input faults
m is 0, 1, 2, 3, 4 and 5.
Field Description
6,4-0 Fault m Pin Interrupt Enable — This bit enables CPU interrupt requests to be generated by the FAULTm input.
FIE[5:0] The fault protection circuit is independent of the FIEm bit and is active when FENm is set. If a fault is detected,
the PWM outputs are disabled or switched to output control according to the PMF Disable Mapping registers.
0 FAULTm CPU interrupt requests disabled
1 FAULTm CPU interrupt requests enabled
m is 0, 1, 2, 3, 4 and 5.
Field Description
6,4-0 Fault m Interrupt Flag — This flag is set after the required number of samples have been detected after an edge
FIF[5:0] to the active level(1) on the FAULTm input. Writing a logic one to FIFm clears it. Writing a logic zero has no effect.
If a set flag is attempted to be cleared and a flag setting event occurs in the same cycle, then the flag remains
set. The fault protection is enabled when FENm is set even when the PWMs are not enabled; therefore, a fault
will be latched in, requiring to be cleared in order to prevent an interrupt.
0 No fault on the FAULTm input
1 Fault on the FAULTm input
Note: Clearing FIFm satisfies pending FIFm CPU interrupt requests.
m is 0, 1, 2, 3, 4 and 5.
1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active-
high. For availability and configurability of fault inputs on pins refer to the device overview section.
1. Read: Anytime
Write: This register cannot be modified after the WP bit is set.
Field Description
7–0 Fault m Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULTm
QSMPm[1:0] input to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault
is present and each sample after that is taken every four core clock cycles. See Table 15-15. This register cannot
be modified after the WP bit is set.
m is 0, 1, 2, 3, 4 and 5.
Field Description
5–0 OUTCTLn Bits — These bits enable software control of their corresponding PWM output. When OUTCTLn is
OUTCTL[5:0] set, the OUTn bit takes over the directly controls the level of the PWMn output.
Note: OUTCTLn is buffered if ENCE is set. If ENCE is set, then the value written does not take effect until the
next commutation cycle begins. Reading OUTCTLn returns the value in the buffer and not necessarily the
value the output control is currently using.If ENCE is not set, then the OUTn bits take immediately effect
when OUTCTLn bit is set. If the OUTCTLn bit is cleared then the OUTn control is disabled at the next
PMF cycle start.
When operating the PWM in complementary mode, these bits must be switched in pairs for proper operation.
That is OUTCTL0 and OUTCTL1 must have the same value; OUTCTL2 and OUTCTL3 must have the same
value; and OUTCTL4 and OUTCTL5 must have the same value. Otherwise see the behavior described on
chapter Section 15.8.2, “BLDC 6-Step Commutation”.
0 Software control disabled
1 Software control enabled
n is 0, 1, 2, 3, 4 and 5.
Field Description
5–0 OUTn Bits — If the corresponding OUTCTLn bit is set, these bits control the PWM outputs, illustrated in
OUT[5:0] Table 15-18.
If the related OUTCTLn=1 a read returns the register contents OUTn else the current PWM output states are
returned(1) On module version V3 the read returns always the register value.
Note: OUTn is buffered if ENCE is set. The value written does not take effect until the next commutation cycle
begins. Reading OUTn (with OUTCTLn=1) returns the value in the buffer and not necessarily the value the
output control is currently using.
n is 0, 1, 2, 3, 4 and 5.
1. only valid for module version V4
Field Description
5–0 DTn Bits — The DTn bits are grouped in pairs, DT0 and DT1, DT2 and DT3, DT4 and DT5. Each pair reflects
DT[5:0] the corresponding IS input value as sampled at the end of deadtime.
n is 0, 1, 2, 3, 4 and 5.
1. Read: Anytime
Write: Anytime
Field Description
5–4 Current Status Sensing Method — This field selects the top/bottom correction scheme, illustrated in Table 15-
ISENS[1:0] 21.
Note: The user must provide current sensing circuitry causing the voltage at the corresponding input to be low
for positive current and high for negative current. The top PWMs are PWM 0, 2, and 4 and the bottom
PWMs are PWM 1, 3, and 5.
Note: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM
cycle.
2 Current Polarity — This buffered bit selects the PMF Value register for PWM4 and PWM5 in top/bottom software
IPOLC correction in complementary mode.
0 PMF Value 4 register in next PWM cycle
1 PMF Value 5 register in next PWM cycle
1 Current Polarity — This buffered bit selects the PMF Value register for PWM2 and PWM3 in top/bottom software
IPOLB correction in complementary mode.
0 PMF Value 2 register in next PWM cycle
1 PMF Value 3 register in next PWM cycle
0 Current Polarity — This buffered bit selects the PMF Value register for PWM0 and PWM1 in top/bottom software
IPOLA correction in complementary mode.
0 PMF Value 0 register in next PWM cycle
1 PMF Value 1 register in next PWM cycle
2. The polarity of the related IS input is latched when both the top and bottom PWMs are off. At the
0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed.
NOTE
The IPOLx bits take effect at the beginning of the next PWM cycle,
regardless of the state of the LDOK bit or global load OK. Select top/bottom
software correction by writing 01 to the current select bits, ISENS[1:0], in
the PWM control register. Reading the IPOLx bits read the buffered value
and not necessarily the value currently in effect.
Field Description
15–0 PMF Value n Bits — The 16-bit signed value in this buffered register is the pulse width in PWM clock periods.
PMFVALn A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than,
or equal to the modulus, activates the PWM output for the entire PWM period. See Table 15-40. The terms
activate and deactivate refer to the high and low logic states of the PWM output.
Note: PMFVALn is buffered. The value written does not take effect until the related or global load OK bit is set
and the next PWM load cycle begins. Reading PMFVALn returns the value in the buffer and not necessarily
the value the PWM generator is currently using.
n is 0, 1, 2, 3, 4 and 5.
Field Description
Field Description
This register is used to control PWM pulse generation for various applications, such as a power-supply
phase-shifting application.
ICCx bits apply only in center-aligned operation during complementary mode. These control bits
determine whether values set in the IPOLx bits control or the whether PWM count direction controls which
PWM value register is used.
NOTE
The ICCx bits are buffered. The value written does not take effect until the
next PWM load cycle begins regardless of the state of the LDOK bit or
global load OK. Reading ICCx returns the value in a buffer and not
necessarily the value the PWM generator is currently using.
The PECx bits apply in edge-aligned and center-aligned operation during complementary mode. Setting
the PECx bits overrides the ICCx settings. This allows the PWM pulses generated by both the odd and even
PWM value registers to be ANDed together prior to the complementary logic and deadtime insertion.
NOTE
The PECx bits are buffered. The value written does not take effect until the
related LDOK bit or global load OK is set and the next PWM load cycle
begins. Reading PECn returns the value in a buffer and not necessarily the
value the PWM generator is currently using.
Field Description
Figure 15-21. PMF Internal Correction Control Register (PMFICCTL) Descriptions (continued)
Field Description
Field Description
5 PWM Compare Invert 5 — This bit controls the polarity of PWM compare output 5. Please see the output operations
CINV5 in Figure 15-42 and Figure 15-43.
0 PWM output 5 is high when PMFCNTC (PMFCNTA if MTG=0) is less than PMFVAL5
1 PWM output 5 is high when PMFCNTC (PMFCNTA if MTG=0) is greater than PMFVAL5
4 PWM Compare Invert 4 — This bit controls the polarity of PWM compare output 4. Please see the output operations
CINV4 in Figure 15-42 and Figure 15-43.
0 PWM output 4 is high when PMFCNTC (PMFCNTA if MTG=0) is less than PMFVAL4
1 PWM output 4 is high when PMFCNTC (PMFCNTA if MTG=0) is greater than PMFVAL4
3 PWM Compare Invert 3 — This bit controls the polarity of PWM compare output 3. Please see the output operations
CINV3 in Figure 15-42 and Figure 15-43.
0 PWM output 3 is high when PMFCNTB (PMFCNTA if MTG=0) is less than PMFVAL3
1 PWM output 3 is high when PMFCNTB (PMFCNTA if MTG=0) is greater than PMFVAL3
2 PWM Compare Invert 2 — This bit controls the polarity of PWM compare output 2. Please see the output operations
CINV2 in Figure 15-42 and Figure 15-43.
0 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is less than PMFVAL2
1 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is greater than PMFVAL2
Field Description
1 PWM Compare Invert 1 — This bit controls the polarity of PWM compare output 1. Please see the output operations
CINV1 in Figure 15-42 and Figure 15-43.
0 PWM output 1 is high when PMFCNTA is less than PMFVAL1
1 PWM output 1 is high when PMFCNTA is greater than PMFVAL1.
0 PWM Compare Invert 0 — This bit controls the polarity of PWM compare output 0. Please see the output operations
CINV0 in Figure 15-42 and Figure 15-43.
0 PWM output 0 is high when PMFCNTA is less than PMFVAL0.
1 PWM output 0 is high when PMFCNTA is greater than PMFVAL0
NOTE
Changing CINVn can affect the present PWM cycle, if the related
PMFVALn is zero.
Field Description
7 PWM Generator A Enable — When MTG is clear, this bit when set enables the PWM generators A, B and C
PWMENA and PWM0–5 outputs. When PWMENA is clear, PWM generators A, B and C are disabled, and the PWM0–5
outputs are in their inactive states unless the corresponding OUTCTL bits are set.
When MTG is set, this bit when set enables the PWM generator A and the PWM0 and PWM1 outputs.When
PWMENA is clear, the PWM generator A is disabled and PWM0 and PWM1 outputs are in their inactive states
unless the OUTCTL0 and OUTCTL1 bits are set.
After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator A and PWM0-1 (2–5 if MTG = 0) outputs disabled unless the respective OUTCTL bit is set
1 PWM generator A and PWM0-1 (2–5 if MTG = 0) outputs enabled
6 Global Load Okay A — When this bit is set, a PMF external global load OK defined on device level replaces the
GLDOKA function of LDOKA. This bit cannot be modified after the WP bit is set.
0 LDOKA controls reload of double buffered registers
1 PMF external global load OK controls reload of double buffered registers
2 Restart Generator A — When this bit is set, PWM generator A will be restarted at the next commutation event.
RSTRTA This bit cannot be modified after the WP bit is set.
0 No PWM generator A restart at the next commutation event.
1 PWM generator A restarts at the next commutation event
Field Description
1 Load Okay A — When MTG is clear, this bit allows loads of the PRSCA bits, the PMFMODA register, and the
LDOKA PMFVAL0-5 registers into a set of buffers. The buffered prescaler A divisor, PWM counter modulus A value, and
all PWM pulse widths take effect at the next PWM reload.
When MTG is set, this bit allows loads of the PRSCA bits, the PMFMODA register, and the PMFVAL0–1 registers
into a set of buffers. The buffered prescaler divisor A, PWM counter modulus A value, and PWM0–1 pulse widths
take effect at the next PWM reload.
Set LDOKA by reading it when it is logic zero and then writing a logic one to it. LDOKA is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKA.
0 Do not load new modulus A, prescaler A, and PWM0–1 (2–5 if MTG = 0) values
1 Load prescaler A, modulus A, and PWM0–1 (2–5 if MTG = 0) values
Note: Do not set PWMENA bit before setting the LDOKA bit and do not clear the LDOKA bit at the same time as
setting the PWMENA bit.
0 PWM Reload Interrupt Enable A — This bit enables the PWMRFA flag to generate CPU interrupt requests.
PWMRIEA 0 PWMRFA CPU interrupt requests disabled
1 PWMRFA CPU interrupt requests enabled
Field Description
7–4 Load Frequency A — This field selects the PWM load frequency according to Table 15-27. See
LDFQA[3:0] Section 15.4.12.3, “Load Frequency” for more details.
Note: The LDFQA field takes effect when the current load cycle is complete, regardless of the state of the
LDOKA bit or global load OK. Reading the LDFQA field reads the buffered value and not necessarily the
value currently in effect.
3 Half Cycle Reload A — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
HALFA on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter
matches the modulus in addition to the start of the PWM period at count zero. See Section 15.4.12.3, “Load
Frequency” for more details.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
2–1 Prescaler A — This buffered field selects the PWM clock frequency illustrated in Table 15-28.
PRSCA[1:0] Note: Reading the PRSCA field reads the buffered value and not necessarily the value currently in effect. The
PRSCA field takes effect at the beginning of the next PWM cycle and only when the LDOKA bit or global
load OK is set.
Field Description
0 PWM Reload Flag A — This flag is set at the beginning of every reload cycle regardless of the state of the
PWMRFA LDOKA bit or global load OK. Clear PWMRFA by reading PMFFQCA with PWMRFA set and then writing a logic
one to the PWMRFA bit. If another reload occurs before the clearing sequence is complete, writing logic one to
PWMRFA has no effect.
0 No new reload cycle since last PWMRFA clearing
1 New reload cycle since last PWMRFA clearing
Note: Clearing PWMRFA satisfies pending PWMRFA CPU interrupt requests.
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
NOTE
The PWM counter modulo register is buffered. The value written does not
take effect until the LDOKA bit or global load OK is set and the next PWM
load cycle begins. Reading PMFMODA returns the value in the buffer. It is
not necessarily the value the PWM generator A is currently using.
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel
operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime
of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration
is determined as follows:
Field Description
7 PWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written.
PWMENB If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 outputs. When
PWMENB is clear, PWM generator B is disabled, and the PWM2 and PWM3 outputs are in their inactive states
unless the corresponding OUTCTL bits are set.
After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator B and PWM2–3 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator B and PWM2–3 outputs enabled
6 Global Load Okay B — When this bit is set, a PMF external global load OK defined on device level replaces the
GLDOKB function of LDOKB. This bit cannot be modified after the WP bit is set.
0 LDOKB controls double reload of buffered registers
1 PMF external global load OK controls reload of double buffered registers
2 Restart Generator B — When this bit is set, PWM generator B will be restarted at the next commutation event.
RSTRTB This bit cannot be modified after the WP bit is set.
0 No PWM generator B restart at the next commutation event
1 PWM generator B restart at the next commutation event
1 Load Okay B — If MTG is clear, this bit reads zero and cannot be written.
LDOKB If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PMFVAL2-3 registers into a set of
buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at
the next PWM reload.
Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKB.
0 Do not load new modulus B, prescaler B, and PWM2–3 values
1 Load prescaler B, modulus B, and PWM2–3 values
Note: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time as
setting the PWMENB bit.
0 PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written.
PWMRIEB If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.
0 PWMRFB CPU interrupt requests disabled
1 PWMRFB CPU interrupt requests enabled
Field Description
7–4 Load Frequency B — This field selects the PWM load frequency according to Table 15-31. See
LDFQB[3:0] Section 15.4.12.3, “Load Frequency” for more details.
Note: The LDFQB field takes effect when the current load cycle is complete, regardless of the state of the
LDOKB bit or global load OK. Reading the LDFQB field reads the buffered value and not necessarily the
value currently in effect.
3 Half Cycle Reload B — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
HALFB on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter
matches the modulus in addition to the start of the PWM period at count zero. See Section 15.4.12.3, “Load
Frequency” for more details.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
2–1 Prescaler B — This buffered field selects the PWM clock frequency illustrated in Table 15-32.
PRSCB[1:0] Note: Reading the PRSCB field reads the buffered value and not necessarily the value currently in effect. The
PRSCB field takes effect at the beginning of the next PWM cycle and only when the LDOKB bit or global
load OK is set.
0 PWM Reload Flag B — This flag is set at the beginning of every reload cycle regardless of the state of the
PWMRFB LDOKB bit. Clear PWMRFB by reading PMFFQCB with PWMRFB set and then writing a logic one to the
PWMRFB bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFB
has no effect.
0 No new reload cycle since last PWMRFB clearing
1 New reload cycle since last PWMRFB clearing
Note: Clearing PWMRFB satisfies pending PWMRFB CPU interrupt requests.
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
NOTE
The PWM counter modulo register is buffered. The value written does not
take effect until the LDOKB bit or global load OK is set and the next PWM
load cycle begins. Reading PMFMODB returns the value in the buffer. It is
not necessarily the value the PWM generator B is currently using.
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel
operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime
of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration
is determined as follows:
Field Description
7 PWM Generator C Enable — If MTG is clear, this bit reads zero and cannot be written.
PWMENC If MTG is set, this bit when set enables the PWM generator C and the PWM4 and PWM5 outputs. When
PWMENC is clear, PWM generator C is disabled, and the PWM4 and PWM5 outputs are in their inactive states
unless the corresponding OUTCTL bits are set.
After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator C and PWM4–5 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator C and PWM4–5 outputs enabled
6 Global Load Okay C — When this bit is set, a PMF external global load OK defined on device level replaces the
GLDOKC function of LDOKC. This bit cannot be modified after the WP bit is set.
0 LDOKC controls reload of double buffered registers
1 PMF external global load OK controls reload of double buffered registers
2 Restart Generator C — When this bit is set, PWM generator C will be restarted at the next commutation event.
RSTRTC This bit cannot be modified after the WP bit is set.
0 No PWM generator C restart at the next commutation event
1 PWM generator C restart at the next commutation event
1 Load Okay C — If MTG is clear, this bit reads zero and can not be written.
LDOKC If MTG is set, this bit loads the PRSCC bits, the PMFMODC register and the PMFVAL4–5 registers into a set of
buffers. The buffered prescaler divisor C, PWM counter modulus C value, PWM4–5 pulse widths take effect at
the next PWM reload.
Set LDOKC by reading it when it is logic zero and then writing a logic one to it. LDOKC is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKC.
0 Do not load new modulus C, prescaler C, and PWM4–5 values
1 Load prescaler C, modulus C, and PWM4–5 values
Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time
as setting the PWMENC bit.
0 PWM Reload Interrupt Enable C — If MTG is clear, this bit reads zero and cannot be written.
PWMRIEC If MTG is set, this bit enables the PWMRFC flag to generate CPU interrupt requests.
0 PWMRFC CPU interrupt requests disabled
1 PWMRFC CPU interrupt requests enabled
Field Description
7–4 Load Frequency C — This field selects the PWM load frequency according to Table 15-35. See
LDFQC[3:0] Section 15.4.12.3, “Load Frequency” for more details.
Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the
LDOKC bit or global load OK. Reading the LDFQC field reads the buffered value and not necessarily the
value currently in effect.
3 Half Cycle Reload C — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
HALFC on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter
matches the modulus in addition to the start of the PWM period at count zero. See Section 15.4.12.3, “Load
Frequency” for more details.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
2–1 Prescaler C — This buffered field selects the PWM clock frequency illustrated in Table 15-36.
PRSCC[1:0] Note: Reading the PRSCC field reads the buffered value and not necessarily the value currently in effect. The
PRSCC field takes effect at the beginning of the next PWM cycle and only when the LDOKC bit or global
load OK is set.
0 PWM Reload Flag C — This flag is set at the beginning of every reload cycle regardless of the state of the
PWMRFC LDOKC bit or global load OK. Clear PWMRFC by reading PMFFQCC with PWMRFC set and then writing a logic
one to the PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to
PWMRFC has no effect.
0 No new reload cycle since last PWMRFC clearing
1 New reload cycle since last PWMRFC clearing
Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests.
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
NOTE
The PWM counter modulo register is buffered. The value written does not
take effect until the LDOKC bit or global load OK is set and the next PWM
load cycle begins. Reading PMFMODC returns the value in the buffer. It is
not necessarily the value the PWM generator A is currently using.
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel
operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime
of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration
is determined as follows:
Field Description
7-6 PWM Disable Mapping Channel n FAULT5 — This bit selects for PWMn whether the output is disabled or
DMPn5 forced to OUTFn at a FAULT5 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This register
cannot be modified after the WP bit is set. This setting takes effect at the next cycle start.
00 PWMn unaffected by FAULT5 event (interrupt flag setting only)
01 PWMn unaffected by FAULT5 event (interrupt flag setting only)
10 PWMn disabled on FAULT5 event
11 PWMn forced to OUTFn on FAULT5 event
n is 0, 1, 2, 3, 4 and 5.
5-4 PWM Disable Mapping Channel n FAULT4 — This bit selects for PWMn whether the output is disabled or
DMPn4 forced to OUTFn at a FAULT4 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This register
cannot be modified after the WP bit is set. This setting takes effect at the next cycle start.
00 PWMn unaffected by FAULT4 event (interrupt flag setting only)
01 PWMn unaffected by FAULT4 event (interrupt flag setting only)
10 PWMn disabled on FAULT4 event
11 PWMn forced to OUTFn on FAULT4 event
n is 0, 1, 2, 3, 4 and 5.
3-0 PWM Disable Mapping Channel n FAULT3-0 — This bit selects for PWMn if the output is disabled at a FAULT3-
DMPn 0 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This bit cannot be modified after the WP bit
is set.
FAULT3-0 have priority over FAULT5-4.This setting takes effect at the next cycle start.
0 PWMn unaffected by FAULT3-0 event
1 PWMn disabled on FAULT3-0 event
n is 0, 1, 2, 3, 4 and 5.
Field Description
5–0 OUTF Bits — When the corresponding DMPn4 or DMPn5 bits are set to switch to output control on a related
OUTF[5:0] FAULT4 or FAULT5 event, these bits control the PWM outputs, illustrated in Table 15-39.This register cannot be
modified after the WP bit is set.
Fault4-5
Detect Deadtime Dist. Correction
0 and Asymmetric PWM
00
OUTF0 1 IPOLA 01
1X
OUT0 OUTCTL0 (A)
IS0 1
Correction Count
Softw. Output Control 1 direction
Generated PWM
ISENS ICCA
Independent Mode
VAL0
Complementary Mode
(A) 1
Gen. 0 PWM0
000 DTMA
COMP
CINV0 x1x SRCA MSK0 TOPNEGA
MODA in INDEPA Fault0-3
10x deadtime Detect
CINV1 MSK1 BOTNEGA
001
PINVA PWM1
Gen. 1
1
(OUTCTL1 & PWMENA)
VAL1 PECA | (~OUTCTL1 & OUT1)
Generated PWM
Softw. Output Control 1
OUT1 OUTCTL1
1 = Functional Block
OUTF1
= Configuration Register Bit
Fault4-5
Detect
Figure 15-41. Detail of PWM0 and PWM1 Signal Paths
NOTE
It is possible to have both channels of a complementary pair to be high. For
example, if the TOPNEGA (negative polarity for PWM0), BOTNEGA
(negative polarity for PWM1), MSK0 and MSK1 bits are set, both the PWM
complementary outputs of generator A will be high. See Section 15.3.2.2,
“PMF Configure 1 Register (PMFCFG1)” for the description of TOPNEG
and BOTNEG bits, and Section 15.3.2.3, “PMF Configure 2 Register
(PMFCFG2)” for the description of the MSK0 and MSK1 bits.
15.4.2 Prescaler
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the core
clock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Each
prescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is set
and a new PWM reload cycle begins.
Alignment Reference
Up/Down Counter
Modulus = 4
CINVn = 1
Alignment Reference
Up Counter
Modulus = 4
CINVn = 1
15.4.3.2 Period
A PWM period is determined by the value written to the PWM counter modulo registers PMFMODx.
The PWM counter is an up/down counter in center-aligned mode. In this mode the PWM highest output
resolution is two core clock cycles.
COUNTER 1 2 3 4 3 2 1 0
UP/DOWN COUNTERER
MODULUS = 4
NOTE
Because of the equals-comparator architecture of this PMF, the modulus
equals zero case is considered illegal in center-aligned mode. Therefore, the
modulus register does not return to zero, and a modulus value of zero will
result in waveforms inconsistent with the other modulus waveforms. If a
modulus of zero is loaded, the counter will continually count down from
0x7FFF. This operation will not be tested or guaranteed. Consider it illegal.
However, the deadtime constraints and fault conditions will still be
guaranteed.
In edge-aligned mode, the PWM counter is an up counter. The PWM output resolution is one core clock
cycle.
COUNTER 1 2 3 4 1
UP COUNTERER
MODULUS = 4
NOTE
In edge-aligned mode the modulus equals zero and one cases are considered
illegal.
NOTE
A PWM value less than or equal to zero deactivates the PWM output for the
entire PWM period. A PWM value greater than or equal to the modulus
activates the PWM output for the entire PWM period when CINVn=0, and
vice versa if CINVn=1.
PWM pulse width = (PWM value) (PWM clock period) 2 Eqn. 15-6
COUNTER 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0
P/DOWN COUNTERER
MODULUS = 4
PWM VALUE = 0
0/4 = 0%
PWM VALUE = 1
1/4 = 25%
PWM VALUE = 2
2/4 = 50%
PWM VALUE = 3
3/4 = 75%
PWM VALUE = 4
4/4 = 100%
PWM pulse width = (PWM value) (PWM clock period) Eqn. 15-7
COUNTER 1 2 3 4 1
UP COUNTERER
MODULUS = 4
PWM VALUE = 0
0/4 = 0%
PWM VALUE = 1
1/4 = 25%
PWM VALUE = 2
2/4 = 50%
PWM VALUE = 3
3/4 = 75%
PWM VALUE = 4
4/4 = 100%
Figure 15-47. Edge-Aligned PWM Pulse Width
BOTTOM
PMFVAL2 PMFVAL3
REGISTER REGISTER
PAIR B
BOTTOM
PMFVAL4 PMFVAL5
REGISTER REGISTER
PAIR C
BOTTOM
The complementary channel operation is for driving top and bottom transistors in a motor drive circuit,
such as the one in Figure 15-49.
TOP (PWM0)
TOP/BOTTOM TO FAULT
OUT1 GENERATOR BOTTOM (PWM1) PROTECTION
OUT0
DEADTIME
MUX GENERATOR
PWM0 &
PWM1
OUTCTL0
TOP (PWM2)
TOP/BOTTOM TO FAULT
OUT3 GENERATOR BOTTOM (PWM3) PROTECTION
OUT2
DEADTIME
MUX GENERATOR
PWM CURRENT
GENERATOR STATUS
PWM2 &
PWM3
OUTCTL2
TOP (PWM4)
TOP/BOTTOM TO FAULT
OUT5 GENERATOR BOTTOM (PWM5) PROTECTION
OUT4
DEADTIME
MUX GENERATOR
PWM4 &
PWM5
OUTCTL4
MODULUS = 4
PWM VALUE = 2
PWM0, NO DEADTIME
PWM1, NO DEADTIME
PWM0, DEADTIME = 1
PWM1, DEADTIME = 1
MODULUS = 3
PWM VALUE = 1
PWM0, NO DEADTIME
PWM1, NO DEADTIME
PWM0, DEADTIME = 2
PWM1, DEADTIME = 2
MODULUS = 3
PWM
PWM VALUE 2 PWM Value = 3 PWM Value = 2 Value = 1
PWM0, NO DEADTIME
PWM1, NO DEADTIME
PWM0, DEADTIME = 3
PWM1, DEADTIME = 3
NOTE
The waveform at the output is delayed by two core clock cycles for
deadtime insertion.
DESIRED V+
LOAD VOLTAGE
DEADTIME
PWM TO TOP
TRANSISTOR
POSITIVE
CURRENT
NEGATIVE
CURRENT
PWM TO BOTTOM
TRANSISTOR
POSITIVE CURRENT
LOAD VOLTAGE
NEGATIVE CURRENT
LOAD VOLTAGE
During deadtime, load inductance distorts output voltage by keeping current flowing through the diodes.
This deadtime current flow creates a load voltage that varies with current direction. With a positive current
flow, the load voltage during deadtime is equal to the bottom supply, putting the top transistor in control.
With a negative current flow, the load voltage during deadtime is equal to the top supply putting the bottom
transistor in control.
Remembering that the original PWM pulse widths were shortened by deadtime insertion, the averaged
sinusoidal output will be less than the desired value. However, when deadtime is inserted, it creates a
distortion in motor current waveform. This distortion is aggravated by dissimilar turn-on and turn-off
delays of each of the transistors. By giving the PWM module information on which transistor is controlling
at a given time, this distortion can be corrected.
For a typical circuit in complementary channel operation, only one of the transistors will be effective in
controlling the output voltage at any given time. This depends on the direction of the motor current for that
pair. See Figure 15-54. To correct distortion one of two different factors must be added to the desired PWM
value, depending on whether the top or bottom transistor is controlling the output voltage. Therefore, the
software is responsible for calculating both compensated PWM values prior to placing them in an odd-
numbered/even numbered PWM register pair. Either the odd or the even PMFVAL register controls the
pulse width at any given time. For a given PWM pair, whether the odd or even PMFVAL register is active
depends on either:
• The state of the current status input, IS, for that driver
• The state of the odd/even correction bit, IPOLx, for that driver if ICC bits in the PMFICCTL
register are set to zeros
• The direction of PWM counter if ICC bits in the PMFICCTL register are set to ones
To correct deadtime distortion, software can decrease or increase the value in the appropriate PMFVAL
register.
• In edge-aligned operation, decreasing or increasing the PWM value by a correction value equal to
the deadtime typically compensates for deadtime distortion.
• In center-aligned operation, decreasing or increasing the PWM value by a correction value equal
to one-half the deadtime typically compensates for deadtime distortion.
In the complementary channel operation, ISENS selects one of three correction methods:
• Manual correction
• Automatic current status correction during deadtime
• Automatic current status correction when the PWM counter value equals the value in the PWM
counter modulus registers
Table 15-41. Correction Method Selection
2. The polarity of the IS input is latched when both the top and bottom PWMs are off. At the 0%
and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed.
NOTE
External current status sensing circuitry is required at the corresponding
inputs which produces a logic zero level for positive current and logic one
for negative current. PWM 0, 2, and 4 are considered the top PWMs while
the bottom PWMs are PWM 1, 3, and 5.
NOTE
IPOLx bits are buffered so only one PWM register is used per PWM cycle.
If an IPOLx bit changes during a PWM period, the new value does not take
effect until the next PWM period.
IPOLx bits take effect at the end of each PWM cycle regardless of the state
of the related LDOK bit or global load OK.
PWM CONTROLLED
BY ODD PMFVAL REGISTER A TOP PWM
DEADTIME
GENERATOR
PWM CONTROLLED BOTTOM PWM
BY EVEN PMFVAL REGISTER B
A/B
IPOLx BIT D Q
To detect the current status, the voltage on each IS input is sampled twice in a PWM period, at the end of
each deadtime. The value is stored in the DTn bits in the PMF Deadtime Sample register (PMFDTMS).
The DTn bits are a timing marker especially indicating when to toggle between PWM value registers.
Software can then set the IPOLx bit to toggle PMFVAL registers according to DTn values.
PWM0
POSITIVE D Q DT0
CURRENT
PWM0 CLK
NEGATIVE
CURRENT IS0 PIN
Both D flip-flops latch low, DT0 = 0, DT1 = 0, during deadtime periods if current is large and flowing out
of the complementary circuit. See Figure 15-56. Both D flip-flops latch the high, DT0 = 1, DT1 = 1, during
deadtime periods if current is also large and flowing into the complementary circuit.
However, under low-current, the output voltage of the complementary circuit during deadtime is
somewhere between the high and low levels. The current cannot free-wheel through the opposition anti-
body diode, regardless of polarity, giving additional distortion when the current crosses zero.
Sampled results will be DT0 = 0 and DT1 = 1. Thus, the best time to change one PWM value register to
another is just before the current zero crossing.
V+
T B T B
DEADTIME
PWM TO TOP
TRANSISTOR
POSITIVE
CURRENT
NEGATIVE
CURRENT
PWM TO BOTTOM
TRANSISTOR
Previously shown, the current direction can be determined by the output voltage during deadtime. Thus, a
simple external voltage sensor can be used when current status is completed during deadtime, ISENS = 10.
Deadtime does not exist at the 100 percent and zero percent duty cycle boundaries. Therefore, the second
automatic mode must be used for correction, ISENS = 11, where current status is sampled at the half cycle
in center-aligned operation and at the end of cycle in edge-aligned operation. Using this mode requires
external circuitry to sense current direction.
PWM CONTROLLED BY
ODD PMFVAL REGISTER A TOP PWM
DEADTIME
GENERATOR
PWM CONTROLLED BY BOTTOM PWM
EVEN PMFVAL REGISTER B
A/B
INITIAL VALUE = 0
ISx PIN D Q D Q
PWM CONTROLLED BY
ODD PMFVAL REGISTER A TOP PWM
DEADTIME
GENERATOR
PWM CONTROLLED BY BOTTOM PWM
EVEN PMFVAL REGISTER B
A/B
INITIAL VALUE = 0
ISx PIN D Q D Q
NOTE
Values latched on the ISx inputs are buffered so only one PWM register is
used per PWM cycle. If a current status changes during a PWM period, the
new value does not take effect until the next PWM period.
When initially enabled by setting the PWMEN bit, no current status has previously been sampled. PWM
value registers one, three, and five initially control the three PWM pairs when configured for current status
correction.
TOP PWM
BOTTOM PWM
LOAD VOLTAGE
TOP PWM
BOTTOM PWM
LOAD VOLTAGE
NOTE
If an ICCx bit in the PMFICCTL register changes during a PWM period, the
new value does not take effect until the next PWM period. ICCx bits take
effect at the end of each PWM cycle regardless of the state of the related
LDOKx bit or global load OK.
4
3
1
Up/Down Counter
Modulus = 4 0
Even PWM Odd PWM Even PWM Odd PWM
Even PWM Value Value Value Value
Value = 1
Odd PWM
Value = 3
Even PWM
Value = 3
Odd PWM
Value = 1
CINV0
PECA=1 PINVA
PWM
GENERATOR 0 to complement
logic and
CINV1 dead time
insertion
COMPSRC
PWM
GENERATOR 1
9
8
EDGEA=1 7
6
PECA=1 5
4
3
2
1
Up Counter
Modulus = 9
PWM0 (PINVA=0)
0%
PWM0 (PINVA=1)
100%
Figure 15-64. Variable Edge Placement Waveform - Phase Shift PWM Output (Edge-Aligned)
9
8
EDGEA=0 7
6
PECA=1 5
4
3
2
1
Up/Down Counter 0
Modulus = 9
PMFVAL0 = 3; CINV0 =1
PMFVAL1 = 6; CINV1 =0
PWM0 (PINV=0)
PWM0 (PINV=1)
9
8
EDGEA=0 7
6
PECA=1 5
4
3
2
1
Up/Down Counter 0
Modulus = 9
PMFVAL0 = 6; CINV0 =1
PMFVAL1 = 3; CINV1 =0
PWM0 (PINV=0) 0%
PWM0 (PINV=1) 100%
PWM = 0
PWM = 0
PWM = 1
CENTER-ALIGNED PWM = 1 EDGE-ALIGNED PWM = 2
POSITIVE POLARITY POSITIVE POLARITY
PWM = 2
PWM = 3
PWM = 3
PWM = 4
PWM = 4
UP COUNTERER
UP/DOWN COUNTERER MODULUS = 4
MODULUS = 4
PWM = 0
PWM = 0
PWM = 1
PWM = 1 EDGE-ALIGNED PWM = 2
CENTER-ALIGNED PWM = 2 NEGATIVE POLARITY
NEGATIVE POLARITY PWM = 3
PWM = 3
PWM = 4
PWM = 4
In independent PWM operation, setting or clearing the OUTn bit activates or deactivates the PWMn
output.
In complementary channel operation, the even-numbered OUTn bits replace the PWM generator outputs
as inputs to the deadtime generators. Complementary channel pairs still cannot drive active level
simultaneously, and the deadtime generators continue to insert deadtime in both channels of that pair,
whenever an even OUTn bit toggles. Even OUTn bits control the top PWM signals while the odd OUT
bits control the bottom PWM signals with respect to the even OUTn bits. Setting the odd OUTn bit makes
its corresponding PWM the complement of its even pair, while clearing the odd OUTn bit deactivates the
odd PWM.
Setting the OUTCTLn bits does not disable the PWM generators and current status sensing circuitry. They
continue to run, but no longer control the outputs. When the OUTCTLn bits are cleared, the outputs of the
PWM generator become the inputs to the deadtime generators at the beginning of the next PWM cycle.
Software can drive the PWM outputs even when PWM enable bit (PWMENx) is set to zero.
NOTE
Avoid an unexpected deadtime insertion by clearing the OUTn bits before
setting and after clearing the OUTCTLn bits.
MODULUS = 4
PWM VALUE = 2
DEADTIME = 2
PWM0
PWM1
OUTCTL0
OUT0
OUT1
PWM0
PWM1
MODULUS = 4
PWM VALUE = 2
DEADTIME = 2
PWM0
PWM1
OUTCTL0
OUT0
OUT1
PWM0
PWM1
MODULUS = 4
PWM VALUE = 2
DEADTIME = 2
PWM0
PWM1
OUTCTL0
OUT0
OUT1
PWM0
PWM1
bus clock
LDOK write
LDOK bit
PWM reload
bus clock
LDOK write
LDOK bit
PWM reload
bus clock
LDOK write
LDOK bit
PWM reload
bus clock
LDOK write
LDOK bit
PWM reload
UP/DOWN
COUNTERER
RELOAD
CHANGE
RELOAD EVERY EVERY EVERY
FREQUENCY TWO OPPORTUNITIES FOUR OPPORTUNITIES OPPORTUNITY
Figure 15-73. Full Cycle Reload Frequency Change
UP/DOWN
COUNTERER
RELOAD
CHANGE
RELOAD EVERY TWO EVERY EVERY EVERY TWO
FREQUENCY OPPORTUNITIES FOUR OPPORTUNITIES OPPORTUNITY OPPORTUNITIES
(HALF bit set (HALF bit set while counting up) (HALF bit set
while counting down) (other case not shown) while counting up)
Figure 15-74. Half Cycle Reload Frequency Change
UP/DOWN
COUNTERER
LDOK = 1 0 1 0
MODULUS = 3 3 3 3
PWM VALUE = 1 2 2 1
PWMRF = 1 1 1 1
PWM
Figure 15-76. Full-Cycle Center-Aligned PWM Value Loading
UP/DOWN
COUNTERER
LDOK = 1 1 1 1 0
MODULUS = 2 3 2 1 2
PWM VALUE = 1 1 1 1 1
PWMRF = 1 1 1 1 1
PWM
Figure 15-77. Full-Cycle Center-Aligned Modulus Loading
UP/DOWN
COUNTERER
1 1
LDOK = 1 1 0 0 1 3 0 3
MODULUS = 3 3 3 3 3 3 3 1
PWM VALUE = 1 2 2 2 1 1 3 1
PWMRF = 1 1 1 1 1 1
PWM
Figure 15-78. Half-Cycle Center-Aligned PWM Value Loading
UP/DOWN
COUNTERER
1
LDOK = 1 0 1 0 4
0 1 0
MODULUS = 2 2 3 4 1 2 1
4 1 1
PWM VALUE = 1 1 1 1 1 1
PWMRF = 1 1 1 1 1 1
1
PWM
Figure 15-79. Half-Cycle Center-Aligned Modulus Loading
UP ONLY
COUNTERER
LDOK = 1 0 1 0 0
MODULUS = 3 3 3 3 3
PWM VALUE = 1 2 2 1 1
PWMRF = 1 1 1 1 1
PWM
UP ONLY
COUNTERER
LDOK = 1 1 1 0
MODULUS = 3 4 2 1
PWM VALUE = 2 2 2 2
PWMRF = 1 1 1 1
PWM
WRITE 1 TO PMFROIF
RESET
VDD
PMFROIF
CLR
D Q CPU INTERRUPT
PMFROIE REQUEST
PWM RELOAD CLK
1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active-
high. For availability and configurability of fault inputs on pins refer to the device overview section.
FAULT INPUT
FAULT0 OR
FAULT2
FIFm CLEARED
FAULT0 OR
FAULT2
FIFm CLEARED
Figure 15-85. Manual Fault Recovery (Faults 0 and 2) — QSMP = 01, 10, or 11
FAULT1 OR
FAULT3
FIFm CLEARED
Figure 15-86. Manual Fault Recovery (Faults 1 and 3-5)
NOTE
PWM half-cycle boundaries occur at both the PWM cycle start and when
the counter equals the modulus, so in edge-aligned operation full-cycles and
half-cycles are equal.
NOTE
Fault protection also applies during software output control when the
OUTCTLn bits are set. Fault recovery still occurs at half PWM cycle
boundaries while the PWM generator is engaged, PWMEN equals one. But
the OUTn bits can control the PWM outputs while the PWM generator is
off, PWMEN equals zero. Thus, fault recovery occurs at IPbus cycles while
the PWM generator is off and at the start of PWM cycles when the generator
is engaged.
15.5 Resets
All PMF registers are reset to their default values upon any system reset.
15.6 Clocks
The gated system core clock is the clock source for all PWM generators. The system clock is used as a
clock source for any other logic in this module. The system bus clock is used as clock for specific control
registers and flags (LDOKx, PWMRFx, PMFOUTB).
15.7 Interrupts
This section describes the interrupts generated by the PMF and their individual sources. Vector addresses
and interrupt priorities are defined at SoC-level.
15.8.1 Initialization
Initialize all registers; read, then set the related LDOK bit or global load OK before setting the PWMEN
bit. With LDOK set, setting PWMEN for the first time after reset immediately loads the PWM generator
thereby setting the PWMRF flag. PWMRF generates a CPU interrupt request if the PWMRIE bit is set. In
complementary channel operation with current-status correction selected, PWM value registers one, three,
and five control the outputs for the first PWM cycle.
NOTE
Even if LDOK is not set, setting PWMEN also sets the PWMRF flag. To
prevent a CPU interrupt request, clear the PWMRIE bit before setting
PWMEN.
Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one,
a PWM value of 0x0000, and an unknown modulus.
The PWM generator uses the last values loaded if PWMEN is cleared and then set while LDOK equals
zero.
Initializing the deadtime register, after setting PWMEN or OUTCTLn, can cause an improper deadtime
insertion. However, the deadtime can never be shorter than the specified value.
IPBus
CLOCK
PWMEN
BIT
IPBus
CLOCK
PWMEN
BIT
HI-Z HI-Z
PWM
OUTPUTS ACTIVE
Table 15-46. Effects of OUTCTL and OUT Bits on PWM Output Pair in Complementary Mode
00 xx PWMgen(even) PWMgen(even)
11 10 OUTB(even)=1 OUTB(even)=0
01 x0 0 OUTB(even)=0
A PWM0 PWMgen 0 0 0
PWM1 PWMgen 0 1 0
B PWM2 0 0 PWMgen 0 0
PWM3 1 0 PWMgen 0 1
C PWM4 0 0 0 PWMgen
PWM5 0 1 0 PWMgen
16.1 Introduction
This block guide provides an overview of the serial communication interface (SCI) module.
The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
16.1.1 Glossary
IR: InfraRed
IrDA: Infrared Design Associate
IRQ: Interrupt Request
LIN: Local Interconnect Network
LSB: Least Significant Bit
MSB: Most Significant Bit
NRZ: Non-Return-to-Zero
RZI: Return-to-Zero-Inverted
16.1.2 Features
The SCI includes these distinctive features:
• Full-duplex or single-wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
• 16-bit baud rate selection
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable polarity for transmitter and receiver
• Programmable transmitter output parity
• Two receiver wakeup methods:
— Idle line wakeup
— Address mark wakeup
• Interrupt-driven operation with eight flags:
— Transmitter empty
— Transmission complete
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
— Receive wakeup on active edge
— Transmit collision detect supporting LIN
— Break Detect supporting LIN
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0000 R
SCIBDH1 SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8
W
0x0001 R
SCIBDL1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
0x0002 R
SCICR11 LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
0x0000 R 0 0 0 0
SCIASR12 RXEDGIF BERRV BERRIF BKDIF
W
0x0001 R 0 0 0 0 0
SCIACR12 RXEDGIE BERRIE BKDIE
W
0x0002 R 0 0
SCIACR22 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE
W
0x0003 R
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
W
0x0005 R 0 0 RAF
SCISR2 AMAP TXPOL RXPOL BRK13 TXDIR
W
0x0006 R R8 0 0 0
SCIDRH T8 Reserved Reserved Reserved
W
0x0007 R R7 R6 R5 R4 R3 R2 R1 R0
SCIDRL W T7 T6 T5 T4 T3 T2 T1 T0
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Field Description
SBR[15:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is
calculated two different ways depending on the state of the IREN bit.
The formulas for calculating the baud rate are:
When IREN = 0 then,
SCI baud rate = SCI bus clock / (SBR[15:0])
When IREN = 1 then,
SCI baud rate = SCI bus clock / (2 x SBR[15:1])
Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the
first time. The baud rate generator is disabled when (SBR[15:4] = 0 and IREN = 0) or (SBR[15:5] = 0 and
IREN = 1).
Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start,
write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second
write later then RT clock.
Field Description
7 Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
LOOPS and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
6 SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
SCISWAI 0 SCI enabled in wait mode
1 SCI disabled in wait mode
5 Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
RSRC input. See Table 16-4.
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
4 Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
M 0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
3 Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
WAKE most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
2 Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The
ILT counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
0 Idle character bit count begins after start bit
1 Idle character bit count begins after stop bit
Field Description
1 Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the
PE most significant bit position.
0 Parity function disabled
1 Parity function enabled
0 Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even
PT parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
0 Even parity
1 Odd parity
Field Description
7 Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
RXEDGIF rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
2 Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
BERRV a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
1 Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
BERRIF sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
0 Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
BKDIF received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
Field Description
7 Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIE RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1 Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
BERRIE requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
0 Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
BKDIE requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
Field Description
7 Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
IREN 0 IR disabled
1 IR enabled
6:5 Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow
TNP[1:0] pulse. See Table 16-8.
2:1 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 16-9.
BERRM[1:0]
0 Break Detect Feature Enable — BKDFE enables the break detect circuitry.
BKDFE 0 Break detect circuit disabled
1 Break detect circuit enabled
Read: Anytime
Write: Anytime
Table 16-10. SCICR2 Field Descriptions
Field Description
7 Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
TIE interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
6 Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
TCIE interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
5 Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
RIE OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
4 Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
ILIE 0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
3 Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
TE the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
2 Receiver Enable Bit — RE enables the SCI receiver.
RE 0 Receiver disabled
1 Receiver enabled
1 Receiver Wakeup Bit — Standby state
RWU 0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes
the receiver by automatically clearing RWU.
0 Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s
SBK if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13
or 14 bits).
0 No break characters
1 Transmit break characters
Read: Anytime
Write: Has no meaning or effect
Table 16-11. SCISR1 Field Descriptions
Field Description
7 Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the
TDRE SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value
to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data
register low (SCIDRL).
0 No byte transferred to transmit shift register
1 Byte transferred to transmit shift register; transmit data register empty
6 Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break
TC character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being
transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1
(SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data,
preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of
the TC flag (transmission not complete).
0 Transmission in progress
1 No transmission in progress
5 Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI
RDRF data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data
register low (SCIDRL).
0 Data not available in SCI data register
1 Received data available in SCI data register
4 Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear
IDLE on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle
condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then
reading SCI data register low (SCIDRL).
0 Receiver input is either active now or has never become active since the IDLE flag was last cleared
1 Receiver input has become idle
Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.
Field Description
3 Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register
OR receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the
second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low
(SCIDRL).
0 No overrun
1 Overrun
Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of
events occurs:
1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear);
2. Receive second frame without reading the first frame in the data register (the second frame is not
received and OR flag is set);
3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register);
4. Read status register SCISR1 (returns RDRF clear and OR set).
Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy
SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received.
2 Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as
NF the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),
and then reading SCI data register low (SCIDRL).
0 No noise
1 Noise
1 Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle
FE as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
0 Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not
PF match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
Read: Anytime
Write: Anytime
Table 16-12. SCISR2 Field Descriptions
Field Description
7 Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset
AMAP condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and
status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible
4 Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by
TXPOL a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
3 Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a
RXPOL mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
2 Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit
BRK13 respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
1 Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to
TXDIR be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire
mode of operation.
0 TXD pin to be used as an input in single-wire mode
1 TXD pin to be used as an output in single-wire mode
0 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start
RAF bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
Field Description
SCIDRH Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
7
R8
SCIDRH Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
6
T8
SCIDRL R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats
7:0 T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
R[7:0]
T[7:0]
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH), then SCIDRL.
IREN R8
SCI Data
Register NF
FE
RXD Infrared Ir_RXD SCRXD Receive PF
Receive
Shift Register
Decoder RAF ILIE IDLE
RE IDLE
RWU RDRF
Receive
R16XCLK
RDRF/OR
RSRC
RIE
Bus M TIE
Clock Receive
Baud Rate WAKE
Generator Data Format
Control ILT TDRE
TDRE
PE
TC SCI
SBR15:SBR0 PT Interrupt
TCIE TC Request
TE
Transmit Transmit RXEDGIE
Baud Rate 16 Control LOOPS
Generator
SBK
Active Edge RXEDGIF
RSRC Detect
Transmit BKDIF
T8 Shift Register Break Detect
RXD
R16XCLK BERRIE
Infrared BERRM[1:0]
Transmit Ir_TXD TXD
Encoder
R32XCLK
TNP[1:0] IREN
Infrared
SCI Data
Infrared
SCI Data
Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit.
Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight
data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame
with nine data bits has a total of 11 bits.
Table 16-14. Example of 8-Bit Data Formats
When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register
high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it.
A frame with nine data bits has a total of 11 bits.
Table 16-15. Example of 9-Bit Data Formats
16.4.5 Transmitter
Internal Bus
SBR15:SBR4 SBR3:SBR0
Start
Stop
11-Bit Transmit Register TXPOL
SCTXD
M H 8 7 6 5 4 3 2 1 0 L
MSB
LOOP To Receiver
T8 CONTROL
Shift Enable
LOOPS
PT Generation
RSRC
TIE
TDRE IRQ
TDRE
Transmitter Control
TC
TC IRQ
TCIE
TE SBK BERRM[1:0]
SCTXD
BERRIF Transmit
BER IRQ Collision Detect SCRXD
TCIE (From Receiver)
The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from
the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag
by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still
shifting out the first byte.
To initiate an SCI transmission:
1. Configure the SCI:
a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud
rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.
Writing to the SCIBDH has no effect without also writing to SCIBDL.
b) Write to SCICR1 to configure word length, parity, and other configuration bits
(LOOPS,RSRC,M,WAKE,ILT,PE,PT).
c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2
register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now
be shifted out of the transmitter shift register.
2. Transmit Procedure for each byte:
a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind
that the TDRE bit resets to one.
b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is
written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not
result until the TDRE flag has been cleared.
3. Repeat step 2 for each subsequent transmission.
NOTE
The TDRE flag is set when the shift register is loaded with the next data to
be transmitted from SCIDRH/L, which happens, generally speaking, a little
over half-way through the stop bit of the previous frame. Specifically, this
transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the
previous frame.
Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data
character is the parity bit.
The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI
data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data
register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI
control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.
When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic
1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal
goes low and the transmit signal goes idle.
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register
continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE
to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use this sequence between messages:
1. Write the last byte of the first message to SCIDRH/L.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH/L.
Figure 16-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,
while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there
will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing
error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later
during the transmission. At the expected stop bit position the byte received so far will be transferred to the
receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate
a parity error will be set. Once the break is detected the BRKDIF flag will be set.
BRKDIF = 1
RXD_1
Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 . . .
FE = 1 BRKDIF = 1
RXD_2
Compare
Bit Error RXD Pin
LIN Bus
Bus Clock
Sample
Point
Transmit Shift
Register TXD Pin
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
• The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
• The transmission is aborted and the byte in transmit buffer is discarded.
• the transmit data register empty and the transmission complete flag will be set
• The bit error interrupt flag, BERRIF, will be set.
• No further transmissions will take place until the BERRIF is cleared.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Output Transmit
Sampling Begin
Sampling Begin
Sampling End
Sampling End
Shift Register
Input Receive
Shift Register
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
NOTE
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
16.4.6 Receiver
Internal Bus
Start
Stop
11-Bit Receive Shift Register
RXPOL Data H 8 7 6 5 4 3 2 1 0 L
SCRXD Recovery
All 1s
From TXD Pin Loop
MSB
or Transmitter Control RE
RAF
LOOPS FE
M RWU
RSRC NF
WAKE Wakeup
Logic PE
ILT
PE Parity R8
PT Checking
Idle IRQ
IDLE
ILIE
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
RT Clock
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT11
RT CLock Count
Reset RT Clock
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Figure 16-17 summarizes the results of the start bit verification samples.
Table 16-17. Start Bit Verification
RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 16-18 summarizes the results of the data bit samples.
Table 16-18. Data Bit Recovery
RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit (logic 0).
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-19
summarizes the results of the stop bit samples.
Table 16-19. Stop Bit Recovery
RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag
000 1 0
001 1 1
010 1 1
011 0 1
100 1 1
101 0 1
110 0 1
111 0 0
In Figure 16-22 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
Start Bit LSB
RXD
Samples 1 1 1 0 1 1 1 0 0 0 0 0 0 0
RT Clock
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT11
RT Clock Count
Reset RT Clock
In Figure 16-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Perceived Start Bit
Actual Start Bit LSB
RXD
Samples 1 1 1 1 1 0 1 0 0 0 0 0
RT Clock
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT11
RT Clock Count
Reset RT Clock
In Figure 16-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of
perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is
successful.
RT Clock
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT11
RT Clock Count
Reset RT Clock
Figure 16-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper
synchronization with the start bit time, it does set the noise flag.
Perceived and Actual Start Bit LSB
RXD
Samples 1 1 1 1 1 1 1 1 1 0 1 0
RT Clock
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT3
RT Clock Count
Reset RT Clock
Figure 16-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.
Start Bit LSB
RXD No Start Bit Found
Samples 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0
RT Clock
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT Clock Count
Reset RT Clock
In Figure 16-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the
noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
Start Bit LSB
RXD
Samples 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1
RT Clock
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT11
RT Clock Count
Reset RT Clock
MSB Stop
Receiver
RT Clock
RT10
RT12
RT13
RT14
RT15
RT16
RT11
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
Data
Samples
Figure 16-28. Slow Data
Receiver
RT Clock
RT10
RT12
RT13
RT14
RT15
RT16
RT11
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
Data
Samples
Figure 16-29. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 9 RTr cycles = 153 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 16-29, the receiver counts 153 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is:
((160 – 153) / 160) x 100 = 4.375%
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 9 RTr cycles = 169 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 16-29, the receiver counts 169 RTr cycles at the point when
the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is:
((176 – 169) /176) x 100 = 3.98%
NOTE
Due to asynchronous sample and internal logic, there is maximal 2 bus
cycles between startbit edge and 1st RT clock, and cause to additional
tolerance loss at worst case. The loss should be 2/SBR/10*100%, it is
small.For example, for highspeed baud=230400 with 25MHz bus, SBR
should be 109, and the tolerance loss is 2/109/10*100=0.18%, and fast data
tolerance is 4.375%-0.18%=4.195%.
The transmitting device can address messages to selected receivers by including addressing information
in the initial frame or frames of each message.
The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby
state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark
wakeup.
Transmitter
TXD
Receiver RXD
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control
register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting
the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as
an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.
NOTE
In single-wire operation data from the TXD pin is inverted if RXPOL is set.
Transmitter TXD
Receiver RXD
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).
NOTE
In loop operation data from the transmitter is not recognized by the receiver
if RXPOL and TXPOL are not the same.
16.5.3.1.2 TC Description
The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed
when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be
transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing
there is no more data queued for transmission) when the break character has been shifted out. A TC
interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and
no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle
(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data
register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to
be sent.
16.5.3.1.4 OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register
receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data
already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status
register one (SCISR1) and then reading SCI data register low (SCIDRL).
Revision Sections
Revision Date Description of Changes
Number Affected
V05.00 24 Mar 2005 17.3.2/17-677 - Added 16-bit transfer width feature.
17.1 Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
17.1.2 Features
The SPI includes these distinctive features:
• Master mode and slave mode
• Selectable 8 or 16-bit transfer width
• Bidirectional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode
• Run mode
This is the basic mode of operation.
• Wait mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of data continues, so that the slave stays synchronized to the master.
• Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of data continues, so that the slave stays
synchronized to the master.
For a detailed description of operating modes, please refer to Section 17.4.7, “Low Power Mode Options”.
SPI
2
SPI Control Register 1
BIDIROE
2
SPI Control Register 2
SPC0
LSBFE=1
SPI Data Register MSB
LSBFE=0 LSB
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0000 R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
SPICR1 W
0x0001 R 0 0 0
XFRW MODFEN BIDIROE SPISWAI SPC0
SPICR2 W
0x0002 R 0 0
SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
SPIBR W
0x0005 R R7 R6 R5 R4 R3 R2 R1 R0
SPIDRL W T7 T6 T5 T4 T3 T2 T1 T0
0x0006 R
Reserved W
= Unimplemented or Reserved
Figure 17-2. SPI Register Summary
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0007 R
Reserved W
= Unimplemented or Reserved
Figure 17-2. SPI Register Summary
Read: Anytime
Write: Anytime
Table 17-2. SPICR1 Field Descriptions
Field Description
7 SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
SPIE 0 SPI interrupts disabled.
1 SPI interrupts enabled.
6 SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
SPE functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
5 SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
SPTIE 0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
4 SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
MSTR Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
Field Description
3 SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
CPOL modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
2 SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
CPHA abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
1 Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
SSOE asserting the SSOE as shown in Table 17-3. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
0 LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
LSBFE writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Field Description
6 Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
XFRW becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to Section 17.3.2.4, “SPI Status Register (SPISR) for
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)(1)
1 16-bit Transfer Width (n = 16)1
4 Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to Table 17-3. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
3 Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
BIDIROE of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
1 SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
SPISWAI 0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
0 Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 17-5. In master
SPC0 mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
1. n is used later in this document as a placeholder for the selected transfer width.
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 17-6. SPIBR Field Descriptions
Field Description
6–4 SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 17-7. In master
SPPR[2:0] mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
2–0 SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 17-7. In master mode,
SPR[2:0] a change of these bits will abort a transmission in progress and force the SPI system into idle state.
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Table 17-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3)
Baud Rate
SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate
Divisor
0 0 0 0 0 0 2 12.5 Mbit/s
0 0 0 0 0 1 4 6.25 Mbit/s
0 0 0 0 1 0 8 3.125 Mbit/s
0 0 0 0 1 1 16 1.5625 Mbit/s
0 0 0 1 0 0 32 781.25 kbit/s
0 0 0 1 0 1 64 390.63 kbit/s
0 0 0 1 1 0 128 195.31 kbit/s
0 0 0 1 1 1 256 97.66 kbit/s
0 0 1 0 0 0 4 6.25 Mbit/s
0 0 1 0 0 1 8 3.125 Mbit/s
0 0 1 0 1 0 16 1.5625 Mbit/s
Table 17-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3)
Baud Rate
SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate
Divisor
0 0 1 0 1 1 32 781.25 kbit/s
0 0 1 1 0 0 64 390.63 kbit/s
0 0 1 1 0 1 128 195.31 kbit/s
0 0 1 1 1 0 256 97.66 kbit/s
0 0 1 1 1 1 512 48.83 kbit/s
0 1 0 0 0 0 6 4.16667 Mbit/s
0 1 0 0 0 1 12 2.08333 Mbit/s
0 1 0 0 1 0 24 1.04167 Mbit/s
0 1 0 0 1 1 48 520.83 kbit/s
0 1 0 1 0 0 96 260.42 kbit/s
0 1 0 1 0 1 192 130.21 kbit/s
0 1 0 1 1 0 384 65.10 kbit/s
0 1 0 1 1 1 768 32.55 kbit/s
0 1 1 0 0 0 8 3.125 Mbit/s
0 1 1 0 0 1 16 1.5625 Mbit/s
0 1 1 0 1 0 32 781.25 kbit/s
0 1 1 0 1 1 64 390.63 kbit/s
0 1 1 1 0 0 128 195.31 kbit/s
0 1 1 1 0 1 256 97.66 kbit/s
0 1 1 1 1 0 512 48.83 kbit/s
0 1 1 1 1 1 1024 24.41 kbit/s
1 0 0 0 0 0 10 2.5 Mbit/s
1 0 0 0 0 1 20 1.25 Mbit/s
1 0 0 0 1 0 40 625 kbit/s
1 0 0 0 1 1 80 312.5 kbit/s
1 0 0 1 0 0 160 156.25 kbit/s
1 0 0 1 0 1 320 78.13 kbit/s
1 0 0 1 1 0 640 39.06 kbit/s
1 0 0 1 1 1 1280 19.53 kbit/s
1 0 1 0 0 0 12 2.08333 Mbit/s
1 0 1 0 0 1 24 1.04167 Mbit/s
1 0 1 0 1 0 48 520.83 kbit/s
1 0 1 0 1 1 96 260.42 kbit/s
1 0 1 1 0 0 192 130.21 kbit/s
1 0 1 1 0 1 384 65.10 kbit/s
1 0 1 1 1 0 768 32.55 kbit/s
1 0 1 1 1 1 1536 16.28 kbit/s
1 1 0 0 0 0 14 1.78571 Mbit/s
1 1 0 0 0 1 28 892.86 kbit/s
1 1 0 0 1 0 56 446.43 kbit/s
1 1 0 0 1 1 112 223.21 kbit/s
1 1 0 1 0 0 224 111.61 kbit/s
Table 17-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
Baud Rate
SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate
Divisor
1 1 0 1 0 1 448 55.80 kbit/s
1 1 0 1 1 0 896 27.90 kbit/s
1 1 0 1 1 1 1792 13.95 kbit/s
1 1 1 0 0 0 16 1.5625 Mbit/s
1 1 1 0 0 1 32 781.25 kbit/s
1 1 1 0 1 0 64 390.63 kbit/s
1 1 1 0 1 1 128 195.31 kbit/s
1 1 1 1 0 0 256 97.66 kbit/s
1 1 1 1 0 1 512 48.83 kbit/s
1 1 1 1 1 0 1024 24.41 kbit/s
1 1 1 1 1 1 2048 12.21 kbit/s
Read: Anytime
Write: Has no effect
Table 17-8. SPISR Field Descriptions
Field Description
7 SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
SPIF information about clearing SPIF Flag, please refer to Table 17-9.
0 Transfer not yet complete.
1 New data copied to SPIDR.
5 SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
SPTEF information about clearing this bit and placing data into the transmit data register, please refer to Table 17-10.
0 SPI data register not empty.
1 SPI data register empty.
4 Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
MODF fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 17.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
or
or
2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
or
or
3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by
writing to SPIDRL after reading SPISR with SPTEF == 1.
SPIF Serviced
SPIF
SPIF
The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the
n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1
register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions
by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data read from the master SPI data
register after a transfer operation is the input data from the slave.
A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.
When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This
data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes.
A common SPI data register address is shared for reading data from the read data buffer and for writing
data to the transmit data register.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1
(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply
selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally
different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see
Section 17.4.3, “Transmission Formats”).
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1
is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
NOTE
A change of CPOL or MSTR bit while there is a received byte pending in
the receive shift register will destroy the received byte and must be avoided.
drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional
mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is
forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If
the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt
sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After
the delay, SCK is started within the master. The rest of the transfer operation differs slightly,
depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1
(see Section 17.4.3, “Transmission Formats”).
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN,
SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in
master mode will abort a transmission in progress and force the SPI into idle
state. The remote slave cannot detect this, therefore the master must ensure
that the remote slave is returned to idle state.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at
the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to
be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the nth1 shift, the transfer is considered complete and the received data is transferred into
the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set.
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or
BIDIROE with SPC0 set in slave mode will corrupt a transmission in
progress and must be avoided.
MISO MISO
SHIFT REGISTER
MOSI MOSI
SHIFT REGISTER
SCK SCK
BAUD RATE
GENERATOR SS SS
VDD
1. n depends on the selected transfer width, please refer to Section 17.3.2.2, “SPI Control Register 2 (SPICR2)
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on
the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master device
to communicate with peripheral slaves having different requirements.
1. n depends on the selected transfer width, please refer to Section 17.3.2.2, “SPI Control Register 2 (SPICR2)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL tT tI tL
MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK
LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB for tT, tl, tL
tL = Minimum leading time before the first SCK edge
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time)
tL, tT, and tI are guaranteed for the master mode and required for the slave mode.
Figure 17-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL tT tI tL
MSB first (LSBFE = 0) MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK
LSB first (LSBFE = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11 Bit 12Bit 13Bit 14 MSB for tT, tl, tL
tL = Minimum leading time before the first SCK edge
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time)
tL, tT, and tI are guaranteed for the master mode and required for the slave mode.
Figure 17-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the
SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the
SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the
LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master
data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
This process continues for a total of n1 edges on the SCK line with data being latched on even numbered
edges and shifting taking place on odd numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and
is transferred to the parallel SPI data register after the last bit is shifted in.
After 2n1 SCK edges:
• Data that was previously in the SPI data register of the master is now in the data register of the
slave, and data that was in the data register of the slave is in the master.
• The SPIF flag bit in SPISR is set indicating that the transfer is complete.
Figure 17-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master
or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the
master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from
the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high
or reconfigured as a general-purpose output not affecting the SPI.
End of Idle State Begin Transfer End Begin of Idle State
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL tT tI tL
MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK
LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB for tT, tl, tL
tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 17-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tL tT tI tL
MSB first (LSBFE = 0) MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK
LSB first (LSBFE = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11 Bit 12Bit 13Bit 14 MSB for tT, tl, tL
tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 17-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
• Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register,
this data is sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection
bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor
becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When
the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 17-7 for baud rate calculations
for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided
by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease IDD current.
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
17.4.5.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and
MODFEN bit as shown in Table 17-3.
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multimaster
system because the mode fault feature is not available for detecting system
errors between masters.
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output,
serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift
register.
• The SCK is output for the master mode and input for the slave mode.
• The SS is the input or output for the master mode, and it is always the input for the slave mode.
• The bidirectional mode does not affect SCK and SS functions.
NOTE
In bidirectional master mode, with mode fault enabled, both data pins MISO
and MOSI can be occupied by the SPI, though MOSI is normally used for
transmissions in bidirectional mode and MISO is not used by the SPI. If a
mode fault occurs, the SPI is automatically switched to slave mode. In this
case MISO becomes occupied by the SPI and MOSI is not used. This must
be considered, if the MISO pin is used for another purpose.
the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur
in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output
buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any
possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is
forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output
enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in
the bidirectional mode for SPI system configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed
by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or
slave again.
NOTE
If a mode fault error occurs and a received data byte is pending in the receive
shift register, this data byte will be lost.
NOTE
Care must be taken when expecting data from a master while the slave is in
wait or stop mode. Even though the shift register will continue to operate,
the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated
until exiting stop or wait mode). Also, the byte from the shift register will
not be copied into the SPIDR register until after the slave SPI has exited wait
or stop mode. In slave mode, a received byte pending in the receive shift
register will be lost when entering wait or stop mode. An SPIF flag and
SPIDR copy is generated only if wait mode is entered or exited during a
tranmission. If the slave enters wait mode in idle mode and exits wait mode
in idle mode, neither a SPIF nor a SPIDR copy will occur.
17.4.7.4 Reset
The reset values of registers and signals are described in Section 17.3, “Memory Map and Register
Definition”, which details the registers and their bit fields.
• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the data last received from the master before the reset.
• Reading from the SPIDR after reset will always read zeros.
17.4.7.5 Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is
a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
17.4.7.5.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see Table 17-3). After MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in Section 17.3.2.4, “SPI Status Register (SPISR)”.
17.4.7.5.2 SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does
not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 17.3.2.4,
“SPI Status Register (SPISR)”.
17.4.7.5.3 SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process, which is described in Section 17.3.2.4, “SPI
Status Register (SPISR)”.
Version
Revision Date Description of Changes
Number
V6 Initial Draft 25-January-2015 Initial Draft based on GDUV4/V5 with following changes for SR Motor support:
• additional drain connections LD[2:0] for SR motor drive
• GDUCTR1 register with control bits for SR motor drive
• Removed EPRES control bit functionality for V5 and V6
• Changed GSUF startup flag functionality for V6
V6 28-January-2016 • Removed EPRES Functionality
• Common specification for GSUF with reference to device
overview
• Common specification for GDUCTR1 with reference to device
overview
V6.1 4-February-2016 • Corrected Table 1-2 TDEL availability and low-side driver on
or off out of reset dependent on NVM option for GDU V4
V6.2 17-May-2016 • Removed desaturation comparator level and desaturation
comparator filter time constant (relocated in electrical spec.)
V6.2 17-May-2016 • Removed desaturation comparator level and desaturation
Current sense amplifier offset adjustable in 5mV adjustable in 3mV adjustable in 3mV steps
steps steps
On chip bootstrap diode not available, off available not available, off chip bootstrap diode
chip bootstrap diode required
required
The GDU module is a Field Effect Transistor (FET) pre-driver designed for three phase motor control
applications.
18.1.1 Features
The GDU module includes these distinctive features:
• 11V voltage regulator for FET pre-drivers
• Boost converter option for low supply voltage condition
• 3-phase bridge FET pre-drivers
• Bootstrap circuit for high-side FET pre-drivers with external bootstrap capacitor
• Charge pump for static high-side driver operation
• Phase voltage measurement with internal ADC
• Two low-side current measurement amplifiers for DC phase current measurement
• Phase comparators for BEMF zero crossing detection in sensorless BLDC applications
• Voltage measurement on HD pin (DC-Link voltage) with internal ADC
• Desaturation comparator for high-side drivers and low-side drivers protection
• Undervoltage detection on FET pre-driver supply pin VLS
• Two overcurrent comparators with programmable voltage threshold
• Overvoltage detection on 3-phase bridge supply HD pin
VSSB
VCP
BST
CP
Boost Converter Charge
Option Pump HD
VBS[2:0]
Control HG[2:0]
Error
HS[2:0]
Level Shifters
IP Bus LG[2:0]
LS[2:0]
LD[2:0]
(only on GDUV6)
AMPP[1:0]
VLS_OUT
AMPM[1:0]
VSUP
NOTE
A 4.7uF or 10uF capacitor should be connected to this pin for stability of the
the voltage regulator output.
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0000 R 0 0
GDUE GWP GCSE1 GBOE GCSE0 GCPE GFDE
W
0x0001 R GVLSLVL
GDUCTR GHHDLVL (1) GBKTIM2[3:0] GBKTIM1[1:0]
W
0x0002 R 0 0 0
GDUIE GOCIE[1:0] GDSEIE GHHDIE GLVLSIE
W
0x0003 R 0 0
GDUDSE GDHSIF[2:0] GDLSIF[2:0]
W
0x0005 R 0 0
GDUSRC GSRCHS[2:0] GSRCLS[2:0]
W
0x0006 R 0
GDUF GSUF GHHDF GLVLSF GOCIF[1:0] GHHDIF GLVLSIF
W
0x0007 R 0
GDUCLK1 GBOCD[4:0] GBODC[1:0]
W
= Unimplemented
Figure 18-2. GDU Register Summary
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0008 R 0 0 0 0
GDUBCL GBCL[3:0]
W
0x0009 R 0 0 0 0 0 0
GDUPHMUX GPHMX[1:0]
W
0x000A R 0 0
GDUCSO GCSO1[2:0] GCSO0[2:0]
W
0x000C R 0 0 0 0 0 GPHL[2:0]
GDUPHL W
0x000D R 0 0 0 0
GDUCLK2 GCPCD[3:0]
W
0x000E R 0
GDUOC0 GOCA0 GOCE0 GOCT0[4:0](2)
W
0x000F R 0
GDUOC1 GOCA1 GOCE1 GOCT1[4:0](3)
W
0x0010 R 0 0 0 0 0
GDUCTR1(4) GSRMOD[1:0] TDEL
W
0x0011-
0x001F
= Unimplemented
Figure 18-2. GDU Register Summary
1. Not available on GDUV4
2. On GDUV4 only GOCT0[3:0] available
3. On GDUV4 only GOCT1[3:0] available
4. GDUCTR1 register availability is defined at device level.
7 6 5 4 3 2 1 0
R 0 0
GWP GCSE1 GBOE GCSE0 GCPE GFDE
W
Reset 0 0 0 0 0 0 0 1
= Unimplemented
Field Description
7 GDU Write Protect— This bit enables write protection to be used for the write protectable bits. While clear, GWP
GWP allows write protectable bits to be written. When set GWP prevents any further writes to write protectable bits.
Once set , GWP is cleared by reset.
0 Write-protectable bits may be written
1 Write-protectable bits cannot be written
4 GDU Current Sense Amplifier 1 Enable— This bit enables the current sense amplifier. See Section 18.4.8,
GCSE1 “Current Sense Amplifier and Overcurrent Comparator
0 Current sense amplifier 1 is disabled
1 Current sense amplifier 1 is enabled
3 GDU Boost Converter Enable — This bit enables the boost option. This bit cannot be modified after GWP bit is
GBOE set. See Section 18.4.10, “Boost Converter
0 Boost option is disabled
1 Boost option is enabled
2 GDU Current Sense Amplifier 0 Enable— This bit enables the current sense amplifier. See Section 18.4.8,
GCSE0 “Current Sense Amplifier and Overcurrent Comparator
0 Current sense amplifier 0 is disabled
1 Current sense amplifier 0 is enabled
Field Description
1 GDU Charge Pump Enable — This bit enables the charge pump. This bit cannot be modified after GWP bit is
GCPE set. See Section 18.4.4, “Charge Pump
0 Charge pump is disabled
1 Charge pump is enabled
0 GDU FET Pre-Driver Enable — This bit enables the low-side and high-side FET pre-drivers. It must also be set
GFDE in order to use the boost converter and the current sense amplifiers. This bit cannot be modified after GWP bit is
set.See Section 18.4.2, “Low-Side FET Pre-Drivers and Section 18.4.3, “High-Side FET Pre-Driver.
0 Low-side and high-side drivers are disabled
1 Low-side and high-side drivers are enabled
NOTE
It is not allowed to set and clear GFDE bit periodically in order
to switch on and off the FET pre-drivers. In order to switch on
and off the FET pre-drivers the PMF module has to be used to
mask and un-mask the PWM channels.
7 6 5 4 3 2 1 0
R
GHHDLVL GVLSLVL GBKTIM2[3:0] GBKTIM1[1:0]
W
Reset 0 1 0 1 0 0 0 0
= Unimplemented
Field Description
7 GDU High HD Level Select — Selects the voltage threshold of the overvoltage detection on HD pin.
GHHDLVL This bit cannot be modified after GWP bit is set.
0 Voltage thresholds of the overvoltage detection on HD pin configured for VHVHDLA and VHVHDLD
1 Voltage thresholds of the overvoltage detection on HD pin configured for VHVHDHA and VHVHDHD
6 GDU VLS Level Select — Selects the voltage threshold of the undervoltage detection on VLS pin.
GVLSLVL This bit cannot be modified after GWP bit is set.
(Not featured 0 Voltage thresholds of the undervoltage detection on VLS pin configured for VLVLSLA and VLVLSLD
on GDUV4) 1 Voltage thresholds of the undervoltage detection on VLS pin configured for VLVLSHA and VLVLSHD
5-2 GDU Blanking Time — These bits adjust the blanking time tBLANK of the desaturation error comparators. The
GBKTIM2[3:0] resulting blanking time tBLANK can be calculated from the equation below. For GBKTIM2[3:0]=$F no
desaturation errors are captured and the drivers are unprotected and the charge pump will not connect to the
high-side drivers. These bits cannot be modified after GWP bit is set.
· GBKTIM1 + 1
t BLANK = GBKTIM2 + 1 2 + 2 T BUS
1-0 GDU Blanking Time — These bits adjust the blanking time tBLANK of the desaturation error comparators. The
GBKTIM1[1:0] resulting blanking time tBLANK can be calculated from the equation in the field description above.These bits
cannot be modified after GWP bit is set.
NOTE
The register bits GBKTIM1 and GBKTIM2 must be set to the required
values before the PWM channel is activated. Once the PWM channel is
activated, the value of GBKTIM1 & GBKTIM2 must not change. If a
different blanking time is required, the PWM channel has to be turned off
before new values to GBKTIM1 & GBKTIM2 are written.
7 6 5 4 3 2 1 0
R 0 0 0
GOCIE[1:0] GDSEIE GHHDIE GLVLSIE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
2 GDU Desaturation Error Interrupt Enable — Enables desaturation error interrupt on low-side or high-side
GDSEIE drivers
0 No interrupt will be requested if any of the flags in the GDUDSE register is set
1 Interrupt will be requested if any of the flags in the GDUDSE register is set
0 GDU Low VLS Interrupt Enable — Enables the interrupt which indicates low VLS supply
GLVLSIE 0 No interrupt will be requested whenever GLVLSIF flag is set
1 Interrupt will be requested whenever GLVLSIF flag is set
7 6 5 4 3 2 1 0
R 0 GDHSIF[2:0] 0 GDLSIF[2:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
6-4 GDU High-Side Driver Desaturation Interrupt Flags — The flag is set by hardware to “1” when a desaturation
GDHSIF[2:0] error on associated high-side driver pin HS[2:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing
a logic “1” to the bit field clears the flag.
0 No desaturation error on high-side driver
1 Desaturation error on high-side driver
2-0 GDU Low-Side Driver Desaturation Interrupt Flag — The flag is set to “1” when a desaturation error on
GDLSIF[2:0] associated low-side driver pin LS[2:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing a logic
“1” to the bit field clears the flag.
0 No desaturation error on low-side driver
1 Desaturation error on low-side driver
7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7-5 GDU Phase Status — The status bits are set to 1 when the voltage on associated pin HS[2:0] is greater than
GPHS[2:0] VHD/2. The flags are cleared when the voltage on associated pin HS[2:0] is less than VHD/2. See Section 18.4.6,
“Phase Comparators
0 Voltage on pin HSx is VHSx < VHD/2
1 Voltage on pin HSx is VHSx > VHD/2
4-3 GDU Overcurrent Status — The status bits are set to 1 when the voltage on the overcurrent comparator input
GOCS[1:0] is above the threshold voltage VOCT. The flag is cleared when the voltage on the overcurrent comparator input
is less than VOCT.Section 18.4.8, “Current Sense Amplifier and Overcurrent Comparator
0 Voltage on overcurrent comparator input is is less than VOCT
1 Voltage on overcurrent comparator is greater than VOCT
1 GDU High HD Supply Status — The status bit is set to 1 when the voltage on HD pin is above the threshold
GHHDS voltage VHVHDLA or VHVHDHA depending on the value of the GHHDLVL bit. The flag is cleared when the voltage
on HD pin is less than VHVHDLD or VHVHDHD depending on the value of the GHHDLVL bit.
0 Voltage on pin HD is less than VHVHDLD or VHVHDHD
1 Voltage on pin HD is greater than VHVHDLA or VHVHDHA
0 GDU Low VLS Status — The status bit is set to 1 when the voltage on VLS_OUT pin is below the threshold
GLVLSS voltage VLVLSA. The flag is cleared when the voltage on VLS_OUT pin is greater than VLVLSD.
0 Voltage on pin VLS_OUT is greater than VLVLSD
1 Voltage on pin VLS_OUT is less than VLVLSA
7 6 5 4 3 2 1 0
R 0 0
GSRCHS[2:0] GSRCLS[2:0]
W
Reset 0 1 0 0 0 1 0 0
= Unimplemented
1. Read: Anytime
Write: Only if GWP=0
Field Description
6:4 GDU Slew Rate Control Bits High-Side FET Pre-Drivers — These bits control the slew rate on the HG[2:0] pins
GSRCHS[2:0] (see FET Pre-Driver Details) .These bits cannot be modified after GWP bit is set.
000 : slowest
.
.
111 : fastest
3:0 GDU Slew Rate Control Bits Low-Side FET Pre-Drivers — These bits control the slew rate on the LG[2:0] pins
GSRCLS[2:0] (see FET Pre-Driver Details). These bits cannot be modified after GWP bit is set.
000 : slowest
.
.
111 : fastest
7 6 5 4 3 2 1 0
R 0
GSUF GHHDF GLVLSF GOCIF[1:0] GHHDIF GLVLSIF
W
= Unimplemented
2. Loaded out of reset depending on mask set implementation as specified in the device overview
Field Description
7 GDU Start-up Flag — The start-up flag is cleared by reset and loaded depending on the device mask set
GSUF implementation, as specified in the device overview, after reset de-asserts. Writing a logic “1” to the bit field
clears the flag. If the flag is set all high-side FET pre-drivers are turned off and all low-side FET pre-drivers are
turned on. If the flag is cleared and there is no error condition present all high-side and low-side FET pre-drivers
are driven by the pwm channels.
0 High-side and low-side FET pre-drivers are driven by pwm channels
1 High-side FET pre-drivers turned off and low-side FET pre-drivers are turned on
6 GDU High VHD Supply Flag — The flag controls the state of the FET pre-drivers. If the flag is set and GOCA1=0
GHHDF the high-side pre-drivers are turned off and the low-side pre-drivers are turned on. If GOCA1=1 all high-side
and low-side FET pre-drivers are turned off. If the flag is cleared and no other error condition is present the high-
side and low-side pre-drivers are driven by the PWM channels. The flag is set by hardware if a high voltage
condition on HD pin occurs. The flag is set if the voltage on pin HD is greater than the threshold voltage VHVHDLA
or VHVHDHA . Writing a logic “1” to the bit field clears the flag.
0 Voltage on pin HD is less than VHVHDLD or VHVHDHD
1 Voltage on pin HD is greater than VHVHDLA or VHVHDHA
5 GDU Low VLS Supply Flag — The flag controls the state of the FET pre-drivers. If the flag is set all high-side
GLVLSF and low-side pre-drivers are turned off. If the flag is cleared and no other error condition is present the high-side
and low-side pre-drivers are driven by the PWM channels. The flag is set by hardware if a low voltage condition
on VLS_OUT pin occurs. Writing a logic “1” to the bit field clears the flag.
0 VLS_OUT pin voltage is above VLVLSD
1 VLS_OUT pin voltage is below VLVLSHA, or VLVLSLA all high-side and low-side FET pre-drivers are turned off
4-3 GDU Overcurrent Interrupt Flag — The interrupt flags are set by hardware if an overcurrent condition occurs.
GOCIF[1:0] The flags are set if the voltage on the overcurrent comparator input is greater than the threshold voltage VOCT.
If the GOCIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag. If the GOCAx
bit is cleared all high-side FET pre-drivers are turned off and fault[4] is asserted. If GOCAx is set all high-side
and low-side FET pre-drivers are turned off and fault[2:0] are asserted.
0 Voltage on overcurrent comparator input is less than VOCT
1 Voltage on overcurrent comparator is greater than VOCT
Field Description
1 GDU High VHD Supply Interrupt Flag— The interrupt flag is set by hardware if GHHDF is set or if GHHDS is
GHHDIF cleared. If the GHHDIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag.
0 GDU Low VLS Supply Interrupt Flag— The interrupt flag is set by hardware if GLVLSF is set or GLVLSS is
GLVLSIF cleared. If the GLVLSIE bit is set an interrupt is requested.Writing a logic “1” to the bit field clears the flag.
NOTE
The purpose of the GSUF flag is to allow dissipation of the energy in the
motor coils through the low side FETs in case of short reset pulses whilst the
motor is spinning.
7 6 5 4 3 2 1 0
R 0
GBOCD[4:0] GBODC[1:0]
W
Reset 0 0 0 0 0 0 0 0
Field Description
6-2 GDU Boost Option Clock Divider — These bits select the clock divider factor which is used to divide down the
GBOCD[4:0] bus clock frequency fBUS for the boost converter clock fBOOST. These bits cannot be modified after GWP bit is
set. See Table 18-11 for divider factors. See also Section 18.4.10, “Boost Converter
1-0 GDU Boost Option Clock Duty Cycle— These bits select the duty cycle of the boost option clock fboost. For
GBODC[1:0] GBOCD[4]= 0 the duty cycle of the boost option clock is always 50%. These bits cannot be modified after GWP
bit is set.
00 Duty Cycle = 50%
01 Duty Cycle = 25%
10 Duty Cycle = 50%
11 Duty Cycle = 75%
NOTE
The GBODC & GBOCD register bits must be set to the required value
before GBOE bit is set. If a different boost clock frequency and duty cycle
is required GBOE has to be cleared before new values to GBODC &
GBOCD are written.
GBOCD[4:0] fBOOST
00000 fBUS / 4
00001 fBUS / 4
00010 fBUS / 4
00011 fBUS / 4
00100 fBUS / 4
00101 fBUS / 4
00110 fBUS / 6
00111 fBUS / 6
01000 fBUS / 8
01001 fBUS / 8
01010 fBUS / 10
01011 fBUS / 10
01100 fBUS / 12
01101 fBUS / 12
01110 fBUS / 14
01111 fBUS / 14
10000 fBUS / 16
10001 fBUS / 24
10010 fBUS / 32
10011 fBUS / 48
10100 fBUS / 64
10101 fBUS / 96
GBOCD[4:0] fBOOST
7 6 5 4 3 2 1 0
R 0 0 0 0
GBCL[3:0]
W
Reset 0 0 0 0 0 0 0 0
Field Description
GBCL[3:0] GDU Boost Current Limit Register— These bits are used to adjust the boost coil current limit ICOIL0,16 on the
BST pin. These bits cannot be modified after GWP bit is set. See GDU electrical parameters.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
GPHMX[1:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
[1:0] GDU Phase Multiplexer — These buffered bits are used to select the voltage which is routed to internal ADC
GPHMUX channel.The value written to the GDUPHMUX register does not take effect until the LDOK bit is set and the next
PWM reload cycle begins. Reading GDUPHMUX register reads the value in the buffer. It is not necessary the
value which is currently used.
00 Pin HD selected , VHD / 12 connected to ADC channel
01 Pin HS0 selected , VHS0 / 6 connected to ADC channel
10 Pin HS1 selected , VHS1 / 6 connected to ADC channel
11 Pin HS2 selected, VHS2 / 6 connected to ADC channel
7 6 5 4 3 2 1 0
R 0 0
GCSO1[2:0] GCSO0[2:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description (See also Section 18.4.8, “Current Sense Amplifier and Overcurrent Comparator)
6:4 GDU Current Sense Amplifier 1 Offset — These bits adjust the offset of the current sense amplifier
GCSO1[2:0] 000 No offset
001 Offset is +3mV (GDUV5 and V6). Offset is +5mV (GDUV4).
010 Offset is +6mV (GDUV5 and V6). Offset is +10mV (GDUV4)
011 Offset is +9mV (GDUV5 and V6). Offset is +15mV (GDUV4)
100 No offset
101 Offset is -9mV (GDUV5 and V6). Offset is -15mV (GDUV4)
110 Offset is -6mV (GDUV5 and V6). Offset is -10mV (GDUV4).
111 Offset is -3mV (GDUV5 and V6). Offset is -5mV (GDUV4).
2:0 GDU Current Sense Amplifier 0 Offset — These bits adjust the offset of the current sense amplifier.
GCSO0[2:0] 000 No offset
001 Offset is +3mV (GDUV5 and V6). Offset is +5mV (GDUV4).
010 Offset is +6mV (GDUV5 and V6). Offset is +10mV (GDUV4)
011 Offset is +9mV (GDUV5 and V6). Offset is +15mV (GDUV4)
100 No offset
101 Offset is -9mV (GDUV5 and V6). Offset is -15mV (GDUV4)
110 Offset is -6mV (GDUV5 and V6). Offset is -10mV (GDUV4).
111 Offset is -3mV (GDUV5 and V6). Offset is -5mV (GDUV4).
7 6 5 4 3 2 1 0
R
GDSFHS GDSLHS[2:0] GDSFLS GDSLLS[2:0]
W
Reset 0 0 0 0 0 1 1 1
= Unimplemented
Field Description
7 GDU Desaturation Filter Characteristic for High-Side Drivers — This bit adjusts the desaturation filter
GDSFHS characteristic of the three high-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See
(Not featured Section 18.4.5, “Desaturation Error.
on GDUV4)
6:4 GDU Desaturation Level for High-Side Drivers — These bits adjust the desaturation levels of the three high-
GDSLHS side FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation
Error
000 Vdesaths = VHD - 0.35V (typical value)
001 to 110 see device electrical specification
111 Vdesaths = VHD - 1.40V (typical value)
3 GDU Desaturation Filter Characteristic for Low-Side Drivers — This bit adjusts the desaturation filter
GDSFLS characteristic of the three low-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See
(Not featured Section 18.4.5, “Desaturation Error.
on GDUV4)
2:0 GDU Desaturation Level for Low-Side Drivers — These bits adjust the desaturation level of the three low-side
GDSLLS FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error
000 Vdesatls = 0.35V (typical value)
001 to 110 see device electrical specification
111 Vdesatls = 1.40V (typical value)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 GPHL[2:0]
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
2:0 GDU Phase Log Bits— If a desaturation error occurs the phase status bits GPHS[2:0] in register GDUSTAT are
GPHL copied to this register. The GDUPHL register is cleared only on reset. See Section 18.4.5, “Desaturation Error
7 6 5 4 3 2 1 0
R 0 0 0 0
GCPCD[3:0]
W
Reset 0 0 0 0 0 0 0 0
Field Description
3-0 GDU Charge Pump Clock Divider — These bits select the clock divider factor which is used to divide down the
GCPCD[3:0] bus clock frequency fBUS for the charge pump clock fCP. See Table 18-18 for divider factors. These bits cannot
be modified after GWP bit is set. See also Section 18.4.4, “Charge Pump
NOTE
The GCPCD bits must be set to the required value before GCPE bit is set. If
a different charge pump clock frequency is required GCPE has to be cleared
before new values to GCPCD bits are written.
GCPCD[3:0] fCP
0000 fBUS / 16
0001 fBUS / 24
0010 fBUS / 32
0011 fBUS / 48
0100 fBUS / 64
0101 fBUS / 96
7 6 5 4 3 2 1 0
R 0
GOCA0 GOCE0 GOCT0[4:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 GDU Overcurrent Action — This bit cannot be modified after GWP bit is set. This bit controls the action in case
GOCA0 of an overcurrent event. See Table 18-24 and Table 18-23
6 GDU Overcurrent Comparator Enable — This bit cannot be modified after GWP bit is set.
GOCE0 0 Overcurrent Comparator is disabled
1 Overcurrent Comparator is enabled
3:0 GDU Overcurrent Comparator Threshold — These bits cannot be modified after GWP bit is set. The overcurrent
GOCT0[3:0] comparator threshold voltage is the output of a 6-bit digital-to-analog converter. The upper two bits of the digital
inputs are tied to one. The other bits of the digital inputs are driven by GOCT0. The overcurrent comparator
threshold voltage can be calculated from equation below.
VDDA
Voct0 = 48 + GOCT0 ------------------
64
4:0 GDU Overcurrent Comparator Threshold — These bits cannot be modified after GWP bit is set. The overcurrent
GOCT0[4:0] comparator threshold voltage is the output of a 6-bit digital-to-analog converter. The upper bit of the digital
inputs is tied to one. The other bits of the digital inputs are driven by GOCT0. The overcurrent comparator
threshold voltage can be calculated from equation below.
VDDA
Voct0 = 32 + GOCT0 ------------------
64
7 6 5 4 3 2 1 0
R 0
GOCA1 GOCE1 GOCT1[4:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 GDU Overcurrent Action — This bit cannot be modified after GWP bit is set. This bit controls the action in case
GOCA1 of an overcurrent event or overvoltage event. See Table 18-24 and Table 18-23
6 GDU Overcurrent Enable — This bit cannot be modified after GWP bit is set.
GOCE1 0 Overcurrent Comparator 1 is disabled
1 Overcurrent Comparator 1 is enabled
3:0 GDU Overcurrent Comparator Threshold — These bits cannot be modified after GWP bit is set. The overcurrent
GOCT1[3:0] comparator threshold voltage is the output of a 6-bit digital-to-analog converter. The upper two bits of the digital
inputs are tied to one. The other bits of the digital inputs are driven by GOCT1. The overcurrent comparator
threshold voltage can be calculated from equation below.
VDDA
Voct1 = 48 + GOCT1 ------------------
64
4:0 GDU Overcurrent Comparator Threshold — These bits cannot be modified after GWP bit is set. The overcurrent
GOCT1[4:0] comparator threshold voltage is the output of a 6-bit digital-to-analog converter. The upper bit of the digital
inputs is tied to one. The other bits of the digital inputs are driven by GOCT1. The overcurrent comparator
threshold voltage can be calculated from equation below.
VDDA
Voct1 = 32 + GOCT1 ------------------
64
7 6 5 4 3 2 1 0
R 0 0 0 0 0
GSRMOD1 GSRMOD0 TDEL
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Field Description
7 GDU Switched Reluctance Motor Mode 1 — This bit cannot be modified after GWP bit is set. This bit controls
GSRMOD1 the routing of the LDx pins to the low-side desaturation comparators for switched reluctance motor. See
Figure 18-23
0 HSx routed to low-side desaturation comparator
1 LDx routed to low-side desaturation comparator
6 GDU Switched Reluctance Motor Mode 0 — This bit cannot be modified after GWP bit is set.
GSRMOD0 0 BLDC mode. Don’t allow HGx and LGx high at the same time.
1 SR mode. Allow HGx and LGx high at the same time.
0 tdelon / tdeloff Control — This bit controls the parameters tdelon and tdeloff. It cannot be modified after GWP bit
TDEL is set. This bit must be set to meet the min and max values for tdelon and tdeloff specified in the electrical
specification. If this bit is cleared the values for tdelon and tdeloff are out of spec.
NOTE
GDU Control Register 1 GDUCTR1 availability is defined at device level.
18.4.1 General
The PMF module provides the values to be driven onto the outputs of the low-side and high-side FET pre-
drivers. If the FET pre-drivers are enabled, the PMF channels drive their corresponding high-side or low-
side FET pre-drivers according Table 18-22.
PMF
PMF Channel Assignment
Channel
NOTE
If the GFDE bit is cleared the high-side gate and source pins and the low-
side gate and source pins are shorted with an internal resistor. The voltage
differences are VHGx-VHSx~ 0V and VLGx-VLSx ~ 0V so that the external
FETs are turned off.
NOTE
The PWM channel outputs for high-side and low-side drivers are delayed by
two core clock cycles.
VBAT
D5
VSUP
Reverse Battery
- Protection
Vref +
VLS_OUT
10uF optional charge pump filter
GCPE
D4
CP C1
100
D1
220nF
VCP
GCPCD[3:0]
C2
HD
GHHDIF
Charge Pump Connect P2
Diode only required
GSRCHS[2:0] VBSx for GDUV4 and V6
optional VBS RC filter
CBS
hs_on HGx
RFILT
CFILT
CG
HSx RHS
Bootstrap Transistor on P1
GSRCLS[2:0] VLSx
ls_on
LGx
LDx (only on GDUV6) CG
LSx
Rsense
Recommended values for optional VBS filter CFLT = 3.3nF, RFLT = 10ohms, RHS = 10ohms
NOTE
Optional charge pump input RC filter can be used to avoid over pumping
effect when voltage spikes are present on the high-side drains.
NOTE
Optional RC filter to VBS pin should be used to avoid overshoot above
maximum voltage on VBS pin. The RC filter needs to be carefully designed
in order not to influence the charging time of the bootstrap capacitor CBS.
NOTE
GDUV4 and V6 does not include Bootstrap Transistor P1. It is only
available on GDUV5. An external bootstrap diode is required for GDUV4
and V6.
On GDUV5 the bootstrap transistor P1 is turned on when the corresponding
low-side driver is turned on and no high voltage condition on HD pin and
no desaturation error is flagged.
GCPE
PWM
hs_on tdelon
tdeloff
tBLANK
charge pump connect
tHGON
tHGOFF
HG
Desturation Comparator
Output
Desaturation Filter
output
tDSFHS / tDSFLS
The low-side and high-side desaturation interrupt flags GDHSIF and GDLSIF are cleared by writing a one
to the associated flag. After the flag is cleared the associated low-side or high-side FET pre-driver is
enabled again and is driven by the source selected in the PMF module.
Figure 18-23. Desaturation Comparators and Phase Comparators in BLDC Mode (LDx not connected)1
Phase Comp.
HSx
+
Phase Status BLDC Motor
- VHD/2 LDx
GSRMOD1
1. LDx pins and the routing option of HSx or LDx to the desaturation comparator of the low-side driver controlled by
GSRMOD1 is only available on GDUV6.
Figure 18-24. Desaturation Comparators and Phase Comparators in SR mode (LDx connected)1
Phase Comp.
HSx
+
Phase Status
SR Motor
- VHD/2
LDx
GSRMOD1
1. LDx pins and the routing option of HSx or LDx to the desaturation comparator of the low-side driver controlled by
GSRMOD1 is only available on GDUV6.
GDU V5 and V6
Fault[3] GLVLSF
GDUV4
Fault[3] GLVLSIF
low normal operation,no error condition, FET 0 0 0 0 0 000 000 PWM PWM PWM PWM PWM PWM
pre-driver driven by PMF module [4] [2] [0] [5] [3] [1]
startup condition after reset deassert, no 1 0 0 0 0 000 000 off off off on/off on/off on/off
error condition (1)
undervoltage condition on VLS_OUT pin x x x x 1 000 000 off off off off off off
overcurrent condition comparator 0 x x 1 x x 000 000 off off off off off off
GOCA0=1
overcurrent condition comparator 1 x x x 1 x 000 000 off off off off off off
GOCA1=1
desaturation error condition on high-side x x x x x 001 000 PWM PWM off PWM PWM PWM
FET pre-drivers [4] [2] [5] [3] [1]
1. Startup condition of the low-side drivers LS[2:0] on GDUV6 depends on the flash option bit. On GDUV4 and V5 the low-side drivers are on out of reset.
735
Chapter 18 Gate Drive Unit (GDU)
NOTE
Since all MOSFET transistors are turned off, VBSX can reach phase voltage
plus bootstrap voltage which may exceed allowable levels during high
supply voltage conditions. If such operating condition exist the application
must make sure that VBSX levels are clamped below maximum ratings for
example by using clamping diodes.
LGx
tBLANK
HGx
VHD HSx shorted to supply
fault
Phase Status correct
Desat. Error
HGx
tBLANK
LGx
VHD correct voltage on HSx
Desat. Error
Overcurrent Condition
GCSE0 GCSO0[2:0]
Output Voltage to ADC
Rp / a
VAMP = a Vsense + Vref + AMPP[0]
=
- Voffset Rp
Rn Rn / a
L
D1
C1 C2
D2
BST VSUP
R GBOE
Vrefcl Vref
= =
GBOCD[4:0]
GBODC[1:0]
VSSB
18.4.11 Interrupts
This section describes the interrupts generated in the GDU module. The interrupts are only available in
CPU run mode. Entering and exiting stop mode has no effect on the interrupt flags. The GDU module has
two interrupt vectors which are listed in Table 18-25. The low-side and high-side desaturation error flags
are combined into one interrupt line and the over and under voltage detection are combined into another
interrupt line. (see device specific section interrupt vector table)
Table 18-25. GDU Module Interrupt Sources
1 GDU over/under voltage GDU low voltage condition on pin VLS GLVLSIE = 1
detection and overcurrent (GLVLSIF)
detection interrupt
GDU high voltage condition on pin HD GHHDIE = 1
(GHHDIF)
Assuming an ideal op-amp the voltage across R1 is equal voltage across R2 and IOUT2 is given by:
• V1 = V2 = IREF R1 = IOUT2 R2
• IOUT2 = IREF (R1/R2)
With the ratio of the transistor sizes of T1 and T2 k=450, and the ratio of the resistors R1/R2=36, and neglect the current through
RHSpul the output current IOUT is:
• IOUT1 = k IOUT2
• IOUT = IOUT1 + IOUT2 = IREF (R1/R2) (1+k)
• IOUT ~ IREF (R1/R2) k
R1 V1 R2 V2
GSRCHS[2:0] CG
Driver Off RHSpul
T3 T4
HS
Rgduoffn Rgduoffp
NOTE
FET pre-driver concept shown in Figure 18-29 for the high-side driver
applies also to low-side driver. The reference current for the low-side driver
is controlled by GSRCLS[2:0].
PWMx Channel
HGx/LGx
Figure 18-31 shows examples of intrinsic dead times. For example assuming minimum values for tHGON
and tdelon for the high side gate HG0 and minimum values for tHGOFF and tdeloff for low-side gate LG0 no
additional dead time setting in the PMF module is required and the PWM channels can change at the same
time without cross conduction of the power MOSFETs.
1. Note that tHGON and tHGOFF is the turn on and turn off time for high-side and low-side gate
PWM0
PWM1
HG0
min turn on delay
and min turn on time tdelon_min
tHGON_min
HG0
max turn on delay
and max turn on time tdelon_max
tHGON_max
tHGOFF_min
tHGOFF_max
Eqn. 18-1
Q BS V BS
- = --------------------
V G = -------------------------- -
C BS + C G CG
1 + ----------- -
C BS
For example if CBS = 20 CG then the resulting gate voltage is VG = 0.95 VBS.
PWM0
hs0_fb
tdelon tdeloff
PWM1
ls0_fb
tdelon tdeloff
gdu_delay_on_off
Overcurrent and
21 Aug 2013 TxD-dominant - Specified the time after which the interrupt flags are set again after having
V02.10
timeout interrupt been cleared while the error condition is still present.
descriptions
19 Sep 2013 All - Removed preliminary note.
V02.11
- Fixed grammar and spelling throughout the document.
19.1 Introduction
This chapter provides information for both the LIN physical interface and the HV interface. Devices
may include either a LINPHY or HVPHY module. The device overview section specifies the
LINPHY/HVPHY to device mapping.
The LIN (Local Interconnect Network) bus pin provides a physical layer for single-wire communication
in automotive applications. The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2
specification from LIN consortium.
The HV physical interface provides a physical layer for single-wire communication. It can be used, among
other examples, for PWM applications since it can be connected to an internal timer.
NOTE
All references to LIN (e.g. names of bits, registers, signals, pins, interrupts,
etc.) apply to the HV physical interface as well. The same names have been
kept to highlight and facilitate the hardware and software compatibility
between both versions. Nevertheless, cases where particular LIN features do
not apply to the HV physical interface version are specifically mentioned.
19.1.1 Features
The LIN Physical Layer module includes the following distinctive features:
• Compliant with LIN Physical Layer 2.2 specification.
• Compliant with the SAE J2602-2 LIN standard.
• Standby mode with glitch-filtered wake-up.
• Slew rate selection optimized for the baud rates: 10.4 kbit/s, 20 kbit/s and Fast Mode (up to
250 kbit/s).
• Switchable 34 k/330 k pullup resistors (in shutdown mode, 330 konly
• Current limitation for LIN Bus pin falling edge.
• Overcurrent protection.
• LIN TxD-dominant timeout feature monitoring the LPTxD signal.
• Automatic transmitter shutdown in case of an overcurrent or TxD-dominant timeout.
• Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive
Applications” v1.3.
The LIN/HV transmitter is a low-side MOSFET with current limitation and overcurrent transmitter
shutdown. A selectable internal pullup resistor with a serial diode structure is integrated, so no external
pullup components are required for the application in a slave node. To be used as a master node, an external
resistor of 1 k must be placed in parallel between VLINSUP and the LIN Bus pin, with a diode between
VLINSUP and the resistor. The fall time from recessive to dominant and the rise time from dominant to
recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions. The
symmetry between both slopes is guaranteed.
2. Normal Mode
The full functionality is available. Both receiver and transmitter are enabled.
3. Receive Only Mode
The transmitter is disabled and the receiver is running in full performance mode.
4. Standby Mode
The transmitter of the LIN/HV Physical Layer is disabled. If the wake-up feature is enabled, the
internal pullup resistor can be selected (330 k or 34 k). The receiver enters a low power mode
and optionally it can pass wake-up events to the Serial Communication Interface (SCI). If the
wake-up feature is enabled and if the LIN Bus pin is driven with a dominant level longer than
tWUFR followed by a rising edge, the LIN/HV Physical Layer sends a wake-up pulse to the SCI,
which requests a wake-up interrupt. (This feature is only available if the LIN/HV Physical Layer
is routed to the SCI).
+
*,
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!
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**
#
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NOTE
The external 220 pF capacitance between LIN and LGND is strongly
recommended for correct operation.
NOTE
Register Address = Module Base Address + Address Offset, where the
Module Base Address is defined at the MCU level and the Address Offset
is defined at the module level.
Address Offset
Bit 7 6 5 4 3 2 1 Bit 0
Register Name
0x0000 R 0 0 0 0 0 0 LPDR0
LPDR1
LPDR W
0x0001 R 0 0 0 0
LPE RXONLY LPWUE LPPUE
LPCR W
0x0002 R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved W
0x0003 R 0 0 0 0 0
LPDTDIS LPSLR1 LPSLR0
LPSLRM W
0x0004 R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved W
0x0005 R LPDT 0 0 0 0 0 0 0
LPSR W
0x0006 R 0 0 0 0 0 0
LPDTIE LPOCIE
LPIE W
0x0007 R 0 0 0 0 0 0
LPDTIF LPOCIF
LPIF W
Write: Anytime
Field Description
1 Port LP Data Bit 1 — The LPTxD input of the LIN/HV Physical Layer (see Figure 19-1) can be directly controlled
LPDR1 by this register bit. The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to
the device PIM description for more info.In the HV Phy version, this bit can be use to send diagnostic feedback.
0 Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time.
LPDR0
Write: Anytime,
Field Description
3 LIN Enable Bit — If set, this bit enables the LIN Physical Layer.
LPE 0 The LIN Physical Layer is in shutdown mode. None of the LIN Physical Layer functions are available, except
that the bus line is held in its recessive state by a high ohmic (330k) resistor. All registers are normally
accessible.
1 The LIN Physical Layer is not in shutdown mode.
2 Receive Only Mode bit — This bit controls RXONLY mode.
RXONLY 0 The LIN Physical Layer is not in receive only mode.
1 The LIN Physical Layer is in receive only mode.
1 LIN Wake-Up Enable — This bit controls the wake-up feature in standby mode.
LPWUE 0 In standby mode the wake-up feature is disabled.
1 In standby mode the wake-up feature is enabled.
0 LIN Pullup Resistor Enable — Selects pullup resistor.
LPPUE 0 The pullup resistor is high ohmic (330 k).
1 The 34 kpullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
mode can alter the module’s functionality.
Table 19-4. Reserved Register Field Description
Field Description
7-0 These reserved bits are used for test purposes. Writing to these bits can alter the module functionality.
Reserved
Field Description
7 TxD-dominant timeout disable Bit — This bit disables the TxD-dominant timeout feature. Disabling this feature
LPDTDIS is only recommended for using the LIN Physical Layer for other applications than LIN protocol. It is only writable
in shutdown mode (LPE=0).
0 TxD-dominant timeout feature is enabled.
1 TxD-dominant timeout feature is disabled.
1-0 Slew-Rate Bits — Please see section 19.4.2 for details on how the slew rate control works. These bits are only
LPSLR[1:0] writable in shutdown mode (LPE=0).
00 Normal Slew Rate (optimized for 20 kbit/s).
01 Slow Slew Rate (optimized for 10.4 kbit/s).
10 Fast Mode Slew Rate (up to 250 kbit/s). This mode is not compliant with the LIN Protocol (LIN electrical
characteristics like duty cycles, reference levels, etc. are not fulfilled). It is only meant to be used for fast data
transmission. Please refer to section 19.4.2.2 for more details on fast mode.Please note that an external
pullup resistor stronger than 1 k might be necessary for the range 100 kbit/s to 250 kbit/s.
11 Reserved .
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
mode can alter the module’s functionality.
Table 19-6. Reserved Register Field Description
Field Description
7-0 These reserved bits are used for test purposes. Writing to these bits can alter the module functionality.
Reserved
1. Read: Anytime
Field Description
7 LIN Transmitter TxD-dominant timeout Status Bit — This read-only bit signals that the LPTxD pin is still
LPDT dominant after a TxD-dominant timeout. As long as the LPTxD is dominant after the timeout the LIN transmitter
is shut down and the LPTDIF is set again after attempting to clear it.
0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout.
1 LPTxD is still dominant after a TxD-dominant timeout.
1. Read: Anytime
Write: Anytime
Field Description
Write: Writing ‘1’ clears the flags, writing a ‘0’ has no effect
Field Description
7 LIN Transmitter TxD-dominant timeout Interrupt Flag — LPDTIF is set to 1 when LPTxD is still dominant (0)
LPDTIF after tTDLIM of the falling edge of LPTxD. For protection, the transmitter is disabled. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPDTIF=1 before trying to clear it.
Clearing LPDTIF is not allowed if LPDTIF=0 already. If the LPTxD is still dominant after clearing the flag, the
transmitter stays disabled and this flag is set again (see 19.4.4.2 TxD-dominant timeout Interrupt).
If interrupt requests are enabled (LPDTIE= 1), LPDTIF causes an interrupt request.
0 No TxD-dominant timeout has occurred.
1 A TxD-dominant timeout has occurred.
6 LIN Transmitter Overcurrent Interrupt Flag — LPOCIF is set to 1 when an overcurrent event happens. For
LPOCIF protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
Please make sure that LPOCIF=1 before trying to clear it. Clearing LPOCIF is not allowed if LPOCIF=0 already.
If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and
this flag is set again (see19.4.4.1 Overcurrent Interrupt).
If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request.
0 No overcurrent event has occurred.
1 Overcurrent event has occurred.
19.4.1 General
The LIN/HV Physical Layer module implements the physical layer of the LIN/HV interface. In the LIN
version, this physical layer can be driven by the SCI (Serial Communication Interface) module or directly
through the LPDR register.In the HV Phy version, the input can be routed to an internal timer to measure
the frequency and duty cycle of the PWM input signal. If required, the output can directly be controlled
by the LPDR register, e.g. to send diagnostic feedback.
19.4.3 Modes
Figure 19-11 shows the possible mode transitions depending on control bits, stop mode, and error
conditions.
If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical
properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the
wake-up feature is not needed.
If LPWUE is set, the receiver is able to pass wake-up events to the SCI (Serial Communication Interface).
If the LIN/HV Physical Layer receives a dominant level longer than tWUFR followed by a rising edge, it
sends a pulse to the SCI which can generate a wake-up interrupt.
Once the device exits stop mode, the LIN/HV Physical Layer returns to normal or receive only mode
depending on the status of the RXONLY bit.
NOTE
Since the wake-up interrupt is requested by the SCI, the wake-up feature is
not available if LPRxD is not connected to the SCI..
The internal pullup resistor is selectable only if LPWUE = 1 (wake-up enabled). If LPWUE = 0, the
internal pullup resistor is not selectable and remains at 330 k regardless of the state of the LPPUE bit.
If LPWUE = 1, selecting the 330 k pullup resistor (LPPUE = 0) reduces the current consumption in
standby mode.
NOTE
The use of the LIN wake-up feature in combination with other non-LIN
device wake-up features (like a periodic time interrupt) must be handled
with care.
If the device leaves stop mode while the LIN bus is dominant, the LIN/HV
Physical Layer returns to normal or receive only mode and the LPRxD
signal is re-routed to the RxD pin of the SCI and triggers the edge detection
interrupt (if the interrupt’s priority of the hardware that awakes the MCU is
less than the priority of the SCI interrupt, then the SCI interrupt will execute
first). It is up to the software to decide what to do in this case because the
LIN/HV Physical Layer may not determine whether it was a valid wake-up
pulse.
&
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!
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#
#
#
#
"!
"!
#$"!
19.4.4 Interrupts
The interrupt vector requested by the LIN/HV Physical Layer is listed in Table 19-10. Vector address and
interrupt priority is defined at the MCU level.
The module internal interrupt sources are combined into a single interrupt request at the device level.
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To protect the LIN bus from a network lock-up, the LIN Physical Layer implements a TxD-dominant
timeout mechanism. When the LPTxD signal has been dominant for more than tDTLIM the transmitter is
disabled and the LPDT status flag and the LPDTIF interrupt flag are set.
In order to re-enable the transmitter again, the following prerequisites must be met:
1) TxD-dominant condition is over (LPDT=0)
2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a
minimum of a transmit bit time
To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1).
NOTE
Please make sure that LPDTIF=1 before trying to clear it. It is not allowed
to try to clear LPDTIF if LPDTIF=0 already.
After clearing LPDTIF, if the TxD-dominant timeout condition is still present or the LPTxD pin is
dominant while being in normal mode, the transmitter remains disabled and the LPDTIF flag is set after a
time again to indicate that the attempt to re-enable has failed. This time is equal to:
• minimum 1 IRC period (1 us) + 2 bus periods
• maximum 2 IRC periods (2 us) + 3 bus periods
If the bit LPDTIE is set in the LPIE register, an interrupt is requested.
Figure 19-13 shows the different scenarios of TxD-dominant timeout interrupt handling.
!
"!
!
!
#
!
"!
!
!
"!
— If the receiver must remain enabled, set the LIN/HV Physical Layer into receive only mode
instead.
2. Do all required configurations (SCI, etc.) to re-enable the transmission.
3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter).
4. Clear the error flag.
5. Enable the interrupts again (LPDTIE and LPOCIE).
6. Enable the LIN/HV Physical Layer or leave the receive only mode (LPCR register).
7. Wait for a minimum of a transmit bit before beginning transmission again.
If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the
ISR will be called again.
20.1 Introduction
The P-Flash (Program Flash) and EEPROM memory sizes are specified at device level (Reference Manual
device overview chapter). The description in the following sections is valid for all P-Flash and EEPROM
memory sizes.
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents. The user interface to the
memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is
written to with the command, global address, data, and any required command parameters. The memory
controller must complete the execution of a command before the FCCOB register can be written to with a
new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
20.1.1 Glossary
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data.
EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be
erased. The EEPROM sector consists of 4 bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two
sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double
bit fault detection within each double word.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 512 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version
ID, and the Program Once field.
20.1.2 Features
Figure 20-1. FTMRZ Block Diagram (Single P-Flash Block plus EEPROM block)
Flash
Interface
Command Registers
16bit
Interrupt internal
Request P-Flash
bus
Error sector 0
Interrupt Protection sector 1
Request
final sector
Security
Bus
Clock Clock
Divider FCLK
Memory Controller
CPU
EEPROM
sector 0
sector 1
final sector
Table 20-2. FTMRZ Block Diagram (Two P-Flash blocks plus EEPROM block)
Flash
Interface
Command Registers
16bit
Interrupt internal
Request P-Flash
bus
Error sector 0
Interrupt Protection sector 1
Request
final sector
Security
HardBlock-0S
Bus
Clock Clock
Divider FCLK
Memory Controller
CPU
EEPROM
P-Flash
sector 0 sector 0
sector 1 sector 1
HardBlock-0N (P-Flash+EEPROM)
The FPROT register, described in Section 20.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address
0xFF_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable
regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the
boot loader code since it covers the vector space. Default protection settings as well as security information
that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as
described in Table 20-4.
Table 20-4. Flash Configuration Field
Size
Global Address Description
(Bytes)
P-Flash START
0xFF_8000
0xFF_8400
0xFF_8800
0xFF_9000 Flash Protected/Unprotected Lower Region
1, 2, 4, 8 KB
Protection
Fixed End
0xFF_A000
0xFF_C000
Protection
Fixed End
0xFF_F000
0xFF_F800
Flash Configuration Field
P-Flash END = 0xFF_FFFF 16 bytes (0xFF_FE00 - 0xFF_FE0F)
Size
Global Address Field Description
(Bytes)
Size
Global Address Description
(Bytes)
0x1F_4000
Reserved 512 bytes
0x1F_41FF
0x1F_8000
Reserved 6 KB
0x1F_97FF
Reserved 10 KB
0x1F_C000
P-Flash IFR 256 bytes
0x1F_C100
Reserved 16,128 bytes
Figure 20-3. Memory Controller Resource Memory Map (NVM Resources Area)
Address
7 6 5 4 3 2 1 0
& Name
0x0000 R FDIVLD
FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
FCLKDIV W
0x0002 R 0 0 0 0 0
CCOBIX2 CCOBIX1 CCOBIX0
FCCOBIX W
Address
7 6 5 4 3 2 1 0
& Name
0x0004 R 0 ERSAREQ
CCIE IGNSF WSTAT[1:0] FDFD FSFD
FCNFG W
0x0005 R 0 0 0 0 0 0 0
SFDIE
FERCNFG W
0x0007 R 0 0 0 0 0 0
DFDF SFDIF
FERSTAT W
0x0008 R RNV6
FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
FPROT W
0x0009 R
DPOPEN DPS6 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0
DFPROT(1) W
0x000B R 0 0 0 0 0 0 0 0
FRSV1 W
0x000C R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB0HI W
0x000D R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB0LO W
0x000E R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB1HI W
0x000F R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB1LO W
0x0010 R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB2HI W
Address
7 6 5 4 3 2 1 0
& Name
0x0011 R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB2LO W
0x0012 R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB3HI W
0x0013 R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB3LO W
0x0014 R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB4HI W
0x0015 R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB4LO W
0x0016 R
CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
FCCOB5HI W
0x0017 R
CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
FCCOB5LO W
= Unimplemented or Reserved
7 6 5 4 3 2 1 0
R FDIVLD
FDIVLCK FDIV[5:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 20-7. FCLKDIV Field Descriptions
Field Description
7 6 5 4 3 2 1 0
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0xFF_FE0F located in P-Flash memory (see Table 20-4) as
indicated by reset condition F in Figure 20-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set
to leave the Flash module in a secured state with backdoor key access disabled.
Field Description
7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 20-10.
5–2 Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
RNV[5:2]
1–0 Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 20-11. If the
SEC[1:0] Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
CCOBIX[2:0]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Field Description
2–0 Common Command Register Index— The CCOBIX bits are used to indicate how many words of the FCCOB
CCOBIX[1:0] register array are being read or written to. See Section 20.3.2.13, “Flash Common Command Object Registers
(FCCOB)“,” for more details.
7 6 5 4 3 2 1 0
R FPOVRD 0 0 0 0 0 0 WSTATACK
W
Reset 0 0 0 0 0 0 0 1
= Unimplemented or Reserved
All bits in the FPSTAT register are readable but are not writable.
Table 20-13. FPSTAT Field Descriptions
Field Description
7 Flash Protection Override Status — The FPOVRD bit indicates if the Protection Override feature is currently
FPOVRD enabled. See Section 20.4.7.17, “Protection Override Command” for more details.
0 Protection is not overridden
1 Protection is overridden, contents of registers FPROT and/or DFPROT (and effective protection limits
determined by their current contents) were determined during execution of command Protection Override
0 Wait-State Switch Acknowledge — The WSTATACK bit indicates that the wait-state configuration is
WSTATACK effectively set according to the value configured on bits FCNFG[WSTAT] (see Section 20.3.2.5, “Flash
Configuration Register (FCNFG)”). WSTATACK bit is cleared when a change in FCNFG[WSTAT] is requested
by writing to those bits, and is set when the Flash has effectively switched to the new wait-state configuration.
The application must check the status of WSTATACK bit to make sure it reads as 1 before changing the
frequency setup (see Section 20.4.3, “Flash Block Read Access”).
0 Wait-State switch is pending, Flash reads are still happening according to the previous value of
FCNFG[WSTAT]
1 Wait-State switch is complete, Flash reads are already working according to the value set on
FCNFG[WSTAT]
7 6 5 4 3 2 1 0
R 0 ERSAREQ
CCIE IGNSF WSTAT[1:0] FDFD FSFD
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and
remaining bits read 0 and are not writable.
Table 20-14. FCNFG Field Descriptions
Field Description
7 Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
CCIE has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 20.3.2.7)
5 Erase All Request — Requests the Memory Controller to execute the Erase All Blocks command and release
ERSAREQ security. ERSAREQ is not directly writable but is under indirect user control. Refer to the Reference Manual for
assertion of the soc_erase_all_req input to the FTMRZ module.
0 No request or request complete
1 Request to:
a) run the Erase All Blocks command
b) verify the erased state
c) program the security byte in the Flash Configuration Field to the unsecure state
d) release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in
Table 20-9 of Section 20.3.2.2.
The ERSAREQ bit sets to 1 when soc_erase_all_req is asserted, CCIF=1 and the Memory Controller starts
executing the sequence. ERSAREQ will be reset to 0 by the Memory Controller when the operation is completed
(see Section 20.4.7.7.1).
4 Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
IGNSF Section 20.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
3–2 Wait State control bits — The WSTAT[1:0] bits define how many wait-states are inserted on each read access
WSTAT[1:0] to the Flash as shown on Table 20-15.Right after reset the maximum amount of wait-states is set, to be later re-
configured by the application if needed. Depending on the system operating frequency being used the number
of wait-states can be reduced or disabled, please refer to the Data Sheet for details. For additional information
regarding the procedure to change this configuration please see Section 20.4.3. The WSTAT[1:0] bits should not
be updated while the Flash is executing a command (CCIF=0); if that happens the value of this field will not
change and no action will take place.
Field Description
1 Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
FDFD read operations. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDF flag in the FERSTAT register to be set (see
Section 20.3.2.7)
0 Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
FSFD read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 20.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 20.3.2.6)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
SFDIE
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
All assigned bits in the FERCNFG register are readable and writable.
Field Description
0 Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
SFDIE is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 20.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 20.3.2.8)
7 6 5 4 3 2 1 0
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Table 20-17. FSTAT Field Descriptions
Field Description
7 Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5 Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
ACCERR caused by either a violation of the command write sequence (see Section 20.4.5.2) or issuing an illegal Flash
command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is
cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4 Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
FPVIOL address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL
bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3 Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
MGBUSY 0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Field Description
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DFDF SFDIF
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
All flags in the FERSTAT register are readable and only writable to clear the flag.
Table 20-18. FERSTAT Field Descriptions
Field Description
1 Double Bit Fault Detect Flag — The setting of the DFDF flag indicates that a double bit fault was detected in
DFDF the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning
invalid data was attempted on a Flash block that was under a Flash command operation.(1) The DFDF flag is
cleared by writing a 1 to DFDF. Writing a 0 to DFDF has no effect on DFDF.(2)
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
running. See Section 20.4.3, “Flash Block Read Access” for details
0 Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
SFDIF indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
while command running
1. In case of ECC errors the corresponding flag must be cleared for the proper setting of any further error, i.e. any new error will
only be indicated properly when DFDF and/or SFDIF are clear at the time the error condition is detected.
2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required after
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
7 6 5 4 3 2 1 0
R RNV6
FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0]
W
Reset F(1) F1 F1 F1 F1 F1 F1 F1
= Unimplemented or Reserved
The (unreserved) bits of the FPROT register are writable Normal Single Chip Mode with the restriction
that the size of the protected region can only be increased see Section 20.3.2.9.1, “P-Flash Protection
Restrictions,” and Table 20-23). All (unreserved) bits of the FPROT register are writable without
restriction in Special Single Chip Mode.
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0xFF_FE0C located in P-Flash memory (see Table 20-4)
as indicated by reset condition ‘F’ in Figure 20-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if
any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 20-19. FPROT Field Descriptions
Field Description
7 Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
FPOPEN erase operations as shown in Table 20-20 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6 Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
RNV[6]
5 Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
FPHDIS protected/unprotected area in a specific region of the P-Flash memory ending with global address 0xFF_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3 Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
FPHS[1:0] in P-Flash memory as shown inTable 20-21. The FPHS bits can only be written to while the FPHDIS bit is set.
Field Description
2 Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
FPLDIS protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0xFF_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
1–0 Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
FPLS[1:0] in P-Flash memory as shown in Table 20-22. The FPLS bits can only be written to while the FPLDIS bit is set.
All possible P-Flash protection scenarios are shown in Figure 20-14 . Although the protection scheme is
loaded from the Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in
normal single chip mode while providing as much protection as possible if reprogramming is not required.
FPOPEN = 1
FPLS[1:0]
0xFF_8000
FPHS[1:0]
0xFF_FFFF
Scenario 3 2 1 0
FLASH START
FPOPEN = 0
FPLS[1:0]
0xFF_8000
FPHS[1:0]
0xFF_FFFF
0 X X X X
1 X X
2 X X
3 X
4 X X
5 X X X X
6 X X X X
7 X X X X X X X X
1. Allowed transitions marked with X, see Figure 20-14 for a definition of the scenarios.
7 6 5 4 3 2 1 0
R
DPOPEN DPS[6:0](1)
W
Reset F(2) F2 F2 F2 F2 F2 F2 F2
= Unimplemented or Reserved
The (unreserved) bits of the DFPROT register are writable in Normal Single Chip mode with the
restriction that protection can be added but not removed. Writes in Normal Single Chip mode must
increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0
(protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. All DPOPEN/DPS
bit registers are writable without restriction in Special Single Chip Mode.
During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in
P-Flash memory (see Table 20-4) as indicated by reset condition F in Table 20-25. To change the
EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the
EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte
during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM
memory fully protected.
Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible
if any of the EEPROM sectors are protected.
Table 20-24. DFPROT Field Descriptions
Field Description
The number of DPS bits depends on the size of the implemented EEPROM. The whole implemented
EEPROM range can always be protected. Each DPS value increment increases the size of the protected
range by 32-bytes. Thus to protect a 1 KB range DPS[4:0] must be set (protected range of 32 x 32 bytes).
7 6 5 4 3 2 1 0
R
NV[7:0]
W
Reset F(1) F1 F1 F1 F1 F1 F1 F1
= Unimplemented or Reserved
All bits in the FOPT register are readable but can only be written in special mode.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0xFF_FE0E located in P-Flash memory (see Table 20-4) as indicated
by reset condition F in Figure 20-16. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 20-26. FOPT Field Descriptions
Field Description
7–0 Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device overview for proper
NV[7:0] use of the NV bits.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
All bits in the FRSV1 register read 0 and are not writable.
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[15:8]
W
Reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
R
CCOB[7:0]
W
Reset 0 0 0 0 0 0 0 0
HI Data 1 [15:8]
011 FCCOB3
LO Data 1 [7:0]
HI Data 2 [15:8]
100 FCCOB4
LO Data 2 [7:0]
HI Data 3 [15:8]
101 FCCOB5
LO Data 3 [7:0]
[15:4] [3:0]
Reserved VERNUM
• VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111
meaning ‘none’.
into the Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 20.3.2.5)
has effect only on the DFDF status bit value and does not result in an invalid access.
To guarantee the proper read timing from the Flash array, the Flash will control (i.e. pause) the S12Z core
accesses, considering that the MCU can be configured to fetch data at a faster frequency than the Flash
block can support. Right after reset the Flash will be configured to run with the maximum amount of wait-
states enabled; if the user application is setup to run at a slower frequency the control bits
FCNFG[WSTAT] (see Section 20.3.2.5) can be configured by the user to disable the generation of wait-
states, so it does not impose a performance penalty to the system if the read timing of the S12Z core is
setup to be within the margins of the Flash block. For a definition of the frequency values where wait-states
can be disabled please refer to the device electrical parameters.
The following sequence must be followed when the transition from a higher frequency to a lower
frequency is going to happen:
• Flash resets with wait-states enabled;
• system frequency must be configured to the lower target;
• user writes to FNCNF[WSTAT] to disable wait-states;
• user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective
when it reads as 1;
• user must re-write FCLKDIV to set a new value based on the lower frequency.
The following sequence must be followed on the contrary direction, going from a lower frequency to a
higher frequency:
• user writes to FCNFG[WSTAT] to enable wait-states;
• user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective
when it reads as 1;
• user must re-write FCLKDIV to set a new value based on the higher frequency;
• system frequency must be set to the upper target.
CAUTION
If the application is going to require the frequency setup to change, the value
to be loaded on register FCLKDIV will have to be updated according to the
new frequency value. In this scenario the application must take care to avoid
locking the value of the FCLKDIV register: bit FDIVLCK must not be set
if the value to be loaded on FDIV is going to be re-written, otherwise a reset
is going to be required. Please refer to Section 20.3.2.1, “Flash Clock
Divider Register (FCLKDIV) and Section 20.4.5.1, “Writing the FCLKDIV
Register.
START
no
CCIF
Set?
yes
More yes
Parameters?
no
EXIT
Unsecured Secured
FCMD Command
NS NS
(1) SS(2) (3) SS(4)
Table 20-32. Allowed P-Flash and EEPROM Simultaneous Operations on a single hardblock
EEPROM
Read OK(1) OK OK OK
Margin Read(2)
Program
Sector Erase
Mass Erase(3) OK
1. Strictly speaking, only one read of either the P-Flash or EEPROM can occur
at any given instant, but the memory controller will transparently arbitrate P-
Flash and EEPROM accesses giving uninterrupted read access whenever
possible.
2. A ‘Margin Read’ is any read after executing the margin setting commands ‘Set
User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’
level specified. See the Note on margin settings in Section 20.4.7.12 and
Section 20.4.7.13.
3. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase
Flash Block’
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will
be set.
Table 20-34. Erase Verify All Blocks Command Error Handling
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be
set.
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT
bits will be set.
Table 20-38. Erase Verify P-Flash Section Command Error Handling
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block will return invalid data.
8
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
Table 20-42. Program P-Flash Command Error Handling
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash will return invalid data.
Table 20-44. Program Once Command Error Handling
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
ACCERR Set if command not available in current mode (see Table 20-29)
Set if any errors have been encountered during the erase verify operation, or
MGSTAT1
FSTAT during the program verify operation
Set if any non-correctable errors have been encountered during the erase verify
MGSTAT0
operation, or during the program verify operation
Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the
selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block
operation has completed.
Table 20-49. Erase Flash Block Command Error Handling
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that
the entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
Table 20-53. Unsecure Flash Command Error Handling
4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 20-54. Verify Backdoor Access Key Command FCCOB Requirements
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0xFF_FE00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
Table 20-55. Verify Backdoor Access Key Command Error Handling
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
NOTE
When the EEPROM block is targeted, the EEPROM user margin levels are
applied only to the EEPROM reads. However, when the P-Flash block is
targeted, the P-Flash user margin levels are applied to both P-Flash and
EEPROM reads. It is not possible to apply user margin levels to the P-Flash
block only.
Valid margin level settings for the Set User Margin Level command are defined in Table 20-57.
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
NOTE
When the EEPROM block is targeted, the EEPROM field margin levels are
applied only to the EEPROM reads. However, when the P-Flash block is
targeted, the P-Flash field margin levels are applied to both P-Flash and
EEPROM reads. It is not possible to apply field margin levels to the P-Flash
block only.
Valid margin level settings for the Set Field Margin Level command are defined in Table 20-60.
Table 20-60. Valid Set Field Margin Level Settings
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will
verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify
EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both
MGSTAT bits will be set.
Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be
transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index
value at Program EEPROM command launch determines how many words will be programmed in the
EEPROM block. The CCIF flag is set when the operation has completed.
Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector
operation has completed.
Table 20-67. Erase EEPROM Sector Command Error Handling
Protection Update
Protection register selection
Selection code [1:0]
If the comparison key successfully matches the key programmed in the Flash Configuration Field the
Protection Override command will preserve the current values of registers FPROT and DFPROT stored in
an internal area and will override these registers as selected by the Protection Update Selection field with
the value(s) loaded on FCCOB parameters. The new values loaded into FPROT and/or DFPROT can
reconfigure protection without any restriction (by increasing, decreasing or disabling protection limits). If
the command executes successfully the FPSTAT FPOVRD bit will set.
If the comparison key does not match the key programmed in the Flash Configuration Field, or if the key
loaded on FCCOB is 16’hFFFF, the value of registers FPROT and DFPROT will be restored to their
original contents before executing the Protection Override command and the FPSTAT FPOVRD bit will
be cleared. If the contents of the Protection Override Comparison Key in the Flash Configuration Field is
left in the erased state (i.e. 16’hFFFF) the Protection Override feature is permanently disabled. If the
command execution is flagged as an error (ACCERR being set for incorrect command launch) the values
of FPROT and DFPROT will not be modified.
The Protection Override command can be called multiple times and every time it is launched it will
preserve the current values of registers FPROT and DFPROT in a single-entry buffer to be restored later;
when the Protection Override command is launched to restore FPROT and DFPROT these registers will
assume the values they had before executing the Protection Override command on the last time. If contents
of FPROT and/or DFPROT registers were modified by direct register writes while protection is overridden
these modifications will be lost. Running Protection Override command to restore the contents of registers
FPROT and DFPROT will not force them to the reset values.
FSTAT Set if Protection Update Selection[1:0] = 00 (in case of CCOBIX[2:0] = 010 or 011)
Set if Protection Update Selection[1:0] = 00, CCOBIX[2:0] = 001 and a valid
comparison key is loaded as a command parameter.
FPVIOL None
MGSTAT1 None
MGSTAT0 None
20.4.8 Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
Table 20-71. Flash Interrupt Sources
Global (CCR)
Interrupt Source Interrupt Flag Local Enable
Mask
Flash Command Complete CCIF CCIE I Bit
(FSTAT register) (FCNFG register)
ECC Single Bit Fault on Flash Read SFDIF SFDIE I Bit
(FERSTAT register) (FERCNFG register)
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
20.5 Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 20-11). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address
0xFF_FE0F. The security state out of reset can be permanently changed by programming the security byte
assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands
are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is
successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM
A secured MCU can be unsecured in special single chip mode using an automated procedure described in
Section 20.4.7.7.1, “Erase All Pin”.
20.6 Initialization
On each system reset the flash module executes an initialization sequence which establishes initial values
for the Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the
FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module
in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a
double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a
portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the
initialization sequence is marked by setting CCIF high which enables user commands.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
Revision Sections
Revision Date Description of Changes
Number Affected
NOTE
The information given in this section are preliminary and should be used as
a guide only. Values in this section cannot be guaranteed and are subject to
change without notice.
21.1 Introduction
The CAN Physical Layer provides a physical layer for high speed CAN area network communication in
automotive applications. It serves as an integrated interface to the CAN bus lines for the internally
connected MSCAN controller through the pins CANH, CANL and SPLIT.
The CAN Physical Layer is designed to meet the CAN Physical Layer ISO 11898-2 and ISO 11898-5
standards.
21.1.1 Features
The CAN Physical Layer module includes these distinctive features:
• High speed CAN interface for baud rates of up to 1 Mbit/s
• ISO 11898-2 and ISO 11898-5 compliant for 12 V battery systems
• SPLIT pin driver for bus recessive level stabilization
• Low power mode with remote CAN wake-up handled by MSCAN module
• Configurable wake-up pulse filtering
• Over-current shutdown for CANH and CANL
• Voltage monitoring on CANH and CANL
• CPTXD-dominant timeout feature monitoring the CPTXD signal
• Fulfills the OEM “Hardware Requirements for (LIN,) CAN (and FlexRay) Interfaces in
Automotive Applications” v1.3
Interrupt VDDC
Generation CHOCIF
CPDTIF
Time
CPTXD out
CHVHIF Status CHVH 5V
Change
Normal/Shutdown/ SPE
CAN BUS
0
Wake-up
intern. Standby mode SPLIT
Wake-up
CPRXD Filter
mid
Receiver
point 2.5V
1 high-z CANL
Standby 0V
Mode
Standby
Mode
CLVLIF Status CLVL
Change
0V
CLOCIF
VSSC
Name Function
CANH CAN Bus High Pin
SPLIT 2.5 V Termination Pin
CANL CAN Bus Low Pin
VDDC Supply Pin for CAN Physical Layer
VSSC Ground Pin for CAN Physical Layer
Address Register
Bit 7 6 5 4 3 2 1 Bit 0
Offset Name
R CPDR7 0 0 0 0 0 CPDR0
0x0000 CPDR CPDR1
W
R 0
0x0001 CPCR CPE SPE WUPE1-0 SLR2-0
W
R
0x0002 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x0004 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x0005 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R 0 0 0 0 0
0x0006 CPIE CPVFIE CPDTIE CPOCIE
W
R 0
0x0007 CPIF CHVHIF CHVLIF CLVHIF CLVLIF CPDTIF CHOCIF CLOCIF
W
= Unimplemented or Reserved
Field Description
Field Description
NOTE
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
Field Description
Field Description
7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
NOTE
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
Reset x x x x x x x x
NOTE
This reserved register is designed for factory test purposes only and is not
intended for general user access. Writing to this register when in special
modes can alter the modules functionality.
Field Description
If any of the flags is asserted an error interrupt is pending if enabled. A flag can be cleared by writing a
logic level 1 to the corresponding bit location. Writing a 0 has no effect.
Field Description
0 No change in CPCHVH
1 CPCHVH has changed
6 CANH Voltage Failure Low Interrupt Flag
CHVLIF This flag is set to 1 when the CPCHVL bit in the CAN Physical Layer Status Register (CPSR) changes.
0 No change in CPCHVL
1 CPCHVL has changed
Field Description
0 No change in CPCLVH
1 CPCLVH has changed
4 CANL Voltage Failure Low Interrupt Flag
CLVLIF This flag is set to 1 when the CPCLVL bit in the CAN Physical Layer Status Register (CPSR) changes.
0 No change in CPCLVL
1 CPCLVL has changed
3 CAN CPTXD-Dominant Timeout Interrupt Flag
CPDTIF This flag is set to 1 when CPTXD is dominant longer than tCPTXDDT. It signals a timeout event and entry of
listen-only mode disabling the transmitter.
Exit of listen-only mode which was entered at timeout is requested by clearing CPDTIF when CPDT is clear after
setting CPTXD to recessive state. It takes 1 to 2 s to return to normal mode.
If CPTXD is dominant or dominant timeout status is still active (CPDT=1) when clearing the flag, the CAN
Physical Layer remains in listen-only mode and this flag is set again after a delay (see 21.5.4.2, “CPTXD-
Dominant Timeout Interrupt”).
21.5.1 General
The CAN Physical Layer provides an interface for the SoC-integrated MSCAN controller.
21.5.2 Modes
Figure 21-10 shows the possible mode transitions depending on control bit CPE, device reduced
performance mode (“RPM”; refer to “Low Power Modes” section in device overview) and bus error
conditions.
Reset
Shutdown
TRM: Off, REC: Off, WUP: Off TRM: Transmitter
REC: Receiver
CANH,CANL: 30Kterm. to VSSC WUP: Wake-up receiver
SPLIT: High-impedance RPM: Reduced performance mode
Normal A Listen-only
TRM: On, REC: On, WUP: WUPE TRM: Off, REC: On, WUP: WUPE
CANH, CANL: Driver on A & CPCLVL CANH, CANL: Driver off
SPLIT: SPE & CPTXD=1 SPLIT: SPE
A & CPCLVL
RPM & CPTXD=1
CPCLVL CPCLVL RPM RPM & A
Pseudo-Normal Standby
RPM
TRM: On, REC: On, WUP: WUPE TRM: Off, REC: Off, WUP: WUPE
CANH: Driver on, CANL: Driver off CANH,CANL: 30K term. to VSSC
SPLIT: SPE RPM & A & CPCLVL SPLIT: High-impedance
to VSSC via high-ohmic input resistors of the receiver. The SPLIT pin as well as the internal mid-point
reference are set to high-impedance.
Shutdown mode cannot be re-entered until reset.
Case A: CPRXD
(CPCR[WUPE]=b00)
Case B: CPRXD
(CPCR[WUPE]=b10)
Case C: CPRXD
(CPCR [WUPE]=b01)
Case D: CPRXD
(CPCR [WUPE]=b11)
MSCAN Wake-up
(CANCTL0[WUPE]=1
& CANCTL1[WUPM]=1) B C D
MSCAN wake-up pulse specification: tWUP tWUP tWUP
21.5.4 Interrupts
This section describes the interrupt generated by the CAN Physical Layer and its individual sources.
Vector addresses and interrupt priorities are defined at MCU level. The module internal interrupt sources
are combined (OR-ed) into one module interrupt output CPI with a single local enable bit each for voltage
failure and over-current errors.
condition instantaneously disappears as soon as the transmit driver is automatically being turned off. This
state is locked and the application software must account for re-enabling the driver.
The recommended procedure to handle an over-current related bus error is:
1. On interrupt abort any scheduled transmissions
2. Read interrupt flag register to determine over-current source(s)
3. Clear related interrupt flag(s)
4. Retry CAN transmission
5. On interrupt abort any scheduled transmissions
6. Read interrupt flag register to determine over-current source(s)
7. If the same over-current error persists do not retry and run appropriate custom diagnostics
Revision Sections
Revision Date Description of Changes
Number Affected
v02.00 Feb. 20, 2009 All Initial revision of scalable PWM. Started from pwm_8b8c (v01.08).
22.1 Introduction
The Version 2 of S12 PWM module is a channel scalable and optimized implementation of S12
PWM8B8C Version 1. The channel is scalable in pairs from PWM0 to PWM7 and the available channel
number is 2, 4, 6 and 8. The shutdown feature has been removed and the flexibility to select one of four
clock sources per channel has improved. If the corresponding channels exist and shutdown feature is not
used, the Version 2 is fully software compatible to Version 1.
22.1.1 Features
The scalable PWM block includes these distinctive features:
• Up to eight independent PWM channels, scalable in pairs (PWM0 to PWM7)
• Available channel number could be 2, 4, 6, 8 (refer to device specification for exact number)
• Programmable period and duty cycle for each channel
• Dedicated counter for each PWM channel
• Programmable PWM enable/disable for each channel
• Software selection of PWM duty pulse polarity for each channel
• Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches zero) or when the channel is disabled.
• Programmable center or left aligned outputs on individual channels
• Up to eight 8-bit channel or four 16-bit channel PWM resolution
• Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
• Programmable clock select logic
In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is
useful for emulation.
Wait: The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1.
Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1.
Channel 6
PWM6
Period and Duty Counter
Clock PWM Clock
Clock Select
Channel 5
PWM5
Period and Duty Counter
Control
Channel 4
PWM4
Period and Duty Counter
Channel 3
PWM3
Enable Period and Duty Counter
Channel 2
Polarity PWM2
Period and Duty Counter
Alignment
Channel 1
PWM1
Period and Duty Counter
Channel 0
PWM0
Period and Duty Counter
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0000 R
PWME(1) PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
W
0x0001 R
PWMPOL1 PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
W
0x0002 R
PWMCLK1 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
0x0003 R 0 0
PWMPRCLK W PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0
0x0004 R
PWMCAE1 W CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
0x0005 R 0 0
PWMCTL1 CON67 CON45 CON23 CON01 PSWAI PFRZ
W
= Unimplemented or Reserved
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0006 R
PWMCLKAB W PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0
1
0x0007 R 0 0 0 0 0 0 0 0
RESERVED W
0x0008 R
PWMSCLA W Bit 7 6 5 4 3 2 1 Bit 0
0x0009 R
PWMSCLB W Bit 7 6 5 4 3 2 1 Bit 0
0x000A R 0 0 0 0 0 0 0 0
RESERVED W
0x000B R 0 0 0 0 0 0 0 0
RESERVED W
= Unimplemented or Reserved
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0014 R
PWMPER02 W Bit 7 6 5 4 3 2 1 Bit 0
0x0015 R
PWMPER12 W Bit 7 6 5 4 3 2 1 Bit 0
0x0016 R
PWMPER22 W Bit 7 6 5 4 3 2 1 Bit 0
0x0017 R
PWMPER32 W Bit 7 6 5 4 3 2 1 Bit 0
0x0018 R
PWMPER42 W Bit 7 6 5 4 3 2 1 Bit 0
0x0019 R
PWMPER52 W Bit 7 6 5 4 3 2 1 Bit 0
0x001A R
PWMPER62 W Bit 7 6 5 4 3 2 1 Bit 0
0x001B R
PWMPER72 W Bit 7 6 5 4 3 2 1 Bit 0
0x001C R
PWMDTY02 W Bit 7 6 5 4 3 2 1 Bit 0
0x001D R
PWMDTY12 W Bit 7 6 5 4 3 2 1 Bit 0
0x001E R
PWMDTY22 W Bit 7 6 5 4 3 2 1 Bit 0
0x001F R
PWMDTY32 W Bit 7 6 5 4 3 2 1 Bit 0
0x0010 R
PWMDTY42 W Bit 7 6 5 4 3 2 1 Bit 0
0x0021 R
PWMDTY52 W Bit 7 6 5 4 3 2 1 Bit 0
0x0022 R
PWMDTY62 W Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Register
Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0023 R
PWMDTY72 W Bit 7 6 5 4 3 2 1 Bit 0
0x0024 R 0 0 0 0 0 0 0 0
RESERVED W
0x0025 R 0 0 0 0 0 0 0 0
RESERVED W
0x0026 R 0 0 0 0 0 0 0 0
RESERVED W
0x0027 R 0 0 0 0 0 0 0 0
RESERVED W
= Unimplemented or Reserved
Read: Anytime
Write: Anytime
Table 22-2. PWME Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
Read: Anytime
Write: Anytime
NOTE
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
Table 22-3. PWMPOL Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
Read: Anytime
Write: Anytime
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
Field Description
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see Section 22.3.2.7, “PWM Clock A/B Select Register (PWMCLKAB)). For Channel
0, 1, 4, 5, the selection is shown in Table 22-5; For Channel 2, 3, 6, 7, the selection is shown in Table 22-6.
Table 22-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
PCLKAB[0,1,4,5] PCLK[0,1,4,5] Clock Source Selection
0 0 Clock A
0 1 Clock SA
1 0 Clock B
1 1 Clock SB
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Field Description
6–4 Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These
PCKB[2:0] three bits determine the rate of clock B, as shown in Table 22-8.
2–0 Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for all channels. These
PCKA[2:0] three bits determine the rate of clock A, as shown in Table 22-8.
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Field Description
Read: Anytime
Write: Anytime
There are up to four control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. If the corresponding channels do not exist on a particular derivative, then
writes to these bits have no effect and reads will return zeroes. When channels 6 and 7are concatenated,
channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are
concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels
2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel.
When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double
byte channel.
See Section 22.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM
Function.
NOTE
Change these bits only when both corresponding channels are disabled.
Field Description
Read: Anytime
Write: Anytime
NOTE
Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock
select is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Table 22-11. PWMCLK Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see Section 22.3.2.3,
“PWM Clock Select Register (PWMCLK)) and PCLKABx bits in PWMCLKAB as shown in Table 22-5
and Table 22-6.
Read: Anytime
Write: Anytime (causes the scale counter to load the PWMSCLA value)
Read: Anytime
Write: Anytime (causes the scale counter to load the PWMSCLB value).
Read: Anytime
Write: Anytime (any value written causes PWM counter to be reset to $00).
Read: Anytime
Write: Anytime
Read: Anytime
Write: Anytime
22.4.1.1 Prescale
The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze
mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze
mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation
in order to freeze the PWM. The input clock can also be disabled when all available PWM channels are
disabled (PWMEx-0 = 0). This is useful for reducing power by disabling the prescale counter.
Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock
A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value
selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The
value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK
register.
Clock A M Clock to
U PWM Ch 0
Clock A/2, A/4, A/6,....A/512 X
PCLK0 PCLKAB0
PCKA2
PCKA1
PCKA0
8-Bit Down Count = 1
Counter M Clock to
U PWM Ch 1
Load X
X PCLK2 PCLKAB2
M Clock to
U
2 4 8 16 32 64 128
PWM Ch 3
X
Prescaler Taps:
Divide by
PCLK3 PCLKAB3
Clock B
M Clock to
Clock B/2, B/4, B/6,....B/512 U PWM Ch 4
X
M PCLK4 PCLKAB4
8-Bit Down Count = 1
U Counter M Clock to
U PWM Ch 5
X Load X
PCLK6 PCLKAB6
Clock
PWME7-0
M Clock to
U PWM Ch 7
X
PCLK7 PCLKAB7
Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale
value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the
8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater
range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value
in the PWMSCLA register.
NOTE
Clock SA = Clock A / (2 * PWMSCLA)
When PWMSCLA = $00, PWMSCLA value is considered a full scale value
of 256. Clock A is thus divided by 512.
Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock
SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.
NOTE
Clock SB = Clock B / (2 * PWMSCLB)
When PWMSCLB = $00, PWMSCLB value is considered a full scale value
of 256. Clock B is thus divided by 512.
As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for
this case will be bus clock divided by 4. A pulse will occur at a rate of once every 255x4 bus cycles. Passing
this through the divide by two circuit produces a clock signal at an bus clock divided by 2040 rate.
Similarly, a value of $01 in the PWMSCLA register when clock A is bus clock divided by 4 will produce
a clock at an bus clock divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.
Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper
rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or
PWMSCLB is written prevents this.
NOTE
Writing to the scale registers while channels are operating can cause
irregularities in the PWM outputs.
Q T
CAEx
Q
R
PWMEx
Figure 22-16. PWM Timer Channel Block Diagram
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.
There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an
edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-
enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on
the next selected clock.
NOTE
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.
However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is
similar to writing the counter when the channel is disabled, except that the new period is started
immediately with the output set according to the polarity bit.
NOTE
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
The counter is cleared at the end of the effective period (see Section 22.4.2.5, “Left Aligned Outputs” and
Section 22.4.2.6, “Center Aligned Outputs” for more details).
Table 22-12. PWM Timer Counter Conditions
NOTE
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
PPOLx = 0
PPOLx = 1
PWMDTYx
Period = PWMPERx
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
• PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
• PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
As an example of a left aligned output, consider the following case:
Clock Source = bus clock, where bus clock = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
The output waveform generated is shown in Figure 22-18.
E = 100 ns
PPOLx = 0
PPOLx = 1
PWMDTYx PWMDTYx
PWMPERx PWMPERx
Period = PWMPERx*2
To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.
• PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
• PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
As an example of a center aligned output, consider the following case:
Clock Source = bus clock, where bus clock= 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/8 = 1.25 MHz
PWMx Period = 800 ns
PWMx Duty Cycle = 3/4 *100% = 75%
Shown in Figure 22-20 is the output waveform generated.
E = 100 ns E = 100 ns
Clock Source 7
High Low
PWMCNT6 PWMCNT7
Clock Source 5
High Low
PWMCNT4 PWMCNT5
Clock Source 3
High Low
PWMCNT2 PWMCNT3
Clock Source 1
High Low
PWMCNT0 PWMCNT1
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low order CAEx bit. The high order CAEx bit has no effect.
Table 22-13 is used to summarize which channels are used to set the various control bits when in 16-bit
mode.
Table 22-13. 16-bit Concatenation Mode Summary
Note: Bits related to available channels have functional significance.
PWMx
CONxx PWMEx PPOLx PCLKx CAEx
Output
CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7
CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5
CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3
CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1
22.5 Resets
The reset state of each individual bit is listed within the Section 22.3.2, “Register Descriptions” which
details the registers and their bit-fields. All special functions or modes which are initialized during or just
following reset are described within this section.
• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters do not count.
22.6 Interrupts
The PWM module has no interrupt.
VDD 1.8 V 1.8V core supply voltage generated by on chip voltage regulator
VSS1 0V Ground pin for 2.8V flash supply voltage generated by on chip voltage regulator
VSS2 0V Ground pin for 1.8V core supply voltage generated by on chip voltage regulator
VDDF 2.8 V 2.8V flash supply voltage generated by on chip voltage regulator
VDDX1 (1) 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator
VSSX1 0V Ground pin for I/O drivers
VDDX2 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator
VDDA 5.0 V 5V Power supply for the analog-to-digital converter and for the reference circuit of the
internal voltage regulator
VSSA 0V Ground pin for VDDA analog supply
LGND 0V Ground pin for LIN physical interface
HD 12 V GDU Highside Drain. Also used as LIN supply, VLINSUP.
VSUP 12 V/18 V External power supply for voltage regulator
VDDC 5V Power supply output for CANPHY
VDDS2 5V Power supply output (5V) for external sensors
VDDS1 5V Power supply output (5V) for external sensors
VLS_OUT 11 V GDU voltage regulator output for low side FET-predriver power supply.
VSSB 0V Ground pin for boost supply.
1. All VDDX pins are internally connected by metal
NOTE
VDDA is connected to VDDX pins by diodes for ESD protection such that
VDDX must not exceed VDDA by more than a diode voltage drop. VSSA
and VSSX are connected by anti-parallel diodes for ESD protection.
A.1.2 Pins
There are 4 groups of functional pins.
SNPS2 pins. These pins are intended to interface to external components operating in the automotive
battery range. They have nominal voltages above the standard 5V I/O voltage range.
A.1.2.3 Oscillator
If the designated EXTAL and XTAL pins are configured for external oscillator operation then these pins
have a nominal voltage of 1.8 V.
A.1.2.4 TEST
This pin is used for production testing only. The TEST pin must be tied to ground in all applications.
power; e.g., if no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
Figure A-1. Current Injection on GPIO Port if Vin > VDDX
VSUP
VBG
+
_
P2 Pad Driver
IDDX
VDDX
ILoad
Iin
C Load
P1 D1
Iin
Px
VSSX
VSSA
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise.
For better immunity to ESD events, the PCB test point for the BST pin should be located at a distance from
the device to increase the track length to the BST pin, but the diode should be located close to the device.
This may require a track branch on the PCB to ensure that the test point is further away from the device
than the diode.
Table A-3. ESD and Latch-up Test Conditions
NOTE
Please refer to the temperature rating of the device with regards to the
ambient temperature TA and the junction temperature TJ. For power
dissipation calculations refer to Section A.1.8, “Power Dissipation and
Thermal Characteristics”.
Table A-6. Operating Conditions
2. The flash program and erase operations must configure fNVMOP as specified in the NVM electrical section.
3. Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between
ambient temperature TA and device junction temperature TJ.
4. Refer to fATDCLK for minimum ADC operating frequency. This is derived from the bus clock.
NOTE
Operation is guaranteed when powering down until low voltage reset
assertion.
T = T + P
J A D JA
T = Junction Temperature, [C
J
T = Ambient Temperature, [C
A
P = Total Chip Power Dissipation, [W]
D
= Package Thermal Resistance, [C/W]
JA
The total power dissipation PD can be calculated from the equation below. Table A-7 below lists the power
dissipation components. Figure A-2 provides an overview of power pin connectivity.
PD = PVSUP + PBCTL + PINT - PGPIO + PLIN - PEVDD1 + PGDU
PINT = VDDX IVDDX + VDDA IVDDA Internal Power through VDDX/A pins.
PGPIO = VI/O II/O Power dissipation of external load driven by GPIO Port.
Assuming the load is connected between GPIO and
ground. This power component is included in PINT and
is subtracted from overall MCU power dissipation PD
PGDU (1) = (-VVLS_OUT IVLS_OUT) + (VVBS IVBS) + Power dissipation of FET-Predriver without the outputs
(VVCPIVCP) + (VVLSn IVLSn) switching
MC9S12ZVM-Family
L Package Option
ILIN
VBAT LIN
IRBATP ISUP
VSUP
GND
VLS_OUT
BCTL
VDDA
IVDDX
VLS[2:0]
VDDX1
VDDX2
VBS[2:0]
VCP
VSSX1
II/O
IEVDD
GPIO
EVDD1
RL2 VI/O
VDDX RL1
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface
resistance
7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. A single layer board is used for this simulation.
Table A-9. 64LQFP-EP Typical Thermal Package Characteristics (ZVML31, ZVM32, ZVM16 devices)
maskset maskset
Num C(1) Rating Symbol Unit
0N14N 1N14N
Table A-10. 64LQFP-EP Typical Thermal Package Characteristics (All other devices)
masksets
maskset
Num C(1) Rating Symbol 1N95G, Unit
3N95G
2N95G
Conditions are 4.5 V < VDDX< 5.5 V , -40C < Tj < 175C for all GPIO pins (defined in A.1.2.1/A-876) unless otherwise noted.
2. For better ADC accuracy, the application should avoid current injection into pin PAD8/VREFH. Refer to Section A.1.3,
“Current Injection” for more details
3. For better ADC accuracy, the application should avoid current injection into pin HS0 and HG0 during ADC conversions. This
can be achieved by correct synchronization of ADC and FET switching..
Table A-13. Pin Timing Characteristics (Junction Temperature From -40C To +175C)
Conditions are 4.5 V < VDDX< 5.5 V unless otherwise noted. I/O Characteristics for all GPIO pins (defined in A.1.2.1/A-876).
Table A-14. High Voltage Input Electrical Characteristics (Junction Temperature From -40C To +175C)
1. Outside of the given VHVI range the error is significant. The ratio can be changed, if outside of the given range.
Table A-16. CPMU Configuration for Run/Wait and Full Stop Current Measurement
CPMUPOSTDIV POSTDIV[4:0]=0
CPMUOSC OSCE=0,
Reference clock for PLL is fref=firc1m trimmed to 1MHz
Table A-16. CPMU Configuration for Run/Wait and Full Stop Current Measurement
Table A-17. Peripheral Configurations for Run & Wait Current Measurement
Peripheral Configuration
ADC The peripheral is configured to operate at its maximum specified frequency and to
continuously convert voltages on a single input channel
PTU The module is enabled, bits TG1EN and TG0EN are set. PTUFRE is also set to generate
automatic reload events.
GDU LDO enabled. Charge pump enabled. Current sense0 enabled. Boost disabled. No
output activity (too load dependent)
BATS Enabled
LINPHY Connected to SCI and continuously transmit data (0x55) at speed of 19200 baud
1. This is the total current flowing into the VSUP and HD pins, to account for mask sets where HD is the LINPHY supply.
2. Stop current values for ZVMC256 are subject to change following characterization.
3. If MCU is in Stop mode long enough then TA = TJ . Die self heating due to stop current can be ignored.
5d Short Circuit VDDX fall back current VDDX <=0.5V IDDX — 100 — mA
12 The first period after enabling the counter by APIFE tsdel — — 100 s
might be reduced by API start up delay
19a Max. Base Current For External PNP (VDDX)(11) IBCTLMAX 2.3 — — mA
-40C < TJ < 150C
19b Max. Base Current For External PNP (VDDX)(11) IBCTLMAX 1.5 — — mA
150C < TJ < 175C
20a Max. Base Current For External PNP (VDDC)(11) IBCTLCMAX 2.3 — — mA
-40C < TJ < 150C
20b Max. Base Current For External PNP (VDDC)(11) IBCTLCMAX 1.5 — — mA
150C < TJ < 175C
1. External PNP regulator has a higher regulation point to ensure that the current flows through the PNP when the application
fails to disable the internal regulator by clearing INTXON.
4. Maximum load current depends on the current gain of the external PNP and available base current
6. LVRX is monitored on the VDDX supply domain only during full performance mode. During reduced performance mode (stop
mode) voltage supervision is solely performed by the POR block monitoring core VDD.
7. For the given maximum load currents and VSUP input voltages, the MCU will stay out of reset.
8. The ACLK trimming must be set that the minimum period equals to 0.2ms
9. CPMUHTTR=0x88. Customer must program CPMUHTTR to 0x88. Default value is 0x0F. Junction temperature depends on
system thermal performance, therefore the offset to ambient temperature must be characterized at system level.
11. This is the minimum base current that can be guaranteed when the external PNP is delivering maximum current.
2. This is the minimum base current that can be guaranteed when the external PNP is delivering maximum current.
Table B-5. OSC electrical characteristics (Junction Temperature From –40C To +175C)
Num C Rating Symbol Min Typ Max Unit
1 Nominal crystal or resonator frequency fOSC 4.0 — 20 MHz
2 Startup Current iOSC 100 — — A
3a Oscillator start-up time (4MHz)(1) tUPOSC — 2 10 ms
3b Oscillator start-up time (8MHz)1 tUPOSC — 1.6 8 ms
3c Oscillator start-up time (16MHz)1 tUPOSC — 1 5 ms
3d Oscillator start-up time (20MHz)1 tUPOSC — 1 4 ms
4 Clock Monitor Failure Assert Frequency fCMFA 200 450 1200 KHz
5 Input Capacitance (EXTAL, XTAL pins) CIN — 7 — pF
6 EXTAL Pin Input Hysteresis VHYS,EXTAL — 120 — mV
7 EXTAL Pin oscillation amplitude (loop controlled VPP,EXTAL — 1.0 — V
Pierce)
8 EXTAL Pin oscillation required amplitude(2) VPP,EXTAL 0.8 — 1.5 V
1. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements.
2. Needs to be measured at room temperature on the application board using a probe with very low (<=5pF) input capacitance.
0 1 2 3 N-1 N
tmin1
tnom
tmax1
tminN
tmaxN
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t N t N
max min
J N = max 1 – ----------------------- , 1 – -----------------------
Nt Nt
nom nom
j1
J N = --------------------------------------------------
N POSTDIV + 1
J(N)
1 5 10 20 N
Figure B-2. Maximum Bus Clock Jitter Approximation (N = number of bus cycles)
NOTE
Peripheral module prescalers eliminate the effect of jitter to a large extent.
Table B-6. PLL Characteristics (Junction Temperature From –40C To +175C)
Appendix C
ADC Electrical Specifications
NOTE: ADC1 is only tested to 10-bit accuracy in the 48LQFP-EP package options.
NOTE: VRL_0 is the preferred reference for low noise.
NOTE: (ZVMC256 only) When using VDDS2 or VDDS1 as the VRH reference, the reference
is impacted by a drop of between 4mV and 15mV across the internal short circuit
protection switch.
Supply voltage 4.5 V < VDDA < 5.5 V, Junction Temperature From –40×oC To +175oC
1 Reference potential
Low VRL VSSA — VDDA/2 V
High VRH VDDA/2 — VDDA V
2 Voltage difference VDDX to VDDA VDDX -0.1 0 0.1 V
3 Voltage difference VSSX to VSSA VSSX –0.1 0 0.1 V
4 Differential reference voltage(1) VRH-VRL 3.13 5.0 5.5 V
5 ADC Clock Frequency (derived from bus clock via the fATDCLK 0.25 — 8.33 MHz
prescaler).
6 Buffer amplifier turn on time (delay after module tREC — — 1 s
start/recovery from Stop mode)
7 ADC disable time tDISABLE — — 3 bus
clock
cycles
ADC Conversion Period (2)
12 bit resolution: NCONV12 19 — 39 ADC
8
10 bit resolution: NCONV10 18 — 38 clock
8 bit resolution: NCONV8 16 — 36 cycles
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. The minimum time assumes a sample time of 4 ATD clock cycles; maximum time assumes a sample time of 24 ATD clock
cycles.
Table C-2. ADC Electrical Characteristics (Junction Temperature From –40C To +175C)
+
Ileakn < 1A
Ctop
-
Cstray < 1.8pF 3.7pF < S/H Cap < 6.2pF
VSSA (incl parasitics)
Cbottom
connected to low ohmic
supply during sampling
Figure C-1.
V –V
i i–1
DNL i = -------------------------- – 1
1LSB
n
V –V
n 0
INL n = DNL i = --------------------- – n
1LSB
i=1
DNL
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$3FC $FF
$3FB
$3FA
$3F9
$3F8 $FE
$3F7
$3F6
$3F5
$3F4 $FD
8-Bit Resolution
$3F3
10-Bit Resolution
9
Ideal Transfer Curve
8 2
7
10-Bit Transfer Curve
6
4 1
3
8-Bit Transfer Curve
2
0
5 10 15 20 25 30 35 40 45 55 60 65 70 75 80 85 90 95 100 105 110 115 120
Vin
5000 + mV
Figure C-2. ADC Accuracy Definitions
Table C-3. ADC Conversion Performance 5 V range (Junction Temperature From –40C To +150C)
Supply voltage 4.5 V < VDDA < 5.5 V, 4.5V < VREF < 5.5 V. ( VREF= VRH - VRL ). fADCCLK = 8.0 MHz
The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions.
Table C-4. ADC Conversion Performance 5 V range (Junction Temperature From 150C To +175C)
Supply voltage 4.5 V < VDDA < 5.5 V, 4.5V < VREF < 5.5 V. ( VREF= VRH - VRL ). fADCCLK = 8.0 MHz
The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions.
1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode.
2. These values include the quantization error which is inherently 1/2 count for any A/D converter.
Appendix D
LIN/HV PHY Electrical Specifications
D.1 Static Electrical Characteristics
Table D-1. Static electrical characteristics of the LIN/HV PHY (Junction Temperature From -40C To +175C)
Characteristics noted under conditions 5.5V <= VLINSUP <= 18V unless otherwise noted(1) (2) (3). Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
2 Current limitation into the LIN pin in dominant state(4) ILIN_LIM 40 — 200 mA
VLIN = VLINSUP_LIN_MAX
1. For 3.5V<= VLINSUP <5V, the LIN/HV PHY is still working but with degraded parametrics.
2. For 5V<= VLINSUP <5.5V, characterization showed that all parameters generally stay within the indicated specification, except
the duty cycles D2 and D4 which may increase and potentially go beyond their maximum limits for highly loaded buses.
3. The VLINSUP voltage is provided by the VLINSUP supply. This supply mapping is described in device level documentation.
4. At temperatures above 25C the current may be naturally limited by the driver, in this case the limitation circuit is not engaged
and the flag is not set.
Characteristics noted under conditions 5.5V V LINSUP 18 V unless otherwise noted(1) (2) (3). Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
2 TxD-dominant timeout (in IRC clock periods) (4) tDTLIM 16388 — 16389 tIRC
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NOMINAL SLEW RATE - 20.0KBIT/S
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/S
Characteristics noted under conditions 5.5V V LINSUP 18 V unless otherwise noted(1) (2) (3). Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST MODE SLEW RATE - 100KBIT/S UP TO 250KBIT/S
1. For 3.5V<= VLINSUP <5V, the LIN/HV PHY is still working but with degraded parametrics.
2. For 5V<= VLINSUP <5.5V, characterization showed that all parameters generally stay within the indicated specification, except
the duty cycles D2 and D4 which may increase and potentially go beyond their maximum limits for highly loaded buses.
3. The VLINSUP voltage is provided by the VLINSUP supply. This supply mapping is described in device level documentation.
Appendix E
GDU Electrical Specifications
NOTE
It is necessary to consider the power dissipation of the FET channel versus
the power dissipation in the FET-Predriver.
FET-Predriver dissipation is Power VSUP x f(PWM) x C(FET-GATE)
FET channel power dissipation is a function of channel current and voltage.
Reducing the RDSON of the external FET to reduce the FET power
dissipation increases the FET gate capacitance.
At a certain FET level, further reduction of FET RDSON actually increases
overall power consumption because the increased charging and discharging
power dissipation due to increased gate capacitance outweighs the FET
power reduction due to RDSON reduction.
Table E-1. GDU Electrical Characteristics (Junction Temperature From –40C To +175C)
4.85V<=VDDX,VDDA<=5.15V
11b HD high voltage monitor deassert trippoint low VHVHDLD 19.5 20.5 21.6 V
12a HD high voltage monitor assert trippoint high VHVHDHA 26.6 28.3 29.4 V
12b HD high voltage monitor deassert trippoint high VHVHDHD 26.2 27.9 29 V
13 HD high voltage monitor filter time constant(6) HVHD — 2.7 4 s
14 HG/LG turn on time vs 10nF load (fastest slew)(7) tHGON 120 190 340 ns
15 HG/LG turn on time vs 10nF load (slowest slew)(7) tHGON 315 560 980 ns
16a HG/LG turn off time vs 10nF load(8) , -40C < Tj < 150C tHGOFF 55 90 210 ns
16b HG/LG turn off time vs 10nF load(8) , 150C < Tj < 175C tHGOFF 55 90 220 ns
(9)
17 PMF channel to HG/LG start of turn on delay
TDEL=0 or devices without TDEL bit (fastest slew) tdelon 0.47 0.68 0.89 s
TDEL=0 or devices without TDEL bit (slowest slew) 0.77 1.10 1.43
TDEL=1 (TDEL only offered on 1N00R or 3N95G masksets) 0.45 0.60 0.71
18 PMF channel to HG/LG start of turn off delay(9)
TDEL=0 or devices without TDEL bit tdeloff 0.25 0.37 0.49 s
TDEL=1 (TDEL only offered on 1N00R or 3N95G masksets) 0.33 0.36 0.43
19 Minimum PMF driver on/off pulse width (fastest slew) tminpulse 2 — — s
20a VBS to HG, VLSx to LGx RDSon (driver on state)(10) Rgduon — 6.3 11.6
-40C < Tj < 150C
20b VBS to HG, VLSx to LGx RDSon (driver on state)(10) Rgduon — 8.4 13.6
150C < Tj < 175C
21a HGx to HSx, LGx to LSx RDSon (driver off state)(11) Rgduoffn — 4 9
nmos part, -40C < Tj < 150C
21b HGx to HSx, LGx to LSx RDSon (driver off state)(11) nmos part, Rgduoffn — 7 11
150C < Tj < 175C
22a HGx to HSx, LGx to LSx RDSon (driver off state)(12) pmos part, Rgduoffp — 16 22
-40C < Tj < 150C
22b HGx to HSx, LGx to LSx RDSon (driver off state)(12) Rgduoffp — 20 26
pmos part, 150C < Tj < 175C
23 VSUP boost turn on trip point (13) VBSTON 9.5 10.1 10.6 V
24 VSUP boost turn off trip point (13) VBSTOFF 9.75 10.3 10.85 V
25a Boost coil current limit (GDUBCL=0x0), -40C < Tj < 150C (13) ICOIL0 90 190 390 mA
25b Boost coil current limit (GDUBCL=0x0), 150C < Tj < 175C(13) ICOIL0 80 160 275 mA
26a Boost coil current limit (GDUBCL=0x8), -40C < Tj < 150C(13) ICOIL8 270 380 670 mA
26b Boost coil current limit (GDUBCL=0x8), 150C < Tj < 175C(13) ICOIL8 230 330 470 mA
27a Boost coil current limit (GDUBCL=0xF), -40C < Tj < 150C(13) ICOIL15 390 530 900 mA
27b Boost coil current limit (GDUBCL=0xF), 150C < Tj < 175C(13) ICOIL15 380 485 640 mA
28 Phase signal division ratio 3V < VHSx < 20V AHSDIV 5.7 6 6.3 —
29a HD signal division ratio 6V < VHD < 20V AHDDIV 4.9 5 5.1 —
29b HD signal division ratio through phase mux. AHDDIV 11.4 12 12.6 —
30a CP driver RDSon highside(14), -40C < Tj < 150C RCPHS — 44 90
(14)
30b CP driver RDSon highside , 150C < Tj < 175C RCPHS — 71 100
31a CP driver RDSon lowside(14), -40C < Tj < 150C RCPLS — 11.5 30
31b CP driver RDSon lowside(14), 150C < Tj < 175C RCPLS — 20 35
32 Current Sense Amplifier input voltage range (AMPP/AMPM) VCSAin 0 — VDDA - V
1.2
Table E-1. GDU Electrical Characteristics (Junction Temperature From –40C To +175C)
4.85V<=VDDX,VDDA<=5.15V
33 Current Sense Amplifier output voltage range VCSAout 0 — VDDA V
34 Current Sense Amplifier open loop gain AVCSA — 100000 — —
35 Current Sense Amplifier common mode rejection ratio CMRRCSA — 400 — —
36 Current Sense Amplifier input offset VCSAoff -15 — 15 mV
37 Max effective Current Sense Amplifier output resistance [0.1V RCSAout — — 2
.. VDDA - 0.2V]
38 Min Current Sense Amplifier output current ICSAout -750 — 750 A
[0.1V .. VDDA - 0.2V](15)
39 Current Sense Amplifier large signal settling time tcslsst — 2.9 — s
40 Current Sense Amplifier unity gain bandwidth GBW — 1.9 — MHz
41 Current Sense Amplifier input resistance (16)
— — — —
(17)
42 Over Current Comparator filter time constant OCC 3 5 10 s
43 Over Current Comparator threshold tolerance VOCCtt -75 — 75 mV
44 HD input current when GDU is enabled IHD — 130 + — A
VHD/63K
45 VLS regulator minimum RDSon (VSUP >= 6V) RVLSmin — — 40
46 VCP to VBSx switch resistance RVCPVBS — 600 1000
47 VBSx current whilst high side inactive IVBS — — 310 A
48a Desaturation comparator filter time constant fast desatf 90 — 250 ns
(GDU V6 GDSFHS/GDSFLS=0)
(GDU V4 high side)
(GDU V4 low side on all mask sets except 3N95G)
48b Desaturation comparator filter time constant slow desats 240 — 670 ns
(GDU V6 GDSFHS/GDSFLS=1)
(GDU V4 mask set 3N95G low side)
49a LS desaturation comparator level, GDUV6, GDSLLS = 000 (18) Vdesatls 0.23 0.35 0.46 V
49b LS desaturation comparator level, GDUV6, GDSLLS = 001(18) Vdesatls 0.355 0.5 0.645 V
49c LS desaturation comparator level, GDUV6, GDSLLS = 010(18) Vdesatls 0.46 0.65 0.84 V
49d LS desaturation comparator level, GDUV6, GDSLLS = 011(18) Vdesatls 0.575 0.8 1.035 V
49e LS desaturation comparator level, GDUV6, GDSLLS = 100(18) Vdesatls 0.69 0.95 1.23 V
49f LS desaturation comparator level, GDUV6, GDSLLS = 101(18) Vdesatls 0.81 1.1 1.41 V
49g LS desaturation comparator level, GDUV6, GDSLLS = 110(18) Vdesatls 0.925 1.25 1.605 V
(18)
49h LS desaturation comparator level, GDUV6, GDSLLS = 111 Vdesatls 1.03 1.4 1.81 V
50a HS desaturation comparator level, GDUV6, GDSLHS = 000 Vdesaths VHD-0.23 VHD-0.35 VHD-0.46 V
50b HS desaturation comparator level, GDUV6, GDSLHS = 001 Vdesaths VHD-0.355 VHD-0.5 VHD-0.645 V
50c HS desaturation comparator level, GDUV6, GDSLHS = 010 Vdesaths VHD-0.46 VHD-0.65 VHD-0.84 V
50d HS desaturation comparator level, GDUV6, GDSLHS = 011 Vdesaths VHD-0.575 VHD-0.8 VHD-1.035 V
50e HS desaturation comparator level, GDUV6, GDSLHS = 100 Vdesaths VHD-0.69 VHD-0.95 VHD-1.23 V
50f HS desaturation comparator level, GDUV6, GDSLHS = 101 Vdesaths VHD-0.81 VHD-1.1 VHD-1.41 V
50g HS desaturation comparator level, GDUV6, GDSLHS = 110 Vdesaths VHD-0.925 VHD-1.25 VHD-1.605 V
50h HS desaturation comparator level, GDUV6, GDSLHS = 111 Vdesaths VHD-1.03 VHD-1.4 VHD-1.81 V
1. Without using the boost option. The minimum level can be relaxed when the boost option is used. The lower limit is sensed on
VLS, the upper limit is sensed on HD.
2. Without using the boost option. The minimum level can be relaxed when the boost option is used. The lower limit is sensed on
VLS, the upper limit is sensed on HD. Operation beyond 20V is limited to 1 hour over lifetime of the device
3. For high side, the performance of external diodes may influence this parameter.
4. If VSUP is lower than 11.2V, external FET gate drive will diminish and roughly follow VSUP - 2* Vbe
5. Total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates are
tolerable by the application and resulting power dissipation does not lead to thermal overload.
6. Blanking time for assert (see device level mask set dependencies)
7. (VBSx - HSx) = 10V respectively VLSx=10V, measured from 1V to 9V HGx/LGx vs HSx/LSx
8. (VBSx - HSx) = 10V respectively VLSx=10V, measured from 9V to 1V HGx/LGx vs HSx/LSx
9. The delay is dependent on slew rate configuration. The variation on a given device for a given slew setting is much less than
the specified range.
10. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V
11. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, nmos branch only
12. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, pmos branch only
13. Not tested on the mask set 2N95G, which does not feature the BST pin function
14. VLS > 6V
15. Output current range for which the effective output resistance specification applies
16. Input resistance can be calculated from the pin input leakage because the sense amp has high impedance MOS inputs
17. Av=10, no frequency compensation in feedback network, 90% output swing
18. Low side desaturation comparator range extends to LSx <= 2.35V - Vdesatls
Table E-2. GDUV5 Electrical Characteristics (Junction Temperature From –40C To +175C)
4.85V<=VDDX,VDDA<=5.15V
13 HD high voltage monitor filter time constant(6) HVHD — 2.7 4 s
14 HG/LG turn on time vs 10nF load (fastest slew)(7) tHGON 150 275 550 ns
15 HG/LG turn on time vs 10nF load (slowest slew)(7) tHGON 740 1170 1800 ns
16a HG/LG turn off time vs 10nF load(8), -40C < Tj < 150C tHGOFF 60 120 230 ns
16b HG/LG turn off time vs 10nF load(8) , 150C < Tj < 175C tHGOFF 130 190 250 ns
17 PMF channel to HG/LG start of turn on delay (9) tdelon TBD 0.7 TBD s
18 PMF channel to HG/LG start of turn off delay(9) tdeloff TBD 0.4 TBD s
19 Minimum PMF driver on/off pulse width (fastest slew) tminpulse 2 — — s
(10)
20a VBS to HG, VLSx to LGx RDSon (driver on state) Rgduon — 9.5 17.4
-40C < Tj < 150C
20b VBS to HG, VLSx to LGx RDSon (driver on state)(10) Rgduon — 12.6 20.5
150C < Tj < 175C
21a HGx to HSx, LGx to LSx RDSon (driver off state)(11) Rgduoffn — 6 14
nmos part, -40C < Tj < 150C
21b HGx to HSx, LGx to LSx RDSon (driver off state)(11) nmos part, Rgduoffn — 10.5 17
150C < Tj < 175C
22a HGx to HSx, LGx to LSx RDSon (driver off state)(12) pmos part, Rgduoffp — 24 35
-40C < Tj < 150C
22b HGx to HSx, LGx to LSx RDSon (driver off state)(12) Rgduoffp — 30 39.5
pmos part, 150C < Tj < 175C
23 VSUP boost turn on trip point VBSTON 9.5 10.1 10.6 V
24 VSUP boost turn off trip point VBSTOFF 9.75 10.3 10.85 V
25a Bootstrap diode resistance, -40C < Tj < 150C Rbsdon — — 67
25b 25c
Bootstrap diode resistance, 150C < Tj < 175C Rbsdon — — 73
26a Boost coil current limit (GDUBCL=0x0), -40C < Tj < 150C ICOIL0 90 190 390 mA
26b Boost coil current limit (GDUBCL=0x0), 150C < Tj < 175C ICOIL0 80 160 275 mA
27a Boost coil current limit (GDUBCL=0x8), -40C < Tj < 150C ICOIL8 270 380 670 mA
27b Boost coil current limit (GDUBCL=0x8), 150C < Tj < 175C ICOIL8 230 330 470 mA
28a Boost coil current limit (GDUBCL=0xF), -40C < Tj < 150C ICOIL15 390 530 900 mA
28b Boost coil current limit (GDUBCL=0xF), 150C < Tj < 175C ICOIL15 380 485 640 mA
29 Phase signal division ratio 3V < VHSx < 20V AHSDIV 5.7 6 6.3 —
30a HD signal division ratio 6V < VHD < 20V AHDDIV 4.9 5 5.1 —
30b HD signal division ratio through phase mux. AHDDIV 11.4 12 12.6 —
31a CP driver RDSon highside(13), -40C < Tj < 150C RCPHS — 44 90
31b CP driver RDSon highside(13), 150C < Tj < 175C RCPHS — 71 100
32a CP driver RDSon lowside(13), -40C < Tj < 150C RCPLS — 11.5 30
32b CP driver RDSon lowside(13), 150C < Tj < 175C RCPLS — 20 35
33 Current Sense Amplifier input voltage range (AMPP/AMPM) VCSAin 0 — VDDA - V
1.2
34 Current Sense Amplifier output voltage range VCSAout 0 — VDDA V
35 Current Sense Amplifier open loop gain AVCSA — 100000 — —
36 Current Sense Amplifier common mode rejection ratio CMRRCSA — 400 — —
37 Current Sense Amplifier input offset VCSAoff -15 — 15 mV
Table E-2. GDUV5 Electrical Characteristics (Junction Temperature From –40C To +175C)
4.85V<=VDDX,VDDA<=5.15V
38 Max effective Current Sense Amplifier output resistance [0.1V RCSAout — — 2
.. VDDA - 0.2V]
39 Min Current Sense Amplifier output current ICSAout -750 — 750 A
[0.1V .. VDDA - 0.2V](14)
40 Current Sense Amplifier large signal settling time tcslsst — 2.9 — s
41 Current Sense Amplifier unity gain bandwidth GBW — 1.9 — MHz
42 Current Sense Amplifier input resistance (15)
— — — —
43 Over Current Comparator filter time constant(16) OCC 3 5 10 s
44 Over Current Comparator threshold tolerance VOCCtt -75 — 75 mV
45 HD input current when GDU is enabled IHD — 130 + — A
VHD/63K
46 VLS regulator minimum RDSon (VSUP >= 6V) RVLSmin — — 40
47 VCP to VBSx switch resistance RVCPVBS — 600 1000
48 VBSx current whilst high side inactive IVBS 200 260 440 A
(17)
49a LS desaturation comparator level, GDSLLS = 000 Vdesatls 0.23 0.35 0.46 V
49b LS desaturation comparator level, GDSLLS = 001 (17) Vdesatls 0.355 0.5 0.645 V
49c LS desaturation comparator level, GDSLLS = 010 (17)
Vdesatls 0.46 0.65 0.84 V
49d LS desaturation comparator level, GDSLLS = 011 (17) Vdesatls 0.575 0.8 1.035 V
49e LS desaturation comparator level, GDSLLS = 100 (17)
Vdesatls 0.69 0.95 1.23 V
49f LS desaturation comparator level, GDSLLS = 101 (17) Vdesatls 0.81 1.1 1.41 V
(17)
49g LS desaturation comparator level, GDSLLS = 110 Vdesatls 0.925 1.25 1.605 V
49h LS desaturation comparator level, GDSLLS = 111 (17) Vdesatls 1.03 1.4 1.81 V
50a HS desaturation comparator level, GDSLHS = 000 Vdesaths VHD-0.23 VHD-0.35 VHD-0.46 V
50b HS desaturation comparator level, GDSLHS = 001 Vdesaths VHD-0.355 VHD-0.5 VHD-0.645 V
50c HS desaturation comparator level, GDSLHS = 010 Vdesaths VHD-0.46 VHD-0.65 VHD-0.84 V
50d HS desaturation comparator level, GDSLHS = 011 Vdesaths VHD-0.575 VHD-0.8 VHD-1.035 V
50e HS desaturation comparator level, GDSLHS = 100 Vdesaths VHD-0.69 VHD-0.95 VHD-1.23 V
50f HS desaturation comparator level, GDSLHS = 101 Vdesaths VHD-0.81 VHD-1.1 VHD-1.41 V
50g HS desaturation comparator level, GDSLHS = 110 Vdesaths VHD-0.925 VHD-1.25 VHD-1.605 V
50h HS desaturation comparator level, GDSLHS = 111 Vdesaths VHD-1.03 VHD-1.4 VHD-1.81 V
1. Without using the boost option. The minimum level can be relaxed when the boost option is used. The lower limit is sensed on
VLS, the upper limit is sensed on HD.
2. Without using the boost option. The minimum level can be relaxed when the boost option is used. The lower limit is sensed on
VLS, the upper limit is sensed on HD. Operation beyond 20V is limited to 1 hour over lifetime of the device
3. For high side, the performance of external diodes may influence this parameter.
4. If VSUP is lower than 11.2V, external FET gate drive will diminish and roughly follow VSUP - 2* Vbe
5. Total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates are
tolerable by the application and resulting power dissipation does not lead to thermal overload.
6. Blanking time for assert.
7. (VBSx - HSx) = 10V respectively VLSx=10V, measured from 1V to 9V HGx/LGx vs HSx/LSx
8. (VBSx - HSx) = 10V respectively VLSx=10V, measured from 9V to 1V HGx/LGx vs HSx/LSx
9. The delay is dependent on slew rate configuration. The variation on a given device for a given slew setting is much less than
the specified range. Subject to adjustment following further characterization.
10. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V
11. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, nmos branch only
12. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, pmos branch only
13. VLS > 6V
14. Output current range for which the effective output resistance specification applies
15. Input resistance can be calculated from the pin input leakage because the sense amp has high impedance MOS inputs
16. Av=10, no frequency compensation in feedback network, 90% output swing
17. Low side desaturation comparator range extends to LSx <= 2.35V - Vdesatls
Appendix F
NVM Electrical Parameters
F.1 NVM Timing Parameters
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV
register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM
module does not have any means to monitor the frequency and will not prevent program or erase operation
at frequencies above or below the specified minimum. When attempting to program or erase the NVM
module at a lower frequency, a full program or erase transition is not assured.
The device bus frequency, below which the flash wait states can be disabled, fWSTAT, is specified in the
device operating conditions table in Table A-6.
The following sections provide equations which can be used to determine the time required to execute
specific flash commands. All timing parameters are a function of the bus clock frequency, fNVMBUS. All
program and erase times are also a function of the NVM operating frequency, fNVMOP.
Timing parameters for the ZVMC128, ZVML128, ZVMC64, ZVML64 and ZVML32 devices are
specified in Table F-1 and Table F-2.
Timing parameters for the ZVML31, ZVM32 and ZVM16 are specified in Table F-3 and Table F-4.
Timing parameters for the ZVMC256 are specified in Table F-5
Table F-1. FTMRZ128K512 NVM Timing Characteristics (Junction Temperature From –40C To +150C)
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
Table F-2. FTMRZ128K512 NVM Timing Characteristics (Junction Temperature From 150C To 175C)
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
Table F-3. FTMRZ32K128 NVM Timing Characteristics (Junction Temperature From –40C To +150C)
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
Table F-4. FTMRZ32K128 NVM Timing Characteristics (Junction Temperature From 150C To +175C)
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
Table F-5. FTMRZ256K1KNVM Timing Characteristics (Junction Temperature From –40C To +150C)
Derivative ZVMC256
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
Table F-6. FTMRZ256K1KNVM Timing Characteristics (Junction Temperature From +150C To +175C)
Derivative ZVMC256
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. Worst times are based on minimum fNVMOP and minimum fNVMBUS plus aging
2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25C using the Arrhenius equation. For additional information on the definition of Typical Data Retention, please refer to
Engineering Bulletin EB618
3. Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on the definition of
Typical Endurance, please refer to Engineering Bulletin EB619.
Appendix G
BATS Electrical Specifications
G.1 Static Electrical Characteristics
Table G-1. Static Electrical Characteristics - BATS (Junction Temperature From -40C To +175C)
Typical values reflect the approximate parameter mean at TA = 25°C(1) under nominal conditions unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C(1) under nominal conditions..
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 175°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 150°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
SPLIT
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 175°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristics noted under conditions 5.5V VSUP 18 V, -40°C TJ 175°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Appendix I
SPI Electrical Specifications
This section provides electrical parametrics and ratings for the SPI.
In Figure I-1. the measurement conditions are listed.
Figure I-1. Measurement Conditions
Description Value Unit
Drive mode full drive mode —
Load capacitance CLOAD(1),
50 pF
on all outputs
Thresholds for delay
(35% / 65%) VDDX V
measurement points
1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
SS1
(OUTPUT)
2 1 12 13 3
SCK 4
(CPOL 0)
(OUTPUT) 4
12 13
SCK
(CPOL 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
10 9 11
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If enabled.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
In Figure I-3. the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS1
(OUTPUT)
1
2 12 13 3
SCK
(CPOL 0)
(OUTPUT)
4 4 12 13
SCK
(CPOL 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
9 11
MOSI
(OUTPUT) MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT
1. If enabled.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Table I-1. SPI Master Mode Timing Characteristics (Junction Temperature From -40C To +175C)
fSCK/fbus
1/2
1/4
5
10 15
20 25
30 35
40 fbus [MHz]
Figure I-4. Derating of maximum fSCK to fbus ratio in Master Mode
In Master Mode the allowed maximum fSCK to fbus ratio (= minimum Baud Rate Divisor, pls. see SPI
Block Guide) derates with increasing fbus, please see Figure I-4..
SS
(INPUT)
1 12 13 3
SCK
(CPOL 0)
(INPUT)
2 4 4
12 13
SCK
(CPOL 1)
(INPUT) 10 8
7 9 11 11
MISO see see
(OUTPUT) note SLAVE MSB BIT 6 . . . 1 SLAVE LSB OUT note
5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
In Figure I-6. the timing diagram for slave mode with transmission format CPHA=1 is depicted.
SS
(INPUT)
1 3
2 12 13
SCK
(CPOL 0)
(INPUT)
4 4 12 13
SCK
(CPOL 1)
(INPUT)
9 11 8
MISO see
(OUTPUT) note SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
9b Data Valid after SCK Edge (150C <Tj < 175C)(1) tvsck — — 25 + 0.5 t bus (2 ns
)
10a Data Valid after SS fall (-40C < Tj < 150C) tvss — — 23 + 0.5 t bus (2 ns
)
10b Data Valid after SS fall (150C < Tj < 175C)(1) tvss — — 25 + 0.5 t bus (2 ns
)
Table J-1. MSCAN Wake-up Pulse Characteristics (Junction Temperature From –40C To +175C)
Appendix K
Package Information
The Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C.
For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.nxp.com,
search by part number and review parametrics.
S12ZVML32, S12ZVML64,
S12ZVM16, S12ZVM32,
Product S12ZVML128, S12ZVMC64, S12ZVMC256
S12ZVML31
S12ZVMC128
Mask-rev 1.0(1) 1.1 3.1 3.2 3.3 1.01 1.1
Maskset-No 0-N14N 1-N14N 1-N95G 2-N95G 3-N95G 0-N00R 1-N00R
Package option 64LQFP- 48LQFP- 64LQFP- 64LQFP- 64LQFP- 64LQFP- 80LQFP- 80LQFP-
EP EP EP EP EP EP EP EP
Typ. Exposed pad 4.9 x 4.9 4.4x 4.4 6.1 x 6.1 4.9 x 4.9 4.9 x 4.9 6.1 x 6.1 5.6 x 5.6 5.6 x 5.6
size (mm)
Min. Solderable 4.0 x 4.0 3.5 x 3.5 5.2 x 5.2 4.0 x 4.0 4.0 x 4.0 5.2 x 5.2 4.9 x 4.9 4.9 x 4.9
area (mm)
Max. Solderable 5.7 x 5.7 5.2 x 5.2 7.0 x 7.0 5.7 x 5.7 5.7 x 5.7 7.0 x 7.0 6.2 x 6.2 6.2 x 6.2
area (mm)
1. These mask revisions were used during prototyping only, they are not supported for production
K.2 64LQFP-EP Mechanical Info (all mask sets except 1N95G, 2N95G)
Figure K-2. 64LQFP-EP Mechanical Information (all mask sets except 1N95G, 2N95G)
Appendix L
Ordering Information
Customers can choose either the mask-specific partnumber or the generic, mask-independent partnumber.
Ordering a mask-specific partnumber enables the customer to specify which particular maskset they
receive whereas ordering the generic partnumber means that the currently preferred maskset (which may
change over time) is shipped. In either case, the marking on the device always shows the generic, mask-
independent partnumber and the mask set number. The below figure illustrates the structure of a typical
mask-specific ordering number.
NOTES
Not every combination is offered. Table 1.2.1 lists available derivatives.
The mask identifier suffix and the Tape & Reel suffix are always both
omitted from the partnumber which is actually marked on the device.
S 9 12ZV ML 12 F0 M KH R
Tape & Reel:
R = Tape & Reel
No R = No Tape & Reel
Package Option:
KK = 80LQFP-EP
KH = 64LQFP-EP
KF = 48LQFP-EP
Temperature Option:
V = -40°C to 105°C
M = -40°C to 125°C
W = -40°C to 150°C
Maskset identifier Suffix:
First digit usually references wafer fab
Second digit usually differentiates mask rev
(This suffix is omitted in generic partnumbers)
Memory Size
25 = 256K Flash
12 = 128K Flash
64 = 64K Flash
31, 32 = 32K Flash
16 = 16K Flash
Device Family Name / Specification
ML = MOSFET predriver with LINPHY
MC = MOSFET predriver with CANPHY or
with MSCAN plus CAN VREG
M = MOSFET predriver with HVPHY interface
Core Family
12Z = S12Z 16-Bit MCU Core
V = MagniV Family
Main Memory Type:
9 = Flash
Status / Partnumber type:
S or SC = Maskset specific partnumber
MC = Generic / mask-independent partnumber
P or PC = prototype status (pre qualification)
Appendix M
Detailed Register Address Map
Registers listed are a superset of all registers in the S12ZVM-Family.
The device overview section specifies module (version) assignment to individual devices.
M.1 0x0000–0x0003 Part ID
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R 0 0 0 0 0 0 0 0
0x0000 PARTID0
W
R 0 0 0 1 Derivative Dependent (see Table 1-6)
0x0001 PARTID1
W
R 0 0 0 0 0 0 0 0
0x0002 PARTID2
W
R Revision Dependent
0x0003 PARTID3
W
R 0 0 0 0
0x0017 INT_CFADDR INT_CFADDR[6:3]
W
R 0 0 0 0 0
0x0018 INT_CFDATA0 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x0019 INT_CFDATA1 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001A INT_CFDATA2 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001B INT_CFDATA3 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001C INT_CFDATA4 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001D INT_CFDATA5 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001E INT_CFDATA6 PRIOLVL[2:0]
W
R 0 0 0 0 0
0x001F INT_CFDATA7 PRIOLVL[2:0]
W
0x0071- Reserved R 0 0 0 0 0 0 0 0
0x007F W
0x0080 MMCECH R
ITR[3:0] TGT[3:0]
W
0x0081 MMCECL R
ACC[3:0] ERR[3:0]
W
0x0084 Reserved R 0 0 0 0 0 0 0 0
W
0x0088- Reserved R 0 0 0 0 0 0 0 0
0x00FF W
R 0 0 0 0
0x0101 DBGC2 CDCM2 ABCM
W
DBGTCRH R
0x0102 2 reserved TSOURCE TRANGE TRCMOD TALIGN
W
DBGCNT R 0 CNT
0x0106 2
W
R
0x0107 DBGSCR1 C3SC1 C3SC0 C2SC12 C2SC02 C1SC1 C1SC0 C0SC1 C0SC0
W
R
0x0108 DBGSCR2 C3SC1 C3SC0 C2SC12 C2SC02 C1SC1 C1SC0 C0SC1 C0SC0
W
R
0x0109 DBGSCR3 C3SC1 C3SC0 C2SC12 C2SC02 C1SC1 C1SC0 C0SC1 C0SC0
W
0x010C- R 0 0 0 0 0 0 0 0
Reserved
0x010F W
R 0 0
0x0110 DBGACTL NDB INST RW RWE reserved COMPE
W
0x0111- R 0 0 0 0 0 0 0 0
Reserved
0x0114 W
R
0x0115 DBGAAH DBGAA[23:16]
W
R
0x0116 DBGAAM DBGAA[15:8]
W
R
0x0117 DBGAAL DBGAA[7:0]
W
R
0x0118 DBGAD0 Bit 31 30 29 28 27 26 25 Bit 24
W
R
0x0119 DBGAD1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x011A DBGAD2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x011B DBGAD3 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x011D DBGADM1 Bit 23 22 21 20 19 18 17 Bit 16
W
R
0x011E DBGADM2 Bit 15 14 13 12 11 10 9 Bit 8
W
R
0x011F DBGADM3 Bit 7 6 5 4 3 2 1 Bit 0
W
R 0 0 0
0x0120 DBGBCTL INST RW RWE reserved COMPE
W
0x0121- R 0 0 0 0 0 0 0 0
Reserved
0x0124 W
R
0x0125 DBGBAH DBGBA[23:16]
W
R
0x0126 DBGBAM DBGBA[15:8]
W
R
0x0127 DBGBAL DBGBA[7:0]
W
0x0128- R 0 0 0 0 0 0 0 0
Reserved
0x012F W
DBGCCTL R 0 0
0x0130 2 NDB INST RW RWE reserved COMPE
W
0x0131- R 0 0 0 0 0 0 0 0
Reserved
0x0134 W
DBGCAH R
0x0135 2 DBGCA[23:16]
W
DBGCAM R
0x0136 2 DBGCA[15:8]
W
DBGCAL R
0x0137 2 DBGCA[7:0]
W
DBGCD0 R
0x0138 2 Bit 31 30 29 28 27 26 25 Bit 24
W
DBGCD1 R
0x0139 2 Bit 23 22 21 20 19 18 17 Bit 16
W
DBGCD2 R
0x013A 2 Bit 15 14 13 12 11 10 9 Bit 8
W
DBGCD3 R
0x013B 2 Bit 7 6 5 4 3 2 1 Bit 0
W
DBGCDM1 R
0x013D 2 Bit 23 22 21 20 19 18 17 Bit 16
W
DBGCDM2 R
0x013E 2 Bit 15 14 13 12 11 10 9 Bit 8
W
DBGCDM3 R
0x013F 2 Bit 7 6 5 4 3 2 1 Bit 0
W
R 0 0 0
0x0140 DBGDCTL INST RW RWE reserved COMPE
W
0x0141- R 0 0 0 0 0 0 0 0
Reserved
0x0144 W
R
0x0145 DBGDAH DBGDA[23:16]
W
R
0x0146 DBGDAM DBGDA[15:8]
W
R
0x0147 DBGDAL DBGDA[7:0]
W
0x0148- R 0 0 0 0 0 0 0 0
Reserved
0x017F W
R 0 0
0x0200 MODRR0 SPI0SSRR SPI0RR SCI1RR S0L0RR2-0(1)
W
R
0x0201 MODRR1 M0C0RR2-0(2) PWMPRR1-0(3) PWM54RR PWM32RR PWM10RR
W
R
0x0202 MODRR2 T0C2RR1-0(4) T0C1RR4 T1IC0RR2 T0IC3RR1-0 T0IC1RR T0IC1RR0
4
W
0x0203– R 0 0 0 0 0 0 0 0
Reserved
0x0207 W
R 0 0 0 0 0 0 0
0x0208 ECLKCTL NECLK
W
R 0 0 0 0 0 0
0x0209 IRQCR IRQE IRQEN
W
R 0 0 0 0 0 0 0
0x020A PIMMISC OCPE1
W
0x020B– R 0 0 0 0 0 0 0 0
Reserved
0x020C W
R
0x020D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x020E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0210– R 0 0 0 0 0 0 0 0
Reserved
0x025F W
R 0 0 0 0 0 0
0x0260 PTE PTE1 PTE0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R 0 0 0 0 0 0 0 0
0x0261 Reserved
W
R 0 0 0 0 0 0 PTIE1 PTIE0
0x0262 PTIE
W
R 0 0 0 0 0 0 0 0
0x0263 Reserved
W
R 0 0 0 0 0 0
0x0264 DDRE DDRE1 DDRE0
W
R 0 0 0 0 0 0 0 0
0x0265 Reserved
W
R 0 0 0 0 0 0
0x0266 PERE PERE1 PERE0
W
R 0 0 0 0 0 0 0 0
0x0267 Reserved
W
R 0 0 0 0 0 0
0x0268 PPSE PPSE1 PPSE0
W
0x0269– R 0 0 0 0 0 0 0 0
Reserved
0x027F W
R
0x0280 PTADH PTADH72 PTADH62 PTADH52 PTADH42 PTADH32 PTADH22 PTADH12 PTADH0
W
R
0x0281 PTADL PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R
0x0284 DDRADH DDRADH72 DDRADH62 DDRADH52 DDRADH42 DDRADH32 DDRADH22 DDRADL12 DDRADH0
W
R
0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0
W
R
0x0286 PERADH PERADH72 PERADH62 PERADH52 PERADH42 PERADH32 PERADH22 PERADH12 PERADH0
W
R
0x0287 PERADL PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0
W
R
0x0288 PPSADH PPSADH72 PPSADH62 PPSADH52 PPSADH42 PPSADH32 PPSADH22 PPSADH12 PPSADH0
W
R
0x0289 PPSADL PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0
W
0x028A– R 0 0 0 0 0 0 0 0
Reserved
0x028B W
R
0x028C PIEADH PIEADH72 PIEADH62 PIEADH52 PIEADH42 PIEADH32 PIEADH22 PIEADH12 PIEADH0
W
R
0x028D PIEADL PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0
W
R
0x028E PIFADH PIFADH72 PIFADH62 PIFADH52 PIFADH42 PIFADH32 PIFADH22 PIFADH12 PIFADH0
W
R
0x028F PIFADL PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0
W
0x0290– R 0 0 0 0 0 0 0 0
Reserved
0x0297 W
R
0x0299 DIENADL DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x029A– R 0 0 0 0 0 0 0 0
Reserved
0x02BF W
R 0 0 0 0
0x02C0 PTT PTT3 PTT2 PTT1 PTT0
W
R 0 0 0 0
0x02C2 DDRT DDRT3 DDRT2 DDRT1 DDRT0
W
R 0 0 0 0
0x02C3 PERT PERT3 PERT2 PERT1 PERT0
W
R 0 0 0 0
0x02C4 PPST PPST3 PPST2 PPST1 PPST0
W
0x02C5– R 0 0 0 0 0 0 0 0
Reserved
0x02CF W
R 0 0
0x02D0 PTS PTS5(5) PTS45 PTS3 PTS2 PTS1 PTS0
W
R 0 0
0x02D2 DDRS DDRS55 DDRS45 DDRS3 DDRS2 DDRS1 DDRS0
W
R 0 0
0x02D3 PERS PERS55 PERS45 PERS3 PERS2 PERS1 PERS0
W
R 0 0
0x02D4 PPSS PPSS55 PPSS45 PPSS3 PPSS2 PPSS1 PPSS0
W
R 0 0 0 0 0 0 0 0
0x02D5 Reserved
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
R 0 0
0x02D6 PIES PIES55 PIES45 PIES3 PIES2 PIES1 PIES0
W
R 0 0
0x02D7 PIFS PIFS55 PIFS45 PIFS3 PIFS2 PIFS1 PIFS0
W
0x02D8– R 0 0 0 0 0 0 0 0
Reserved
0x02DE W
R 0 0
0x02DF WOMS WOMS55 WOMS45 WOMS3 WOMS2 WOMS1 WOMS0
W
0x02E0– R 0 0 0 0 0 0 0 0
Reserved
0x02EF W
R 0 0 0 0 0
0x02F0 PTP PTP25 PTP1 PTP0
W
R 0 0 0 0 0
0x02F2 DDRP DDRP25 DDRP1 DDRP0
W
R 0 0 0 0 0
0x02F3 PERP PERP25 PERP1 PERP0
W
R 0 0 0 0 0
0x02F4 PPSP PPSP25 PPSP1 PPSP0
W
R 0 0 0 0 0 0 0 0
0x02F5 Reserved
W
R 0 0 0 0
0x02F6 PIEP OCIE1 PIEP25 PIEP1 PIEP0
W
R 0 0 0 0
0x02F7 PIFP OCIF1 PIFP25 PIFP1 PIFP0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x02F8– R 0 0 0 0 0 0 0 0
Reserved
0x02FC W
R 0 0 0 0 0 0 0
0x02FD RDRP RDRP0
W
0x02FE– R 0 0 0 0 0 0 0 0
Reserved
0x0330 W
R 0 0 0 0 0 0 0 PTIL0
0x0331 PTIL2
W
R 0 0 0 0 0 0 0 0
0x0332 Reserved
W
R 0 0 0 0 0 0 0
0x0333 PTPSL2 PTPSL0
W
R 0 0 0 0 0 0 0
0x0334 PPSL2 PPSL0
W
R 0 0 0 0 0 0 0 0
0x0335 Reserved
W
R 0 0 0 0 0 0 0
0x0336 PIEL2 PIEL0
W
R 0 0 0 0 0 0 0
0x0337 PIFL2 PIFL0
W
Global Register
Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x0338– R 0 0 0 0 0 0 0 0
Reserved
0x0339 W
R 0 0 0 0 0 0 0
0x033A PTABYPL2 PTABYPL0
W
R 0 0 0 0 0 0 0
0x033B PTADIRL2 PTADIRL0
W
R 0 0 0 0 0 0 0
0x033C DIENL2 DIENL0
W
R 0 0 0 0 0 0 0
0x033D PTAENL2 PTAENL0
W
R 0 0 0 0 0 0 0
0x033E PIRL2 PIRL0
W
R 0 0 0 0 0 0 0
0x033F PTTEL2 PTTEL0
W
R 0 0 0 0 0
0x0382 FCCOBIX CCOBIX2 CCOBIX1 CCOBIX0
W
WSTAT
R FPOVRD 0 0 0 0 0 0
0x0383 FPSTAT ACK
W
R 0 ERSAREQ
0x0384 FCNFG CCIE IGNSF WSTAT[1:0] FDFD FSFD
W
R 0 0 0 0 0 0 0
0x0385 FERCNFG SFDIE
W
R 0 0 0 0 0 0
0x0387 FERSTAT DFDF SFDIF
W
R RNV6
0x0388 FPROT FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
W
R 0 0 0
0x0389 DFPROT DPOPEN DPS3 DPS2 DPS1 DPS0
W
R 0 0 0 0 0 0 0 0
0x038B FRSV1
W
R
0x038C FCCOB0HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x038D FCCOB0LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R
0x038E FCCOB1HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x038F FCCOB1LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R
0x0390 FCCOB2HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x0391 FCCOB2LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R
0x0392 FCCOB3HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x0393 FCCOB3LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R
0x0394 FCCOB4HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x0395 FCCOB4LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R
0x0396 FCCOB5HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8
W
R
0x0397 FCCOB5LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0
W
R 0 0 0 0 0 0 0 RDY
0x03C0 ECCSTAT
W
R 0 0 0 0 0 0 0
0x03C1 ECCIE SBEEIE
W
R 0 0 0 0 0 0 0
0x03C2 ECCIF SBEEIF
W
0x03C3 - R 0 0 0 0 0 0 0 0
Reserved
0x03C6 W
0x03C7 R
ECCDPTRH DPTR[23:16]
W
R
0x03C8 ECCDPTRM DPTR[15:8]
W
R 0
0x03C9 ECCDPTRL DPTR[7:1]
W
0x03CA - R 0 0 0 0 0 0 0 0
Reserved
0x03CB W
R
0x03CC ECCDDH DDATA[15:8]
W
R
0x03CD ECCDDL DDATA[7:0]
W
R 0 0
0x03CE ECCDE DECC[5:0]
W
0x03CF R 0 0 0 0 0
ECCDCMD ECCDRR ECCDW ECCDR
W
R
0x0400 TIM1TIOS IOS1 IOS0
W
R 0 0
0x0401 TIM1CFORC
W FOC1 FOC0
R
0x0402 Reserved
W
R
0x0403 Reserved
W
R
0x0404 TIM1TCNTH TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
R
0x0405 TIM1TCNTL TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
R 0 0 0
0x0406 TIM1TSCR1 TEN TSWAI TSFRZ TFFCA PRNT
W
R
0x0407 TIM1TTOV TOV1 TOV0
W
R
0x0408 TIM1TCTL1
W
R
0x0409 TIM1TCTL2 OM1 OL1 OM0 OL0
W
R
0x040A TIM1TCTL3
W
R
0x040B TIM1TCTL4 EDG1B EDG1A EDG0B EDG0A
W
R
0x040C TIM1TIE C1I C0I
W
R 0 0 0
0x040D TIM1TSCR2 TOI PR2 PR1 PR0
W
R
0x040E TIM1TFLG1 C1F C0F
W
R 0 0 0 0 0 0 0
0x040F TIM1TFLG2 TOF
W
R
0x0410 TIM1TC0H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x0411 TIM1TC0L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
R
0x0412 TIM1TC1H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x0413 TIM1TC1L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0414– R
Reserved
0x042B W
R
0x042C TIM1OCPD OCPD1 OCPD0
W
R
0x042D Reserved
W
R
0x042E TIM1PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
W
R
0x042F Reserved
W
R
0x0481 PWMPOL PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
W
R
0x0482 PWMCLK PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
PWMPRCL R 0 0
0x0483 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0
K W
R
0x0484 PWMCAE CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
R 0 0
0x0485 PWMCTL CON67 CON45 CON23 CON01 PSWAI PFRZ
W
PWMCLKA R
0x0486 PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0
B W
R 0 0 0 0 0 0 0 0
0x0487 RESERVED
W
R
0x0488 PWMSCLA Bit 7 6 5 4 3 2 1 Bit 0
W
0x048A - R 0 0 0 0 0 0 0 0
RESERVED
0x048B W
R Bit 7 6 5 4 3 2 1 Bit 0
0x048C PWMCNT0
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x048D PWMCNT1
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x048E PWMCNT2
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x048F PWMCNT3
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x0490 PWMCNT4
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x0491 PWMCNT5
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x0492 PWMCNT6
W 0 0 0 0 0 0 0 0
R Bit 7 6 5 4 3 2 1 Bit 0
0x0493 PWMCNT7
W 0 0 0 0 0 0 0 0
R
0x0494 PWMPER0 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x0495 PWMPER1 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x0496 PWMPER2 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x0497 PWMPER3 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x0498 PWMPER4 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x0499 PWMPER5 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x049A PWMPER6 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x049C PWMDTY0 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x049D PWMDTY1 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x049E PWMDTY2 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x049F PWMDTY32 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x04A0 PWMDTY42 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x04A1 PWMDTY52 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x04A2 PWMDTY62 Bit 7 6 5 4 3 2 1 Bit 0
W
R
0x04A3 PWMDTY72 Bit 7 6 5 4 3 2 1 Bit 0
W
0x04A4 - R 0 0 0 0 0 0 0 0
RESERVED
0x04AF W
R 0
0x0501 PMFCFG1 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA
W
R
0x0502 PMFCFG2 REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
W
R 0
0x0503 PMFCFG3 PMFWAI PMFFRZ VLMODE PINVC PINVB PINVA
W
R 0 0
0x0504 PMFFEN FEN5 FEN4 FEN3 FEN2 FEN1 FEN0
W
R 0 0
0x0505 PMFFMOD FMOD5 FMOD4 FMOD3 FMOD2 FMOD1 FMOD0
W
R 0 0
0x0506 PMFFIE FIE5 FIE4 FIE3 FIE2 FIE1 FIE0
W
R 0 0
0x0507 PMFFIF FIF5 FIF4 FIF3 FIF2 FIF1 FIF0
W
R 0 0 0 0
0x0508 PMFQSMP0 QSMP5 QSMP4
W
R
0x0509 PMFQSMP1 QSMP3 QSMP2 QSMP1 QSMP0
W
0x050A- R 0 0 0 0 0 0 0 0
Reserved
0x050B W
R 0 0
0x050C PMFOUTC OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0
W
R 0 0
0x050D PMFOUTB OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
W
R 0 0 0
0x050F PMFCCTL ISENS IPOLC IPOLB IPOLA
W
R
0x0510 PMFVAL0 PMFVAL0
W
R
0x0511 PMFVAL0 PMFVAL0
W
R
0x0512 PMFVAL1 PMFVAL1
W
R
0x0513 PMFVAL1 PMFVAL1
W
R
0x0514 PMFVAL2 PMFVAL2
W
R
0x0515 PMFVAL2 PMFVAL2
W
R
0x0516 PMFVAL3 PMFVAL3
W
R
0x0517 PMFVAL3 PMFVAL3
W
R
0x0519 PMFVAL4 PMFVAL4
W
R
0x051A PMFVAL5 PMFVAL5
W
R
0x051B PMFVAL5 PMFVAL5
W
R 0 0
0x051E PMFICCTL PECC PECB PECA ICCC ICCB ICCA
W
R 0 0
0x051F PMFCINV CINV5 CINV4 CINV3 CINV2 CINV1 CINV0
W
R 0 0 0
0x0520 PMFENCA PWMENA GLDOKA RSTRTA LDOKA PWMRIEA
W
R
0x0521 PMFFQCA LDFQA HALFA PRSCA PWMRFA
W
R 0 PMFCNTA
0x0522 PMFCNTA
W
R PMFCNTA
0x0523 PMFCNTA
W
R 0
0x0524 PMFMODA PMFMODA
W
R
0x0525 PMFMODA PMFMODA
W
R 0 0 0 0
0x0526 PMFDTMA PMFDTMA
W
R
0x0527 PMFDTMA PMFDTMA
W
R 0 0 0
0x0528 PMFENCB PWMENB GLDOKB RSTRTB LDOKB PWMRIEB
W
R 0 PMFCNTB
0x052A PMFCNTB
W
R PMFCNTB
0x052B PMFCNTB
W
R 0
0x052C PMFMODB PMFMODB
W
R
0x052D PMFMODB PMFMODB
W
R 0 0 0 0
0x052E PMFDTMB PMFDTMB
W
R
0x052F PMFDTMB PMFDTMB
W
R 0 0 0
0x0530 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC
W
R
0x0531 PMFFQCC LDFQC HALFC PRSCC PWMRFC
W
R 0 PMFCNTC
0x0532 PMFCNTC
W
R PMFCNTC
0x0533 PMFCNTC
W
R 0
0x0534 PMFMODC PMFMODC
W
R
0x0535 PMFMODC PMFMODC
W
R 0 0 0 0
0x0536 PMFDTMC PMFDTMC
W
R
0x0537 PMFDTMC PMFDTMC
W
R
0x0538 PMFDMP0 DMP05 DMP04 DMP03 DMP02 DMP01 DMP00
W
R
0x0539 PMFDMP1 DMP15 DMP14 DMP13 DMP12 DMP11 DMP10
W
R
0x053B PMFDMP3 DMP35 DMP34 DMP33 DMP32 DMP31 DMP30
W
R
0x053C PMFDMP4 DMP45 DMP44 DMP43 DMP42 DMP41 DMP40
W
R
0x053D PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50
W
R 0 0
0x053E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0
W
R 0 0 0 0 0 0 0 0
0x053F Reserved
W
R 0 0 0 0 0
0x0580 PTUE PTUFRZ TG1EN TG0EN
W
R 0 0 0 0 0 0 0
0x0581 PTUC PTULDOK
W
R 0 0 0 0 0 0 0
0x0582 PTUIEH PTUROIE
W
R
0x0583 PTUIEL TG1AEIE TG1REIE TG1TEIE TG1DIE TG0AEIE TG0REIE TG0TEIE TG0DIE
W
R 0 0 0 0 0 0
0x0584 PTUIFH PTUDEEF PTUROIF
W
R
0x0585 PTUIFL TG1AEIF TG1REIF TG1TEIF TG1DIF TG0AEIF TG0REIF TG0TEIF TG0DIF
W
R 0 0 0 0 0 0 0
0x0586 TG0LIST TG0LIST
W
R 0 0 0 TG0TNUM[4:0]
0x0587 TG0TNUM
W
R TG0TV[15:8]
0x0588 TG0TVH
W
R 0 0 0 0 0 0 0
0x058A TG1LIST TG1LIST
W
R 0 0 0 TG1TNUM4:0]
0x058B TG1TNUM
W
R TG1TV[15:8]
0x058C TG1TVH
W
R TG1TV[7:0]
0x058D TG1TVL
W
R PTUCNT[15:8]
0x058E PTUCNTH
W
R PTUCNT[7:0]
0x058F PTUCNTL
W
R 0 0 0 0 0 0 0 0
0x0590 Reserved
W
R
0x0591 PTUPTRH PTUPTR[23:16]
W
R
0x0592 PTUPTRM PTUPTR[15:8]
W
R 0
0x0593 PTUPTRL PTUPTR[7:1]
W
R 0 0 0 0 0 0 0 0
0x0594 TG0L0IDX
W
R 0
0x0595 TG0L1IDX TG0L1IDX[6:0]
W
R 0
0x0596 TG1L0IDX TG1L0IDX[6:0]
W
R 0
0x0597 TG1L1IDX TG1L1IDX[6:0]
W
0x0598 - R 0 0 0 0 0 0 0 0
Reserved
0x059E W
R 0 0 0 0 0
0x059F PTUDEBUG PTUREPE PTUT1PE PTUT0PE
W PTUFRE TG1FTE TG0FTE
R
0x05C0 TIM0TIOS IOS3 IOS2 IOS1 IOS0
W
R 0 0 0 0 0 0 0 0
0x05C1 TIM0CFORC
W FOC3 FOC2 FOC1 FOC0
R
0x05C2 Reserved
W
R
0x05C3 Reserved
W
R
0x05C4 TIM0TCNTH TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
R
0x05C5 TIM0TCNTL TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
R 0 0 0
0x05C6 TIM0TSCR1 TEN TSWAI TSFRZ TFFCA PRNT
W
R
0x05C7 TIM0TTOV TOV3 TOV2 TOV1 TOV0
W
R
0x05C8 TIM0TCTL1
W
R
0x05C9 TIM0TCTL2 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
W
R
0x05CA TIM0TCTL3
W
R
0x05CB TIM0TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
R
0x05CC TIM0TIE C3I C2I C1I C0I
W
R 0 0 0
0x05CD TIM0TSCR2 TOI PR2 PR1 PR0
W
R
0x05CE TIM0TFLG1 C3F C2F C1F C0F
W
R 0 0 0 0 0 0 0
0x05CF TIM0TFLG2 TOF
W
R
0x05D0 TIM0TC0H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x05D1 TIM0TC0L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
R
0x05D2 TIM0TC1H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x05D3 TIM0TC1L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
R
0x05D4 TIM0TC2H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x05D5 TIM0TC2L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
R
0x05D6 TIM0TC3H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
R
0x05D7 TIM0TC3L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x05D8– R
Reserved
0x05DF W
R
0x05E0 Reserved
W
R
0x05E1 Reserved
W
R
0x05E2 Reserved
W
R
0x05E3 Reserved
W
0x05E4– R
Reserved
0x05EB W
R
0x05EC TIM0OCPD OCPD3 OCPD2 OCPD1 OCPD0
W
R
0x05ED Reserved
W
R
0x05EE TIM0PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
W
R
0x05EF Reserved
W
R 0 0 RIDX_IMD
0x060F ADC0IMDRI_1
W
R CSL_EOL RVL_EOL 0 0 0 0 0 0
0x0610 ADC0EOLRI
W
R 0 0 0 0 0 0 0 0
0x0611 Reserved
W
R 0 0 0 0 0 0 0 0
0x0612 Reserved
W
R Reserved 0 0
0x0613 Reserved
W
R 0 0
0x0614 ADC0CMD_0 CMD_SEL INTFLG_SEL[3:0]
W
ADC0CMD_1 R
0x0615 VRH_SEL VRL_SEL CH_SEL[5:0]
(not ZVMC256) W
ADC0CMD_1 R
0x0615 VRH_SEL[1:0] CH_SEL[5:0]
(ZVMC256) W
R 0 0 RIDX_IMD
0x064F ADC1IMDRI_1
W
R CSL_EOL RVL_EOL 0 0 0 0 0 0
0x0650 ADC1EOLRI
W
R 0 0 0 0 0 0 0 0
0x0651 Reserved
W
R 0 0 0 0 0 0 0 0
0x0652 Reserved
W
R 0 0 0 0 0 0 0 0
0x0653 Reserved
W
R 0 0
0x0654 ADC1CMD_0 CMD_SEL INTFLG_SEL[3:0]
W
ADC1CMD_1 R
0x0655 VRH_SEL VRL_SEL CH_SEL[5:0]
(not ZVMC256) W
ADC1CMD_1 R
0x0655 VRH_SEL[1:0] CH_SEL[5:0]
(ZVMC256) W
R 0 0
0x06A0 GDUE GWP GCS1E GBOE GCS0E GCPE GFDE
W
R GVLSLVL
0x06A1 GDUCTR GHHDLVL (1) GBKTIM2[3:0] GBKTIM1[1:0]
W
R 0 0 0
0x06A2 GDUIE GOCIE[1:0] GDSEIE GHHDIE GLVLSIE
W
R 0 0
0x06A3 GDUDSE GDHSIF[2:0] GDLSIF[2:0]
W
R 0 0
0x06A5 GDUSRC GSRCHS[2:0] GSRCLS[2:0]
W
R 0
0x06A6 GDUF GSUF GHHDF GLVLSF GOCIF[1:0] GHHDIF GLVLSIF
W
R 0
0x06A7 GDUCLK1 GBOCD[4:0] GBODC[1:0]
W
R 0 0 0 0
0x06A8 GDUBCL GBCL[3:0]
W
R 0 0 0 0 0 0
0x06A9 GDUPHMUX GPHMX[1:0]
W
R 0 0
0x06AA GDUCSO GCSO1[2:0] GCSO0[2:0]
W
R
0x06AB GDUDSLVL GDSFHS1 GDSLHS[2:0] GDSFLS1 GDSLLS[2:0]
W
R 0 0 0 0 0 GPHL[2:0]
0x06AC GDUPHL
W
R 0 0 0 0
0x06AD GDUCLK2 GCPCD[3:0]
W
R 0
0x06AE GDUOC0 GOCA0 GOCE0 GOCT0[4:0](2)
W
R 0
0x06AF GDUOC1 GOCA1 GOCE1 GOCT1[4:0](3)
W
GDUCTR1(4) R 0 0 0 0 0
0x06B0 GSRMOD[1:0] TDEL
W
0x06B1- R
Reserved
0x06BF W
CPMU R 0 0 0 0 0 0 0 0
0x06C1
RESERVED01 W
CPMU R 0 0 0 0 0 0 0 0
0x06C2
RESERVED02 W
R 0 0 0
0x06C3 CPMURFLG PORF LVRF COPRF OMRF PMRF
W
CPMU R
0x06C4 VCOFRQ[1:0] SYNDIV[5:0]
SYNR W
CPMU R 0 0
0x06C5 REFFRQ[1:0] REFDIV[3:0]
REFDIV W
CPMU R 0 0 0
0x06C6 POSTDIV[4:0]
POSTDIV W
R 0 0 LOCK 0 UPOSC
0x06C7 CPMUIFLG RTIF LOCKIF OSCIF
W
R 0 0 0 0 0
0x06C8 CPMUINT RTIE LOCKIE OSCIE
W
R COP RTI COP
0x06C9 CPMUCLKS PLLSEL PSTP CSAD PRE PCE
W OSCSEL1 OSCSEL OSCSEL0
R 0 0 0 0 0 0
0x06CA CPMUPLL FM1 FM0
W
R
0x06CB CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
R 0 0 0
0x06CC CPMUCOP WCOP RSBCK WRTMAS CR2 CR1 CR0
W
K
RESERVED R 0 0 0 0 0 0 0 0
0x06CD
CPMUTEST0 W
CPMU R 0 0 0 0 0 0 0 0
0x06CF
ARMCOP W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPMU R 0 0 0 HTDS
0x06D0 VSEL HTE HTIE HTIF
HTCTL W
CPMU R 0 0 0 0 LVDS
0x06D1 VDDSIE LVIE LVIF
LVCTL W
CPMU R 0 0
0x06D2 APICLK APIES APIEA APIFE APIE APIF
APICTL W
CPMUACLKT R 0 0
0x06D3 ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0
R W
R
0x06D4 CPMUAPIRH APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
R
0x06D5 CPMUAPIRL APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
RESERVED R 0 0 0 0 0 0 0 0
0x06D6
CPMUTEST3 W
R 0 0 0
0x06D7 CPMUHTTR HTOE HTTR3 HTTR2 HTTR1 HTTR0
W
CPMU R 0
0x06D8 TCTRIM[4:0] IRCTRIM[9:8]
IRCTRIMH W
CPMU R
0x06D9 IRCTRIM[7:0]
IRCTRIML W
R
0x06DA CPMUOSC OSCE Reserved Reserved Reserved
W
R 0 0 0 0 0 0 0
0x06DB CPMUPROT PROT
W
RESERVED R 0 0 0 0 0
0x06DC 0 0 0
CPMUTEST2 W
CPMU R 0
0x06DD VRH2EN VRH1EN EXTS2ON EXTS1ON EXTCON EXTXON INTXON
VREGCTL W
R 0 0 0 0 0 0
0x06DE CPMUOSC2 OMRE OSCMOD
W
R SCS2 SCS1 LVDS2 LVDS1
0x06DF CPMUVDDS SCS2IF SCS1IF LVS2IF LVS1IF
W
R 0 0 0
0x06F0 BATE BVHS BVLS[1:0] BSUAE BSUSE
W
R 0 0 0 0 0 0 BVHC BVLC
0x06F1 BATSR
W
R 0 0 0 0 0 0
0x06F2 BATIE BVHIE BVLIE
W
R 0 0 0 0 0 0
0x06F3 BATIF BVHIF BVLIF
W
0x06F4 - R 0 0 0 0 0 0 0 0
Reserved
0x06F5 W
0x06F6 - R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0x06F7 W
R
0x0701 SCI0BDL1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
R
0x0702 SCI0CR11 LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
R 0 0 0 0 BERRV
0x0700 SCI0ASR12 RXEDGIF BERRIF BKDIF
W
0x0701 R 0 0 0 0 0
SCI0ACR12 RXEDGIE BERRIE BKDIE
W
R 0 0
0x0702 SCI0ACR22 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE
W
R
0x0703 SCI0CR2 TIE TCIE RIE ILIE TE RE RWU SBK
W
R 0 0 RAF
0x0705 SCI0SR2 AMAP TXPOL RXPOL BRK13 TXDIR
W
R R7 R6 R5 R4 R3 R2 R1 R0
0x0707 SCI0DRL
W T7 T6 T5 T4 T3 T2 T1 T0
1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
R
0x0711 SCI1BDL1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
R
0x0712 SCI1CR11 LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
R 0 0 0 0 BERRV
0x0710 SCI1ASR12 RXEDGIF BERRIF BKDIF
W
R 0 0 0 0 0
0x0711 SCI1ACR12 RXEDGIE BERRIE BKDIE
W
R 0 0
0x0712 SCI1ACR22 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE
W
R
0x0713 SCI1CR2 TIE TCIE RIE ILIE TE RE RWU SBK
W
R 0 0 RAF
0x0715 SCI1SR2 AMAP TXPOL RXPOL BRK13 TXDIR
W
R R8 0 0 0 0 0 0
0x0716 SCI1DRH T8
W
R R7 R6 R5 R4 R3 R2 R1 R0
0x0717 SCI1DRL
W T7 T6 T5 T4 T3 T2 T1 T0
1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
R 0 0 0
0x0781 SPI0CR2 XFRW MODFEN BIDIROE SPISWAI SPC0
W
R 0 0
0x0782 SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
W
R R7 R6 R5 R4 R3 R2 R1 R0
0x0785 SPI0DRL
W T7 T6 T5 T4 T3 T2 T1 T0
R
0x0786 Reserved
W
R
0x0787 Reserved
W
R 0 0 0 0
0x0981 LP0CR LPE RXONLY LPWUE LPPUE
W
R
0x0982 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R LPDTDIS 0 0 0 0 0
0x0983 LP0SLRM LPSLR1 LPSLR0
W
R
0x0984 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R LPDT 0 0 0 0 0 0 0
0x0985 LP0SR
W
R 0 0 0 0 0 0
0x0986 LP0IE LPDTIE LPOCIE
W
R 0 0 0 0 0 0
0x0987 LP0IF LPDTIF LPOCIF
W
R 0
0x0991 CPCR CPE SPE WUPE1-0 SLR2-0
W
R
0x0992 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x0994 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R
0x0995 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
R 0 0 0 0 0
0x0996 CPIE CPVFIE CPDTIE CPOCIE
W
R 0
0x0997 CPIF CHVHIF CHVLIF CLVHIF CLVLIF CPDTIF CHOCIF CLOCIF
W
= Unimplemented or Reserved
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