COA Lab Manual

Computer Organization & Architecture Lab Manual
Greater Noida, U.P-201306
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
LAB MANUAL
Computer Organization & Architecture Lab
Subject Code: ETCS 250
SEMESTER - IV
Prepared By:
Garima Mehra
Assistant Professor
Department of Computer Science & Engineering
JIMS Engineering Management Technical Campus -Department of Computer Science & Engineering
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Syllabus
UNIT- I
Computer Arithmetic and Register transfer language:
Unsigned notation, signed notation, binary coded decimal, floating point numbers, IEEE 754 floating point standard,
Micro-operation, Bus and Memory Transfers, Bus Architecture, Bus Arbitration, Arithmetic Logic, Shift Micro
operation, Arithmetic Logic Shift Unit.
[T1,T2][No. of hrs. 11]
UNIT- II
Instruction set architecture & computer organization:
Levels of programming languages, assembly language instructions, 8085 instruction set architecture, Instruction
Codes, Computer Registers, Computer Instructions, Timing & Control, Instruction Cycle, Memory Reference
Instructions, Input-Output and Interrupts
[T1,T2][No. of hrs. 11]
UNIT- III
Control Design:
Instruction sequencing & interpretation, Hardwired & Micro Programmed (Control Unit), Micrprogrammed
computers, Microcoded CPU: Pentium processor. Specifying a CPU, Design & implementation of simple CPU,
General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Internal architecture of
8085 microprocessor.
[T1,T2][No. of hrs. 11]
UNIT- IV
Memory & Input/Output organization: Memory Technology, Main Memory (RAM and ROM Chips), Virtual
memory, High-speed memories
Asynchronous Data Transfers, Programmed I/O, interrupts, Direct memory Access, Serial communication, UARTs,
RS-232-C & RS-422 standard
[T1,T2][No. of hrs. 11]
Text Books:
[T1] J. D. Carpinelli, “Computer Systems Organization and Architecture”, Pearson Education, 2006.
[T2] J. P. Hayes, “Computer Architecture and Organization”, McGraw Hill, 1988.
Reference Books:
[R1] J. L Hennessy and D. A. Patterson, “Computer Architecture: A quantitative approach”, Morgon Kauffman,
1992.
[R2] W. Stallings, “Computer organization and Architecture”, PHI, 7th ed, 2005.
[R3] B. Parhami, “Computer Architecture: From Microprocessors to Supercomputers”, Oxford University press,
2006.
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Hardware and Software Requirements
Software Requirement: j8085 simulator, java development kit
Hardware Requirements:
a) Microsoft Windows 7 (SP1) and Windows 8 Professional
operating system; Apple Mac OS X 10.9.5 and 10.10.x
operating system
b) P-IV C2D 2.9 GHZ
c) 1.44 FDD LAN Card
d) 2 GB RAM Cabinet
e) 320 GB HDD
f) Three-button mouse
g) Keyboard
h) 14” TFT Monitor
i) Laser Printer
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How to start with j8085 simulator.
An 8085 simulator on Java platform. Supports all 8085 interrupts and instructions. User enters
8085 assembly language programs, whose simulation is performed by the software. For
academic purposes only.
Features
 Supports all 8085 instructions
 Simulates 8085 Interrupts - INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
 An easy-to-use GUI
STEP 1: click onto icon of simulator, window will open on the screen
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Step 2: Write the program in the white blank area
Step 3: Press Ctrl+S button to save the program. A wizard will open, write program name
and press save button to save program.
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Step 4: Press the green triangle button in the top ribbon, to run the program.
Simultaneously the values in Registers will also change.
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Lab Assignment – 1
Assignment Date: Submission Date:
Objective: To study 8085 microprocessor in detail.
1. Introduction to 8085
The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and
introduced in 1976.[2] It is a software-binary compatible with the more-famous Intel 8080 with
only two minor instructions added to support its added interrupt and serial input/output features.
However, it requires less support circuitry, allowing simpler and less
expensive microcomputer systems to be built.
The "5" in the part number highlighted the fact that the 8085 uses a single +5-volt (V) power
supply by using depletion-mode transistors, rather than requiring the +5 V, −5 V and +12 V
supplies needed by the 8080. This capability matched that of the competing Z80, a popular 8080-
derived CPU introduced the year before. These processors could be used in computers running
the CP/M operating system.
The 8085 is supplied in a 40-pin DIP package. To maximise the functions on the available pins,
the 8085 uses a multiplexed address/data (AD^0-AD^7) bus. However, an 8085 circuit requires
an 8-bit address latch, so Intel manufactured several support chips with an address latch built in.
These include the 8755, with an address latch, 2 KB of EPROM and 16 I/O pins, and the 8155
with 256 bytes of RAM, 22 I/O pins and a 14-bit programmable timer/counter. The multiplexed
address/data bus reduced the number of PCB tracks between the 8085 and such memory and I/O
chips.
Both the 8080 and the 8085 were eclipsed by the Zilog Z80 for desktop computers, which took
over most of the CP/M computer market, as well as a share of the booming home-
computer market in the early-to-mid-1980s.
The 8085 had a long life as a controller, no doubt thanks to its built-in serial I/O and 5 prioritized
interrupts, arguably microcontroller-like features that the Z80 CPU did not have. Once designed
into such products as the DECtape II controller and the VT102 video terminal in the late 1970s,
the 8085 served for new production throughout the lifetime of those products. This was typically
longer than the product life of desktop computers.
2. Features of 8085
It has the following configuration −
 8-bit data bus

 16-bit address bus, which can address upto 64KB
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 A 16-bit program counter

 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.
3. Internal Architecture and Functional Block Diagram of 8085
8085 consists of the following functional units −
Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction,
AND, OR, etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so
that the program counter points to the memory address of the next instruction that is going to be
executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
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Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Instruction register and decoder
It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following are
the timing and control signals, which control external and internal circuits −
 Control Signals: READY, RD’, WR’, ALE
 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is completed,
the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are
connected to these buses; the CPU can exchange the desired data with the memory and I/O
chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location
to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O
devices.
8085 Architecture
We have tried to depict the architecture of 8085 with this following image −
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4. Pin Configuration of 8085

The following image depicts the pin diagram of 8085 Microprocessor −
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The pins of a 8085 microprocessor can be classified into seven groups −

Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3 status
signals.
Three control signals are RD, WR & ALE.
 RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
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 ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
 CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to perform
a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will
discuss interrupts in detail in interrupts section.
 INTA − It is an interrupt acknowledgment signal.
 RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
 RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
 READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
 HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
 HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after
the HOLD signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
 SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
 SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.
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5. Addressing modes of 8085

These are the instructions used to transfer the data from one register to another register, from
the memory to the register, and from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups −
Immediate addressing mode
In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand. For
example: MVI K, 20F: means 20F is copied into register K.
Register addressing mode
In this mode, the data is copied from one register to another. For example:MOV K, B: means
data in register B is copied to register K.
Direct addressing mode
In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000K: means the data at address 5000K is copied to register B.
Indirect addressing mode
In this mode, the data is transferred from one register to another by using the address pointed by
the register. For example: MOV K, B: means data is transferred from the memory address
pointed by the register to the register K.
Implied addressing mode
This mode doesn’t require any operand; the data is specified by the opcode itself. For
example: CMP.
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to
the processor so, the interrupt address needs to be sent externally by the device to
perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example:RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software interrupts in
8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts,
i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
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Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement.
TRAP has the highest priority, then RST7.5 and so on.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting source
is called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is
enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to
backup memory. This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the
PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by
resetting the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each
instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
6. Instruction format
An instruction is a command to the microprocessor to perform a given task on a specified
data. Each instruction has two parts: one is task to be performed, called the operation code
(opcode), and the second is the data to be operated on, called the operand. The operand (or
data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal
register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is
implicit.
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Instruction word size

The 8085 instruction set is classified into the following three groups according to word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.
1 One-Byte Instructions : A 1-byte instruction includes the opcode and operand in the same
byte. Operand(s) are internal register and are coded into the instruction
These instructions are 1-byte instructions performing three different tasks. In the first instruction,
both operand registers are specified. In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the
implicit operand. These instructions are stored in 8- bit binary format in memory; each requires
one memory location.
MOV rd, rs
rd ß rs copies contents of rs into rd.

Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the
destination of the data, sss is the code of the source register.
Example: MOV A,B
Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such
processors).
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ADD r
AßA+r
2 Two-Byte Instructions: In a two-byte instruction, the first byte specifies the operation code
and the second byte specifies the operand. Source operand is a data byte immediately following
the opcode. For example:
The instruction would require two memory locations to store in memory.

MVI r,dat
r ß data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes.
This is an example of immediate addressing.
ADI data
A ß A + data
OUT port 0011 1110

DATA
Where port is an 8-bit device address. (Port) ß A.
Since the byte is not the data but points directly to where it is located this is called direct
addressing.
3 Three-Byte Instructions: In a three-byte instruction, the first byte specifies the opcode, and
the following two bytes specify the 16-bit address. Note that the second byte is the low-order
address and the third byte is the high-order address.
opcode + data byte + data byte


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This instruction would require three memory locations to store in memory.
Three byte instructions - opcode + data byte + data byte
LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are 16-
bit data in L H order of significance.
rp ß data16
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.
LDA addr
A ß (addr) Addr is a 16-bit address in L H order.
Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing.
7. Instruction set of 8085

7.1 Control Instructions
Opcode Operand Explanation of Description

Instruction
NOP none No operation No operation is performed. The instruction is fetched and decoded.
However no operation is executed.
Example: NOP
HLT none Halt and enter The CPU finishes executing the current instruction and halts any further
wait state execution. An interrupt or reset is necessary to exit from the halt state.
Example: HLT
DI none Disable interrupts The interrupt enable flip-flop is reset and all the interrupts except the
TRAP are disabled. No flags are affected.
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Example: DI
EI none Enable interrupts The interrupt enable flip-flop is set and all interrupts are enabled. No
flags are affected. After a system reset or the acknowledgement of an
interrupt, the interrupt enable flipflop is reset, thus disabling the
interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI
RIM none Read interrupt This is a multipurpose instruction used to read the status of interrupts
mas 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight
bits in the accumulator with the following interpretations.
Example: RIM
SIM none Set interrupt This is a multipurpose instruction and used to implement the 8085
mask interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets
the accumulator contents as follows.
Example: SIM
7.2 LOGICAL INSTRUCTIONS

Instruction
CMP R Compare register The contents of the operand (register or memory) are M compared
M or memory with with the contents of the accumulator. Both contents are preserved .
accumulator The result of the comparison is shown by setting the flags of the PSW
as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
CPI 8-bit Compare The second byte (8-bit data) is compared with the contents of the
data immediate with accumulator. The values being compared remain unchanged. The
accumulator result of the comparison is shown by setting the flags of the PSW as
follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
ANA R Logical AND The contents of the accumulator are logically ANDed with M the
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M register or memory contents of the operand (register or memory), and the result is placed
with accumulator in the accumulator. If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are modified to
reflect the result of the operation. CY is reset. AC is set.
Example: ANA B or ANA M
ANI 8-bit Logical AND The contents of the accumulator are logically ANDed with the
data immediate with 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 86H
XRA R Exclusive OR The contents of the accumulator are Exclusive ORed with M the
reflect the result of the operation. CY and AC are reset.
Example: XRA B or XRA M
XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive ORed with the 8-bit
data immediate with data (operand) and the result is placed in the accumulator. S, Z, P are
accumulator modified to reflect the result of the operation. CY and AC are reset.
Example: XRI 86H
ORA R Logical OR The contents of the accumulator are logically ORed with M the
reflect the result of the operation. CY and AC are reset.
Example: ORA B or ORA M
ORI 8-bit Logical OR The contents of the accumulator are logically ORed with the 8-bit
data immediate with data (operand) and the result is placed in the accumulator. S, Z, P are
accumulator modified to reflect the result of the operation. CY and AC are reset.
Example: ORI 86H
RLC none Rotate Each binary bit of the accumulator is rotated left by one position. Bit
accumulator left D7 is placed in the position of D0 as well as in the Carry flag. CY is
modified according to bit D7. S, Z, P, AC are not affected.
Example: RLC
RRC none Rotate Each binary bit of the accumulator is rotated right by one position. Bit
accumulator right D0 is placed in the position of D7 as well as in the Carry flag. CY is
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Example: RRC
RAL none Rotate Each binary bit of the accumulator is rotated left by one position
accumulator left through the Carry flag. Bit D7 is placed in the Carry flag, and the
through carry Carry flag is placed in the least significant position D0. CY is
Example: RAL
RAR none Rotate Each binary bit of the accumulator is rotated right by one position
accumulator right through the Carry flag. Bit D0 is placed in the Carry flag, and the
through carry Carry flag is placed in the most significant position D7. CY is
Example: RAR
CMA none Complement The contents of the accumulator are complemented. No flags are
accumulator affected.
Example: CMA
CMC none Complement carry The Carry flag is complemented. No other flags are affected.
Example: CMC
STC none Set Carry Set Carry

Example: STC
7.3 BRANCHING INSTRUCTIONS
Opcode Operand Explanation Description

of Instruction
JMP 16-bit Jump The program sequence is transferred

address unconditionally to the memory location specified by
the 16-bit address given in the
operand.
Example: JMP 2034H or JMP XYZ
Flag 16-bit Jump The program sequence is transferred

Opcode Description address conditionally to the memory location specified by
Status
JC Jump on Carry CY = 1 operand based on the specified flag
Jump on no of the PSW as described below.
JNC CY = 0
Carry Example: JZ 2034H or JZ XYZ
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Jump on
JP S=0
positive
JM Jump on minus S=1
JZ Jump on zero Z=1
JNZ Jump on no zero Z = 0
Jump on parity
JPE P=1
even
Jump on parity
JPO P=0
odd
Flag 16-bit Unconditional The program sequence is transferred

Opcode Description address subroutine call to the memory location specified by
Status
CC Call on Carry CY = 1 operand. Before the transfer, the
Call on no address of the next instruction after
CNC CY = 0
Carry CALL (the contents of the program
CP Call on positive S = 0 counter) is pushed onto the stack.
Example: CALL 2034H or CALL
CM Call on minus S=1 XYZ
CZ Call on zero Z=1
CNZ Call on no zero Z = 0
Call on parity
CPE P=1
even
Call on parity
CPO P=0
odd
RET none Return from The program sequence is transferred

subroutine from the subroutine to the calling
unconditionally program. The two bytes from the top
of the stack are copied into the
program counter,and program
execution begins at the new address.
Example: RET
Flag none Return from The program sequence is transferred

Opcode Description subroutine from the subroutine to the calling
Status
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RC Return on Carry CY = 1 conditionally program based on the specified flag

of the PSW as described below. The
Return on no two bytes from the top of the stack
RNC CY = 0
Carry are copied into the program counter,
Return on and program execution begins at the
RP S=0
positive new address.
RM Return on minus S = 1 Example: RZ
RZ Return on zero Z=1

Return on no
RNZ Z=0
zero
Return on parity
RPE P=1
even
Return on parity
RPO P=0
odd
PCHL none Load program The contents of registers H and L

counter with are copied into the program counter.
HL contents The contents of H are placed as the
high-order byte and the contents of L
as the low-order byte.
Example: PCHL
RST 0-7 Restart The RST instruction is equivalent to

a 1-byte call instruction to one of
eight memory locations depending
upon the number. The instructions
are generally used in conjunction
with interrupts and inserted using
external hardware. However these
can be used as software instructions
in a program to transfer program
execution to one of the eight
locations. The addresses are:
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
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RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four additional
interrupts and these interrupts
generate RST instructions internally
and thus do not require any external
hardware. These instructions and
their Restart addresses are:
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
7.4 Arithmetic Instructions

Instruction
ADD R Add register or The contents of the operand (register or memory) are added to
M memory, to the contents of the accumulator and the result is stored in the
accumulator accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADD B or ADD M
ADC R Add register to The contents of the operand (register or memory) and M the
M accumulator with Carry flag are added to the contents of the accumulator and the
carry result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the
addition.
Page 23
Example: ADC B or ADC M
ADI 8-bit data Add immediate to The 8-bit data (operand) is added to the contents of the
accumulator accumulator and the result is stored in the accumulator. All flags
are modified to reflect the result of the addition.
Example: ADI 45H
ACI 8-bit data Add immediate to The 8-bit data (operand) and the Carry flag are added to the
accumulator with contents of the accumulator and the result is stored in the
carry accumulator. All flags are modified to reflect the result of the
addition.
Example: ACI 45H
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in
16-bit data immediate the operand.
Example: LXI H, 2034H or LXI H, XYZ
DAD Reg. pair Add register pair The 16-bit contents of the specified register pair are added to the
to H and L contents of the HL register and the sum is stored in the HL
registers register. The contents of the source register pair are not altered. If
the result is larger than 16 bits, the CY flag is set. No other flags
are affected.
Example: DAD H
SUB R Subtract register or The contents of the operand (register or memory ) are subtracted
M memory from from the contents of the accumulator, and the result is stored in
accumulator the accumulator. If the operand is a memory location, its location
is specified by the contents of the HL registers. All flags are
modified to reflect the result of the subtraction.
Example: SUB B or SUB M
SBB R Subtract source The contents of the operand (register or memory ) and M the
M and borrow from Borrow flag are subtracted from the contents of the accumulator
accumulator and the result is placed in the accumulator. If the operand is a
memory location, its location is specified by the contents of the
HL registers. All flags are modified to reflect the result of the
subtraction.
Example: SBB B or SBB M
SUI 8-bit data Subtract The 8-bit data (operand) is subtracted from the contents of the
immediate from accumulator and the result is stored in the accumulator. All flags
accumulator are modified to reflect the result of the subtraction.
Example: SUI 45H
Page 24
SBI 8-bit data Subtract The contents of register H are exchanged with the contents of
immediate from register D, and the contents of register L are exchanged with the
accumulator with contents of register E.
borrow Example: XCHG
INR R Increment register The contents of the designated register or memory) are
M or memory by 1 incremented by 1 and the result is stored in the same place. If the
operand is a memory location, its location is specified by the
contents of the HL registers.
Example: INR B or INR M
INX R Increment register The contents of the designated register pair are incremented by 1
pair by 1 and the result is stored in the same place.
Example: INX H
DCR R Decrement register The contents of the designated register or memory are M
M or memory by 1 decremented by 1 and the result is stored in the same place. If the
operand is a memory location, its location is specified by the
Example: DCR B or DCR M
DCX R Decrement register The contents of the designated register pair are decremented by 1
pair by 1 and the result is stored in the same place.
Example: DCX H
DAA none Decimal adjust The contents of the accumulator are changed from a binary value
accumulator to two 4-bit binary coded decimal (BCD) digits. This is the only
instruction that uses the auxiliary flag to perform the binary to
BCD conversion, and the conversion procedure is described
below. S, Z, AC, P, CY flags are altered to reflect the results of
the operation.
If the value of the low-order 4-bits in the accumulator is greater
than 9 or if AC flag is set, the instruction adds 6 to the low-order
four bits.
If the value of the high-order 4-bits in the accumulator is greater
than 9 or if the Carry flag is set, the instruction adds 6 to the
high-order four bits.
Example: DAA
Page 25
7.5 Data Transfer Instructions

Instruction
MOV Rd, Rs Copy from source(Rs) This instruction copies the contents of the source register into the
M, Rs to destination(Rd) destination register; the contents of the source register are not
Rd, M altered. If one of the operands is a memory location, its location
is specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M
MVI Rd, data Move immediate 8-bit The 8-bit data is stored in the destination register or memory. If
M, data the operand is a memory location, its location is specified by the
Example: MVI B, 57H or MVI M, 57H
LDA 16-bit Load accumulator The contents of a memory location, specified by a 16-bit address
address in the operand, are copied to the accumulator. The contents of the
source are not altered.
Example: LDA 2034H
LDAX B/D Reg. Load accumulator The contents of the designated register pair point to a memory
pair indirect location. This instruction copies the contents of that memory
location into the accumulator. The contents of either the register
pair or the memory location are not altered.
Example: LDAX B
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in
16-bit data immediate the operand.
Example: LXI H, 2034H or LXI H, XYZ
LHLD 16-bit Load H and L The instruction copies the contents of the memory location
address registers direct pointed out by the 16-bit address into register L and copies the
contents of the next memory location into register H. The
contents of source memory locations are not altered.
Example: LHLD 2040H
STA 16-bit 16-bit address The contents of the accumulator are copied into the memory
address location specified by the operand. This is a 3-byte instruction, the
second byte specifies the low-order address and the third byte
specifies the high-order address.
Example: STA 4350H
STAX Reg. pair Store accumulator The contents of the accumulator are copied into the memory
Page 26
indirect location specified by the contents of the operand (register pair).

The contents of the accumulator are not altered.
Example: STAX B
SHLD 16-bit Store H and L The contents of register L are stored into the memory location
address registers direct specified by the 16-bit address in the operand and the contents of
H register are stored into the next memory location by
incrementing the operand. The contents of registers HL are not
altered. This is a 3-byte instruction, the second byte specifies the
low-order address and the third byte specifies the high-order
address.
Example: SHLD 2470H
XCHG none Exchange H and L The contents of register H are exchanged with the contents of
with D and E register D, and the contents of register L are exchanged with the
contents of register E.
Example: XCHG
SPHL none Copy H and L The instruction loads the contents of the H and L registers into
registers to the stack the stack pointer register, the contents of the H register provide
pointer the high-order address and the contents of the L register provide
the low-order address. The contents of the H
and L registers are not altered.
Example: SPHL
XTHL none Exchange H and L The contents of the L register are exchanged with the stack
with top of stack location pointed out by the contents of the stack pointer register.
The contents of the H register are exchanged with the next stack
location (SP+1); however, the contents of the stack pointer
register are not altered.
Example: XTHL
PUSH Reg. pair Push register pair The contents of the register pair designated in the operand are
onto stack copied onto the stack in the following sequence. The stack
pointer register is decremented and the contents of the highorder
register (B, D, H, A) are copied into that location. The stack
pointer register is decremented again and the contents of the low-
order register (C, E, L, flags) are copied to that location.
Example: PUSH B or PUSH A
POP Reg. pair Pop off stack to The contents of the memory location pointed out by the stack
register pair pointer register are copied to the low-order register (C, E, L,
status flags) of the operand. The stack pointer is incremented by
1 and the contents of that memory location are copied to the
Page 27
high-order register (B, D, H, A) of the operand. The stack pointer

register is again incremented by 1.
Example: POP H or POP A
OUT 8-bit port Output data from The contents of the accumulator are copied into the I/O port
address accumulator to a port specified by the operand.
with 8-bit address Example: OUT F8H
IN 8-bit port Input data to The contents of the input port designated in the operand are read
address accumulator from a and loaded into the accumulator.
port with 8-bit Example: IN 8CH
address
Page 28
Objective: Write a program to add two hexadecimal numbers 23H & 84H and store the result in
a register.
Example –
Algorithm –
1. Load the first number from memory location 2050 to accumualtor.
2. Move the content of accumulator to register H.
3. Load the second number from memory location 2051 to accumaltor.
4. Then add the content of register B and accumulator using “ADD” instruction and storing
result at 3050
5. The carry generated is recovered using “ADC” command and is stored at memory location
3051
Program –
MEMORY ADDRESS MNEMONICS COMMENT
2000 LDA 2050 A<-[2050]
2003 MOV H, A H<-A
2004 LDA 2051 A<-[2051]
Page 29
2007 ADD H A<-A+H
2006 MOV L, A L←A
2007 MVI A 00 A←00
2009 ADC A A←A+A+carry
200A MOV H, A H←A
200B SHLD 3050 H→3051, L→3050
200E HLT
Explanation –
1. LDA 2050 moves the contents of 2050 memory location to the accumulator.
2. MOV H, A copies contents of Accumulator to register H to A
3. LDA 2051 moves the contents of 2051 memory location to the accumulator.
4. ADD H adds contents of A (Accumulator) and H register (F9). The result is stored in A
itself. For all arithmetic instructions A is by default an operand and A stores the
result as well
5. MOV L, A copies contents of A (34) to L
6. MVI A 00 moves immediate data (i.e., 00) to A
7. ADC A adds contents of A(00), contents of register specified (i.e A) and carry (1). As
ADC is also an arithmetic operation, A is by default an operand and A stores the result as
well
8. MOV H, A copies contents of A (01) to H
9. SHLD 3050 moves the contents of L register (34) in 3050 memory location and contents of
H register (01) in 3051 memory location
10. HLT stops executing the program and halts any further execution
Page 30
Objective: Write a program to subtract two hexadecimal numbers 23H & 84H and store the
result in a register.
Example –
Algorithm –
1. Load 00 in a register C (for borrow)
2. Load two 8-bit number from memory into registers
3. Move one number to accumulator
4. Subtract the second number with accumulator
5. If borrow is not equal to 1, go to step 7
6. Increment register for borrow by 1
7. Store accumulator content in memory
8. Move content of register into accumulator
9. Store content of accumulator in other memory location
10. Stop
Program –
MEMORY MNEMONICS OPERANDS COMMENT
2000 MVI C, 00 [C] <- 00
2002 LHLD 2500 [H-L] <- [2500]
2005 MOV A, H [A] <- [H]
2006 SUB L [A] <- [A] – [L]
Page 31
2007 JNC 200B Jump If no borrow
200A INR C [C] <- [C] + 1
200B STA 2502 [A] -> [2502], Result
200E MOV A, C [A] <- [C]
2010 STA 2503 [A] -> [2503], Borrow
2013 HLT Stop
Explanation – Registers A, H, L, C are used for general purpose:

1. MOV is used to transfer the data from memory to accumulator (1 Byte)
2. LHLD is used to load register pair directly using 16-bit address (3 Byte instruction)
3. MVI is used to move data immediately into any of registers (2 Byte)
4. STA is used to store the content of accumulator into memory(3 Byte instruction)
5. INR is used to increase register by 1 (1 Byte instruction)
6. JNC is used to jump if no borrow (3 Byte instruction)
7. SUB is used to subtract two numbers where one number is in accumulator(1 Byte)
8. HLT is used to halt the program
Page 32
Objective: Write a program to 1’s and 2’s complement of an 8 bit number.
Example –
Algorithm –
1. Load the data from memory 3000 into A (accumulator)
2. Complement content of accumulator
3. Store content of accumulator in memory 3001 (1’s complement)
4. Add 01 to Accumulator content
5. Store content of accumulator in memory 3002 (2’s complement)
6. Stop
Program –
2000 LDA [3000] [A] <- [3000]
2003 CMA [A] <- [A^]
2004 STA [3001] 1’s complement
2007 ADI 01 [A] <- [A] + 01
2009 STA [3002] 2’s complement
200C HLT Stop
Page 33
Explanation –
1. A is an 8-bit accumulator which is used to load and store the data directly
2. LDA is used to load accumulator direct using 16-bit address (3 Byte instruction)
3. CMA is used to complement content of accumulator (1 Byte instruction)
4. STA is used to store accumulator direct using 16-bit address (3 Byte instruction)
5. ADI is used to add data into accumulator immediately (2 Byte instruction)
6. HLT is used to halt the program
Page 34
Objective: Write a program to multiply two 8 bit numbers in 8085.
Example –
Algorithm –
1. We are taking adding the number 43 seven(7) times in this example.
2. As the multiplcation of two 8 bit numbers can be maximum of 16 bits so we need
register pair to store the result.
Program –
2000 LHLD 2050 H←2051, L←2050
2003 XCHG H↔D, L↔E
2004 MOV C, D C←D
2005 MVI D 00 D←00
2007 LXI H 0000 H←00, L←00
Page 35
200A DAD D HL←HL+DE
200B DCR C C←C-1
200C JNZ 200A If Zero Flag=0, goto 200A
200F SHLD 3050 H→3051, L→3050
2012 HLT
Explanation –
Registers used: A, H, L, C, D, E
1. LHLD 2050 loads content of 2051 in H and content of 2050 in L
2. XCHG exchanges contents of H with D and contents of L with E
3. MOV C, D copies content of D in C
4. MVI D 00 assigns 00 to D
5. LXI H 0000 assigns 00 to H and 00 to L
6. DAD D adds HL and DE and assigns the result to HL
7. DCR C decreaments C by 1
8. JNZ 200A jumps program counter to 200A if zero flag = 0
9. SHLD stores value of H at memory location 3051 and L at 3050
10. HLT stops executing the program and halts any further execution
Page 36
Objective: Write a program to divide two 16 bit numbers in 8085.
Assumption –
 Starting address of program: 2000
 Input memory location: 2050, 2051, 2052, 2053
 Output memory location: 2054, 2055, 2056, 2057.
Example –
INPUT:
(2050H) = 04H
(2051H) = 00H
(2052H) = 02H
(2053H) = 00H
OUTPUT:
(2054H) = 02H
(2055H) = 00H
(2056H) = FEH
(2057H) = FFH
Algorithm –
1. Intialise register BC as 0000H for Quotient.
2. Load the divisor in HL pair and save it in DE register pair.
3. Load the dividend in HL pair.
4. Subtract the content of accumulator with E register.
5. Move the content A to C and H to A.
6. Subtract with borrow the content of A with D.
7. Move the value of accumulator to H.
8. If CY=1, goto step 10, otherwise next step.
9. Increment register B and jump to step 4.
10. ADD both contents of DE and HL.
11. Store the remainder in memory.
12. Move the content of C to L & B to H.
13. Store the quotient in memory.
Page 37
Program –
MEMORY ADDRESS MNEMONICS COMMENTS
2000 LXI B, 0000H INITIALISE QUOTIENT AS 0000H
2003 LHLD 2052H LOAD THE DIVISOR IN HL
2006 XCHG EXCHANGE HL AND DE
2007 LHLD 2050 LOAD THE DIVIDEND
200B MOV A, L A<-L
200C SUB E A<-A-E
200D MOV L, A L<-A
200E MOV A, H A<-H
200F SBB D A<-A-D
2010 MOV H, A H<-A
2011 JC 2018 JUMP WHEN CARRY
2014 INX B B<-B+1
Page 38
MEMORY ADDRESS MNEMONICS COMMENTS
2015 JMP 200B
2018 DAD D HL<-DE+HL
2019 SHLD 2056 HL IS STORED IN MEMORY
201C MOV L, C L<-C
201D MOV H, B H<-B
201E SHLD 2054 HL IS STORED IN MEMORY
2021 HLT TERMINATES THE PROGRAM
Explanation –
1. LXI B, 0000H: intialise BC register as 0000H.

2. LHLD 2052H: load the HL pair with address 2052.
3. XCHG: exchange the content of HL pair with DE pair register.
4. LHLD 2050: load the HL pair with address 2050.
5. MOV A, L: move the content of register L into register A.
6. SUB E: subtract the contents of register E with contents of accumulator.
7. MOV L, A: move the content of register A into register L.
8. MOV A, H: move the content of register H into register A.
9. SBB D: subtract the contents of register D with contents of accumulator with carry.
10. MOV H, A: move the content of register A into register H.
11. JC 2018: jump to address 2018 if there is carry.
12. INX B: increment BC register by one.
13. JMP 200B: jump to address 200B.
Page 39
14. DAD D: add the contents of DE and HL pair.

15. SHLD 2056: stores the content of HL pair into memory address 2056 and 2057.
16. MOV L, C: move the content of register C into register L.
17. MOV H, B: move the content of register B into register H.
18. SHLD 2054: stores the content of HL pair into memory address 2054 and 2055.
19. HLT: terminates the execution of program.
Page 40
Objective: Write a program to divide two 16 bit numbers in 8085.
Example –
Input : 04H
Output : 18H
as 04*03*02*01 = 24 in decimal => 18H
In 8085 microprocessor, no direct instruction exists to multiply two numbers, so multiplication is

done by repeated addition as 4×3 is equivalent to 4+4+4 (i.e., 3 times).
Load 04H in D register -> Add 04H 3 times -> D register now contains 0CH -> Add 0CH 2
times -> D register now contains 18H -> Add 18H 1 time -> D register now contains 18H ->
Output is 18H
Algorithm –
1. Load the data into register B
2. To start multiplication set D to 01H
3. Jump to step 7
4. Decrements B to multiply previous number
5. Jump to step 3 till value of B>0
6. Take memory pointer to next location and store result
7. Load E with contents of B and clear accumulator
Page 41
8. Repeatedly add contents of D to accumulator E times

9. Store accumulator content to D
10. Go to step 4
PROGRAM
ADDRESS LABEL MNEMONIC COMMENT
2000H Data Data Byte
2001H Result Result of factorial
2002H LXI H, 2000H Load data from memory
2005H MOV B, M Load data to B register
2006H MVI D, 01H Set D register with 1
Subroutine call for

2008H FACTORIAL CALL MULTIPLY multiplication
200BH DCR B Decrement B
200CH JNZ FACTORIAL Call factorial till B becomes 0
Page 42
200FH INX H Increment memory
2010H MOV M, D Store result in memory
2011H HLT Halt
2100H MULTIPLY MOV E, B Transfer contents of B to C
Clear accumulator to store

2101H MVI A, 00H result
2103H MULTIPLYLOOP ADD D Add contents of D to A
2104H DCR E Decrement E
JNZ
2105H MULTIPLYLOOP Repeated addition
Page 43
2108H MOV D, A Transfer contents of A to D
2109H RET Return from subroutine
Explanation –
1. First set register B with data.
2. Set register D with data by calling MULTIPLY subroutine one time.
3. Decrement B and add D to itself B times by calling MULTIPLY subroutine as 4*3 is
equivalent to 4+4+4 (i.e., 3 times).
4. Repeat the above step till B reaches 0 and then exit the program.
5. The result is obtained in D register which is stored in memory
Page 44
Objective: Write a program to maximum and minimum among 10 numbers in 8085.
Example –
Minimum: 01H, Maximum: FFH

In CMP instruction:
If Accumulator > Register then carry and zero flags are reset
If Accumulator = Register then zero flag is set
If Accumulator < Register then carry flag is set
Assumption – List of numbers from 2050H to 2059H and output at 2060H and 2061H.
Algorithm –
1. Maximum number is stored in B register and minimum in C register
2. Load counter in D register
3. Load starting element in Accumulator, B and C register
4. Compare Accumulator and B register
5. If carry flag is not set then transfer contents of Accumulator to B. Else, compare
Accumulator with C register, if carry flag is set transfer contents of Accumulator to C
6. Decrement D register
7. If D>0 take next element in Accumulator and go to point 4
8. If D=0, store B and C register in memory
9. End of program
Program-
ADDRESS LABEL INSTRUCTION COMMENT
2000H LXI H, 2050H Load starting address of list
2003H MOV B, M Store maximum
2004H MOV C, M Store minimum
2005H MVI D, 0AH Counter for 10 elements
2007H LOOP MOV A, M Retrieve list element in Accumulator
Page 45
ADDRESS LABEL INSTRUCTION COMMENT
2008H CMP B Compare element with maximum number
2009H JC MIN Jump to MIN if not maximum
200CH MOV B, A Transfer contents of A to B as A > B
200DH MIN CMP C Compare element with minimum number
200EH JNC SKIP Jump to SKIP if not minimum
2011H MOV C, A Transfer contents of A to C if A < minimum
2012H SKIP INX H Increment memory
2013H DCR D Decrement counter
2014H JNZ LOOP Jump to LOOP if D > 0
2017H LXI H, 2060H Load address to store maximum
201AH MOV M, B Move maximum to 2060H
201BH INX H Increment memory
201CH MOV M, C Move minimum to 2061H
201DH HLT Halt

Explanation –
1. One by one all elements are compared with B and C register.
2. Element is compared with maximum, if it greater than maximum then it is stored in B
register. Else, it is compared with minimum and if it is less than minimum then it stored in
C regiter.
3. Loop executes 10 number of times.
4. At the end of 10 iterations, maximum and minimum are stored at 2060H and 2061H
respectively.
Page 46
Objective: Write a program to find the nth power of a number in 8085.
Example –
Input : Base=>02H
Exponent=>03H
Output :08H
In 8085 microprocessor, no direct instruction exists to multiply two numbers, so multiplication is

done by repeated addition as 4*4 is equivalent to 4+4+4+4(ie 4 times).
Load 02H(base) to register B and 03H(exponent) to register C -> set D register to 02H -> Add
02H B(ie 2) times -> D register now contains 04H -> Add 04H B(ie 2) times -> D register now
contains 08H -> Output is 08H.
Algorithm –
1. Load the base into register B and exponent into register C.
2. To start multiplication set D to 01H.
3. Jump to step 7.
4. Decrements C.
5. Jump to step 3 till value of C>0.
6. Take memory pointer to next location and store result.
7. Load E with contents of B and clear accumulator.
8. Repeatedly add contents of D to accumulator E times.
9. Store accumulator content to D.
10. Go to step 4.
Page 47
Program :
2000H Base Data Byte for base
2001H Exponent Data Byte for exponent
2002H Result Result of factorial
2003H LXI H, 2000H Load data from memory
2006H MOV B, M Load base to B register
2007H INX H Increment memory
2008H MOV C, M Load exponent to C register
2009H MVI D, 01H Set D register to 1
Subroutine call for

200BH POWER_LOOP CALL MULTIPLY multiplication
200EH DCR C Decrement C
Call power_loop till C

200FH JNZ POWER_LOOP becomes 0
2012H INX H Increment memory
2013H MOV M, D Store result in memory
2014H HLT Halt
2100H MULTIPLY MOV E, B Transfer contents of B to E
Clear accumulator to store

2101H MVI A, 00H result
2103H MULTIPLYLOOP ADD D Add contents of D to A
2104H DCR E Decrement E
Page 48
JNZ
2105H MULTIPLYLOOP Repeated addition
2108H MOV D, A Transfer contents of A to D
2109H RET Return from subroutine
Explanation –
1. Set register B with base and register C with exponent.
2. Set register D with base by calling MULTIPLY subroutine one time.
3. Decrement C and add D to itself B times by calling MULTIPLY subroutine.
4. Repeat the above step till C reaches 0 and then exit the program.
5. The result is obtained in D register which is stored in memory
Page 49
Objective: Write a program to count total even numbers in series of 10 in 8085.
Example –
Assumption – Ten 8-bit numbers are stored from starting memory location 2050. Value of count
is stored at memory location 3050.
Algorithm –
1. Initialize register H with 20 and register L with 4F so that indirect memory points to
memory location 204F.
2. Initialize register C with 00 and register D with 0A.
3. Increment indirect memory by 1.
4. Store value of M in accumulator A.
5. Check whether the content in A is even or odd by performing AND operation of A with 01.
6. If content of A is 00 after AND operation then number scanned was even, If so then
increment C by 01 else if content of A is 01 after AND operation then number scanned was
odd, If so then decrements D by 01.
7. Check if zero flag is not set i.e. ZF = 0 then jump to step 3 otherwise store value of C at
memory location 3050.
Program –
Page 50
2000 LXI H 204F H <- 20, L <- 4F
2003 MVI C, 00 C <- 00
2005 MVI D, 0A D <- 0A
2007 INX H M <- M + 01
2008 MOV A, M A <- M
2009 ANI 01 A <- A (AND) 01
200B JNZ 200F Jump if ZF = 0
200E INR C C <- C + 01
200F DCR D D <- D – 01
2010 JNZ 2007 Jump if ZF = 0
2013 MOV A, C A <- C
2014 STA 3050 M[3050] <- A
2017 HLT END
Page 51
Explanation – Registers A, B, C, D, H, L are used for general purpose.

1. LXI H 204F: assign 20 to H and 4F to L.
2. MVI C, 00: assign 00 to C.
3. MVI D, 0A: assign 0A to D.
4. INX H: increment indirect memory location M by 01.
5. MOV A, M: move content of M to A.
6. ANI 01: perform AND operation of A with 01 and store the result in A.
7. JNZ 200F: jump if ZF = 0 to memory location 200F.
8. INR C: increment C by 01.
9. DCR D: decrements D by 01.
10. JNZ 2007: jump if ZF = 0 to memory location 2007.
11. MOV A, C: moves the content of C to A.
12. STA 3050: store the content of A to memory location 3050.
13. HLT: stops executing the program and halts any further execution.
Page 52

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Computer Organization & Architecture Lab Manual

Greater Noida, U.P-201306

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Hardware and Software Requirements

Software Requirement: j8085 simulator, java development kit

a) Microsoft Windows 7 (SP1) and Windows 8 Professional

operating system; Apple Mac OS X 10.9.5 and 10.10.x

b) P-IV C2D 2.9 GHZ

c) 1.44 FDD LAN Card

h) 14” TFT Monitor

How to start with j8085 simulator.

 Supports all 8085 instructions

Step 2: Write the program in the white blank area

Assignment Date: Submission Date:

Objective: To study 8085 microprocessor in detail.

It has the following configuration −

 8-bit data bus

 A 16-bit program counter

Its bit position is shown in the following table −

4. Pin Configuration of 8085

The pins of a 8085 microprocessor can be classified into seven groups −

5. Addressing modes of 8085

Instruction word size

rd ß rs copies contents of rs into rd.

Example: MOV A,B

The instruction would require two memory locations to store in memory.

OUT port 0011 1110

opcode + data byte + data byte

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

A ß (addr) Addr is a 16-bit address in L H order.

7. Instruction set of 8085

Opcode Operand Explanation of Description

7.2 LOGICAL INSTRUCTIONS

Opcode Operand Explanation of Description

STC none Set Carry Set Carry

7.3 BRANCHING INSTRUCTIONS

Opcode Operand Explanation Description

JMP 16-bit Jump The program sequence is transferred

Flag 16-bit Jump The program sequence is transferred

Flag 16-bit Unconditional The program sequence is transferred

RET none Return from The program sequence is transferred

Flag none Return from The program sequence is transferred

RC Return on Carry CY = 1 conditionally program based on the specified flag

RZ Return on zero Z=1

PCHL none Load program The contents of registers H and L

RST 0-7 Restart The RST instruction is equivalent to

7.4 Arithmetic Instructions

Opcode Operand Explanation of Description

Example: ADC B or ADC M

7.5 Data Transfer Instructions

Opcode Operand Explanation of Description

indirect location specified by the contents of the operand (register pair).

high-order register (B, D, H, A) of the operand. The stack pointer

MEMORY ADDRESS MNEMONICS COMMENT

2000 LDA 2050 A<-[2050]

2003 MOV H, A H<-A

2004 LDA 2051 A<-[2051]