VLSI & E-CAD LAB

B.Tech. IV Year I Sem. Course Code: EC703PC

List of Experiments
Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor
Graphics / Synopsys /Equivalent CAD tools.
The design shall include
Gate-level design,
Transistor-level design,
Hierarchical design,
Verilog HDL/VHDL design,
Logic synthesis,
Simulation and verification,
Scaling of CMOS Inverter for different technologies,
study of secondary effects ( temperature, power supply and process corners),
Circuit optimization with respect to area,
performance and/or power,
Layout,
Extraction of parasitics and back annotation,
modifications in circuit parameters and
layout consumption,
DC/transient analysis,
Verification of layouts (DRC, LVS)
E-CAD programs: Programming can be done using any complier. Down load the programs on
FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and
logic analyzer apart from verification by simulation with any of the front end tools.
1. HDL code to realize all the logic gates
2. Design of 2-to-4 decoder
3. Design of 8-to-3 encoder (without and with priority)
4. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer
5. Design of 4 bit binary to gray code converter
6. Design of 4 bit comparator
7. Design of Full adder using 3 modeling styles
8. Design of flip flops: SR, D, JK, T
9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
10. Finite State Machine
Design VLSI programs:
Introduction to layout design rules.
Layout,
physical verification,
placement & route for complex design,
static timing analysis,
IR drop analysis and
crosstalk analysis of the following:
1. Basic logic gates
2. CMOS inverter
3. CMOS NOR/ NAND gates
4. CMOS XOR and MUX gates
5. Static / Dynamic logic circuit (register cell)
6. Latch
7. Pass transistor
8. Layout of any combinational circuit (complex CMOS logic gate).
9. Analog Circuit simulation (AC analysis) – CS & CD amplifier
Note: Any SIX of the above experiments from each part are to be conducted (Total 12)

MICROWIND: A CMOS LAYOUT TOOL

DSCH: TOOL FOR LOGIC DESIGN
MICROWIND
MICROWIND is truly integrated EDA software encompassing IC designs from concept to completion,
enabling chip designers to design beyond their imagination.
MICROWIND integrates traditionally separated front -end and back-end chip design into one flow,
accelerating the design cycle and reduces design complexities.
It tightly integrates mixed-signal implementation with digital implementation, circuit simulation,
transistor-level extraction and verification – providing an innovative education initiative to help
individuals to develop the skills needed for design positions in virtually every domain of IC industry.

MICROWIND supports entire front-end to back-end design flow.

For front-end designing, we have DSCH (digital schematic editor) which posses in-built pattern based
simulator for digital circuits. User can also build analog circuits and convert them into SPICE files and
use 3rd party simulators like WinSpice or pSPICE.
DSCH can convert the digital circuits into Verilog file which can be further synthesize d for FPGA/CPLD
devices of any vendor. The same Verilog file can be compiled for layout conversion in MICROWIND.
The back-end design of circuits is supported by MICROWIND. User can design digital circuits and
compile here using Verilog file. MICROWIND auto matically generates a error free CMOS layout.
Although this place-route is not optimized enough as we do not indulge in complex place & route
algorithms.
User can also create CMOS layout of their own using compile one line Verilog syntax or custom build th e
layouts by manual drawing.
The CMOS layouts can be verified using inbuilt mix -signal simulator and analyzed further for DRC,
crosstalks, delays, 2D cross section, 3D veiw, etc.

FINFET ADVANTAGES
 Instead of a continuous channel, the FinFET uses fins, allowing transistor be low power,faster,
compact and continue scaling.
 FinFET provides the same Ion current at a smaller size.
 FinFET provides lower leakage current Ioff at the same Ion.
 Microwind will now allow student to explore future technology which is different from 45 years
old planar style.
 Learn about process variation and manufacturability issue with/without dummy gates.
 Planar MOS were almost about to break Moore’s law, know how FinFET kept it intact.
FINFET TECHNOLOGY
FinFET, also known as Fin Field Effect Transistor, is a type of non -planar or "3D" transistor used in the
design of modern processors. FinFET designs also use a conducting channel t hat rises above the level of
the insulator, creating a thin silicon structure, shaped like a fin, which is called a gate electrode. This fin -
shaped electrode allows multiple gates to operate on a single transistor. This type of multi -gate process
extends Moore's law, allowing semiconductor manufacturers to create CPUs and memory modules that are
smaller, perform faster, and consume less energy.

FINFET GENERATOR IN MICROWIND

In Microwind 3.8 you can generate FiNFET transistors or compiler using Verilog file too. Below are the
outline of generated transistor.
 Fin Length, equal to gate length, (LG) is 2 lambda (16 nm) by default
 Fin thickness (TF) is set to 1 lambda (8 nm)
 Fin pitch (PF) is set to 6 lambda (48nm)
 FinFET comme with dummy gates for manufacturability
 HD: High density drawing style : 2 fins
 HP : High performance drawing style : 4 fins

VLSI Design – EEE434 Course Material

A comprehensive introduction to design and fabrication of Very Large Scale Integrated (VLSI) circuits in
CMOS technology. The course gives an excellent insight into VLSI chip design and high-performance,
low-power circuit techniques.
Announcements:
2019-03-18: Lab Groups for Sessional – 1 are here.
2019-02-20: Quiz 01 on Monday 25th Feb from Chapter 01 and 02
2019-02-11: Lab File is here
2019-02-11: For Lab01 Download DSCH, see a short tutorial video here about how to launch the console.
2019-02-01 : Download DSCH and Microwind from links below and take with you in Lab.
2019-02-01 : You will get all the announcements regarding the VLSI Class here. You are Requested to
Visit Often.
Lectures:
Lecture 01: Introduction to VLSI Design
Lecture 02: Logic Design using MOSFETs – Part 1
Lecture 03: Logic Design using MOSFETs – Part 2
Lecture 04: Logic Design using MOSFETs – Part 3
Lecture 05: Quiz 01 and Lab02 Discussion
Lecture 06: Physical Structure of CMOS ICs – Part 1
Lecture 07: Physical Structure of CMOS ICs – Part 2
Lecture 08: Fabrication Process of CMOS ICs – Part 1
Lecture 09: Fabrication Process of CMOS ICs – Part 2
Lecture 10: Elements of Physical Design – Part 1
Lecture 11: Sessional – 1
Lecture 12: Sessional 1 Discussion
Lecture 13: Elements of Physical Design – Part 2
Lecture 14: Electrical Characteristics of MOSFETs – Part 1
Lecture 16: Electrical Characteristics of MOSFETs – Part 2
Lecture 17: Quiz No 2
Lecture 18: Electronic Analysis of CMOS Logic Gates – Part 1
Lecture 19: Electronic Analysis of CMOS Logic Gates – Part 2
Lecture 20: Sessional – II
Lecture 21: Sessional – II Discussion
Lecture 22: Advanced Techniques in CMOS Logic Circuits – Part 1
Lecture 23: Quiz 03
Lecture 24: Advanced Techniques in CMOS Logic Circuits – Part 2
Lecture 25: Advanced Techniques in CMOS Logic Circuits – Part 3
Lecture 27: VLSI Design of Complex Algorithms
Lecture 27 Additional Material: SoC Encounter Manual – Cadence Design Tools

Lab Sessions: Labs will be uploaded in this section

Lab01: Introduction to DSCH and gate implementation using DSCH
Lab02: Designing Complex Logic Circuits using CMOS and Transmission Gates
Lab03: Design and Simulation of Basic Logical Operations in ModelSim
Lab04: Design and Simulation of 4-bit ALU using HDL Architecture
Lab05: Introduction to Microwind, Design and Simulation of an Inverter
Lab06; Layout of Basic Logic Gates using 0.25 micron Technology in Microwind
Lab07: Layout of Complex Logic Function using 0.25 micron Technology
Lab08: Layout Design and Simulation of Full Adder in Microwind using Cell Concept
Lab09: Design and Implementation of Static RAM Cell Layout using 0.12 micron Technology
Lab10: Controlling Rise and Fall Time of Complex Function in Layout Design
Lab11: Designing a Chip in Microwind
Lab11: Lab 12

Quizes: Quiz solutions will be uploaded in this section

Quiz 01: Solution

Assignments: Assignment Questions will be updated in this section

Assignment 01 Question 1 &2
Assignment 3 and 4

Software for Labs:

Microwind – A CMOS Layout Tool
DSCH – Tool for Logic Design
DSCH
Q1 Can Wires be connected at user-defined angles?
Yes, to have any angle for the connection lines, open file menu go to the properties option, select misc.
option in which select allow any an gle of contact.
Q2 How to count the number of symbols, nodes, wires used in schematic?
To count the resources used in the schematic, go to properties option in file menu, in which go to general
properties where you can see the resources used by schematic.
Q3 Can we generate SPICE netlist of DSCH schematic?
Yes, to generate the SPICE netlist for the given schematic, go to the file menu and select the generate
SPICE file option.
Q4 Can we see the Verilog module of the particular symbol?
Yes, to have any angle for the connection lines, open file menu go to the properties option, select misc.
option in which select allow any angle of contact.
Q5 Can we see the complete netlist of the schematic?
Yes, to see the complete netlist of the schematic go to the view men u in which select the design hierarchy
option.
Q6 Can we use the third party simulation tool for the functional simulation of the schematic?
Yes, you can use the third party simulation tool like modelsim by converting the schematic into Verilog
file and we can use that Verilog file for the simulation.
Q7 Can we see the symbol state at the time of simulation?
yes you can see the state of the individual symbol by selecting symbol state option in the simulation
control window.
Q8 Can we see timing simulation of the schematic?
Yes, you can see the functional (timing) simulation of the schematic, by opening it in the waveform editor
provided.
Q9 Can we control the simulation parameters like wire delay, gate delay etc?
For user specified parameters create your own technology file, save it and import it when using DSCH.
Q10 Can we change the value of Vdd (i.e. 1.2 V for 0.12um technology) while extracting the spice
netlist from schematic?
Double click on the VDD symbol, edit the tech. Vdd which would be inserted in the spice netlist.
Q11 How to save the extracted spice netlist?
spice file is saved automatically at the time of extraction with a ".CIR" extension
Q12 Can we go for higher (level) MOS model spice netlist extraction?
Yes, the models can be updated in or user can go for his/her own library by adding the text as the label in
the design.
Q13 Can we import SPICE netlist?
No, DSCH can not import the SPICE net list as of now.
Q14 Can we import schematic from another file?
Yes, by insert menu option.
Q15 How to find propagation delay?
To find out longest propagation delay between input and output go to simulate and click on option.
All Circuits in VLSI can implemented and simulated in DSCH software
later the verilog file of the that corresponding circuit can be analysed in Microwind software.