STUDY OF CHARACTERIZATION OF DEGRADATION OF

DRAIN SATURATION CURRENT OF nMOSFET DUE TO

HOT CARRIER INJECTION

TRAINING REPORT

Prepared in partial fulfilment of the requirements for the degree of

Bachelor of Technology

in

Electronics and Communication Engineering

Meerut Institute of Engineering and Technology, Meerut

Affiliated to

DR. A.P.J Abdul Kalam Technical University, Lucknow

Under Guidance of: Submitted by:

Mrs.Preetika Pavitra

R&QA ST00205

Submitted to

Reliability and Quality Assurance Division

Semi-Conductor Laboratory

Department of Space, Govt. of India

S.A.S Nagar, Punjab.

1
 DECLARATION

I “Pavitra” hereby declare that I have taken Six Weeks Industrial Training at Semiconductor
Laboratory Mohali, Punjab during a period from 11th June to 20th July 2018 in partial
fulfilments for the degree of Bachelor and Technology (Electronics and Communication
Engineering). The work which is being presented in training report submitted to Meerut
Institute of Engineering and Technology, Meerut is an authentic record of training work.

Signature

2
 CERTIFICATE

This is to certify that this report entitled “To Characterize The Degradation of Saturation
Current of nMOSFET Due To Hot Carrier Injection” submitted to Department of Electronics
and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut
affiliated to Dr. A.P.J. Abdul Kalam University, Lucknow, is a bonafide record of work done
by Pavitra at Semiconductor Laboratory Department of Space, Government of India Mohali,
Punjab under my supervision.

Signature

Mrs.Preetika

R&QA

3
 ACKNOWLEDGEMENT

I would like to acknowledge my deep gratitude to the Head of R&QA Department “Mr. Anil
Singh” for encouraging and allowing me to work.

I am also grateful to my project guide – Mrs.Preetika, SCL S.A.S. Nagar, Punjab, for her
invaluable guidance and cordial support given for the completion of this project. It is a great
privilege for me to have completed the project under such an experienced and knowledgeable
project guide.

I pay my sincere thanks to all staff members of R&QA team for sharing their knowledge and
experience.

Sincerely

Pavitra

ST00205

4
SCL PROFILE
Semi-Conductor Laboratory (SCL); an autonomous body under Department of Space,
Government of India; is engaged in Research & Development in the area of Microelectronics
to meet the strategic needs of the country.

Formerly known as Semiconductor Complex Limited, a Government of India Enterprise,

which was converted into Semi-Conductor Laboratory under Department of Space,
Government of India w.e.f. September 1, 2006. SCL has integrated facilities / supporting
infrastructure all under one roof and undertakes activities focused on Design, Development,
Fabrication, Assembly & Packaging, Testing and Quality Assurance of CMOS and MEMS
Devices for various applications. SCL is also engaged in Fabrication of Hi-Rel Boards, Radio
Sonde Systems and indigenisation of electronic sub systems.

VISION
 Create a strong R & D base in the country in the field of microelectronics.
 Design and Development of devices in cutting edge technology.
 Manufacture VLSI/MEMS based systems and sub-systems.
 Transform SCL as a Centre of Excellence in microelectronics in the country.

RELIABILITY & QUALITY ASSURANCE (R&QA) DIVISION

The Reliability & Quality of the devices / boards / sub-systems / systems manufactured at
SCL is maintained throughout design, chip fabrication, assembly / packaging and testing
phases. Regular inline QA inspection / audits are carried out to ensure defect free
manufacturing. Screening and qualification of products for required applications is an integral
part of the process. The quality and reliability assurance requirements are guided by global
performance specifications as per MIL-PRF-38535, JEDEC, MIL883 and other relevant
standards. Continuous improvements in processes are implemented through feedbacks at
appropriate stages and performing failure analysis.

Figure1.Environment Test Facility (ETF) Lab

5
 CONTENTS
Cover page 1

Declaration 2

Certificate 3

Acknowledgement 4

SCL Profile 5

1: HOT CARRIER INJECTION 9-13

1.1. Introduction 9

1.1.1. CMOS Scaling: 9

1.1.2. Hot Carriers 9

1.2. Hot Carrier Degradation Phenomena 10

1.2.1 The Channel Electric Field 10

1.2.2 Secondary Carrier Generation 10

1.3 Energy Barrier for Injection of Carriers in Oxide Layer 11

1.4. Different Hot Carrier Injection Mechanisms 11

1.4.1. Channel Hot Electron 11

1.4.2. Substrate Hot Electron 12

1.4.3. Drain Avalanche Hot Carriers 12

1.4.4. Secondary Generated Hot Carriers 13

2. DEGRADATION OF MOSFET PARAMETERS DUE TO HCI 14-15

2.1 Id-Vds Characteristics Degradation 14

2.2 The Linear Region Transfer Characteristics Degradation 14

2.2.1 Id –Vg Characteristics Degradation 15

2.2.2 gm-Vg Characteristics Degradation 15

2.3. HCI Impact on Reliability 15

6
3. FACTORS AFFECTING HCI 16-17

3.1. Temperature 16

3.2 Voltage Dependence 17

3.3 Time 17

3.4 Lightly Doped (Source/Drain) 17

4. PROJECT WORK 18-31

4.1. Name of Project 18

4.2 Introduction 18

4.3. Test Structures 18

4.4. Equipment Used 18

4.5. Experimental Details: 18

4.5.1. Stress Conditions 18

4.5.2 Monitoring Parameter: 19

4.5.3. Parameter Shift vs. Time 19

4.6.Characterization Methodology 19

4.7. Experimental Data 20

4.7.1. Pre Stress Device Parameters 20

4.7.2. Post Stress Device Parameters 20

4.7.3. Results 21

4.7.4. Summary 31

5.REFERENCES 32

7
 LIST OF FIGURES
Figure 2. Environment Test Facility (ETF) Lab 5
Figure 2. Distribution of Lateral electric field along the channel 10

Figure 3. Hot carrier generation in nMOSFET 11

Figure 4: Energy band diagram showing the barrier heights for injection of electron and 11

holes from Si to SiO2

Figure 5.Channel Hot Carriers 12

Figure 6. Substrate Hot Electron 12

Figure 7. Drain Avalanche Hot Carriers 13

Figure 8: Secondary Generated Hot Carriers 13

Figure 9. Id-Vds Characteristics 14

Figure 10. Id –Vg Characteristics 14

Figure 11.gm-Vg Characteristics

Figure 12. HCI degradation increases significantly as temperature decreases 15

Figure 13.Schematic of voltage dependence of HCI. 16

Figure 14.HCI power-law time dependence 16

Figure 15. Schematic cross section and doping profile of MOSFET transistor with 17

LDD source and drain junction

Figure 16.log (∆Idsat(%)) vs log (t) for DUT-201 22

Figure 17.log (∆Idsat(%)) vs log (t) for DUT-202 23

Figure 18.log (∆Idsat(%)) vs log (t) for DUT-203 24

Figure 19.log (∆Idsat(%)) vs log (t) for DUT-204 25

Figure 20.log (∆Idsat(%)) vs log (t) for DUT-205 26

Figure 21.log (∆Idsat(%)) vs log (t) for DUT-207 27

Figure 22.log (∆Idsat(%)) vs log (t) for DUT-208 28

Figure 23.log (∆Idsat(%)) vs log (t) for DUT-209 29

Figure 24.log (∆Idsat(%)) vs log (t) for DUT-211 30

Figure 25.log (∆Idsat(%)) vs log (t) for DUT-212 31

8
1. HOT CARRIER INJECTION
1.1. INTRODUCTION
1.1.1. CMOS SCALING:

The scaling of silicon integrated circuits to smaller physical dimensions became a primary
activity of advanced device development almost as soon as the basic technology was
established. The importance and persistence of this activity is rooted in the confluence of two
of the major goals - to increase density and speed of digital ICs in which such scaled down
devices are used. [2]

Increase in density means using smaller channel lengths and widths. Whereas to increase
speed of digital ICs, the MOSFET saturation drain current must be increased (ie.to allow
faster charging and discharging of parasitic capacitances).Since quest for greater device
performance require reduction in size beyond ~2µm, it will never the less be necessary to
confront phenomena termed as short channel effects and reliability problems associated with
short channel device structures. [4]

The reliability problems that arise are:

 Hot Carrier Degradation

 Thin gate oxide breakdown
 Problems associated with interconnects between MOSFETs (eg. Electro migration)

1.1.2. HOT CARRIERS

Carriers (electrons or holes) can gain large kinetic energies from transit through regions of
high electric field. When the mean carrier energy is significantly larger than that associated
with the lattice in thermal equilibrium (EAVG=3/2kTL), they are called “hot”. Hot carriers
can gain enough energy to be injected into the gate oxide or cause interfacial damage,
introducing instabilities in the electrical characteristics of a MOSFET device. Hot carrier
degradation is a critical reliability concern, particularly when the design of MOSFET
transistors allows large electric fields at operating conditions. [1]

1.2. HOT CARRIER DEGRADATION PHENOMENA

Two mechanisms are responsible for carrier generation: the channel electric field and/or
secondary carrier energy gain in processes such as impact ionization.

1.2.1 THE CHANNEL ELECTRIC FIELD

The electric field is the main driving force of the hot carrier generation in MOSFET devices
and modulates the injection of hot carriers in the gate oxide. Depending on the bias conditions
in saturation, the lateral electric field in the pinch-off region heats up the channel carriers,
while the vertical oxide field can favour or prevent the injection of either hot holes or
electrons in the gate oxide by modulating the barrier height at the Si/SiO2 interface.[5]

9
 Emax = (Vds-Vdsat) /∆L

Where,

Emax is peak of the lateral field and

∆L is length of the pinch-off region.

Figure 2. Distribution of Lateral electric field along the channel

1.2.2 SECONDARY CARRIER GENERATION

Energetic channel carriers accelerated by the lateral field can produce additional carriers by
impact ionization in the channel region. The electrons created by impact ionization are either
collected by drain or injected into the oxide. The holes formed by this process give rise to
substrate current, providing a measurable quantity for assessing the degree of impact
ionization under conditions of gate bias much smaller than drain bias some of these holes can
also cause a hot holes gate current.

If the level of impact ionization is quite high a substantial substrate current can flow.
Excessive holes flow into the substrate can lead to undesirable behaviour as snapback and
latch up. Hence it is essential to monitor substrate current in a production environment and
ensure that it does not become excessive in normal device operation.[1]

Figure 3. Hot carrier generation in nMOSFET

10
1.3 ENERGY BARRIER FOR INJECTION OF CARRIERS IN OXIDE
LAYER
The carriers near the Si–SiO2 interface in the silicon substrate of a MOSFET have to
overcome an energy barrier in order to enter the oxide. The energy barrier for electrons is
about 3.1 eV whereas 4.8 eV for holes. As a result of the large difference between the energy
barriers for electrons and holes, under similar conditions, electrons will be injected into SiO2
in much larger quantities than holes. Due to these differences between energy barriers hot
carrier effects are more significant in nMOS devices.

Figure 4: Energy band diagram showing the barrier heights for injection of electron
and holes from Si to SiO2

1.4. DIFFERENT HOT CARRIER INJECTION MECHANISMS

1.4.1 Channel Hot Electron:

When the gate voltage is approximately equal to the drain voltage, the channel hot electron
(CHE) injection effect is at its maximum. So-called ‘lucky electrons’ gain sufficient energy to
surmount the Si/SiO2 barrier at the drain end of the channel, without losing energy due to
collisions with atoms in the channel.[3]

Figure 5.Channel Hot Carriers

11
1.4.2. Substrate Hot Electron:

Substrate hot electron (SHE) or substrate hot hole (SHH) injection is the result of a high
positive or a high negative bias at the bulk of the transistor. This leads to carriers in the
substrate driven to the Si/SiO2 interface, gaining kinetic energy and potentially surmounting
the energy barrier at the channel/gate-oxide interface to be injected into the oxide.[3]

Figure 6. Substrate Hot Electron

1.4.3. Drain Avalanche Hot Carrier Generation (DAHC):

At stress conditions with high drain voltage and low gate voltage, electron-hole pairs can be
created due to impact ionization of the channel current near the drain of the transistor.

Each of these electrons and holes can then accelerate in the channel electric field and can
potentially surmount the Si/SiO2 barrier to get trapped or to create interface states.This,
phenomenon is known as avalanche multiplication and results in drain avalanche hot carrier
generation (DAHC).[3]

Figure 7. Drain Avalanche Hot Carriers

1.4.4. Secondary generated hot electron injection (SGHE):

Secondary generated hot electron injection involves the generation of hot carriers from
impact ionization with a secondary carrier that was created by an earlier impact ionization
incident. This earlier generated carrier can be generated under DAHC conditions or from
photons generated in the high field region near the drain. Under the influence of the field
generated by the substrate’s bulk bias, the first carriers are accelerated and potentially
generate secondary carriers.[3]

12
Figure 8: Secondary Generated Hot Carriers

13
2. DEGRADATION OF MOSFET PARAMETERS DUE TO HCI
2.1 ID-VDS CHARACTERISTICS DEGRADATION:
The energetic electrons which surmount the potential barrier between Si channel and gate
oxide can go through gate oxide and can be collected as gate current, thereby reducing input
impedence. More importantly, some of these electrons can be trapped in the gate oxide as
fixed oxide charges. This increases the flatband voltage and therefore the Vt. Therefore, for
higher gate bias, the MOSFET goes from the saturation region into the linear region when
fixed VDdrops below Vdsat = Vg-Vt.[5]

Figure 9. Id-Vds Characteristics

2.2 THE LINEAR REGION TRANSFER CHARACTERISTICS

DEGRADATION:
The energetic hot carriers injected into gate oxide increases the fixed oxide charge and can
also rupture Si-H bonds exist at Si-SiO2 interface increasing fast interface states by reducing
the concentration of S/D. The depletion width at the reverse drain channel junction is
increased and electric field is reduced.[5]

2.2.1 Id –VgCHARACTERISTICS DEGRADATION:

Figure 10. Id –Vg Characteristics

14
2.2.2 gm-Vg Characteristics Degradation:

Figure 11.gm-Vg Characteristics

2.3. HCI IMPACT ON RELIABILITY

HCI does not cause any hard functional failure. Typically, it reduces the circuit speed
although large speed reduction can cause device failure. HCI results in the interface state
generation and charge trapping and these traps can be filled with electrons/holes which lead
to shifts in transistor and circuit parameters: threshold voltage, mobility/trans conductance,
subthreshold slope, drive current, leakage current and circuit speed. [4]

15
3. FACTORS AFFECTING HCI
3.1. TEMPERATURE:
As the stress temperature decreases, there is a small increase in bandgap of Si (from 1.1 eV at
300K to about 1.15 eV at 100 K), implying lower impact ionization and, hence, lower
degradation. This trend is countered by the fact that at lower temperatures phonon scattering
of channel electrons is also reduced which leads to increase in the average energy of the
electrons and as such an increase in the impact ionization rate. On balance, impact-ionization
increases with lower temperature. Thus, for equal amount of applied stress, a MOS device at
lower temperature will have larger number of hot carriers being injected leading to hole
ionization and hence leading to larger device degradation.[2]

Figure 12. HCI degradation increases significantly as temperature decreases.

3.2 VOLTAGE DEPENDENCE:

When operating voltages (VDD) are increased, for a given gate voltage, the carrier gets hotter
and hence, the ionization efficiency increases, leading to greater effect of HCI degradation.[2]

Figure 13.Schematic of voltage dependence of HCI.

16
3.3 TIME :
Hot carrier degradation has been studied widely to assess the reliability implications. The
degradation was to found to be mainly interface traps (for VG~VD/2). This implies that the
damage is due to interface trap generation by Si-H bond breaking, similar to NBTI.[1]
Furthermore, NMOS.HCI also shows power-law (~tn) time dependence, with time exponents
in the range of 0.3 to 0.70.

Figure 14. HCI shows power-law time dependence

3.4 LIGHTLY DOPED (SOURCE/DRAIN):

The main objective of LDD design is to reduce the lateral electric field in the drain region for
a given power supply and channel length.[1]

Figure 15. Schematic cross section and doping profile of MOSFET transistor with LDD
source and drain junction

17
4. PROJECT WORK
4.1. NAME OF PROJECT:
To characterize the degradation of drain saturation current of nMOSFET dueto Hot Carrier
Injection.

4.2 INTRODUCTION:
Hot Carrier Injection results in an increase in the threshold voltage Therefore, for higher
gate bias, the MOSFET goes from the saturation region into the linear region when fixed VD
drops below VDsat = Vg-Vt.

The purpose of this project is to characterize the degradation of drain saturation current due to
hot carrier injection from the results obtained by testing the test structures at highly
accelerated conditions for 180nm standard CMOS.

4.3. TEST STRUCTURES: LV-nMOSFET

W/L :- 10/0.18µm

4.4. EQUIPMENT USED: 1. Agilent Technologies B1500

2. AETRUM-1164 Reliability Test System

4.5. EXPERIMENTAL DETAILS:

4.5.1. STRESS CONDITIONS:

Hot carrier stressing is performed under constant voltage bias conditions. The device is
stressed using Vdstress, Vgstress while the measured parameters are Idstress&Isubstress.

1. Stress Force:

Vd= 2.7V

Vg=1.35V

2. Total stress Duration:

1200 hours

3. Cycle Duration:
First cycle duration=10sec

Max Cycle duration =10hours

Cycling interval=6cycles/decade

Total Stress Cycle = 143




18
4. Stress temperature:

30°C ± 2°C

4.5.2 MONITORING PARAMETER:

MOSFET parameter Idsat show variations with the increase in the stress time. It is monitored
at the logarithmically spaced time intervals. When it shows degradation by 10% the test is
stopped.

4.5.3. PARAMETER SHIFT VS. TIME: Typical parameter shift/degradation follows the
power law with time. It should be fitted to the following equation using least square method.

|∆Id (t)| = C * tn

Where, ∆Id(t) = shift in drain current w.r.t stress time

C = material dependent parameter

t = stress time

n = empirically determined exponent, a function of stress voltages, temperature and

effective transistor channel length.

4.6. CHARACTERIZATION METHODOLOGY:

 Initial characterization is done to select good devices and to record the values of the
parameters of initial unstressed device.

 Isub – Vg and ID –Vg Characteristics were studied at Agilent B1500 to find out Isub
and Vthcc.

 Ten devices were loaded on DUT (Devices Under Test) boards of AETRUM-1164
Reliability Test System.

 Various stress conditions (Voltage and temperature) are applied.

 The devices were left under Vdstress =2.7V and Vgstress=1.35V for 1200 hours. The
change in saturation current is monitored after each 10 hours cycle. The time was
recorded for the devices which encountered 10% degradation in saturation current.

 The test ended as soon as all the devices reached 10% degradation of saturation
current.

19
  Plot of log(∆Idsat) versus log(∆t) gives the slope(n) and intercept(log C).

 It shows HCI dependence on time.

4.7. EXPERIMENTAL DATA

Vtcc : It is that value of gate voltage at which drain saturation current is approximately equal
to 5.55µA.

Idsat = 0.1×W/L

= 0.1×10/0.18 µA

Isub : It is the value of maximum substrate current obtained for the device. It results due to the
hot holes drifted towards the body terminal.

Vg: The gate voltage applied to get the maximum substrate current for the device.

Idoff : The drain leakage current before the channel inversion(ie, device is OFF).

Igmax: The maximum gate current.

4.7.1. PRE STRESS DEVICE PARAMETERS

Serial No. DUT No. Vtcc Isub(µA) Vg(V) Idoff(pA) Idsat(mA) Igmax(pA)
1 201 0.39 -0.91 1.05 61 5.261 19
2 202 0.42 -0.822 1.10 34 5.182 17
3 203 0.39 -0.0946 1.05 72 5.390 17
4 204 0.42 -0.769 1.05 30 5.00 18
5 205 0.41 -0.879 1.05 40 5.194 16
6 207 0.43 -0.761 1.10 33 4.917 18
7 208 0.42 -0.742 1.05 33 4.986 17
8 209 0.42 -0.807 1.10 37 5.107 17
9 211 0.41 -0.85 1.05 52 5.254 17
10 212 0.43 -0.704 1.05 25 4.899 13

20
4.7.2. POST STRESS DEVICE PARAMETERS

Serial No. DUT No. Vtcc Isub(µA) Vg(V) Idoff(pA) Idsat (mA) Igmax(pA)
1 201 0.52 -0.338 1.15 61 4.676 22
2 202 0.54 -0.295 1.15 39 4.581 20
3 203 0.52 -0.349 1.15 72 4.761 20
4 204 0.53 -0.271 1.10 37 4.458 22
5 205 0.52 -0.331 1.15 45 4.612 19
6 207 0.54 -0.269 1.10 39 4.388 21
7 208 0.52 -0.274 1.05 39 4.491 22
8 209 0.54 -0.292 1.15 43 4.524 21
9 211 0.53 -0.284 1.15 55 4.644 21
10 212 0.54 -0.245 1.10 31 4.377 16

4.7.3.RESULTS

DUT#201

Time(hrs) IdSat(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.002 5.253 0.079 -2.531 -1.098
0.351 5.196 1.160 -0.454 0.065
0.700 5.177 1.522 -0.154 0.182
1.049 5.160 1.854 0.021 0.268
1.400 5.145 2.142 0.146 0.331
1.752 5.133 2.363 0.243 0.373
2.107 5.124 2.540 0.323 0.405
2.466 5.116 2.682 0.392 0.429
2.832 5.108 2.845 0.452 0.454
3.206 5.099 3.002 0.506 0.477
3.593 5.090 3.173 0.556 0.502
4.000 5.085 3.275 0.602 0.515
4.435 5.077 3.44 0.646 0.536
4.912 5.066 3.647 0.691 0.567
5.450 5.057 3.8164 0.736 0.582
6.077 5.049 3.971 0.783 0.599
6.835 5.041 4.122 0.834 0.615
7.785 5.030 4.318 0.891 0.635
9.017 5.019 4.532 0.955 0.656
10.664 5.002 4.864 1.027 0.686
12.918 4.984 5.202 1.111 0.716
16.064 4.959 5.673 1.206 0.753
20.521 4.928 6.272 1.312 0.797
26.900 4.870 7.375 1.429 0.867
36.102 4.815 8.408 1.557 0.924
46.451 4.769 9.290 1.667 0.968
56.800 4.783 9.016 1.754 0.955
67.151 4.752 9.618 1.827 0.983
77.502 4.707 10.470 1.889 1.019
77.502 4.707 10.470 1.889 1.019

21
 Figure 16.log(∆Idsat(%)) vs log (t) for DUT-201

DUT#202

Time(hrs) IdSat(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.040 5.161 0.340 -1.389 -0.468
0.388 5.121 1.110 -0.410 0.045
0.737 5.101 1.506 -0.132 0.178
1.086 5.082 1.868 0.035 0.271
1.435 5.069 2.123 0.157 0.327
1.787 5.058 2.322 0.252 0.365
2.142 5.050
.
2.481 0.330 0.394
2.500 5.040 2.684 0.398 0.428
2.865 5.030 2.870 0.457 0.457
3.239 5.019 3.080 0.510 0.488
3.626 5.012 3.211 0.559 0.506
4.032 5.007 3.319 0.605 0.521
4.467 4.996 3.526 0.650 0.547
4.944 4.985 3.737 0.694 0.572
5.481 4.979 3.859 0.738 0.586
6.107 4.968 4.065 0.785 0.609
6.864 4.961 4.213 0.836 0.624
7.819 4.948
.
4.455 0.892 0.648
9.046 4.937 4.676 0.956 0.669
10.691 4.919 5.010 1.029 0.699
12.945 4.898 5.428 1.112 0.734
16.091 4.880 5.775 1.206 0.761
20.548 4.847 6.398 1.313 0.806
26.926 4.787 7.563 1.430 0.878
36.127 4.723 8.803 1.557 0.944
46.476 4.680 9.624 1.667 0.983
56.826 4.692 9.392 1.754 0.972
67.175 4.667 9.879 1.827 0.994
77.526 4.620 10.781 1.889 1.032

22
 Figure 17.log(∆Idsat(%)) vs log (t) for DUT-202

DUT#203

Time(hrs) IdSat(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.079 5.346 0.557 -1.100 -0.253
0.427 5.303 1.361 -0.368 0.134
0.776 5.283 1.736 -0.109 0.239
1.125 5.267 2.026 0.051 0.306
1.474 5.254 2.264 0.168 0.355
1.826 5.242 2.487 0.261 0.395
2.181 5.234 2.653 0.338 0.423
2.539 5.224 2.827 0.404 0.451
2.904 5.216 2.985 0.463 0.475
3.278 5.206 3.168 0.515 0.500
3.665 5.199 3.291 0.564 0.517
4.071 5.192 3.417 0.609 0.533
4.506 5.183 3.592 0.653 0.555
4.982 5.170 3.838 0.697 0.584
5.520 5.162 3.988 0.741 0.600
6.146 5.157 4.085 0.788 0.611
6.903 5.145 4.290 0.839 0.632
7.853 5.134 4.495 0.895 0.652
9.084 5.121 4.741 0.958 0.675
10.730 5.106 5.030 1.030 0.701
12.984 5.083 5.459 1.113 0.737
16.130 5.060 5.877 1.207 0.769
20.586 5.028 6.478 1.313 0.811
26.965 4.967 7.615 1.430 0.881
36.166 4.903 8.792 1.558 0.944
46.515 4.862 9.569 1.667 0.980
56.865 4.874 9.332 1.754 0.970
67.215 4.845 9.873 1.827 0.994
77.567 4.797 10.765 1.889 1.032

23
 Figure 18.log(∆Idsat(%)) vs log (t) for DUT-203

DUT#204

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.117 4.954 0.651 -0.931 -0.185
0.465 4.923 1.258 -0.331 0.100
0.814 4.906 1.601 -0.089 0.204
1.163 4.893 1.876 0.065 0.273
1.512 4.884 2.045 0.179 0.310
1.864 4.876 2.205 0.270 0.343
2.219 4.869 2.346 0.346 0.370
2.577 4.862 2.486 0.411 0.395
2.942 4.853 2.667 0.468 0.426
3.316 4.845 2.824 0.520 0.450
3.703 4.836 3.004 0.568 0.477
4.109 4.831 3.108 0.613 0.492
4.544 4.824 3.259 0.657 0.513
5.020 4.816 3.409 0.700 0.532
5.558 4.810 3.535 0.743 0.548
6.184 4.803 3.669 0.791 0.564
6.941 4.796 3.820 0.841 0.582
7.891 4.786 4.012 0.897 0.603
9.122 4.775 4.234 0.960 0.626
10.768 4.759 4.545 1.032 0.657
13.022 4.746 4.823 1.114 0.683
16.168 4.725 5.238 1.208 0.719
20.624 4.691 5.923 1.314 0.772
27.003 4.634 7.067 1.431 0.849
36.204 4.578 8.184 1.558 0.912
46.553 4.534 9.058 1.667 0.957
56.903 4.548 8.784 1.755 0.943
67.253 4.523 9.290 1.827 0.968
77.605 4.480 10.149 1.889 1.006

24
 Figure 19.log(∆Idsat(%)) vs log (t) for DUT-204

DUT#205

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.155 5.152 0.738 -0.807 -0.131
0.504 5.125 1.265 -0.297 0.102
0.852 5.107 1.608 -0.069 0.206
1.201 5.095 1.848 0.079 0.266
1.551 5.084 2.057 0.190 0.313
1.902 5.076 2.212 0.279 0.344
2.257 5.069 2.342 0.353 0.369
2.616 5.062 2.489 0.417 0.396
2.980 5.054 2.628 0.474 0.419
3.354 5.047 2.777 0.525 0.443
3.741 5.039 2.922 0.573 0.465
4.147 5.032 3.057 0.617 0.485
4.582 5.024 3.211 0.661 0.506
5.059 5.014 3.408 0.704 0.532
5.596 5.006 3.563 0.747 0.551
6.223 5.000 3.674 0.794 0.565
6.980 4.991 3.853 0.843 0.585
7.929 4.979 4.071 0.899 0.609
9.161 4.968 4.299 0.961 0.633
10.807 4.949 4.656 1.033 0.668
13.061 4.928 5.057 1.115 0.703
16.207 4.909 5.419 1.209 0.733
20.663 4.879 5.990 1.315 0.777
27.042 4.817 7.193 1.432 0.856
36.243 4.754 8.405 1.559 0.924
46.592 4.708 9.304 1.668 0.968
56.942 4.716 9.152 1.755 0.961
67.292 4.690 9.649 1.827 0.984
77.645 4.646 10.494 1.890 1.020

25
 Figure 20.log(∆Idsat(%)) vs log (t) for DUT-205

DUT#207

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.194 4.876 0.772 -0.712 -0.112
0.542 4.852 1.257 -0.265 0.099
0.891 4.840 1.507 -0.05 0.178
1.239 4.824 1.835 0.093 0.263
1.5895 4.814 2.033 0.201 0.308
1.941 4.805 2.217 0.288 0.345
2.295 4.798 2.360 0.360 0.372
2.654 4.791 2.504 0.423 0.398
3.019 4.785 2.624 0.479 0.418
3.393 4.778 2.753 0.530 0.439
3.780 4.771 2.908 0.577 0.463
4.186 4.763 3.063 0.621 0.486
4.621 4.756 3.218 0.664 0.507
5.097 4.744 3.446 0.707 0.537
5.635 4.738 3.582 0.750 0.554
6.261 4.733 3.686 0.796 0.566
7.018 4.724 3.857 0.846 0.586
7.968 4.716 4.020 0.901 0.604
9.200 4.706 4.233 0.963 0.626
10.845 4.689 4.564 1.035 0.659
13.099 4.670 4.951 1.117 0.694
16.245 4.648 5.401 1.210 0.732
20.701 4.620 5.976 1.316 0.776
27.080 4.561 7.183 1.432 0.856
36.282 4.505 8.317 1.559 0.920
46.631 4.464 9.157 1.668 0.962
56.980 4.479 8.839 1.755 0.946
67.330 4.456 9.316 1.828 0.969
77.683 4.415 10.159 1.890 1.007

26
 Figure 21.log(∆Idsat(%)) vs log (t) for DUT-207

DUT#208

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.232 4.945 0.759 -0.633 -0.119
0.581 4.926 1.127 -0.235 0.052
0.929 4.913 1.402 -0.031 0.147
1.278 4.900 1.657 0.106 0.219
1.627 4.892 1.805 0.211 0.256
1.979 4.884 1.972 0.296 0.294
2.334 4.878 2.100 0.368 0.322
2.692 4.870 2.252 0.430 0.352
3.057 .
4.863 2.389 0.485 0.378
3.431 4.855 2.563 0.535 0.408
3.818 4.849 2.679 0.581 0.427
4.224 4.842 2.809 0.625 0.448
4.659 4.835 2.949 0.668 0.469
5.136 4.826 3.144 0.710 0.497
5.673 4.819 3.288 0.753 0.516
6.299 4.814 3.376 0.799 0.528
7.056 4.809 3.488 0.848 0.542
8.006 4.797 3.722 0.903 0.570
9.238 4.788 3.911 0.965 0.592
10.884 4.776 4.152 1.036 0.618
13.137 4.760 4.466 1.118 0.649
16.283 4.741 4.844 1.211 0.685
20.739 4.710 5.460 1.31 0.737
27.119 4.657 6.528 1.433 0.814
36.320 4.608 7.508 1.560 0.875
46.67 4.565 8.382 1.669 0.923
57.019 4.582 8.039 1.756 0.905
67.37 4.562 8.432 1.828 0.925
77.723 4.526 9.159 1.890 0.961
87.802 4.504 9.606 1.943 0.982
97.841 4.483 10.028 1.990 1.001

27
 Figure 22.log(∆Idsat(%)) vs log (t) for DUT-208

DUT#209

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.271 5.059
.
0.882 -0.566 -0.054
0.619 5.038 1.295 -0.207 0.112
0.968 5.020 1.637 -0.013 0.214
1.316 5.012 1.808 0.119 0.257
1.666 5.001 2.021 0.221 0.305
2.018 4.993 2.175 0.304 0.337
2.372 4.984 2.355 0.375 0.372
2.731 4.976 2.502 0.436 0.398
3.096 4.969 2.641 0.490 0.421
3.470 4.962 2.780 0.540 0.444
3.857 4.956 2.902 0.586 0.462
4.263 4.949 3.035 0.629 0.482
4.698 4.940 3.201 0.671 0.505
5.175 4.933 3.349 0.713 0.524
5.712 4.924 3.519 0.756 0.546
6.338 4.916 3.673 0.802 0.565
7.095 4.905 3.895 0.851 0.590
8.045 4.893
.
4.133 0.905 0.616
9.277 4.882 4.339 0.967 0.637
10.923 4.865 4.689 1.038 0.671
13.176 4.849 4.993 1.119 0.698
16.323 4.822 5.516 1.212 0.741
20.779 4.794 6.074 1.317 0.783
27.158 4.733 7.261 1.433 0.861
36.359 4.673 8.436 1.560 0.926
46.709 4.626 9.362 1.669 0.971
57.059 4.631 9.264 1.756 0.966
67.409 4.607 9.740 1.828 0.988
77.762 4.562 10.613 1.890 1.0258

28
 \

Figure 23.log(∆Idsat(%)) vs log (t) for DUT-209

DUT#211

Time(hrs) IdSat1(mA) ∆ Idsat(%) log (t) log(∆Idsat(%))

0.309 5.192 1.092 -0.509 0.038
0.658 5.169 1.544 -0.181 0.188
1.006 5.153 1.853 0.002 0.267
1.355 5.142 2.062 0.132 0.314
1.705 5.128 2.312 0.231 0.364
2.056 .
5.118 2.504 0.313 0.398
2.411 5.109 2.680 0.382 0.428
2.77 5.099 2.876 0.442 0.458
3.134 5.091 3.027 0.496 0.481
3.508 5.084 3.159 0.545 0.499
3.895 5.078 3.281 0.590 0.516
4.302 5.072 3.391 0.633 0.530
4.737 5.062 3.583 0.675 0.554
5.213 5.052 3.759 0.717 0.575
5.750 5.046 3.885 0.759 0.589
6.377 5.036 4.065 0.804 0.609
7.134 5.029 4.210 0.853 0.624
8.083 5.016 4.446 0.907 0.647
9.315 5.002 4.722 0.969 0.674
10.961 4.986 5.0258 1.039 0.701
13.215 4.967 5.378 1.121 0.730
16.361 4.937 5.964 1.213 0.775
20.817 4.900 6.655 1.318 0.823
27.196 4.838 7.851 1.434 0.894
36.396 4.778 8.987 1.561 0.953
46.747 4.731 9.880 1.669 0.994
57.098 4.738 9.748 1.756 0.988
67.448 4.715 10.178 1.828 1.007

29
 Figure 24.log(∆Idsat(%)) vs log (t) for DUT-211

DUT#212

Time(hrs) IdSat1(mA) ∆Idsat(%) log (t) log(∆Idsat(%))

0.347 4.835 1.017 -0.458 0.007
0.696 4.817 1.382 -0.156 0.140
1.045 4.804 1.650 0.019 0.217
1.393 4.794 1.839 0.144 0.264
1.743 4.785 2.028 0.241 0.307
2.095 4.779 2.165 0.321 0.335
2.449 4.772 2.303 0.389 0.362
2.808 4.766 2.412 0.448 0.3824
3.173 4.757 2.614 0.501 0.417
3.547 4.751 2.736 0.549 0.437
3.933 4744 2.871 0.594 0.458
4.340 4.736 3.026 0.637 0.480
4.775 4.729 3.179 0.679 0.502
5.251 4.721 3.335 0.720 0.523
5.789 4.715 3.475 0.762 0.541
6.415 4709 3.598 0.807 0.556
7.172 4.702 3.733 0.855 0.572
8.122 4.691 3.965 0.909 0.598
9.353 4.676 4.255 0.970 0.628
10.999 4.666 4.466 1.041 0.649
13.256 4.650 4.788 1.122 0.680
16.399 4.631 5.178 1.214 0.714
20.855 4.601 5.808 1.319 0.764
27.234 4.546 6.933 1.435 0.841
36.435 4.489 8.082 1.561 0.908
46.784 4.452 8.853 1.670 0.947
57.133 4.462 8.638 1.756 0.936
67.483 4.443 9.024 1.829 0.955
77.798 4.402 9.883 1.890 0.995
87.836 4.386 10.201 1.943 1.009

30
 Figure 25.log(∆Idsat(%)) vs log (t) for DUT-212

4.7.4. SUMMARY:

Serial NO DUT NO ∆ Idsat(mA) Time duration for 10% n log C

Degradation(hrs)
1 201 0.585 97.232 0.455 0.220
2 202 0.601 104.343 0.444 0.239
3 203 0.629 132.070 0.415 0.276
4 204 0.542 143.714 0.418 0.231
5 205 0.582 128.574 0.429 0.225
6 207 0.529 126.923 0.431 0.216
7 208 0.495 143.509 0.429 0.172
8 209 0.583 114.565 0.443 0.207
9 211 0.61 122.195 0.424 0.265
10 212 0.522 140.108 0.425 0.207

HCI shows power-law (~tn) time dependence, with time exponents in the range of 0.3 to
0.70.

31
5.REFERENCES
1. Reliability Wearout Mechanisms in Advanced CMOS Technologies by Alvin W.
Strong (Wiley-IEEE Press 2009).


2.

Silicon Processing for the VLSI Era, Vol. 3: The Submicron MOSFET by Stanley Wolf

3. Mosfet Modelling for VLSI Simulation: Theory And Practice (International Series on
Advances in Solid State Electronics) (International Series on Advances in Solid State
Electronics and Technology)



4. Ben Street Men solid state electronic devices

5. Introduction to Microfabrication by Sami Franssila.

32
33