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LDC - V - 1 - 0.pdsprj 13-01-2019 LDC - V - 1 - 0.pdsprj

The document contains a circuit schematic showing a voltage regulator circuit using an LM2576 voltage regulator IC to step down a 24V DC input to 5V. The schematic includes the voltage regulator IC, an inductor, capacitors, resistors, and an LED for indicating output voltage. The circuit is designed to provide a regulated 5V output from an unregulated 24V DC input source.

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sureshpawan2010
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© © All Rights Reserved
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0% found this document useful (0 votes)
97 views5 pages

LDC - V - 1 - 0.pdsprj 13-01-2019 LDC - V - 1 - 0.pdsprj

The document contains a circuit schematic showing a voltage regulator circuit using an LM2576 voltage regulator IC to step down a 24V DC input to 5V. The schematic includes the voltage regulator IC, an inductor, capacitors, resistors, and an LED for indicating output voltage. The circuit is designed to provide a regulated 5V output from an unregulated 24V DC input source.

Uploaded by

sureshpawan2010
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
You are on page 1/ 5

A B C D E F G H J K

0 0

1 1

2 2
U1
LM2576(V2)

+3.3V
J1 4 U2
3 +5V LM1117DT-3,3 3
1 1 LM2576
+24V DC L1
GND 2 R1
1 2 IN OUT 3
2 100UH INDUCTOR 2
330
C1 C3

C
GND
3

5
100U 100n LD1
4 D1 C2 C4 4
1 C5 LED_SMD
1N5822 100n

A
1000U 100n

5 5

6 6

7 7

8 8

FILE NAME: LDC_V_1_0.pdsprj DATE:

DESIGN TITLE: LDC_V_1_0.pdsprj


13-01-2019
PAGE:
9 PATH: P.S E:\PCB_SCHEMATIC\PCB_SCHEMATIC_PROTEUS\JASSI\LDC
1 of 5
9

BY: @AUTHOR REV:@REV TIME: 16:06:36


A B C D E F G H J K
A B C D E F G H J K

+3.3V +3.3V
0 +3.3V U3 0
23 PA0-WKUP PE0
24 97 J2
J3 RMII_REF_CLK
25
PA1 PE1
98 C32 1
4 MII_MDIO PA2 PE2 100n
3
26 PA3 PE3
1 2 R6
SWDIO 29 2 3 10k
2 PA4 PE4
SWCLK 30 3 TX 4
1 1 PA5 PE5 HM10_RX 1
31 4 RX 5
PA6 PE6 HM10_TX
32 5 6
PROG RMII_CRSDV PA7 PE7 RST
67 38
MCO PA8 PE8
68 39 HM10_BLE
PA9 PE9
69 PA10 PE10
40 C10
70 41 100n
PROG PA11 PE11
71 42
2 PA12 PE12
43
2
SWDIO 72 PA13 PE13
76 44 BLUETOOTH
SWCLK PA14 PE14
77 45
(SPI_3) CS PA15 PE15
+3.3V 46
35 PB0 PD0 RESET
36 81
3 CS
U20 37
PB1 PD1
82 3
1 PB2 PD2 +3.3V
/CS VCC 89 83
2 8 PB3 PD3
MISO DO /HOLD 90 84
3 7 PB4 PD4
+3.3V /WP CLK SCLK 91 85
4 6 PB5 PD5
GND DI MOSI 92 86
5 PB6 PD6
93 87 L2
W25Q64 PB7 PD7
95 88
PB8 PD8 HM10_RX
4 96 PB9 PD9
55
HM10_TX 4
MEMORY 47 56
PB10 PD10
48 57 R7
MII_TX_EN PB11 PD11
51 58 VREF+ VDDA
MII_TXD0 PB12 PD12
52 59 47
MII_TXD1 PB13 PD13
53 60
MII_INT PB14 PD14
54 PB15 PD15
61
C15 C16 C13 C14
5 62 1.0u 100n 5
15
R8 1.0u 100n
PC0 RFU
16 99
MII_MDC PC1 NRST RST 10k
17 14
PC2
18 PC3 VREF+ VREF+
33 21
C8 12pF MII_RXD0
34
PC4 VBAT
6
VBAT C12
6 R4 0R MII_RXD1 PC5 6
63 PC6 VCAP_2 2.2u
64 73
PC7 VCAP_1 ADC POWER SUPPLY
65 49 +3.3V
PC8 C11
2

66 VDDA 2.2u
PC9 VDDA
X2 78 22
SCLK PC10 VDD
79 100
32.768 KHz SPI_3 MISO PC11 VDD
80 75
7 MOSI PC12 VDD
50
C17 C18 C19 C20 C21 C22 7
7 PC13-RTC_AF1 VDD +3.3V
1

8 28
PC14-OSC32_IN VDD 100n 100n 100n 100n 100n 100n
9 19
PC15-OSC32_OUT VDD VBAT
11
C7 R5 0R
C9 12pF 12
1

PH0-OSC_IN VSSA

1
13 20
20pF X1
R3 PH1-OSC_OUT VSS
74
8 VSS 8
25MHz 390 94 BOOT0 VSS
27 BAT
10
2

LDC_V_1_0.pdsprj
2

STM32F207 FILE NAME: DATE:


R2
C6 20pF 0R DESIGN TITLE: LDC_V_1_0.pdsprj
13-01-2019
PAGE:
9 PATH: MCU E:\PCB_SCHEMATIC\PCB_SCHEMATIC_PROTEUS\JASSI\LDC
2 of 5
9

BY: @AUTHOR REV:@REV TIME: 16:06:36


A B C D E F G H J K
A B C D E F G H J K

+3.3V +3.3V
0 0
+3.3V

R25 R20 R21


1.50k 2.20K 2.20K
1 1
C30

R16
51.0
R17
R18
R19
U4 100n
MII_MDC 31 MDC RSV C24 C25
30 20 C23
MII_MDIO 0R MDIO RSV
21
2 R24
1
PFBIN1
18 100n 100n 2
TX_CLK PFBOUT R10 10u
R26 2 23 CN1
MII_TX_EN 51.0 TX_EN RBIAS R1
R27 51.0 3 24 TD+
MII_TXD0 TXD_0 PFBIN2 4.87K +3.3V R2
R28 51.0 4 37 C26 TD-
MII_TXD1 TXD_1 R7
R29 5 TXD_2 TDI RD+
+3.3V MII_RXD0 51.0 6 12 R8 RD-
R30 TXD_3/SNI_MODE TRST# 100n R3
3 38 11 CT 3
MII_RXD1 51.0 RX_CLK TMS
R31 39 10 R11 240
RX_DV/MII_MODE TDO L1
RMII_CRSDV 51.0 41 9 LED(YELLOW)_A
R32 RX_ER/MDIX_EN TCK L2
R33 43 8 YEL_LED_K LED(YELLOW)_K
RXD_0/PHY AD1 L3
2.20K 51.0 44 RXD_1/PHY AD2 TD+ TD+ LED(GREEN)_A
+3.3V 45 17 240 R12 GRN_LED_K L4 LED(GREN)_K
MII_RX_ER RXD_2/PHY AD3 TD- TD-
TP1 46 16
RXD_3/PHY AD4 RD+ RD+ C31 R4
4 1 40 14 NC 4
RMII_REF_CLK CRS/CRS_DV/LED_CFG RD- RD- R5
42 13 100n NC
COL/PHY AD0 R6
IOVDD33 NC
R9 7

+3.3V
R14

2.20K

32
R15

R13

MCO 34 X1 IOVDD33 SHIELD


PA8 33 48 8 SHIELD
51.0 X2 AVDD33
25 22
CLK_OUT UDE_MAG_JACK
5 YEL_LED_K 28 LED_LINK/AN0 AGND
5
27 15
LED_SPEED/AN1 AGND
26 19
GRN_LED_K LED_ACT/COL/AN_EN IOGND
35
IOGND
29 47
RST RESET_N DGND
+3.3V

7 36
PWR_DOWN/INT
6 R22 2.20K 6
DP83848CVV
MII_INT +3.3V
R23 0R

C27 C28 C29


7 100n
7
100n 100n

8 8

ETHERNET CONNECTION FILE NAME:LDC_V_1_0.pdsprj DATE:

DESIGN TITLE: LDC_V_1_0.pdsprj


13-01-2019
9 PAGE: 9
PATH: E:\PCB_SCHEMATIC\PCB_SCHEMATIC_PROTEUS\JASSI\LDC
3 of 5
BY: @AUTHOR REV:@REV TIME: 16:06:36
A B C D E F G H J K
A B C D E F G H J K
24V_S1 24V_S7 +5V
R41 +5V R71
R34 2.00K
0 U5 LD8 2.00K R58 2.00K
U11 LD20 2.00K
0
1 A C 4
1 A C 4
C A
R40 R70
R49 C A
A C 2 3 2.00K R64 A C 2 3 2.00K
2.00K K E
OP_1 2.00K K E OP_7
LD2 PC817
1 24V_S2 +5V LD14 PC817 1
24V_S8 +5V
R43 R73
R35 U6 LD9 2.00K R59 U12
2.00K LD21 2.00K
1 A C 4 2.00K
1 A C 4
C A
R42 R72
2 R50 C A 2
A C 2 3 2.00K R65 A C 2 3 2.00K
2.00K K E OP_2 OP_8
2.00K K E
LD3 PC817
24V_S3 +5V LD15 PC817
24V_S9 +5V
R45 R75
R36 U7 LD10 2.00K R60 U13
3 2.00K
A C 2.00K
LD22 2.00K 3
1 4 A C
R44 1 4
C A
C A
R74
R51 A C 2 3 2.00K R66 A C 2 3 2.00K
2.00K K E OP_3
2.00K K E OP_9
LD4 PC817
24V_S4 +5V LD16 PC817
4 24V_S10 +5V 4
R47 R77
R37 U8 LD11 2.00K R61 U14
2.00K LD23 2.00K
1 A C 4 2.00K
1 A C 4
C A
R46 R76
R52 C A
5 A C 2 3 2.00K R67 A C 2 3 2.00K 5
2.00K K E OP_4
2.00K K E OP_10
LD5 PC817
24V_S5 +5V LD17 PC817
24V_S11 +5V
R55 R79
R38 U9 LD12 2.00K R62 U15 LD24
6 2.00K A C 2.00K 6
1 4 2.00K A C
R48 1 4
C A
C A
R78
R53 A C 2 3 2.00K R68 A C 2 3 2.00K
K E OP_5 2.00K OP_11
2.00K K E +5V
LD6 PC817
+5V LD18 PC817 R81
24V_S6 24V_S12
7 R57 R63 U16 7
LD25 2.00K
2.00K A C
R39 1 4
2.00K
U10 LD13 2.00K R80
1 A C 4 C A
R56 R69 A C 2 3 2.00K
C A
R54 2.00K K E OP_12
8 A C 2 3 2.00K PC817 8
K E OP_6 LD19
2.00K
LD7 PC817
FILE NAME: LDC_V_1_0.pdsprj DATE:

DESIGN TITLE: LDC_V_1_0.pdsprj


13-01-2019
9 INPUT SECTION PATH:
PAGE:
4 of 5
9
E:\PCB_SCHEMATIC\PCB_SCHEMATIC_PROTEUS\JASSI\LDC
BY: @AUTHOR REV:@REV TIME: 16:06:36
A B C D E F G H J K
A B C D E F G H J K

0 24V_S13 0
R89 +5V ADC_IN
R82 2.00K
U17 LD29 2.00K
1 A C 4
C A
R88
1 R85 R94 1
A C 2 3 2.00K 6.80k
2.00K K E OP_13
PC817
24V_S14 LD26
+5V
R96
V_OUT
R91 0R
R83 U18
2 2.00K
LD30 2.00K R95 D2 2
1 A C 4 BZT52C5V1S-7-F
2.20K
C A
R90
R86 A C 2 3 2.00K
K E OP_14
2.00K
LD27 PC817
24V_S15 +5V
3 3
R93
R84 U19 LD31 2.00K
2.00K
1 A C 4
C A
R92 J4
R87 A C 2 3 2.00K 24V_S1 1 2 24V_S2
4 3 4 4
K E OP_15 24V_S3
2.00K 5 6
24V_S16 LD28 PC817 +5V 7 8
R100 24V_S5 9 10 24V_S4
24V_S7 11 12 24V_S6
R97 U21 13 14
LD33 2.00K 24V_S9 24V_S8
2.00K 15 16
1 A C 4 24V_S11 24V_S10
5 R99 17 18 5
C A 19 20
R98 A C 2 3 2.00K
24V_S13
21 22
24V_S12
24V_S15
K E OP_16 23 24
2.00K 25 26
LD32 PC817
27 28 ADC_IN
29 30
6 31 32
6
24V_S14 24V_S16
33 34

INPUT_SECTION 10056845-134LF

7 7

8 8

FILE NAME: LDC_V_1_0.pdsprj DATE:

DESIGN TITLE: LDC_V_1_0.pdsprj


13-01-2019
9 PAGE: 9
PATH: E:\PCB_SCHEMATIC\PCB_SCHEMATIC_PROTEUS\JASSI\LDC
5 of 5
BY: @AUTHOR REV:@REV TIME: 16:06:36
A B C D E F G H J K

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