Order this document by MC44602/D


 

    
The MC44602 is an enhanced high performance fixed frequency current
mode controller that is specifically designed for off–line and high voltage HIGH PERFORMANCE
dc–to–dc converter applications. This device has the unique ability of
changing operating modes if the converter output is overloaded or shorted,
CURRENT MODE
offering the designer additional protection for increased system reliability. CONTROLLER
The MC44602 has several distinguishing features when compared to
conventional current mode controllers. These features consist of a foldback SEMICONDUCTOR
amplifier for overload detection, valid load and demag comparators with a TECHNICAL DATA
fault latch for short circuit detection, thermal shutdown, and separate high
current source and sink outputs that are ideally suited for driving a high
voltage bipolar power transistor, such as the MJE18002, MJE18004, or
MJE18006.
Standard features include an oscillator with a sync input, a temperature
compensated reference, high gain error amplifier, and a current sensing
comparator. Protective features consist of input and reference undervoltage
lockouts each with hysteresis, cycle–by–cycle current limiting, a latch for 16
single pulse metering, and a flip–flop which blanks the output off every other 1
oscillator cycle, allowing output deadtimes to be programmed from 50% to
70%. This device is manufactured in a 16 pin dual–in–line heat tab package
for improved thermal conduction. P2 SUFFIX
• Separate High Current Source and Sink Outputs Ideally Suited for PLASTIC PACKAGE
Driving Bipolar Power Transistors: 1.0 A Source, 1.5 A Sink CASE 648C
DIP (12 + 2 + 2)
• Unique Overload and Short Circuit Protection
• Thermal Protection
• Oscillator with Sync Input
• Current Mode Operation to 500 kHz Output Switching Frequency PIN CONNECTIONS
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting Compensation 1 16 Vref

• Input and Reference Undervoltage Lockouts with Hysteresis

Load Detect Input 2 15 VCC
• Low Startup and Operating Current
Voltage Feedback Input 3 14 VC

4 13
Simplified Block Diagram Sink Gnd Sink Gnd
5 12
VCC
5.0V Undervoltage
Vref VCC
Reference Lockout 15 Current Sense Input 6 11 Source Output
16
Vref
Undervoltage Sync Input 7 10 Sink Output
Lockout
Short Circuit RT/CT 8 9 Gnd
Sync Input Detection Load Detect Input
7 2

VC
(Top View)
RT/CT Oscillator 14
8 Flip Flop
and Source Output
Latching Thermal 11
Compensation PWM Sink Output
1 Error 10
Amplifier
Sink Ground
Voltage Feedback–Input 4, 5, 12, 13 ORDERING INFORMATION
3 Foldback
Amplifier
Current Sense Input
Operating
6 Device Temperature Range Package
MC44602 TA = – 25 to 85°C DIP (12 + 2 + 2)
Gnd 9

 Motorola, Inc. 1996 Rev 0

MOTOROLA ANALOG IC DEVICE DATA 1
 MC44602
MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Sink Ground Voltage VSink(neg) –5.0 V
with Respect to Gnd (Pin 9)

Output Supply Voltage VC 20 V

with Respect to Sink Gnd (Pins 4, 5, 12, 13)

Output Current (Note 1) A

Source IO(Source) 1.0
Sink IO(Sink) 1.5
Output Energy (Capacitive Load per Cycle) W 5.0 µJ
Current Sense and Voltage Feedback Inputs Vin –0.3 to 5.5 V
Sync Input
High State Voltage VIH 5.5 V
Low State Reverse Current IIL –20 mA
Load Detect Input Current Iin –20 to +10 mA
Error Amplifier Output Sink Current IEA (Sink) 10 mA
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation at TA = 25°C PD 2.5 W
Thermal Resistance, Junction–to–Air RθJA 80 °C/W
Thermal Resistance, Junction–to–Case RθJC 15 °C/W
Operating Junction Temperature TJ 150 °C
Operating Ambient Temperature TA –25 to +85 °C
NOTE: 1. Maximum package power dissipation limits must be observed.

ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V [Note 2], RT = 10k, CT = 1.0 nF, for typical values TA = 25°C, for min/max
values TA = –25°C to +85°C [Note 3] unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5V) VFB 2.45 2.5 2.65 V
Input Bias Current (VFB = 2.5 V) IIB – –0.6 –2.0 µA
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 – dB
Unity Gain Bandwidth BW MHz
TJ = 25°C 1.0 1.4 1.8
TA = –25 to +85°C 0.8 – 2.0
Power Supply Rejection Ratio (VCC = 10 V to 16 V) PSRR 65 70 – dB
Output Current mA
Sink (VO = 1.5 V, VFB = 2.7 V) ISink
Sink TJ = 25°C – 5.0 –
Sink TA = –25 to +85°C 1.5 – 10

Source (VO = 5.0 V, VFB = 2.3 V) ISource

Source TJ = 25°C – –1.1 –
Source TA = –25 to +85°C –2.0 – –0.2
Output Voltage Swing V
High State (IO(Source) = 0.5 mA, VFB = 2.3 V) VOH 6.0 7.0 –
Low State (IO(Sink) = 0.33 mA, VFB = 2.7 V) VOL – 1.0 1.1
NOTES: 2. Adjust VCC above the startup threshold before setting to 12V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

2 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V [Note 2], RT = 10k, CT = 1.0 nF, for typical values TA = 25°C, for min/max
values TA = –25°C to +85°C [Note 3] unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
OSCILLATOR SECTION
Frequency fOSC kHz
TJ = 25°C 168 180 192
TA = –25°C to +85°C 160 – 200
Frequency Change with Voltage (VCC = 12 V to 18 V) ∆fOSC/∆V – 0.1 0.2 %/V
Frequency Change with Temperature ∆fOSC/∆T – 0.05 – %/°C
Oscillator Voltage Swing (Peak–to–Peak) VOSC(pp) 1.3 1.6 – V
Discharge Current (VOSC = 3.0 V) Idischg mA
TJ = 25°C 6.5 10 13.5
TA = –25°C to +85°C 6.0 – 14
Sync Input Threshold Voltage V
High State VIH 2.5 2.8 3.2
Low State VIL 1.0 1.3 1.7
Sync Input Resistance Rin kΩ
TJ = 25°C 6.5 10 13.5
TA = –25°C to +85°C 6.0 – 18

REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA) Vref 4.7 5.0 5.3 V
Line Regulation (VCC = 12 V to 18 V) Regline – 1.0 10 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload – 3.0 15 mV
Temperature Stability TS – 0.2 – mV/°C
Total Output Variation over Line, Load and Temperature Vref 4.65 – 5.35 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn – 50 – µV
Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – mV
Output Short Circuit Current ISC mA
TJ = 25°C – –130 –
TA = –25°C to +85°C –70 – –180

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 4 & 5) AV V/V
TJ = 25°C 2.85 3.0 3.15
TA = –25°C to +85°C 2.7 – 3.2
Maximum Current Sense Input Threshold (Note 4) Vth 0.9 1.0 1.1 V
Input Bias Current IIB – –4.0 –10 µA
Propagation Delay (Current Sense Input to Sink Output) tPLH(in/out) – 100 150 ns
UNDERVOLTAGE LOCKOUT SECTIONS
Startup Threshold (VCC Increasing) Vth 13 14.1 15 V
Minimum Operating Voltage After Turn–On (VCC Decreasing) VCC(min) 9.0 10.2 11 V
Reference Undervoltage Threshold (Vref Decreasing) Vref(UVLO) 3.0 3.35 3.7 V
NOTES: 2. Adjust VCC above the startup threshold before setting to 12V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. This parameter is measured at the latch trip point with IFB = –5.0 µA, refer to Figure 9.
∆V Compensation
5. Comparator gain is defined as AV =
∆V Current Sense Input

MOTOROLA ANALOG IC DEVICE DATA 3

 MC44602

ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V [Note 2], RT = 10k, CT = 1.0 nF, for typical values TA = 25°C, for min/max
values TA = –25°C to +85°C [Note 3] unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
OUTPUT SECTION
Output Voltage (TA = 25°C) V
Low State (ISink = 100 mA) VOL – 0.6 0.3
Low State (ISink = 1.0A) – 1.8 2.0
Low State (ISink = 1.5 A) – 2.1 2.6

High State (ISource = 50 mA) (VCC–VOH) – 1.4 1.7

High State (ISource = 0.5 A) – 1.7 2.0
High State (ISource = 0.75 A) – 1.8 2.2
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) – 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr – 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf – 50 150 ns
PWM SECTION
Duty Cycle %
Maximum DC(max) 46 48 50
Minimum DC(min) – – 0

TOTAL DEVICE
Power Supply Current ICC mA
Startup (VCC = 5 V) – 0.2 0.5
Operating (Note 2)
TJ = 25° C – 17 20
TA = –25°C to +85° C 10 – 22
Power Supply Zener Voltage (ICC = 25 mA) VZ 18 20 23 V
OVERLOAD AND SHORT CIRCUIT PROTECTION
Foldback Amplifier Threshold (Figures 9,10) ∆VFB (VFB–100) (VFB–200) (VFB–300) mV
Load Detect Input
Valid Load Comparator Threshold (VPin 2 Increasing) Vth(VL) 2.0 2.5 3.0 V
Demag Comparator Threshold (VPin 2 Decreasing) Vth(Demag) 50 88 120 mV
Propagation Delay (Input to Sink or Source Output) tPLH(in/out) – 1.1 1.6 µS
Input Resistance Rin 12 18 30 kΩ
NOTES: 2. Adjust VCC above the startup threshold before setting to 12V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Figure 1. Timing Resistor Figure 2. Output Deadtime

versus Oscillator Frequency

ÄÄÄÄ
versus Oscillator Frequency
80 75

ÄÄÄÄ
1. CT = 10 nF Note: Output switches at
50 CT=100 pF 2. CT = 5.0 nF one–half the oscillator
% DT, PERCENT OUTPUT DEADTIME

CT=500 pF

ÄÄÄÄ
3. CT = 2.0 nF frequency.
30 70 4. CT = 1.0 nF
R T, TIMING RESISTOR (k Ω)

ÄÄÄÄ ÄÄ
ÄÄ
CT=200 pF 5. CT = 500 pF
20 CT=5.0 nF
6. CT = 100 pF 5

Ä ÄÄ Ä
CT=2.0 nF
65
4

ÄÄ Ä Ä
10 CT=1.0 nF
8.0 3 6
CT=10 nF

Ä ÄÄ
5.0 60
2
3.0
2.0
VCC = 12 V
TA = 25°C
Note: Output switches at
55 Ä 1

VCC = 12 V
1.0 one–half the oscillator frequency. TA = 25°C
0.8 50
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (Hz) fOSC, OSCILLATOR FREQUENCY (Hz)

4 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

Figure 3. Oscillator Discharge Current Figure 4. Oscillator Voltage Swing

versus Temperature versus Temperature
12 5.0

V OSC , OSCILLATOR VOLTAGE SWING (V)

VCC = 12 V VCC = 12 V
I dischg , DISCHARGE CURRENT (mA)

VOSC = 3.0 V RT = 10 k
11 4.0 CT = 1.0 nF

10 3.0 Peak Voltage

9.0 2.0

8.0 1.0 Valley Voltage

7.0 0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 5. Error Amp Small Signal Figure 6. Error Amp Large Signal
Transient Response Transient Response

2.55 V VCC = 12 V 3.0 V VCC = 12 V

AV = –1.0 AV = –1.0
TA = 25°C TA = 25°C

200 mV/DIV
20 mV/DIV

2.5 V 2.5 V

2.45 V 2.0 V

t, TIME (0.5 µs/DIV) t, TIME (1.0 µs/DIV)

Figure 7. Error Amp Open Loop Gain and Figure 8. Current Sense Input Threshold versus
Phase versus Frequency Error Amp Output Voltage
100 0 1.2
Vth, CURRENT SENSE INPUT THRESHOLD (V)

VCC = 12 V
A VOL , OPEN LOOP VOLTAGE GAIN (dB)

VO = 2.0 V to 4.0 V
80 RL = 100 k 30 1.0
EXCESS PHASSE (DEGREES)

TA = 25°C TA = 125°C
Gain
60 60 0.8

Phase TA = –40°C
40 90 0.6
TA = 25°C
20 120 0.4

0 150 0.2
VCC = 12 V
–20 180 0
0.1 k 1.0 k 10 k 100 k 1.0 M 10 M 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V)

MOTOROLA ANALOG IC DEVICE DATA 5

 MC44602

Figure 9. Voltage Feedback Input, Figure 10. Voltage Feedback Input

Voltage versus Current versus Current Sense Clamp Level
2.6 2.6
VClamp = 1.0 V VCC = 12 V

2.2 2.2
V in , INPUT VOLTAGE (V)

V in , INPUT VOLTAGE (V)

VCC = 12 V VClamp = 0.7 V
TA = 25°C
TA = 125°C
1.8 1.8
TA = 25°C

VClamp = 0.3 V VClamp = 0.5 V TA = –55°C

1.4 1.4

VClamp = 0.1 V
1.0 1.0
–500 –400 –300 –200 –100 0 0 0.2 0.4 0.6 0.8 1.0
Iin, INPUT CURRENT (µA) VClamp, CURRENT SENSE CLAMP LEVEL (V)

Figure 11. Reference Short Circuit Current Figure 12. Reference Line and Load
versus Temperature Regulation versus Temperature
I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)

200 3.0
∆V ref , REFERENCE VOLTAGE CHANGE (mA)
VCC = 12 V
RL ≤ 0.1 Ω 2.0

160 1.0
Line Regulation
0 VCC = 12 V to 18 V
Iref = 0 mA
120 –1.0

–2.0
Load Regulation
80 –3.0 VCC = 12 V
Iref = 1.0 mA to 20 mA
–4.0

40 –5.0
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 13. Reference Voltage Change Figure 14. Thermal Resistance and Maximum
versus Source Current Power Dissipation versus P.C.B. Copper Length
R θ JA , THERMAL RESISTANCE JUNCTION TO AIR (° C/W)

0
∆V ref , REFERENCE VOLTAGE CHANGE (mV)

100 5.0
TA = –55°C

ÉÉÉ
ÉÉÉ P D , MAXIMUM POWER DISSIPATION (W)
Printed circuit board heatsink example
–5.0

ÉÉÉ
ÉÉÉ
80 L 2.0 oz 4.0
Copper
–10
TA = 25°C RθJA L 3.0 mm
60 Graphs represent symmetrical layout 3.0
–15
TA = 125°C
40 2.0
–20

PD(max) for TA = 70°C

–25 20 1.0
VCC = 12 V
–30
0 30 60 90 120 150 180 0 0
0 10 20 30 40 50
Iref, REFERENCE SOURCE CURRENT (mA)
L, LENGTH OF COPPER (mm)

6 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

Figure 15. Output Waveform Figure 16. Output Cross Conduction

V O , OUTPUT VOLTAGE
VCC = 12 V VCC = 12 V
Voltage CL = 2.0 nF CL = 15 pF –90%
TA = 25°C TA = 25°C
90% 1.0 A

Current –10%
0

I CC, SUPPLY CURRENT

20 mA/DIV
10% –1.0 A

t, TIME (100 ns/DIV) t, TIME (50 ns/DIV)

Figure 17. Sink Output Saturation Voltage Figure 18. Source Output Saturation Voltage
versus Sink Current versus Load Current
3.0 0
Vsat, SINK OUTPUT SATURATION VOLTAGE (V)

Vsat, SINK OUTPUT SATURATION VOLTAGE (V)

Sink Saturation TJ = –55°C VCC = 12 V
VCC 80 µs Pulsed Load
2.5 (Load to VCC) –0.5
120 Hz Rate

2.0 –1.0
TJ = 25°C TJ = 125°C
1.5 –1.5

TJ = 125°C
1.0 –2.0 TJ = 25°C
TJ = –55°C

0.5 VCC = 12 V –2.5

80 µs Pulsed Load Source Saturation
Gnd 120 Hz Rate (Load to Ground)
0 –3.0
0 250 500 750 1000 1250 1500 1750 0 150 300 450 600 750 900
Isink, SINK OUTPUT CURRENT (mA) Isource, OUTPUT SOURCE CURRENT (mA)

Figure 20. Power Supply Zener Voltage

Figure 19. Supply Current versus Supply Voltage versus Temperature
32 23
RT = 10 k ICC = 25 mA
CT = 1.0 nF
VFB = 0 V
I CC , SUPPLY CURRENT (mA)

Current Sense = 0 V
V CC , ZENER VOLTAGE (V)

24 22
TA = 25°C

16 21

8.0 20

0 19
0 4.0 8.0 12 16 20 24 –55 –25 0 25 50 75 100 125
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

MOTOROLA ANALOG IC DEVICE DATA 7

 MC44602

Figure 21. Valid Load Comparator Threshold Figure 22. Demag Comparator Threshold
versus Temperature versus Temperature

V th(Demag), DEMAG COMPARATOR THRESHOLD (mV)

V th(VL) , VALID LOAD COMPARATOR THRESHOLD (V)
3.2 120
VCC = 12 V VCC = 12 V

2.8 100

2.4 80

2.0 60
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 23. Load Detect Input Figure 24. Startup Threshold Voltage
t PLH(IN/OUT) , LOAD DETECT PROPAGATION DELAY ( µ s)

Propagation Delay versus Temperature versus Temperature

1.4 14.5
VCC = 12 V Vth, STARTUP THRESHOLD VOLTAGE (V) VCC Increasing
RT = 10 k
CT = 1.0 nF
14.3
1.2

14.1

1.0
13.9

0.8 13.7
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 25. Minimum Operating Voltage Figure 26. Reference Undervoltage Threshold
V ref(UVLO), REFERENCE UNDERVOLTAGE THRESHOLD (V)

After Turn–On versus Temperature versus Temperature

10.35 3.42
V CC(min), MINIMUM OPERATING VOLTAGE (V)

VCC Decreasing Vref Decreasing

10.25
3.38

10.15

3.34
10.05

9.95 3.30
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

8 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

Figure 27. Representative Block Diagram

VCC
VCC

+ 20V 15
Reference
Regulator 14V
VCC
Vref Reference UVLO
UVLO
16 R Vin
3.6V
Internal
R Bias Load
2.5V Demag
+ Detect
Comparator 85mV Input
Valid Load 2 Vout
Comparator 18k
Sync Input VC
R
Q 2.5V 14
7 10k
S Source Output
RT
Fault Latch
11
Oscillator Q1
CT 8 + TQ Sink Output
Compensation 1.0 mA S 10
1 Error Thermal RQ Sink Ground
Voltage Feedback Amplifier R
Input 2.5V PWM Substrate 4, 5, 12, 13
2R R Latch
3 Current Sense Input
Foldback
I Amplifier Current Sense 6 RS
Comparator
2.5V 1.0V

Gnd 9

R1 R2 CO
= Sink Only
Positive True Logic

Figure 28. Timing Diagram

2.8V
Capacitor CT 1.2V
0V
PWM Latch
“Set” Input

Toggle Flip Flop C

Q Output
NC NC C C
VClamp* C NC NC
Current Sense C NC
Input

PWM Latch
“Set” Input

Source Output

2.5V
Load Detect 85mV
Input 0V

Demag Output

Fault Latch Q

2.5V
Sync Input
0V

Startup With Foldback Startup Without Foldback Normal Operation Output Overload
*C = Comparison of Current Sense Input With VClamp NC = No Comparison of Current Sense Input With VClamp

MOTOROLA ANALOG IC DEVICE DATA 9

 MC44602
OPERATING DESCRIPTION
The MC44602 is a high performance, fixed frequency, guarantees that no drive pulses appear at the Source Output
current mode controller specifically designed to directly drive (Pin 11) when Pin 1 is at its lowest state (VOL). This occurs
a bipolar power switch in off–line and high voltage dc–to–dc when the power supply is operating and the load is removed,
converter applications. This device offers the designer a cost or at the beginning of a soft–start interval. The Error Amp
effective solution with minimal external components. The minimum feedback resistance is limited by the amplifier’s
representative block and timing diagrams are shown in minimum source current (0.5 mA) and the required output
Figures 27 and 28. voltage (VOH) to reach the comparator’s 1.0 V clamp level:
V) ) 1.4 V
Oscillator
The oscillator frequency is programmed by the values
Rf(min) [ 3.0 (1.00.5mA + 8800 W
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to Figure 29. Error Amplifier Compensation
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
+
generates an internal blanking pulse that holds one of the
Compensation 1.0 mA
inputs of the NOR gate high. This causes the Source and
Sink outputs to be in a low state, thus producing a controlled 1 Error
RFB
amount of output deadtime. An internal toggle flip–flop has Rf Amplifier
2R
been incorporated in the MC44602 which blanks the output Cf 3 2.5V
off every other clock cycle by holding one of the inputs of the R
Voltage
NOR gate high. This in combination with the CT discharge Foldback
Feedback I Current Sense
Amplifier
period yields output deadtimes programmable from 50% to Input Comparator
70%. Figure 1 shows RT versus Oscillator Frequency and 2.5V 1.0V
Figure 2, Output Deadtime versus Frequency, both for a
given value of CT. Note that many values of RT and CT will Gnd 9
give the same oscillator frequency but only one combination
From Power Supply Output
will yield a specific output deadtime at a given frequency. R1 R2
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a narrow rectangular
Current Sense Comparator and PWM Latch
clock signal with an amplitude of 3.2 V to 5.5 V to the Sync
Input (Pin 7). For reliable locking, the free–running oscillator The MC44602 operates as a current mode controller,
frequency should be set about 10% less than the clock where output switch conduction is initiated by the oscillator
frequency. If the clock signal is ac coupled through a and terminated when the peak inductor current reaches the
capacitor, an external clamp diode may be required if the threshold level established by the Error Amplifier output (Pin
negative sync input current is greater than –5.0 mA. 1). Thus the error signal controls the peak inductor current on
Connecting Pin 7 to Vref will cause CT to discharge to 0 V, a cycle–by–cycle basis. The Current Sense Comparator
inhibiting the Oscillator and conduction of the Source Output. PWM Latch configuration used ensures that only a single
Multi–unit synchronization can be accomplished by pulse appears at the Source Output during the appropriate
connecting the CT pin of each IC to a single MC1455 timer. oscillator cycle. The inductor current is converted to a voltage
by inserting the ground referenced sense resistor RS in series
Error Amplifier with the emitter of output switch Q1. This voltage is monitored
A fully compensated Error Amplifier with access to the by the Current Sense Input (Pin 6) and compared to a level
inverting input and output is provided. It features a typical dc derived from the Error Amp output. The peak inductor current
voltage gain of 90 dB, and a unity gain bandwith of under normal operating conditions is controlled by the
1.0 MHz with 57 degrees of phase margin (Figure 7). The voltage at Pin 1 where:
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided lpk [ V (Pin1) * 1.4V
down and monitored by the inverting input. The maximum 3 RS
input bias current with the inverting input at 2.5 V is –2.0 µA. Abnormal operating conditions occur when the power
This can cause an output voltage error that is equal to the supply output is overloaded or if output voltage sensing is
product of the input bias current and the equivalent input lost. Under these conditions, the Current Sense Comparator
divider source resistance. threshold will be internally clamped to 1.0 V. Therefore the
The Error Amp Output (Pin 1) is provided for external loop maximum peak switch current is:
compensation (Figure 29). The output voltage is offset by two
diodes drops (≈1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
lpk(max) [ 1.0RSV

10 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

A narrow spike on the leading edge of the current This becomes particularly useful when reducing the Ipk(max)
waveform can usually be observed and may cause the power clamp level.
supply to exhibit an instability when the output is lightly
Reference
loaded. This spike is due to the power transformer
interwinding capacitance and the output rectifier recovery The 5.0 V bandgap reference has a tolerance of ±6.0%
time. The addition of an RC filter on the Current Sense Input over a junction temperature range of –25°C to 85°C. Its
with a time constant that approximates the spike duration will primary purpose is to supply charging current to the oscillator
usually eliminate the instability; refer to Figure 30. timing capacitor. The reference has short circuit protection
and is capable of providing in excess of 20 mA for powering
Undervoltage Lockout additional control system circuitry.
Two undervoltage lockout comparators have been
Figure 30. Bipolar Transistor Drive
incorporated to guarantee that the IC is fully functional before
and Current Spike Suppression
the output stage is enabled. The positive power supply Vin
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in IB
hysteresis to prevent erratic output behavior as their +
respective thresholds are crossed. The VCC comparator 0
upper and lower thresholds are 14.1 V/10.2 V. The Vref – Base Charge
comparator upper and lower thresholds are 3.6 V/3.3 V. The VC Removal
large hysteresis and low startup current of the MC44602 14 CB
make it ideally suited for off–line converter applications
(Figures 33, 34) where efficient bootstrap startup techniques Source
are required. 11 RB1 RB2
Q1
A 20 V zener is connected as a shunt regulator from VCC to TQ Sink
ground. Its purpose is to protect the IC from excessive
S 10 LB
voltage that can occur during system startup. The upper limit
RQ Sink Gnd
for the minimum operating voltage of the MC44602 is 11V.
R
Outputs PWM Substrate 4, 5, 12, 13
The MC44602 contains a high current split totem pole Latch
Current Sense R
output that was specifically designed for direct drive of
Current Sense 6 C RS
Bipolar Power Transistors. By splitting the totem pole into
Comparator
separate source and sink outputs, the power supply designer
has the ability to independently adjust the turn–on and
Thermal Protection and Package
turn–off base drive to the external power transistor for optimal
Internal Thermal Shutdown circuitry is provided to protect
switching. The Source and Sink outputs are capable of up to
the integrated circuit in the event that the maximum junction
1.0 A and 1.5 A respectively and feature 50 ns switching
temperature is exceeded. When activated, typically at 160°C,
times with a 1.0 nF load. Additional internal circuitry has been
the PWM Latch is held in the “reset” state, forcing the Source
added to keep the Source Output “Off” and the Sink Output
Output “Off” and the Sink Output “On”. This feature is
“On” whenever an undervoltage lockout is active. This
provided to prevent catastrophic failures from accidental
feature eliminates the need for an external pull–down resistor
device overheating. It is not intended to be used as a
and guarantees that the power transistor will be held in the
substitute for proper heatsinking.
“Off” state.
The MC44602 is contained in a heatsinkable 16–lead
Separate output stage power and ground pins are
plastic dual–in–line package in which the die is mounted on a
provided to give the designer added flexibility in tailoring the
special heat tab copper alloy lead frame. This tab consists of
base drive circuitry for a specific application. The Source
the four center Sink Ground pins that are specifically
Output high–state is controlled by applying a positive voltage
designed to improve the thermal conduction from the die to
to VC (Pin 14) and is independent of VCC. A zener clamp is
the circuit board. Figure 14 shows a simple and effective
typically connected to this input when driving power
method of utilizing the printed circuit medium as a heat
MOSFETs in systems where VCC is greater than 20V. The
dissipater by soldering these pins to an adequate area of
Sink Output low–state is controlled by applying a negative
copper foil. This permits the use of standard layout and
voltage to the Sink Ground (Pins 4, 5, 12, 13). The Sink
mounting practices while having the ability to halve the
Ground can be biased as much as 5.0 V negative with
junction to air thermal resistance. This example is for a
respect to Ground (Pin 7). Proper implementation of the VC
symmetrical layout on a single–sided board with two ounce
and Sink Ground pins will significantly reduce the level of
per square foot of copper.
switching transient noise imposed on the control circuitry.

MOTOROLA ANALOG IC DEVICE DATA 11

 MC44602
Design Considerations paths back to the input filter capacitor. Ceramic bypass
Do not attempt to construct the converter on capacitors (0.1 µF) connected directly to VCC, VC, and
wire–wrap or plug–in prototype boards. High frequency Vref may be required depending upon circuit layout. This
circuit layout techniques are imperative to prevent provides a low impedance path for filtering the high frequency
pulse–width jitter. This is usually caused by excessive noise noise. All high current loops should be kept as short as
pick–up imposed on the Current Sense or Voltage Feedback possible using heavy copper runs to minimize radiated EMI.
inputs. Noise immunity can be improved by lowering circuit The Error Amp compensation circuitry and the converter
impedances at these points. The printed circuit layout should output voltage divider should be located close to the IC and
contain a ground plane with low–current signal, and high as far as possible from the power switch and other noise
current switch and output grounds returning on separate generating components.

PROTECTION MODES
The MC44602 operates as a conventional fixed frequency Figure 31. Output Foldback Characteristic
current mode controller when the power supply output load is
less than the design limit. For enhanced system reliability, this Vout
device has the unique ability of changing operating modes if lpk(max)
the power supply output is overloaded or shorted.
VO Nominal
Overload Protection
Power supply overload protection is provided by the
Foldback Amplifier. As the output load gradually increases,
the Error Amplifier senses that the voltage at Pin 3 is less than
Low Value R1
the 2.5 V threshold. This causes the voltage at Pin 1 to rise, New Startup
increasing the Current Sense Comparator threshold in order Sequence Initiated High Value R1
to maintain output regulation. As the load further increases, VCC UVLO
Threshold
the inverting input of the Current Sense Comparator reaches
the internal 1.0 V clamp level, limiting the switch current to the Iout
Nominal Load Overload
calculated Ipk(max). At this point any further increase in load Range
will cause the power supply output to fall out of regulation. As
the voltage at Pin 3 falls below 2.5 V, current will flow out of Short Circuit Protection
the Foldback Amplifier input, and the internal clamp level will Short circuit protection for the power supply is provided by
be proportionally reduced (Figures 9, 10). The increase in the Valid Load Comparator, Fault Latch, and Demag
current flowing out of the Foldback Amplifier input in Comparator. Figure 32 shows the logic truth table of the
conjunction with the reduced clamp level, causes the power functional blocks. When operating the power supply with
supply output voltage to fall at a faster rate than the voltage at nominal output loading, the Fault Latch is “Set” by the NOR
Pin 3. This results in the output foldback characteristic shown gate driver during the Power Transistor “On” time and “Reset”
in Figure 31. The shape of the current limit “knee” can be by the Fault Comparator during the “Off” time. When a severe
modified by the value of resistor R1 in the feedback divider. overload or short circuit occurs on any output, the voltage
Lower values of R1 will reduce the Ipk(max) clamp level at a during the “Off” time (flyback voltage) at the Load Detect
faster rate. Input, is unable to reach the 2.5 V threshold of the Valid Load
Improper operation of the Foldback Amp can be Comparator. This causes the Fault Latch to remain in the
encountered when the Error Amp compensation capacitor Cf “Set” state with output Q “Low”. During the “Off” time the
exceeds 2.0 nF. The problem appears at Startup when the Demag Comparator output will also be “Low”. This causes
output voltage of the power supply is below nominal, causing the NOR gate to internally hold the Sync Input “High”,
the Error Amp output to rise quickly. The rapid change in inhibiting the next fixed frequency Oscillator cycle and
output voltage will be coupled through Cf to the Inverting Input switching of the Power Transistor. As the load dissipates the
(Pin 3), keeping it at its 2.5 V threshold as the 1.0 mA Error stored transformer energy, the voltage at the Load Detect
Amp current source charges Cf. This has the effect of Input will fall. When this voltage reaches 85 mV, the Demag
disabling the Foldback Amp by preventing Pin 3 and the Comparator output goes “High”, allowing the Sync Input to go
clamp level at the inverting input of the Current Sense “Low”, and the Power Transistor to turn “On”.
Comparator, from rising in proportion to the power supply Note that as long as there is an output short, the switching
output voltage. By adding resistor RFB in series with Cf, the frequency will shift to a much lower frequency than that set by
voltage at Pin 3 can be held to 1.0 V, corresponding to a RT/CT. The frequency shift has the effect of lowering the duty
Current Sense clamp level of 0.08 V (Figure 10), while cycle, resulting in a significant reduction in Power Transistor
allowing the Error Amp output to reach its high state VOH of and Output Rectifier heating when compared to conventional
7.0 V. The required resistor to keep Pin 3 below 1.0 V during current mode controllers. The extended “On” time is the result
initial Startup is: of CT charging from 0 V to 2.8 V instead of 1.2 V to 2.8 V. The
extended “Off” time is the result of the output short time
RFB Rf R1 R2 constant. The time constant consists of the output filter
≥6
RFB + Rf R 1 + R2 capacitance, and the equivalent series resistance (ESR) of
the capacitor plus the associated wire resistance.

12 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

Figure 32. Logic Truth Table of Functional Blocks

Demag Fault Latch Sync
Output Power
Load Transistor Input Out S R Q Input Operating Comments

Nominal On <85mV 1 1 0 0 0 NOR gate driver sets Fault Latch.

Narrow spike at Sync Input (<2.5 V) as transformer voltage

At Turn–Off >85 mV, <2.5 V 0 0 0 0 rises quickly, Oscillator is not affected.

Off >2.5 V 0 0 1 1 0 Valid Load Comparator resets Fault Latch.

Short On <85 mV 1 1 0 0 0 Short is not detected until transistor turn–off.

Valid Load Comparator fails to reset Fault Latch, Pulse at

At Turn–Off >85 mV, <2.5 V 0 0 0 0 1 Sync Input exceeds 2.5 V, Oscillator is disabled.

Off <85 mV 1 0 0 0 0 Load dissipates transformer energy, Oscillator enabled.

During the initial power supply startup the controller Comparator threshold. This causes CT to discharge down
sequences through the Short Circuit and Overload Protection towards ground, generating a second negative going edge
modes as the output filter capacitors charge–up. If an output on the oscillator waveform. This second edge results in the
is shorted and the auxiliary feedback winding is used to divide–by–two flip–flop being clocked twice for each “On”
power the control IC as in Figure 33, the VCC UVLO lower time of the switch transistor. During initial startup, this effect
threshold level will be reached after several cycles, disabling can be eliminated by insuring that the Foldback Amplifier is
the IC and initiating a new startup sequence. The Short fully active with the addition of resistor RFB. With the Foldback
Circuit Protection mode can be disabled by grounding the Amplifier active, the clamp level at the inverting input of the
Sync Input. Narrow switching spikes are present on this pin Current Sense Comparator will be low, allowing a comparison
during normal operation. These spikes are caused by the rise to take place during the switch transistor “On” time. When the
time of the flyback voltage from the 85 mV Demag Load Detect Input exceeds 85 mV, the Sync Input will go
Comparator threshold to the 2.5 V Valid Load Comparator high, discharging CT to ground after 1.0 µs, thus eliminating
threshold. In high power applications, the increased negative the second negative edge. Operation with the output
current at the Load Detect Input can extend the switching overloaded will cause the toggle flip–flop to be clocked twice
spikes to the point where they exceed the Sync Input for each “On” time. This should not be a problem since the
threshold. This problem can be eliminated by placing an next “On” time is delayed by the Demag Comparator until the
external small signal clamp diode at the Load Detect Input. load dissipates the transformers energy.
The diode is connected with the cathode at Pin 2 and the The point where the IC detects that there is a severe
anode at ground. output overload, or that the transformer has reached zero
The divide–by–two toggle flip–flop will appear not to current, is controlled by the voltage of the auxiliary winding
function properly during power supply startup without and a resistor divider. The divider consists of an external
foldback, or operation with an overloaded output. This series resistor and an internal shunt resistor. The shunt
phenomena appears at the end of the oscillator cycle if there resistor is nominally 18 kΩ but can range from 12 kΩ to 30 kΩ
was not a current sense comparison, and after the flyback due to process variations. If more precise overload and zero
voltage at the Load Detect Input failed to exceed 2.5 V. Under current detection is required, the internal resistor variations
these conditions, the Sync input will go high approximately can be swamped out by connecting a low value external
1.0 µs after the Load Detect Input exceeds the 85 mV Demag resistor (≤2.7 kΩ) from Pin 2 to ground.

MOTOROLA ANALOG IC DEVICE DATA 13

 MC44602

PIN FUNCTION DESCRIPTION

Pin Function Description
1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 Load Detect Input A voltage indicating a severe overload or short circuit condition at any output of the
switching power supply is connected to this input. The Oscillator is controlled by this
information making the power supply short circuit proof.
3 Voltage Feedback Input This is the inverting input of the Error Amplifier and the noninverting input of the
Foldback Amplifier. It is normally connected to the switching power supply output
through a resistor divider.
4, 5, 12, 13 Sink Ground The Sink Ground pins form a single power return that is typically connected back to the
power source on a separate path from Pin 9 Ground, to reduce the effects of switching
transient noise on the control circuitry. These pins can be used to enhance the package
power capabilities (Figure 14). The Sink Output low state (VOL) can be modified by
applying a negative voltage to these pins with respect to Ground (Pin 9) to optimize
turn–off of a bipolar junction transistor.
6 Current Sense Input A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate conduction of the output switch transistor.
7 Sync Input A narrow rectangular waveform applied to this input will synchronize the Oscillator. A dc
voltage within the range of 3.2 V to 5.5 V will inhibit the Oscillator.
8 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed at this pin by
connecting resistor RT to Vref and capacitor CT to ground.
9 Ground This pin is the control circuitry ground and is typically connected back to the power
source on a separate path from the Sink Ground (Pins 4, 5, 12, 13).
10 Sink Output Peak currents up to 1.5 A are sunk by this output suiting it ideally for turning–off a bipolar
junction transistor. The output switches at one–half the oscillator frequency.
11 Source Output Peak currents up to 1.0 A are sourced by this output suiting it ideally for turning–on a
bipolar junction transistor. The output switches at one–half the oscillator frequency.
14 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate
connection to the power source, it can reduce the effects of switching transient noise on
the control circuitry.
15 VCC This pin is the positive supply of the control IC. The minimum operating voltage range
after startup is 11 V to 18 V.
16 Vref This is the 5.0 V reference output. It provides charging current for capacitor CT through
resistor RT and can be used to bias any additional system circuitry.

14 MOTOROLA ANALOG IC DEVICE DATA

 MC44602

Figure 33. 60 Watt Off–Line Flyback Regulator

2.2 1N5404 220pF

85 to 265 390
Vac 470 T1
47k MUR 220 0.1 85V/0.5A
2.0W 4100
1N4148 270 220pF
0.1 470pF 1N4934
15k
1.0µH MUR
1N4148 470 0.1 20V/0.6A
415
220pF
8.2k
0.1µF 1 16 2.0W
24k
2 15 MBR
47k 220 MUR 470 0.1 6.8V/0.8A
460 340
10k 3 14
470k
MC44602

4 13 3.3nF
1.0k 47nF 470pF
5 12 1.0
22
6 11
10k 7 10 MJE18006
0.33µH 47
8 9
2.2nF
1.0nF/1.0kV
1.0k

1.0nF 0.82 4.7M

Test Conditions Results

Line Regulation Vin = 85 Vac to 265 Vac
85V IO = 0.5 A ∆ = 1.0 V or ± 0.6%
20V IO = 0.5 A ∆ = 0.04 V or ± 0.1%
6.8V IO = 0.8 A ∆ = 0.07 V or ± 0.5%
Load Regulation Vin = 220 Vac
85V IO = 0.1 A to 0.5 A ∆ = 1.0 V or ± 0.6%
20V IO = 0.1 A to 0.5 A ∆ = 0.4 V or ± 1.0%
6.8V IO = 0.1 A to 0.8 A ∆ = 0.2 V or ± 1.5%
Efficiency Vin = 110 Vac, PO = 58 W 81%
Standby Power Vin = 110 Vac, PO = 0 W 2.0 W
T1 – Orega SMT2 (G4787–01)
Primary: 41 Turns, #25AWG
Auxiliary Feedback: 12 Turns, #25AWG
Secondary: 85 V – 60 Turns, #25AWG
Secondary: 20 V – 15 Turns, #25AWG (2 Strands) Bifiliar Wound
Secondary: 6.8 V – 5 Turns, #25AWG (2 Strands) Bifiliar Wound
Core – ETD39 34x17x11 B52
Gap – ≈ 0.020″ for a primary inductance of 750 µH, AL = 500 nH/Turn2

MOTOROLA ANALOG IC DEVICE DATA 15

 MC44602

Figure 34. 150 Watt Off–Line Flyback Regulator

4.7 1N5404 220pF

390
220 Vac
100 T1
47k MUR 220 0.1 155V/0.5A
2.0W 4100
1N4148 270 220pF
0.1 470pF 1N4934
15k
1.0µH MUR
1N4148 470 0.1 24.5V/1.8A
415
220pF
8.2k
0.1µF 1 16 2.0W
24k
2 15 MUR
47k 220 MUR 470 0.1 15.5V/1.8A
460 415
10k 3 14
470k
MC44602

4 13 3.3nF
1.0k 47nF 470pF
5 12 1.0
22
6 11
10k 7 10 MJE18006
2.2µH 47
8 9
2.2nF
1.0nF/1.0kV
1.0k

1.0nF 0.47 4.7M

Test Conditions Results

Line Regulation Vin = 185 Vac to 265 Vac
155V IO = 0.5 A ∆ = 1.0 V or ± 0.3%
24.5V IO = 1.0. A ∆ = 0.4 V or ± 0.8%
15.5V IO = 1.0 A ∆ = 0.3 V or ± 1.0%
Load Regulation Vin = 220 Vac
155V IO = 0.1 A to 0.5 A ∆ = 2.0 V or ± 0.7%
24.5V IO = 0.1 A to 1.0 A ∆ = 0.4 V or ± 0.8%
15.5V IO = 0.1 A to 1.0 A ∆ = 0.2 V or ± 0.7%
Efficiency Vin = 220 Vac, PO = 117.5 W 83%
Standby Power Vin = 220 Vac, PO = 0 W 5.0 W
T1 – Orega SMT2 (G4717–01)
Primary: 55 Turns, #25AWG
Auxiliary Feedback: 6 Turns, #25AWG
Secondary: 155 V – 52 Turns, #25AWG
Secondary: 24.5 V – 9 Turns, #25AWG (2 Strands) Bifiliar Wound
Secondary: 15.5 V – 6 Turns, #25AWG (2 Strands) Bifiliar Wound
Core – GETV 53x18x18 B52
Gap – ≈ 0.020″ for a primary inductance of 1.35 µH, AL = 450 nH/Turn2

16 MOTOROLA ANALOG IC DEVICE DATA

 MC44602
OUTLINE DIMENSIONS
P2 SUFFIX
PLASTIC PACKAGE
CASE 648C–03
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16 9 4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
–B– 5. INTERNAL LEAD CONNECTION BETWEEN 4 AND
5, 12 AND 13.
1 8
L INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.840 18.80 21.34
B 0.240 0.260 6.10 6.60
NOTE 5
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
E 0.050 BSC 1.27 BSC
C F 0.040 0.70 1.02 1.78
G 0.100 BSC 2.54 BSC
–T– J 0.008 0.015 0.20 0.38
SEATING N M K 0.115 0.135 2.92 3.43
PLANE L 0.300 BSC 7.62 BSC
K M 0_ 10_ 0_ 10_
E
F J 16 PL N 0.015 0.040 0.39 1.01
G
D 16 PL 0.13 (0.005) M T B S

0.13 (0.005) M T A S

MOTOROLA ANALOG IC DEVICE DATA 17

 MC44602

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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Opportunity/Affirmative Action Employer.

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INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

18 MOTOROLA ANALOG IC DEVICE DATA

*MC44602/D*
◊ MC44602/D