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2N7002KDW: 60V N-Channel Enhancement Mode MOSFET - ESD Protected

2N7002KDW datasheet

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Herdhis Vega
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© © All Rights Reserved
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0% found this document useful (0 votes)
48 views

2N7002KDW: 60V N-Channel Enhancement Mode MOSFET - ESD Protected

2N7002KDW datasheet

Uploaded by

Herdhis Vega
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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2N7002KDW

60V N-Channel Enhancement Mode MOSFET - ESD Protected

FEATURES
• RDS(ON), VGS@10V,IDS@500mA=3Ω
• RDS(ON), [email protected],IDS@200mA=4Ω

• Advanced Trench Process Technology


• High Density Cell Design For Ultra Low On-Resistance
• Very Low Leakage Current In Off Condition
• Specially Designed for Battery Operated Systems, Solid-State Relays
Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.
• ESD Protected 2KV HBM
• Component are in compliance with EU RoHS 2002/95/EC directives

MECHANICALDATA
• Case: SOT-363 Package
6 5 4
• Terminals : Solderable per MIL-STD-750,Method 2026
• Marking : K27

1 2 3

Maximum RATINGS and Thermal Characteristics (TA=25OC unless otherwise noted )

PA RA M E TE R S ym b o l Li mi t U ni t s

D r a i n- S o ur c e Vo l t a g e VD S 60 V

G a t e - S o ur c e Vo l t a g e VGS +20 V

C o nt i nuo us D r a i n C ur r e nt ID 11 5 mA

1)
P ul s e d D r a i n C ur r e nt ID M 800 mA

TA = 2 5 O C 200
M a xi m um P o w e r D i s s i p a t i o n PD mW
TA = 7 5 O C 120

O
O p e r a t i n g J u n c t i o n a n d S t o r a g e Te m p e r a t u r e R a n g e TJ , TS T G -5 5 to + 1 5 0 C

Junction-to Ambient Thermal Resistance(PCB mounted)2 RθJ A 625 O


C /W

Note: 1. Maximum DC current limited by the package


2. Surface mounted on FR4 board, t < 5 sec

PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE

STAD-JAN.11.2007 PAGE . 1
2N7002KDW
ELECTRICALCHARACTERISTICS

P a ra me te r S ym b o l Te s t C o n d i t i o n M i n. Ty p . M a x. U ni t s

S ta ti c

D r a i n- S o ur c e B r e a k d o w n Vo l t a g e BVD SS V G S = 0 V , ID = 1 0 u A 60 - - V

G a t e Thr e s ho l d Vo l t a g e V G S (th) V D S = V G S , ID = 2 5 0 u A 1 - 2 .5 V

D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e RD S (o n) VG S =4.5V, I D =200mA - - 4 .0

D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e RD S (o n) VG S =10V, I D =500mA - - 3.0

Ze r o G a t e Vo l t a g e D r a i n C ur r e nt ID S S VD S =60V, VG S =0V - - 1 uA

Gate Body Leakage IG S S V G S =+ 2 0 V , V D S = 0 V - - +10 uA

Forward Transconductance g fS V D S = 1 5 V , ID = 2 5 0 m A 100 - - mS

D i o d e F o rwa rd Vo lta g e VSD IS = 2 0 0 m A , V G S = 0 V - 0 .8 2 1 .3 V

Dynamic

V D S = 1 5 V , ID = 2 0 0 m A
To t a l G a t e C h a r g e Qg - - 0 .8 nC
VGS=4.5V

Tu r n - O n D e l a y Ti m e to n VD D =30V , RL =150Ω - - 20
ID =200mA , VG E N =10V ns
Tu r n - O f f D e l a y Ti m e to ff RG =10Ω - - 40

In p u t C a p a c i t a n c e Ciss - - 35

V D S =2 5 V, V G S =0 V
O ut p ut C a p a c i t a nc e Coss - - 10 pF
f=1 .0 MHZ

R e v e r s e Tr a n s f e r C a p a c i t a n c e C rs s - - 5

Switching V DD Gate Charge V DD


Test Circuit Test Circuit
V IN RL V GS RL

V OUT

1mA
RG

RG

STAD-JAN.11.2007 PAGE . 2
2N7002KDW

Typical Characteristics Curves (TA=25OC,unless otherwise noted)

1.2 1.2
V DS=10V

I D - Drain Source Current (A)


V GS = 10V ~ 6.0V
5.0V
ID - Drain-to-Source Current (A)

1 1

0.8 4.0V 0.8

0.6 0.6

0.4 0.4
3.0V T J=25 O C
0.2 0.2

0 0
0 1 2 3 4 5 0 1 2 3 4 5 6

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Fig. 1-TYPICAL FORWARD


FIG.1- Output CHARACTERISTIC
Characteristic FIG.2- Transfer Characteristic

5 5
R DS(ON) - On-Resistance ( W )
R DS(ON) - On-Resistance ( W )

4 4

3 3

I D=500mA
2 V GS=4.5V 2

I D=200mA
1 V GS=10V 1

0 0
0 0.2 0.4 0.6 0.8 1 2 3 4 5 6 7 8 9 10

ID - Drain Current (A) V GS - Gate-to-Source Voltage (V)

FIG.3- On Resistance vs Drain Current FIG.4- On Resistance vs Gate to Source Voltage

1.8
V GS=10V
RDS(ON) - On-Resistance(Normalized)

1.6 I D=500mA

1.4

1.2

0.8

0.6
-50 -25 0 25 50 75 100 125 150
o
TJ - Junction Temperature ( C)

FIG.5- On Resistance vs Junction Temperature

STAD-JAN.11.2007 PAGE . 3
2N7002KDW

10
V DS=10V

V GS - Gate-to-Source Voltage (V)


Vgs
I D=250mA
Qg 8

Vgs(th) Qsw
0
0 0.2 0.4 0.6 0.8 1
Qg(th)
Qgs Qgd Qg Qg - Gate Charge (nC)

Fig.6 - Gate Charge Waveform Fig.7 - Gate Charge


Vth - G-S Threshold Voltage (NORMALIZED)

1.2 88
I D=250uA
BVDSS - Breakdown Voltage (V)

I D=250uA
86
1.1
84

1 82

80
0.9
78

76
0.8
74

0.7 72
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
o o
TJ - Junction Temperature ( C) TJ - Junction Temperature ( C)

Fig.8 - Threshold Voltage vs Temperature Fig.9 - Breakdown Voltage vs Junction Temperature

10
V GS=0V
IS - Source Current (A)

0.1 T J=125 O C 25 O C

-55 O C
0.01
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

VSD - Source-to-Drain Voltage (V)

Fig.10 - Source-Drain Diode Forward Voltage

STAD-JAN.11.2007 PAGE . 4
2N7002KDW

MOUNTING PAD LAYOUT

ORDER INFORMATION

• Packing information
T/R - 10K per 13" plastic Reel
T/R - 3K per 7” plastic Reel

LEGAL STATEMENT

Copyright PanJit International, Inc 2007


The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.

STAD-JAN.11.2007 PAGE . 5

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