AN4971
AN4971
AN4971
Power Meter IC
A Maxim Integrated Products Brand
APPLICATION NOTE
2 SCHEMATIC DESIGN
2.1 Pure LCD Pins (SEG Pins)
These pins cannot be configured and are dedicated LCD driver pins. In some designs, restrictions on the
choice for LCD_NUM may require that some DIO/SEG pins are configured as LCD pins. If not connected
to an LCD pin, these unused SEG pins should be terminated to DGND with 22 pF capacitors as shown in
Figure 1.
XIN
XOUT
Ferrite
TEST
GND 71M65XX
Figure 2: Connecting a Crystal to XIN/XOUT
2.5 V1 Pin
The V1 input pin detects power faults and provides a means to disable the hardware watchdog timer for
debugging purposes. When the voltage at the V1 pin falls below +1.6 VDC (VBIAS), the device enters its
power-down mode (brownout mode). The firmware decides whether to proceed from there to LCD or
sleep mode or whether the IC stays in brownout mode.
Since the hardware watchdog timer (WDT) is automatically disabled when the ICE_E pin is pulled high,
the V1 pin need not have a jumper to V3P3 to disable the WDT for emulator connection.
R1 R3
V3P3
5kΩ
C1 V1
R2
100pF
GND
Figure 3: V1 Circuit
The R1 (16.9 kΩ) and R2 (20 kΩ) component values are selected to provide a prompt response to a loss
of line power (V1 = 54% of V3P3SYS). That way, V1 crosses VBIAS (1.6 VDC) when V3P3SYS falls
below the safe operating voltage of 3.0 VDC, as shown in Figure 4. This figure shows the voltage at V1
following V3P3 in linear fashion, i.e. without hysteresis.
On closer inspection, the development of the voltage at V1 is a little more complex than what Figure 4
shows. The IC itself loads V1 with 1 µA nominal if V1 < VBIAS, and with close to 0 µA if V1 > VBIAS.
This is shown in Figure 5. The voltage drop in R3 will cause a hysteresis of R3 * 1 µA, and an additional
voltage drop will be created in R1. Combined, the hysteresis current will cause the IC to transition to
brownout mode at a slightly lower supply voltage when system/board power is moving down, whereas the
transition from brownout to mission mode still happens at the supply voltage determined by the resistor
divider ratio formed by R1 and R2. This creates the narrow voltage band shown in yellow in Figure 6 that
guarantees that the IC is not rapidly transitioning in between power modes when the V1 voltage stays
close to 1.6 VDC.
REV 2.2 © 2007-2009 Teridian Semiconductor Corporation 3
Design for EMC
3.5 Reliable
3
operation
2.5
V3P3
2
VBIAS
1.5 V1
0.5
0 Battery modes
0 20 40 60 80 100 120
71M65XX
R1 R3
V1
V3P3
R2 I
GND
I = 1 µA if V1 < VBIAS
I = 0 µA if V1 > VBIAS
Battery modes
4.00
3.50 Reliable
3.00
operation
2.50
V3P3
2.00 VBIAS
V1 down
1.50
V1 up
1.00
0.50
0.00
0 20 40 60 80 100 120
71M6521
RESET
DGND
LCD Segments
V3P3D (optional) 71M6521BE
ICE_E
62Ω
E_RST
62Ω
E_RXTX
E_TCLK
62Ω
22pF 22pF
Figure 9: ICE-Interface
It is useful to bring out the ICE_E signal to the programming connector. This is useful when the 71M6521
is programmed with the TFP2 flash programmer. In some situations, the TFP-2 can implement the proper
sequence for erasing and programming the 71M6521. When the SECURE bit is set, and reprogramming is
required on a meter board that utilizes a battery, the following sequence is used by the TFP-2:
• TFP-2 erases flash using ICE_E = high
• TFP-2 then pulls ICE_E = low a watchdog reset occurs
• TFP-2 pulls ICE_E = high
• TFP-2 programs the 71M6521
2.12 Connecting Other IC Pins
All signals to and from the 71M652X IC must be examined carefully for EMC/EMI susceptibility.
The following list of precautions detail design considerations for the IC pins not mentioned above:
1. Terminate all unused current and voltage inputs (IA, IB, VA, VB) to V3P3.
2. A 10 μF tantalum capacitor must decouple the power and ground star points. The V3P3A pin and
ground pin of the IC must have a clean and direct connection to the star points.
3. The V3P3SYS, V3P3A should be fed from the Star point as described.
4. The GNDD and GNDA pins should also be fed from the GND star point.
5. Place a 0.1μF capacitor adjacent to the V2P5 pin between the V2P5 pin and ground.
6. CKTEST/SEG19 can be terminated with 22 pF as a dummy SEG load if this pin is not used for
clock output.
7. Connect the VBAT pin to V3P3 when no battery is used.
8. Connect the X4MHZ pin directly to ground.
9. V3P3D should not be loaded by more than a 0.1 µF capacitor.
3 SENSOR INTERFACE
The interfaces to sensors such as CTs, shunt resistors and resistive voltage dividers are very critical for
the EMC performance of a meter. Accurate display and recording of energy under EMI conditions
depends on the design of the current and voltage inputs. Improper design may lead to erroneous
measurements or resets.
The input signal conditioning circuit depends on the type of current sensor used. Each of the current
sensor types are individually discussed in this section.
3.1 Current Transformers
Figure 10 shows the recommended input signal conditioning circuit.
750Ω
IA
CT Input
Ferrites 1.7Ω 1000pF
220pF
V3P3A
NC NC
.
R15 R16 R17 R18
L2
2M, 1%, 1W 274K, 1% 270K, 1% 698, 1%
VA_IN VA
600 OHM
R32 C9
750, 1% 1000pF
NEUTRAL
L12
V3P3
C14
1000pF C11 600 OHM
0.1uF
2) V1 is considered an analog signal and its connections should be part of the star-point.
3) Another very important issue is the impedance for the V3P3A net. All vias should be large, and
traces should be wide in order to minimize impedance.
4) Decoupling of the V3P3A net to ground should be done as closely as possible to the V3P3A pin
with several capacitors, preferably with 10 µF, 100 nF, and 1nF capacitors placed in this order, so
that the lower capacitor value is closer to the V3P3A pin.
5) All longer V3P3A traces, for instance the ones connected to channel B, should be decoupled to
ground at several locations, in order to reduce noise.
6) Care must be taken to avoid low-voltage TVSs (“Tranzorbs”) for the V3P3A net, since these
components tend to generate leakage currents that have negative effects on low-current
accuracy.
7) The V3P3A net should be connected to V3P3SYS right at the shunt resistor. This is the preferred
arrangement (see Figure 12). If this is not possible, the two nets should be joined as soon as they
enter the PCB. V3P3A and V3P3SYS should only be connected at one point and otherwise
always routed separately (see Figure 13).
8) Analog inputs should have wide traces and large vias in order to minimize impedance.
9) Shunt resistors with three tabs (terminals) should be used (see Figure 12). Commercially
available shunt resistors have two tabs on one side and one tab on the opposing side.
10) Using ferrite beads at the sensor inputs brings good results, but care must be taken regarding the
impedance of the V3P3A net. Using ferrite beads with high DC resistance decreases low-current
accuracy. Even a resistance as low as 0.3 Ω can cause inaccuracy at low currents. Therefore,
ferrites with the lowest possible DC resistance should be used. These ferrites are usually of larger
size (2220 and larger). A ferrite that works well is the HI2220R181R-10 by Steward/Laird
Technologies.
11) A common problem with accuracy is low capacity of the power supply capacitors. Relatively low
power supply ripple can result in significant reduction of accuracy and/or repeatability. This
makes adding a large electrolytic capacitor at the 3.3 VDC output of the power supply advisable.
to LOAD from
NEUTRAL
Figure 12: Shunt Connections
Neutral
V3P3SYS
V3P3A
Shunt R
IA
Load
GND
Line Power
Supply
V3P3
Key recommendations for passing EMC/EMI testing for the current shunt input signal conditioning circuit:
1. L1 and L2 are ferrite beads with very low DC resistance.
2. R1 and C3 provide a low-pass filter for differential signals with a cutoff frequency of around 212
kHz. Depending on the length of the sensor cable harness, the value of C3 may vary. It is not
advisable to make C3 greater than 1000pF.
3. The connector to the shunt resistor should have a third pin for a GND connection. Connect pin 3
of J1 to the shield of the shunt cable (if available) to minimize high-frequency noise entering
through the shunt sensor plate and the sensor cables.
4. The combination of C1, L2, and C2 eliminates high-frequency noise spikes (EFT) on the analog
reference signal V3P3. The value of C1 and C2 can be modified based on the desired filtering
characteristics. The larger the value, the better EFT rejection will be. However, large values for
C1 and C2 affect low-current accuracy. Good starting values for C1 and C2 are 330 pF.
5. A 10 kΩ resistor may be used in parallel with C2 to dampen EMI noise.
6. C4 is used to eliminate noise picked up by longer circuit traces causing accuracy issues. C4
should be located very close to the IA pin of the 71M652X IC.
C5 L9
C32 R2 0.1uF 600 OHM
0.03uF, 250VDC 8.06K
1
C1 U2 C50 C10
2
1
VARISTOR 6.8V 1W C2 GND GND
10uF, 6.3V C4
6
R8 R4 10uF, 6.3V
1
1.5 C6 25.5K D8
0.47uF, 1000VDC D4 R7 UCLAMP3301D
2
1N4148 130
GND
R6 TANTALUM
R118 100, 2W
100, 2W
L8
600 OHM
J4 LIVE
VA_IN 1
VA_IN
NEUTRAL
4 LAYOUT PRECAUTIONS
4.1 Copper Layers
Four-layer printed circuit boards provide optimum performance with fastest time to market. The two
internal layers are partitioned for ground and V3P3/V3P3SYS.
A two-layer board structure demands careful attention to the ground and V3P3A/3P3SYS signal integrity.
Excessive copper voids and copper discontinuities will cause signal interference resulting in poor mea-
surement accuracy and poor EFT/EMC performance. For two-layer boards:
• Allocate the bottom layer for ground to maximize the ground surface under the device.
• Use the top layer for signal routing and for additional GND structures, as shown in Figure 18.
• “Stitch” gaps in the GND structures to GND bridges on the other PCB side, as shown in
Figure 16.
GND
GND
TOP LAYER
BOTTOM LAYER
TRACES
Reset,
ICE_E Meter IC
Voltage V1
Dividers
Current
High Voltage
Inputs (IA, IB)
Power Supply
DC Power
Supply
CRYSTAL
FERRITE
GND PLANE
XIN XOUT
GND ISLAND
VIA
9=V3P3SYS
STAR 50=V3P3A
POINT
C31
V3P3D
5 FIRMWARE RECOMMENDATIONS
1. Configure all unused DIO pins as outputs. This prevents unwanted signals from entering the IC.
2. Disable the emulator clock by disabling the emulator port (ICE_E pin pulled low). No firmware
instructions are required for this.
3. Disable the CKTEST clock output (by configuring CKOUT_DIS to 1) if not in use.
4. Place dummy interrupt service routines containing a RETI instruction at all locations pointed to by
unused interrupt vectors.
5. All interrupt service routines (ISRs) are to be as short as possible and must minimize any memory
manipulation operations.
6 EXTERNAL COMPONENTS
After all recommendations of this Application Note have been incorporated into the meter design, there
should not be any issue passing EMC tests. If the meter still fails to produce the desired results, the
addition of external ferrite components to the sensor and power wires may be required.
The current shunt configuration is the most difficult application due to the direct connection of the
NEUTRAL wire to the V3P3 nets of the board. External clamp-on ferrites or external toroid ferrites on the
following wires provide additional noise suppression:
1. NEUTRAL power entry wire
2. Second NEUTRAL power entry wire
3. Current shunt sensor wires
7 REVISION HISTORY
Revision Date Description
Rev. 1.0 3/13/2007 First publication.
Rev. 1.1 3/13/2007 Added figures showing emulator interface signals.
Rev. 1.2 3/14/2007 Deleted references to Rogowski coils. Added alternative connection for
reset button and button connected to PB. Added information on components
at XIN and XOUT pins.
Rev. 2.0 10/01/2008 Completely revised to reflect latest Demo Board design techniques.
Integrated many graphs from EMC web presentation.
Rev. 2.1 10/01/2008 Updated reference designator in description to Figures 8 and 12.
Rev. 2.2 12/10/2008 Added note on pure SEG pins in designs where no LCD is used.
Added explanation of hysteresis at V1.
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patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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