RC7017-datasheet-V3 6 5
RC7017-datasheet-V3 6 5
RC7017-datasheet-V3 6 5
RC7017
Datasheet
V3.6.5
Mar. 2011
Raycom CO.,LTD.
RC7017 Datasheet V3.6.5 Page 1 of 48
Revision History
Copyright notice
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subject to change without notice, which are suitable for reading by employees, agents
and clients of Raycom during their usage of relevant products. Without written
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strictly forbidden.
Contents
1. GENERAL DESCRIPTION
DESCRIPTION--------------------------------------------------------------------------------
-------------------------------------------------------------------------------- 5
2. FEATURES
FEATURES----------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------- 5
4. FUNCTIONAL DESCRIPTION
DESCRIPTION--------------------------------------------------------------------------
-------------------------------------------------------------------------- 17
4.1 INTRODUCTION----------------------------------------------------------------------------------------------- 17
4.2 FUNCTIONAL DETAILS--------------------------------------------------------------------------------------- 18
4.2.1 Optical Interface Processing---------------------------------------------------------------------- 18
4.2.2 PDH-------------------------------------------------------------------------------------------------------20
4.2.3 100BASE-FX MII------------------------------------------------------------------------------------- 22
4.2.4 EOW------------------------------------------------------------------------------------------------------22
4.2.5 Alarm Output------------------------------------------------------------------------------------------- 23
4.2.6 Customer Channels----------------------------------------------------------------------------------23
4.2.7 Management UART----------------------------------------------------------------------------------27
5. TECHNICAL PARAMETERS
PARAMETERS----------------------------------------------------------------------------
---------------------------------------------------------------------------- 36
6. PACKAGE
PACKAGE----------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------- 42
----------------------------------------------------------------------------------------------------42
7. APPLICATION GUIDE
GUIDE------------------------------------------------------------------------------------
------------------------------------------------------------------------------------ 43
Figure Index
Table Index
1. General Description
2. Features
3.2.2 E1 Interface
A.
Low level = The data from port B is
selected for deframer and all the
optical line alarms come from fiber
B.
21 FORCEAI I, PD Automatic Protect Switching
Configuration.
22 FORCEBI I, PD See Table 4-2-7-2-2 for details.
4. Functional Description
4.1 Introduction
PHONE_LEDO
CLK2MO
TD64KO
RD64KI
FS8KO
HOOKI
RINGO
HJBLI RESETI
CLK65MI
RD232I[0:3] RX232 EOW
BIASEI
B IA S E O
E1NI[0:7]
E1 RX OS_ENAO
E1PI[0:7]
TSDPAO
TSDNAO
MTXD[3:0] Framer Scrambler P /S
OS_ENBO
M TXEN ETH
TSDPBO
RX
M TXC TSDNBO
SCRAM_MODI
CLK9MI APLL FORCEAI
FORCEBI
CRNT_W ORKO
MRXD[3:0]
M RXDV ETH OSDAI
TX S /P RSDPAI
MRXC
DeFramer DeScrambler & RSDNAI
CDR
RSDPBI
E1NO[0:7]
E1 TX RSDNBI
E1PO[0:7]
OSDBI
TD232O[0:3] TX232
UART CONTROL ALARM
H JB LO
HDB3_NRZ_SELI
E1_LOOPI
MUTE_ENI
MASK_ENI
SPD_SELI
LOOP_FN_SELI
ALM_SELI
ADDRI
SIBUSO
NOPO
SIBUSI
TS_MODEI[0:1]
E1ASDO
ALMO
LERR3O
LERR6O
LOFO
With the process of clock recovery and HDB3 decoding 8 E1 signals enter
the chip and are then merged with the data stream from the MII interface. They
are then sent out through the dual PCML interfaces in a special frame after being
scrambled.
From the other direction, by monitoring the quality, the RC7017 selects one
data stream from the two PCML interfaces, abstracts the line clock and recovers
the data. After de-scrambling and frame alignment, each type of data is
separated. Meanwhile, the line bit rate is supervised and the result is reported.
All alarms and performance records are gathered and filtered according to
their priority. Then they are sent to the UART interface and some to pins for
direct display.
Switching Point
P o rt A P o rt B
Optical Line
Input Data
Alarm Confirmation
Optical Line
A la r m
Re-Synchronization
S can
4.2.2 PDH
+ 3 .3 V E1 LO S Alarm Collect
Detect Block B lo c k
E1 LO S
LED
R
non-use port E1ASDO
1
port with LOS
1
normal port
0
G lo b a l A L M
R C 7017
By setting PIN MASK_ENI high, all current E1 LOS alarms due to cable
disconnection can be masked. It also can be realized by configuring certain bits
The RC7017 provides local and remote loop-back capability for each of the
E1 tributaries.
Corresponding to 8 E1 tributaries, there are 8 control bits designed for E1
loop-back. They are serially input through the PIN E1_LOOPI and clocked by the
PIN CLK2MO with the load pulse of FS8KO. So external parallel-in /
serial-output shift registers are needed.
These 8bits can also be set through the UART. Non-loop back is the default
if the internal pull down resistor is floated.
Another PIN LOOP_FN_SELI is used to select where the loop back will
occur. When high level is on LOOP_FN_SELI, the instruction is transmitted to
remote chip and the E1 tributary loop-back is enabled there. Otherwise, local E1
tributary loop-back is enabled. See Fig. 4-2-2-2 for E1 tributary loop-back
position and direction.
Framer DeFramer
E1 Optical E1
DeFramer Framer
UART
E1_LOOPI
LOOP_FN_SELI
Local Loopback
Framer DeFramer
E1 Optical E1
DeFramer Framer
UART
E1_LOOPI
LOOP_FN_SELI
Remote Loopback
R C 7017 K S 8993
No. Nam e I/O I/O Nam e No.
P79 MRXDV O I M TXEN P57
P78 MRXD3 O I M TX D 3 P58
P77 MRXD2 O I M TX D 2 P59
P76 MRXD1 O I M TX D 1 P60
P75 MRXD0 O I M TX D 0 P61
GND I M TXER P62
P74 MRXC O I M R X C LK P71
P69 M TXEN I O MRXDV P64
P68 M TX D 3 I O MRXD3 P65
P67 M TX D 2 I O MRXD2 P66
P65 M TX D 1 I O MRXD1 P67
P64 M TX D 0 I O MRXD0 P68
P72 M TXC O I M TX C L K P63
Fig. 4-2-3 The Pin-to-Pin Map Between the RC7017 and the SWITCH
KS8993
4.2.4 EOW
The RC7017 provides point-to-point EOW function and the 64Kbps interface
can be connected with CODEC directly. The RC7017 performs signaling
procedure and generates ringing back tones, engaged tones, howling tones and
bell tones. The bell tones output and alarm tones output share the pin RINGO.
Unlike other alarms, the ring bell can’t be muted by the PIN MUTE_ENI.
The status of EOW is indicated by the PIN PHONE_LEDO. The low is for idle,
the high for engaged, and the toggle is for others.
Either the local global alarm or the remote global alarm is declared. The
toggle is provided on the pin RINGO, which is used to connect with the circuit of
a buzzer or speaker driver. When MUTE_ENI is logic high, the alarm tones are
disabled.
The optical line alarms have the priority NOP > LOF > ALE3 > ALE6 from
high to low. For example, when the NOP is declared, the other three lower
priority alarms are shielded.
When the RC7017 detects NOP or LOF, the Alarm Indication Signals (AIS)
are inserted in all of the E1 tributaries of the de-multiplexing side, all-zero
patterns are inserted in Ethernet data stream out of the MII, high level is on the
serial channel bus output pins TD232 (3:0) O and low level is on low-speed
asynchronous serial channel output pin HJBLO.
The RC7017 detects Loss of E1 tributary rail signals and HDB3 coding
violation. The alarm of signal loss has the higher priority than coding violation.
When an E1 tributary channel is regarded as non-use or in NRZ mode (HDB3
Coder/Decoder bypassed), the alarm of this channel will not be output.
All the E1 tributary alarms share the pin E1ASDO to output, so the external
serial-in/parallel-out shift register logics like 74HC595 is required.
6 5 .5 3 6 M 9 .3 7 5 M
CLK2M O TX
ECO
FS8KO Tim er
Tim er
Framer
74HC165 S /P Optical
HJBLI P ort
A syn
S am ple
RD232_I E1
S ync
TS_MODEI[1:0]
During the transmission, these 32 bits of data are retrieved from the signal
on the HJBLI according to the timing of 74/54HC165, synchronously sampled by
the 9.375MHz clock and filled in the overhead of the optical frame.
6 5 .5 3 6 M
RX CLK2M O
CDR ECO
Tim er FS8KO
Tim er
H JB LO
D e fra m P /S 74HC595
Optical er
P ort A syn
S am ple
E1
D esync
T D 232_O
TS_MODEI[1:0]
While receiving, 32 bits of data are picked from the optical frame, sampled to
be synchronous with the 65.536MHz domain and transformed into a serial signal
according to the timing of 74/54HC595.
In fact the 32 low-speed channels are asynchronous although the HJBLI
and HJBLO both look like the synchronous interface. The recommended
maximum baud rate is 1K for one channel, which is designed for low-speed
signal such as Link, TX, RX indications of the Ethernet switch and other
environment variables.
These 32 channels can also be accessed as registers through the
management UART.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H G F E D C B A H G F E D C B A
MC54/74HC165 MC54/74HC165
Serial Shift/ Serial Shift/
Parallel Load C lo c k Parallel Load C lo c k
FS8KO
R C 7017
CLK2M O
L a tc h Shift L a tc h Shift
C lo c k C lo c k C lo c k C lo c k
MC54/74HC595 MC54/74HC595
A B C D E F G H A B C D E F G H
CODEC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK2M O
FS8KO
Not
CLK2M O
Not
FS8KO
HJBLO HJBLO(8) HJBLO(7) HJBLO(6) HJBLO(5) HJBLO(4) HJBLO(3) HJBLO(2) HJBLO(1) HJBLO(0) e m p ty
Shift Load
CLK2M O
FS8KO
Not
CLK2M O
Not
FS8KO
HJBLI HJBLI(0) HJBLI(1) HJBLI(2) HJBLI(3) HJBLI(4) HJBLI(5) HJBLI(6) HJBLI(7) HJBLI(8) HJBLI(9)
Shift
The management UART protocol defines the three types of frames: the
configuration frame, the alarm query frame and the low-speed asynchronous
serial channel access frame (serial channel access frame). Each frame consists
of several 11-bit packets and each packet contains 1 start bit, 8 data bits, 1 odd
parity bit and 1 stop bit.
The baud rate of the management UART is configurable. When high level is
on pin SPD_SELI, the baud rate is 19200bps; otherwise the baud rate is
9600bps.
If there is no effective data to be output, the management UART output pin
SIBUSO is forced to high impedance (tri-state). See Fig. 4-2-7-1-1 for
connection details. This allows the system designers to use one processor to
control multi-RC7017 through UART interface.
TX SIBUSI ADDRI
PC M A X 232 RC7017(0)
RX S IB U S O 0
SIBUSI ADDRI
RC7017(0)
S IB U S O 1
SIBUSI ADDRI
RC7017(0)
S IB U S O 2
.
.
.
Each frame contains header, body and end. The header includes three bytes
as following: 0x7E, 0x82, 6-bit Address and 2-bit Sign, which indicates frame
types (10 represents query frame, 11 represents configuration frame, and 01
represents serial channel access frame). The end byte should be 0x33. Only
when the end mark is received successfully, a frame is seen as valid.
MSB LSB
0x7E
0x82 Header
Sign(2bit) Address(6bit)
Content Body
0x33 End
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Configuration Frame Sign = 11
2.5:0 Address Assigned by ADDRI
CMD1
3.7:0 Instruction to make E1 tributary remote Loop-back.
3.7~3.0 control E1 channel 7~ 0 respectively.
1 = Loop-back enable;
0 = Loop-back disable.
These control bits provide the same capability as the control pin
E1_LOOPI.
CMD2
4.7 Reserved
4.6:5 Automatic Protect Switching Configuration.
See Table 4-2-7-2-2 for details.
4.4 Hook.
1 = Hook.
0 = Off-Hook.
This control bit provides the same capability as control pins
HOOKI without reference to control bit 5.5.
4.3:2 Setting threshold for Automatic Protect Switching.
If 4.6:5 is 00 and both FORCEI and FORCEBI are low level,
these two control bits determine the threshold, at which auto protect
switching will start. See Table 4-2-7-2-3 for details.
4.1 E1 Tributary Alarm Mask.
1 = Mask enable;
0 = Mask disable.
This control bit provides the same capability as control pin
MASK_ENI.
4.0 Alarm Sound MaskMask.
1 = Mask enable;
0 = Mask disable.
This control bit provides the same capability as control pin
MUTE_ENI.
CMD3
5.7 Unit A transmission enable for ALS.
In customer protection switching mode (low level is on
ALS_ENI), this control bit drives OS_ENAO directly.
Bit Description
5.6 Unit B transmission enable for ALS.
In customer protection switching mode (low level is on
ALS_ENI), this control bit drives OS_ENBO directly.
5.5 Configuration Control Pins Mask.
1 = All the configuration control pins are disabled and the
configuration depends on management UART.
0 = Both configuration control pins and management UART are
enabled.
5.4 Reserved.
5.3 Reserved.
5.2 Low-speed Asynchronous channel Input Pin Mask.
1 = Data of channel 0 to 7 from the pin HJBLI is disabled. The data
only comes from management UART.
0 = Data of channel 0 to 7 from the pin HJBLI is enabled. The
data only comes from the pin HJBLI.
5.1 Low-speed Asynchronous Channel Input Pin Mask.
1 = Data of channel 8 to 15 from the pin HJBLI is disabled. The data
only comes from management UART.
0 = Data of channel 8 to 15 from the pin HJBLI is enabled. The
data only comes from the pin HJBLI.
5.0 Low-speed Asynchronous Channel Input Pin Mask.
1 = Data of channel 16 to 31 from the pin HJBLI is disabled. The
data only comes from management UART.
0 = Data of channel 16 to 31 from the pin HJBLI is enabled. The
data only comes from the pin HJBLI.
CMD4
6.7:0 E1 Tributary Local Port Loop-back.
6.7~6.0 control port 7~port 0 respectively.
1 = Loop-back enable;
0 = Loop-back disable.
These control bits provide the same capability as control pins
E1_LOOPI.
CMD5~CMD7
7.7:0 Reserved.
8.7:0 Reserved.
9.7:0 Reserved.
End
10.7:0 0x33
FORCEAI FORCEBI
Description
(4.6) (4.5)
Low (0) Low (0) Performing Automatic Protection Switching
operations.
Low (0) High (1) Forced selection of data stream from the
input of the optical line B.
High (1) Low (0) Forced selection of data stream from the
input of the optical line A.
4.3:2 Description
00 Perform Automatic Protection Switching operation when Loss of
Optical Line Signals is detected.
01 Perform Automatic Protection Switching operation when either
Loss of Optical Line Signals or Loss of Line Frame is detected.
(Default)
10 Perform Automatic Protection Switching operation when Loss of
Optical Line Signals, Loss of Optical Line Frame or BER exceeding
10-3 is detected.
11 Perform Automatic Protection Switching operation when Loss of
Optical Line Signals, Loss of Optical Line Frame, BER exceeding
10-3 or BER exceeding 10-6 is detected.
There are three types of query frame differentiated by the 4-bit TYP. When
the TYP is 0x0, the RC7017 sends back the frame defined in Table 4-2-7-3;
when the TYP is 0x1, the RC7017 sends back the frame defined in Table
4-2-7-2-1; when the TYP is 0x2, the RC7017 sends back the frame defined in
Table 4-2-7-4-2.
In the alarm query frame sent back by the RC7017, a 1 always indicates
that the corresponding alarm is detected.
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Alarm Query Frame Sign = 10
2.5:0 Address assigned by ADDRI
EOW
3.7:3 Reserved
3.2 Hook status at remote.
1 = Remote off-hook;
0 = Remote hook.
3.1 Active Fiber Input Indication.
1 = The data from fiber A is selected for deframer;
Bit Description
3.0 EOW Status.
1 = On talking;
0 = Other Status.
E1LOS
4.7:0 Loss of Local E1 Tributary Port Signal
Signal.
4.7 is for E1 tributary 7 and 4.0 is for E1 tributary 0.
DETCV
5.7:0 HDB3 Coding Violation of Local E1 Tributary Port.
5.7 is for E1 tributary 7 and 5.0 is for E1 tributary 0.
ALM
6.7 Local Global Alarm.
6.6 Loss of Local Optical Signal.
6.5 Loss of Local Optical Line Frame.
6.4 Local Line Bit Error Rate (BER) exceeding 10-3.
6.3 Local Line Bit Error Rate (BER) exceeding 10-6.
6.2:0 Reserved.
R_E1LOS
7.7:0 Loss of Remote E1 Tributary Port Signal Signal.
7.7 is for E1 tributary 7 and 7.0 is for E1 tributary 0.
R_DETCV
8.7:0 HDB3 Coding Violation of Remote E1 Tributary Port.
8.7 is for E1 tributary 7 and 8.0 is for E1 tributary 0.
R_ALM
9.7 Remote Global Alarm.
9.6 Loss of Remote Optical Signal Alarm.
9.5 Loss of Remote Optical Line Frame Alarm.
9.4 Remote Line Bit Error Rate (BER) exceeding 10-3.
9.3 Remote Line Bit Error Rate (BER) exceeding 10-6.
9.2:0 Reserved.
RESERVED1- RESERVED4
10.7:0 Reserved.
11.7:0 Reserved.
12.7:0 Reserved.
13.7:0 Reserved.
End
14.7:0 0x33
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Alarm Query Frame Sign = 01
2.5:0 Address assigned by ADDRI
RW12
3.7:4 Reserved
3.3:2 R/W1.
11 = Writing operation of low-speed asynchronous serial channel
0~7;
Others = Reading operation of low-speed asynchronous serial
channel 0~7.
3.1:0 R/W2.
11 = Writing operation of low-speed asynchronous serial channel
8~15;
Others = Reading operation of low-speed asynchronous serial
channel 8~15.
REG1
4.7:0 Data written to low-speed asynchronous serial channel 0~7 if
R/W1 is 11.
4.7 is for channel 0 and 4.0 is for channel 7.
Bit Description
REG2
5.7:0 Data written to low-speed asynchronous serial channel 8~15 if
R/W2 is 11.
5.7 is for channel 8 and 5.0 is for channel 15.
RW34
6.7:4 Reserved
6.3:2 R/W3.
11 = Writing operation of low-speed asynchronous serial channel
16~23;
Others = Reading operation of low-speed asynchronous serial
channel 16~23.
6.1:0 R/W4.
11 = Writing operation of low-speed asynchronous serial channel
24~31;
Others = Reading operation of low-speed asynchronous serial
channel 24~31.
REG3
7.7:0 Data written to low-speed asynchronous serial channel 16~23 if
R/W3 is 11.
7.7 is for channel 16 and 7.0 is for channel 23.
REG4
8.7:0 Data written to low-speed asynchronous serial channel 24~31 if
R/W4 is 11.
8.7 is for channel 24 and 8.0 is for channel 31.
End
9.7:0 0x33
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Alarm Query Frame Sign = 01
2.5:0 Address assigned by ADDRI
REG1
3.7:0 Data written to low-speed asynchronous serial channel 0~7.
3.7 is for channel 0 and 3.0 is for channel 7.
REG2
4.7:0 Data written to low-speed asynchronous serial channel 8~15.
4.7 is for channel 8 and 4.0 is for channel 15.
REG3
5.7:0 Data written to low-speed asynchronous serial channel 16~23.
5.7 is for channel 16 and 5.0 is for channel 23.
REG4
Bit Description
6.7:0 Data written to low-speed asynchronous serial channel 24~31.
6.7 is for channel 24 and 6.0 is for channel 31.
R_REG1
7.7:0 Received data of low-speed asynchronous serial channel 0~7.
7.7 is for channel 0 and 7.0 is for channel 7.
R_REG2
8.7:0 Received data of low-speed asynchronous serial channel 8~15.
8.7 is for channel 8 and 8.0 is for channel 15.
R_REG3
9.7:0 Received data of low-speed asynchronous serial channel
16~23.
9.7 is for channel 16 and 9.0 is for channel 23.
R_REG4
10.7:0 Received data of low-speed asynchronous serial channel
24~31.
10.7 is for channel 24 and 10.0 is for channel 31.
End
11.7:0 0x33
5. Technical Parameters
The maximum ratings are threshold values that must not be exceeded even
momentarily. Any exceeding may cause permanent damage to the device.
(VSS=0V)
5.2 DC Characteristics
Ratings
Parameter Symbol Unit
Min. Typ. Max.
Supply voltage VDD 3.0 3.3 3.6 V
High 3V Normal VIH VDDx0.65 - VDD+0.3 V
level CMOS Schmitt VDDx0.80
Input 5V Normal VDDx0.65 - 5.5
voltage Tolerant Schmitt VDDx0.80
3V Normal VIL VDD - VDDx0.25 V
CMOS Schmitt VDDx0.20
5V
Tolerant
Junction Temperature Tj 0 - 100 °C
(VDD=3.3V+/-0.3V, VSS=0V)
5.2.2 DC Characteristics
Value
Parameter Symbol Condition Unit
Min. Typ. Max.
Supply IDDS Static state (VIH=VDD, - - 300 uA
Current VIL=VSS)
High level VOH 2mA IOH=-2mA VDD-0.5 - VDD V
output buffer IOH=-4mA
voltage 4mA
buffer
Low level VOL 2mA IOL=2mA VSS - 0.4 V
output buffer IOL=4mA
voltage 4mA
buffer
Output IOS 2mA VO=0V or VDD - - +/-30 mA
short-circuit buffer +/-60
Current 4mA
buffer
Input ILI Input VI=0V~VDD -5 - 5 uA
leakage cell
current ILZ BUS
input
Input RP Typical type VI=VDD 25 50 100 KΩ
pull-down Tolerant type VI=5V 200
resistance
Input Typical type VI=0V 25 50 100
pull-up Tolerant type VI=0V 200
resistance
(VDD=3.3V+/-0.3V,VSS=0V,Tj=0~100 ºC)
Paramete Value
Symbol Condition Unit
r Min. Typ. Max.
Center VC VC=1.3V V
level VC=1.6V
VC=2.0V
High level VIH Differential VIL+0.3 - VDD V
input input pin
voltage VIH Single REF+0.3
input pin
Low level VIL Differential VSS - VIL-0.3 V
input input pin
voltage VIL Single REF-0.3
input pin
High level VOH Output pin Vt-0.05 Vt Vt+0.05 V
output
voltage
Low level VOL Output pin Vr-0.05 Vr Vr+0.05 V
output
voltage
BIAS Low Vr VC=1.3V Vt*-0.85 - Vt-0.35 V
level input VC=1.6V
voltage VC=2.0V
Reference REF Single VC-0.05 VC VC+0.05 V
level input
5.3 AC Characteristics
(Tj=+25 ºC ,VDD=VI=0V,F=1MHz)
M RXC
MRXDV
M RXD3~0
Teod
M TXC
M TXEN
M TXD3~0
T e is T e ih
Value
Symbol Parameter Unit
Min. Typ. Max.
Teod MRXDV, 10 - 22 ns
MRXD
Output
Delay to
MRXC
rising edge
Teis MTXEN, 5 - -
MTXD
Setup to
MTXC
rising edge
Teih MTXEN, 5 - -
MTXD
Hold to
MTXC
rising edge
E1N O
E1PO
Tpod
E1NI
E1PI
T p is T p ih
Value
Symbol Parameter Unit
Min. Typ. Max.
Tpod E1PO Output - 0 - ns
Delay to E1NO
falling edge
Tpis E1PI Setup to 10 - -
E1NI rising edge
Tpih E1PI Hold to 10 - -
E1NI rising edge
6. Package
22
20
108 73
109 72
20
22
RC7017
144 37
1 36
0 .5 0 .2 2
0 .4 0 .6
7. Application Guide
MC54/
Conver
74H C 1 M A X 232
te r
65
1xE1
(NRZ)
L IU 1~8xE 1
Optical
Transceiver
R C 7017
Optical
Transceiver SW I
M II
TCH
MC54/
CODE
74H C 5
C
95
Phone A la r m
The RC7017 integrates PDH and Ethernet operations in a single chip with
two optical line ports and abundant auxiliary channels. It is easy to design an
optical terminal device series with the following features:
One PCB suitable for all devices with different numbers of E1 ports.
Devices with both a PDH interface and a full-speed Ethernet interface.
Safe optical terminal with capability of point-to-point 1+1 optical line
protection switching and Automatic Leaser Shutdown/Reduction.
Abundant auxiliary channels for some special conditions.
In order to support ALS, a fiber transceiver with tx_dis is needed. See the
figure below for connection details.
OSDAI
100
1 .6 V 3 .3 V
BIASEAI
B IA S E B O
3 .3 V LM
110 510
1u 0 .0 1 u 358
33 rd +
RSDAPI
rd -
RSDANI
1
820 620 18
RX
RC7017 0 .1 u 0 .1 u 1 0 u
tx_ d is sd
1 .2 u H
OS_ENAO VCC
3 .3 V 5V
5V 1 .2 u H
TX
0 .1 u 0 .1 u 1 0 u
200 10
82 9
75 td -
TSDANO
td + T o p V ie w
TSDAPO
0 .0 1 u
510 510
Fig. 7-2-3: Connection between the RC7017 and Fiber Transceiver with
tx_dis
FS8KO(P60) 1
S H /L D
GND 15 16 VCC
C L K IN H VCC
2
C LK
CLK2MO(P58)
GND 10
SER
GND 11
A
GND 12
B 74HC165
13
C
14 9 ADDRI(P103)
D QH
3 7
E nQ H
4
F
5
G
6 8 GND
H GND
5 4 3 2 1 0
MSB LSB
FS8KO(P60) 1
S H /L D
GND 15 16 VCC
C L K IN H VCC
2
CLK
CLK2MO(P58)
GND 10
SER
11
A
12
B 74HC165
13
C HDB3_NRZ_SELI(P31)
14 9
D QH E1_LOOPI(P28)
3 7
E nQH MASK_ENI(P47)
4
F
5
G
6 8 GND
H GND
7 6 5 4 3 2 1 0
MSB LSB
GND
SER QH SER QH
74HC165 74HC165
A B C D E F G H A B C D E F G H
3130292827262524 2322212019181716
MSB
HJBLI(P32)
SER QH SER QH
74HC165 74HC165
A B C D E F G H A B C D E F G H
151413121110 9 8 7 6 5 4 3 2 1 0
LSB
15 14 E1A S D O (P4 4 )
Q0 DS
1 16 VCC
Q1 VCC
2 8 GND
Q2 GND
3 13 GND
Q3 OE
4 7 4 H C 595 12 F S 8K O (P6 0 )
Q4 STCP
5 11
Q5 SHCP
6 10 VCC
Q6 MR
7 9
Q7 Q7~
C L K 2M O (P5 8 )
0 1 2 3 4 5 6 7
LSB MSB
E1 L O S
15 14
Q0 DS
1 16 VCC
Q1 VCC
2 8 GND
Q2 GND
3 13 GND
Q3 OE
4 7 4 H C 595 12 F S 8K O (P6 0 )
Q4 STCP
5 11
Q5 SHCP
6 10 VCC
Q6 MR
7 9
Q7 Q7~
C L K 2M O (P5 8 )
0 1 2 3 4 5 6 7
LSB MSB
E1 H D B 3 Code Violation
Q7~ DS Q7~ DS
74HC595 74HC595
QQ Q QQQQ Q Q QQQQ Q QQ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
3130292827262524 2322212019181716
MSB
HJBLO(P38)
Q7~ DS Q7~ DS
74HC595 74HC595
QQ Q QQQQ Q Q QQQQ Q QQ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
151413121110 9 8 7 6 5 4 3 2 1 0
LSB