Datasheet - HK Pic16f73 271716 PDF
Datasheet - HK Pic16f73 271716 PDF
Datasheet - HK Pic16f73 271716 PDF
PIC16F77/74
branches which are two cycle RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
• Operating speed: DC - 20 MHz clock input
RE2/CS/AN7 10 31 VSS
DC - 200 ns instruction cycle VDD 11 30 RD7/PSP7
• Up to 8K x 14 words of FLASH Program Memory, VSS 12 29 RD6/PSP6
Up to 368 x 8 bytes of Data Memory (RAM) OSC1/CLKIN 13 28 RD5/PSP5
OSC2/CLKOUT 14 27 RD4/PSP4
• Pinout compatible to the PIC16C73B/74B/76/77 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
• Pinout compatible to the PIC16F873/874/876/877 RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
• Interrupt capability (up to 12 sources)
RC3/SCK/SCL 18 23 RC4/SDI/SDA
• Eight level deep hardware stack RD0/PSP0 19 22 RD3/PSP3
MCLR/VPP 1 28 RB7
RA0/AN0 2 27 RB6
RA1/AN1 3 26 RB5
RA2/AN2 4 25 RB4
PIC16F76/73
RA3/AN3/VREF 5 24 RB3
RA4/T0CKI 6 23 RB2
RA5/AN4/SS 7 22 RB1
VSS 8 21 RB0/INT
OSC1/CLKIN 9 20 VDD
OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
RA3/AN3/VREF
MCLR/VPP
RA2/AN2
RA1/AN1
RA0/AN0
PLCC
RB7
RB6
RB5
RB4
NC
NC
6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI 7 39 RB3
RA5/AN4/SS 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F77 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F74 33 RD7/PSP7
OSC1/CLKIN 14 32 RD6/PSP6
OSC2/CLKOUT 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
282
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RC4/SDI/SDA
RC6/TX/CK
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC5/SDO
NC
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
NC
QFP
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
RD6/PSP6 4 30 OSC1/CLKIN
RD7/PSP7 5 PIC16F77 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F74 27 RE2/AN7/CS
RB0/INT 8 26 RE1/AN6/WR
RB1 9 25 RE0/AN5/RD
RB2 10 24 RA5/AN4/SS
RB3 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
NC
NC
RB4
RB5
RA0/AN0
RA1/AN1
RA2/AN2
RB6
RB7
MCLR/VPP
RA3/AN3/VREF
Key Features
PICmicro™ Mid-Range Reference Manual PIC16F73 PIC16F74 PIC16F76 PIC16F77
(DS33023)
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)
FLASH Program Memory 4K 4K 8K 8K
(14-bit words, 100 E/W cycles)
Data Memory (bytes) 192 192 368 368
Interrupts 11 12 11 12
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3 3 3 3
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART
Parallel Communications — PSP — PSP
8-bit Analog-to-Digital Module 5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
erature number) you are using.
Synchronous
CCP1,2 USART
Serial Port
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Synchronous
CCP1,2 USART
Serial Port
SSOP
DIP I/O/P Buffer
Pin Name SOIC Description
Pin# Type Type
Pin#
access can occur and is detailed in this section. The CALL, RETURN 13
Program Memory can be read internally by user code RETFIE, RETLW
(see Section 4.0).
Additional information on device memory may be found Stack Level 1
in the PICmicro Mid-Range Reference Manual,
Stack Level 2
(DS33023).
CALL, RETURN 13
RETFIE, RETLW
1FFFh
Stack Level 1
Stack Level 2
Stack Level 8
17FFh
1800h
Page 3
1FFFh
Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
PORTD(1) 08h TRISD(1) 88h 108h 188h
PORTE(1) 09h TRISE(1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATA 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh PMADR 10Dh 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh 8Fh PMADRH 10Fh 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h 95h 115h 195h
CCPR1H 16h 96h 116h 196h
CCP1CON 17h 97h General 117h General 197h
Purpose Purpose
RCSTA 18h TXSTA 98h Register 118h Register 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah 9Ah 11Ah 19Ah
CCPR2L 1Bh 9Bh 11Bh 19Bh
CCPR2H 1Ch 9Ch 11Ch 19Ch
CCP2CON 1Dh 9Dh 11Dh 19Dh
ADRES 1Eh 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
PORTD(1) 08h TRISD(1) 88h 108h 188h
PORTE(1) 09h TRISE(1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATA 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh PMADR 10Dh 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh 8Fh PMADRH 10Fh 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h 91h
T2CON 12h PR2 92h
SSPBUF 13h SSPADD 93h
SSPCON 14h SSPSTAT 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah 9Ah
CCPR2L 1Bh 9Bh
CCPR2H 1Ch 9Ch
CCP2CON 1Dh 9Dh
ADRES 1Eh 9Eh
ADCON0 1Fh ADCON1 9Fh
120h 1A0h
20h A0h
General General
Purpose Purpose accesses accesses
Register Register
20h-7Fh A0h - FFh
96 Bytes 96 Bytes 16Fh 1EFh
170h 1F0h
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 (3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIF
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register Byte xxxx xxxx uuuu uuuu
GO/
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 — ADON 0000 00-0 0000 00-0
DONE
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
104h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch PMDATA Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh PMADR Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH — — Data Register High Byte xxxx xxxx uuuu uuuu
10Fh PMADRH — — — Address Register High Byte xxxx xxxx uuuu uuuu
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
OPTION_
181h RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
184h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch PMCON1 — (6) — — — — — — RD 1--- ---0 1--- ---0
18Dh — Unimplemented — —
18Eh — Reserved maintain clear 0000 0000 0000 0000
18Fh — Reserved maintain clear 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
The PIE1 register contains the individual enable bits for Note: Bit PEIE (INTCON<6>) must be set to
the peripheral interrupts. enable any peripheral interrupt.
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Data
Memory(1)
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
TRIS Latch
RB0/INT D Q
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
RD TRIS
Q D
ENEN
RD Port
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or
analog input:
RD
1 = Idle
0 = Read operation. Contents of PORTD register output to PORTD I/O
pins (if chip selected).
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 = Idle
0 = Write operation. Value of PORTD I/O pins latched into PORTD
register (if chip selected).
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
8
M 1
0
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 reg
1 0
X Cycles
T0SE
T0CS
PSA Set Flag bit T0IF
on Overflow
PRESCALER
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: To avoid an unintended device RESET, the instruction sequence shown in the
PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed
when changing the prescaler assignment from Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
T1CKI
(Default high)
T1CKI
(Default low)
6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is
Counter Mode synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
Counter mode is selected by setting bit TMR1CS. In caler stage is an asynchronous ripple counter.
this mode, the timer increments on every rising edge of
In this configuration, during SLEEP mode, Timer1 will
clock input on pin RC1/T1OSI/CCP2, when bit
not increment even if the external clock is present,
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
since the synchronization circuit is shut off. The
bit T1OSCEN is cleared.
prescaler however, will continue to increment.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchro-
16-bit value of the TMR1 register when an event occurs nized Counter mode for the CCP module to use the
on pin RC2/CCP1. An event is defined as one of the fol- capture feature. In Asynchronous Counter mode, the
lowing and is configured by CCPxCON<3:0>: capture operation may not work.
• Every falling edge 8.3.3 SOFTWARE INTERRUPT
• Every rising edge
• Every 4th rising edge When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
• Every 16th rising edge
CCP1IE (PIE1<2>) clear to avoid false interrupts and
An event is selected by control bits CCP1M3:CCP1M0 should clear the flag bit CCP1IF following any such
(CCP1CON<3:0>). When a capture is made, the inter- change in operating mode.
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another 8.3.4 CCP PRESCALER
capture occurs before the value in register CCPR1 is
There are four prescaler settings, specified by bits
read, the old captured value is overwritten by the new
CCP1M3:CCP1M0. Whenever the CCP module is
captured value.
turned off, or the CCP module is not in Capture mode,
8.3.1 CCP PIN CONFIGURATION the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
In Capture mode, the RC2/CCP1 pin should be config-
Switching from one capture prescaler to another may
ured as an input by setting the TRISC<2> bit.
generate an interrupt. Also, the prescaler counter will
Note: If the RC2/CCP1 pin is configured as an not be cleared, therefore, the first capture may be from
output, a write to the port can cause a a non-zero prescaler. Example 8-1 shows the recom-
capture condition. mended method for switching between capture pres-
calers. This example also clears the prescaler counter
FIGURE 8-1: CAPTURE MODE OPERATION and will not generate the “false” interrupt.
BLOCK DIAGRAM
EXAMPLE 8-1: CHANGING BETWEEN
Set Flag bit CCP1IF CAPTURE PRESCALERS
Prescaler (PIR1<2>)
÷ 1, 4, 16 CLRF CCP1CON ;Turn CCP module off
RC2/CCP1 CCPR1H CCPR1L MOVLW NEW_CAPT_PS ;Load the W reg with
Pin ; the new prescaler
and Capture ; move value and CCP ON
edge detect Enable MOVWF CCP1CON ;Load CCP1CON with this
; value
TMR1H TMR1L
CCP1CON<3:0>
Q’s
8.4.3 SOFTWARE INTERRUPT MODE Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
SDI (SMP = 0)
bit7 bit0
SDI (SMP = 1)
bit7 bit0
SSPIF
SCK (CKP = 0)
SCK (CKP = 1)
SDI (SMP = 0)
bit7 bit0
SSPIF
SCK (CKP = 0)
SCK (CKP = 1)
SDI (SMP = 0)
bit7 bit0
SSPIF
0Bh,8Bh. INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>) Cleared in software
BF (SSPSTAT<0>)
From SSP Interrupt
SSPBUF is written in software Service Routine
CKP (SSPCON<4>)
Master mode of operation is supported in firmware In Multi-Master mode, the interrupt generation on the
using interrupt generation on the detection of the detection of the START and STOP conditions, allows
START and STOP conditions. The STOP (P) and the determination of when the bus is free. The STOP
START (S) bits are cleared from a RESET or when the (P) and START (S) bits are cleared from a RESET or
SSP module is disabled. The STOP (P) and START (S) when the SSP module is disabled. The STOP (P) and
bits will toggle based on the START and STOP condi- START (S) bits will toggle based on the START and
tions. Control of the I 2C bus may be taken when the P STOP conditions. Control of the I 2C bus may be taken
bit is set, or the bus is idle and both the S and P bits are when bit P (SSPSTAT<4>) is set, or the bus is idle and
clear. both the S and P bits clear. When the bus is busy,
In Master mode, the SCL and SDA lines are manipu- enabling the SSP Interrupt will generate the interrupt
lated by clearing the corresponding TRISC<4:3> bit(s). when the STOP condition occurs.
The output level is always low, irrespective of the In Multi-Master operation, the SDA line must be moni-
value(s) in PORTC<4:3>. So when transmitting data, a tored to see if the signal level is the expected output
’1’ data bit must have the TRISC<4> bit set (input) and level. This check only needs to be done when a high
a ’0’ data bit must have the TRISC<4> bit cleared (out- level is output. If a high level is expected and a low level
put). The same scenario is true for the SCL line with the is present, the device needs to release the SDA and
TRISC<3> bit. Pull-up resistors must be provided SCL lines (set TRISC<4:3>). There are two stages
externally to the SCL and SDA pins for proper opera- where this arbitration can be lost, these are:
tion of the I2C module. • Address Transfer
The following events will cause SSP Interrupt Flag bit, • Data Transfer
SSPIF, to be set (SSP Interrupt will occur if enabled):
When the slave logic is enabled, the slave continues to
• START condition receive. If arbitration was lost during the address trans-
• STOP condition fer stage, communication to the device may be in
• Data transfer byte transmitted/received progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
Master mode of operation can be done with either the
stage, the device will need to re-transfer the data at a
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
later time.
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
(2) (2)
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I2C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
2: Maintain these bits clear in I2C mode.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
Interrupt RCIF
Data Bus
RCIE
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
SPEN
Interrupt RCIF
Data Bus
RCIE
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Write to
TXREG reg
Write Word1 Write Word2
TXIF bit
(Interrupt Flag)
TRMT
TRMT bit
’1’ ’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000 A A A A A A A A VDD
001 A A A A VREF A A A RA3
010 A A A A A D D D VDD
011 A A A A VREF D D D RA3
100 A A D D A D D D VDD
101 A A D D VREF D D D RA3
11x D D D D D D D D VDD
A = Analog input
D = Digital I/O
Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VIN
(Input Voltage) 011
RA3/AN3/VREF
010
A/D RA2/AN2
Converter
001
RA1/AN1
VDD 000
RA0/AN0
000 or
010 or
VREF 100 or
11x
(Reference
Voltage) 001 or
011 or
101
PCFG2:PCFG0
Note 1: Not available on PIC16F73/76.
CHOLD
VA CPIN I leakage = DAC Capacitance
5 pF VT = 0.6V ± 500 nA = 51.2 pF
VSS
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
(2) — — — — — ---- -xxx ---- -uuu
09h PORTE RE2 RE1 RE0
89h TRISE(2) IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2: These registers are reserved on the PIC16F73/76.
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
MCLR
SLEEP
WDT WDT
Module Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1
(1) PWRT
On-chip
RC OSC 10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
PSPIF
PSPIE
ADIF Wake-up (If in SLEEP mode)
T0IF
ADIE T0IE
RCIF INTF
RCIE INTE
Interrupt to CPU
TXIF RBIF
TXIE RBIE
SSPIF
SSPIE
PEIE
CCP1IF
CCP1IE GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
0
M Postscaler
1 U
WDT Timer
X 8
8 - to - 1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0 1
MUX PSA
WDT
Note: PSA and PS2:PS0 are bits in the OPTION_REG register. Time-out
2007h Config. bits (1) BODEN(1) — CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(0004h)
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0005h)
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
executed Inst(PC - 1) Inst(0004h)
PD Power-down bit 13 8 7 0
OPCODE k (literal)
The instruction set is highly orthogonal and is grouped
into three basic categories: k = 8-bit immediate value
• Byte-oriented operations
CALL and GOTO instructions only
• Bit-oriented operations
13 11 10 0
• Literal and control operations
OPCODE k (literal)
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
24CXX/
25CXX/
TABLE 14-1:
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
®
MPLAB Integrated
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
®
MPLAB C17 Compiler
á á
á á
®
MPLAB C18 Compiler
®
MPLAB -ICE **
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á á
ICEPIC‰ Low-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
®
MPLAB -ICD In-Circuit
* *
Debugger
á
á
á
PICSTART‚Plus
Low-Cost Universal Dev. Kit **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PRO MATE‚ II
Universal Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
† †
PICDEM-2
DEVELOPMENT TOOLS FROM MICROCHIP
á
á á
á
PICDEM-3
á
Advance Information
PICDEM-14A
á
PICDEM-17
á
®
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB -ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
DS30325A-page 123
PIC16F7X
PIC16F7X
NOTES:
6.0 V
5.5 V
5.0 V
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz 20 MHz
Frequency
6.0 V
5.5 V
5.0 V
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz 10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
Note: Refer to Figure 15-3 for load conditions.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
VDD VBOR
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40°C to +85°C
31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset Pulse Width 100 — — µs VDD ≤ VBOR (D005)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50 51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53 54
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-3 for load conditions.
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 15-3 for load conditions.
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
Note: Refer to Figure 15-3 for load conditions.
82
SS
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb IN BIT6 - - - -1 LSb IN
74
Note: Refer to Figure 15-3 for load conditions.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Note: Refer to Figure 15-3 for load conditions.
RC6/TX/CK
Pin 121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 15-3 for load conditions.
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
A01 NR Resolution PIC16F7X — — 8 bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LF7X — — 8 bits bit VREF = VDD = 2.0V
A02 EABS Total Absolute error — — <±1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — <±1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — <±1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity (Note 3) — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 2.0V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of — — 10.0 kΩ
analog voltage source
A40 IAD A/D conversion PIC16F7X — 180 — µA Average current con-
current (VDD) PIC16LF7X — 90 — µA sumption when A/D is
on (Note 1).
A50 IREF VREF input current (Note 2) 10 — 1000 µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see
Section 12.1.
During A/D Conversion
— — 10 µA cycle.
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
130 TAD A/D clock period PIC16F7X 1.6 — — µs TOSC based, VREF ≥ 3.0V
PIC16LF7X 2.0 — — µs TOSC based,
2.0V ≤ VREF ≤ 5.5V
PIC16F7X 2.0 4.0 6.0 µs A/D RC mode
PIC16LF7X 3.0 6.0 9.0 µs A/D RC mode
131 TCNV Conversion time (not including S/H 9 — 9 TAD
time) (Note 1)
132 TACQ Acquisition time 5* — — µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time 1.5 § — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 for min. conditions.
XXXXXXXXXXXXXXXXXXXX PIC16F76-I/SO
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 0010SAA
XXXXXXXXXXXX PIC16F73-I/SS
XXXXXXXXXXXX
YYWWNNN 0010SBP
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, and traceability code. For
marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For
QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXX PIC16F77-
XXXXXXXXXX I/PT
XXXXXXXXXX
YYWWNNN 0011HAT
XXXXXXXXXX PIC16F77-I/L
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN 0003SAT
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A 2000 This is a new data sheet. However, these devices are similar to the PIC16C7X
devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X
devices (DS30292).
Packages 28-pin PDIP, 28-pin SOIC, 28-pin SSOP 40-pin PDIP, 44-pin TQFP, 44-pin PLCC
Timers 3 3 3
Interrupts 11 or 12 13 or 14 11 or 12
Communication PSP, USART, SSP (SPI, PSP, USART, SSP (SPI, PSP, USART, SSP (SPI,
I2C Slave) I2C Master/Slave) I2C Slave)
CCP 2 2 2
RAM 192, 368 bytes 192, 368 bytes 192, 368 bytes
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All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 9/00 Printed on recycled paper.
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