SV

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What System Verilog data structure can be used for communication between a monitor
and a score board or checker?
Dynamic Array
Classes
Queues or mailbox
interfaces
2.Why do we need virtual interfaces in system verilog?

Because we need a way to connect the dynamic world of modules(design) to static
world of classes (Testbench)
Because we need a way to connect the static world of modules(design) to dynamic

world of classes (Testbench)
Because Interfaces can never be physical
None Of The Above
What is meant by an Abstract class ?

Class that has all members and methods as static
Class that has all members and methods as constant
Class that is inherited from a base class
Class that has only virtual functions and is meant to be only used for implementing
derived class
Which of this is not true with respect to a queue and a mailbox?

A mailbox size can be pounded while a queue has no limits in size
No difference and mailbox is just a queue

A queue supports adding, removing or modifying an entry in the queue at any given
time while a mailbox can only be accessed at head of it
None Of The Above5.If a clocking block definition has timing specified as follows -
what does it mean?
default input #2ns output #3ns
All input signals in the clocking block are sampled 2ns before clocking event and all
output signals are driven 3ns before clocking event
All input signals in the clocking block are sampled 2ns after clocking event and all
output signals are driven 3ns before clocking event
All input signals in the clocking block are sampled 2ns after clocking event and all
output signals are driven 3ns after clocking event
All input signals in the clocking block are sampled 2ns before clocking event and all
output signals are driven 3ns after clocking event
What is difference between get() and peek() methods in mailbox?

Both are non-blocking while get() removes the item from mailbox while peek only
makes a copy
Both are blocking while get() removes the item from mailbox while peek only makes
a copy
get() is a blocking method while peek() is non-blocking
get() is a non-blocking method while peek() is blocking
.A single SystemVerilog “interface” can have multiple modports and multiple clocking
blocks inside
True
False
.Which of the following statement related to assertions is not correct ?

Assertions helps in debugging and checking of design correctness
Assertions are useful in both Simulation and Formal Verification
Assertions are a way to generate stimulus for verification
Assertions are useful to judge quality of stimulus used for verification
Which of the following is not correct with respect to formal verification?

Formal Verification needs effort in creating stimulus generator for verifying design
Formal Verification on FSM based models to prove FSM state transitions and
behavior is known as model checking
Formal Verification can use assertions to capture design intent
Formal Verification uses mathematical models and algorithms to exhaustively verify

design intent
What is the difference between a local member and a protected member inside a system
verilog class?
local member can only be accessed in class while protected member can be
acessed inside as well as in derived class
protected members are local to the class while local member can be accessed from
same class or derived class
Both can be accessed only inside same class where it is defined
local member can be accessed from anywhere while protected member can be
acessed inside as well as in derived class
.Which of the following is not supported inside a System Verilog interface?

functions
tasks
modules
always blocks
.Polymorphism is based on the concept that a base class pointer can be used to reference
any of the derived class objects
True
False
.Which of the following are true with respect to System Verilog arrays?
Associative arrays can be used when size of an array is not known as it can be built
as key/value pairs
Dynamic arrays are useful for contiguous collection of variables whose number
keeps varying
Dynamic arrays can be re-sized after size is allocated once
All Of The Above
.What is meant by inheritance in object oriented programming like System Verilog?

It is a concept in which same object can exist in multiple forms
It is a way in which a class can hide all its properties and attributes being accessed
from outside
It is the concept that allows a class to instantiate another class as its member
It is a way in which a class can extend all properties and methods of a base class
.Which of the following is not a good coding convention using Verilog/SystemVerilog ?

Always use non-blocking assignments in a combinational block, and blocking
assignments in a sequential block
Always use blocking assignments in a combinational block, and non-blocking

assignments in a sequential block
All Of The Above
None Of The Above

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2.Why do we need virtual interfaces in system verilog?

Because we need a way to connect the static world of modules(design) to dynamic

Because Interfaces can never be physical

None Of The Above

What is meant by an Abstract class ?

Class that has all members and methods as constant

Class that is inherited from a base class

Which of this is not true with respect to a queue and a mailbox?

No difference and mailbox is just a queue

What is difference between get() and peek() methods in mailbox?

get() is a blocking method while peek() is non-blocking

get() is a non-blocking method while peek() is blocking

.Which of the following statement related to assertions is not correct ?

Assertions are a way to generate stimulus for verification

Assertions are useful to judge quality of stimulus used for verification

Which of the following is not correct with respect to formal verification?

Formal Verification can use assertions to capture design intent

Formal Verification uses mathematical models and algorithms to exhaustively verify

Both can be accessed only inside same class where it is defined

.Which of the following is not supported inside a System Verilog interface?

Dynamic arrays can be re-sized after size is allocated once

All Of The Above

.What is meant by inheritance in object oriented programming like System Verilog?

.Which of the following is not a good coding convention using Verilog/SystemVerilog ?

Always use blocking assignments in a combinational block, and non-blocking

All Of The Above

None Of The Above

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