Digital Logic Design

Chapter 3

Combinational Logic

0
 Combinational Logic

 Logic circuits for digital systems may be combinational or

sequential.
 A combinational logic circuit has:
● A set of m Boolean inputs,
● A set of n Boolean outputs, and
● n switching functions, each mapping the 2m input combinations to an output such
that the current output depends only on the current input values
 Block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

1
 Combinational Logic
 Combinational logic: Output is function of input only
i.e. no feedback

Combinational
n inputs • • m outputs
• Circuits •
• •


Combinational logic circuits contain no memory (no ability to
store information)

2
 Basic Combinational Logic Circuits
AND-OR LOGIC

Represents SOP implementation – AND gate for product term, OR gate for
summing the product terms

3
 Basic Combinational Logic Circuits
AND-OR-INVERT LOGIC

Represents POS implementation – AND gate for product term, OR gate for
summing the product terms, NOT gate to complement the AND-OR circuit.

4
 Basic Combinational Logic Circuits
XOR LOGIC

Combination of 2 AND gates, 1 OR gate, & 2 NOT gates.

Considered a type of logic with own unique symbol (  ).

AB  AB  A  B

5
 Basic Combinational Logic Circuits
XOR LOGIC

Example: Use exclusive-OR gates to implement an even-parity code generator

for an original 4-bit code.

Exercise: Use exclusive-OR gates to implement an even-parity checker

for the 5-bit code generated by the circuit in the above Example.
 Basic Combinational Logic Circuits
XNOR LOGIC

The complement of XOR logic.

AB  AB  (A  B)(A  B)  AB  AB  A  B

7
 Universal Property - NAND & NOR
NAND GATE AS A UNIVERSAL LOGIC ELEMENT

NAND gate is a universal gate because it can be used to produce the NOT,
AND, OR and NOR functions.

8
 Universal Property - NAND & NOR
NAND GATE AS A UNIVERSAL LOGIC ELEMENT (OR & NOR Gate)

9
 Universal Property - NAND & NOR
NOR GATE AS A UNIVERSAL LOGIC ELEMENT

NOR gate is also a universal gate because it can be used to produce the NOT,
AND, OR and NAND functions.

10
 Universal Property - NAND & NOR
NOR GATE AS A UNIVERSAL LOGIC ELEMENT (Cont.)

11
 Universal Property - NAND & NOR

NAND LOGIC
NAND Gate can function as either a NAND or a negative-OR because by
DeMorgan’s Theorem:
AB = A + B

NAND Negative-OR
The NAND symbol and the negative-OR symbol are called dual-symbol.

12
 Universal Property - NAND & NOR

NOR LOGIC
NOR Gate can function as either a NOR or a negative-AND because by
DeMorgan’s Theorem:
A+ B = A B

NOR Negative-AND
The NOR symbol and the negative-AND symbol are called dual-symbol.

13
 Universal Property - NAND & NOR

Example:
Using appropriate dual symbols, redraw the logic diagram and develop the
output expression for the following circuit:

14
 Universal Property - NAND & NOR

Exercise: Implement each expression with NAND logic using appropriate dual
symbols:
 Combinational Logic: Analysis and Design
 Analysis
● Given a circuit, find out its function
● Function may be expressed as: A
B
C
F1
?
♦ Boolean function A
B
C

♦ Truth table A
B

A
F2
C
?
 Design B
C

● Given a desired function, determine its circuit

● Function may be expressed as:
♦ Boolean function ?
♦ Truth table

16
 Analysis Procedure

 To obtain the output Boolean functions from a logic diagram,

proceed as follows:

1. Label all gate outputs that are a function of input variables with arbitrary
symbols. Determine the Boolean functions for each gate output.

2. Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean functions for
these gates.

3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.

4. By repeated substitution of previously defined functions, obtain the

output Boolean functions in terms of input variables.

17
 Analysis Procedure

 Boolean Expression Approach

A
B
F1
C T2=ABC
A T1=A+B+C
B T6=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)
T3=AB
A
F2
C T4=AC
F2=AB+AC+BC
B
C
T5=BC F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
18
 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0

19
 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

21
 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1
B =1 0 0 1 1 0 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

22
 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0
1 1 0 0
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0
0 1 0 0 1 0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

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 Analysis Procedure

 Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
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 Design Procedure

1. Specification
● Write a specification for the circuit if one is not already available
2. Formulation
● Derive a truth table or initial Boolean equations that define the
required relationships between the inputs and outputs, if not in the
specification
● Apply hierarchical design if appropriate
3. Optimization
● Apply optimization
● Draw a logic diagram or provide a netlist for the resulting circuit
using ANDs, ORs, and inverters

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 Design Procedure

4. Technology Mapping
● Map the logic diagram to the implementation technology selected

5. Verification
● Verify the correctness of the final design manually or using
simulation

 In simple words, given a problem statement:

● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit

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 Design Example 1
Design a circuit to convert a “BCD” code to “Excess 3” code

 4-bits  4-bits
?
 0-9 values  Value+3

1. Specification
● Transforms BCD code for the decimal digits to Excess-3 code for the
decimal digits
● BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001,
respectively
● Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of
3 (binary 0011) added to each BCD code word
● Implementation:
♦ multiple-level circuit
♦ NAND gates (including inverters)
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 Design Example 1

2. Formulation
● Conversion of 4-bit codes can be most easily formulated by a
truth table
● Variables
- BCD: Input BCD Output Excess-3
A,B,C,D ABCD WXYZ
0000 0011
● Variables 0001 0100
- Excess-3 0010 0101
W,X,Y,Z 0011 0110
● Don’t Cares 0100 0111
- BCD 1010 0101 1000
to 1111 0110 1001
0111 1010
1000 1011
1001 1 1 00
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 Design Example 1
3. Optimization
using
K-maps
W = A + BC + BD
X = BC + B D + BC D
Y = CD + C D
Z= D

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 Design Example 1
4. Technology Mapping
● Mapping with a library containing available logic gates

A
W

B X

C Y
D
Z

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 Design Example 2
 BCD-to-Seven-Segment Decoder
7-Segment display

BCD
code BCD to 7-
segmant
Decoder
Display

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Design Example 2 – Assignment 2
Seven-Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
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 Arithmetic Circuit Design

• Arithmetic Circuits
• Adder
• Subtractor
• BCD Adder
• Multiplier

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 Binary Adder

 Design an Adder for 1-bit numbers?

 1. Specification: 3. Optimization/implementation
2 inputs (X,Y) S = XY'+X‘Y
2 outputs (C,S)
C = XY
 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

This adder is called a Half Adder

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Binary Adder

 Half Adder Logic symbol

● Adds 1-bit plus 1-bit x S
y HA
C
● Produces Sum and Carry
x
+ y
x y C S ───
C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C

Logic Diagram
37
Binary Adder

Full Adder
 A combinational circuit that adds 3 input bits to generate a Sum
bit and a Carry bit x S
y FA
z C

X Y Z C S
0 0 0 0 0 S = X’Y’Z + X’YZ’
+ XY’Z’ +XYZ
0 0 1 0 1
= (X  Y)  Z
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 C = XY + YZ + XZ
C = XY + (X ⊕ Y)Z
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 Binary Adder

Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z

x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z x
x
x
y y
y z y
x
x z C
y z
y
z x C
z
z
y
z

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 Binary Adder
x S

Full Adder y C

x S
y HA HA

z C

x
S

Think of y
Z as a C
carry in
z

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 Parallel Adders

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

1 0 0 0

0101
0110
1011

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 Parallel Adders
x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x 2 x 1 x 0
Carry + y3 y 2 y 1 y 0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
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 Binary Adder

 Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S1 S0

43
 Parallel Adders

Figure: Logic symbol for 4-bit parallel adder

 Parallel Adders

Figure: The 74HC283/74LS283 4-bit parallel adder.

Adder Expansion
Application(A voting system using full-adders and parallel binary adders.)
 Reading Assignment
Ripple Carry and Look-Ahead Carry Adders
 Carry propagation
● When the correct outputs are available
● The critical path counts (the worst case)
● (A1, B1, C1) → C2 → C3 → C4 → (C5, S4)
● When 4-bits full-adder → 8 gate levels (n-bits: 2n gate
levels)

Figure: Full Adder with P and G Shown

48
 Parallel Adders

 Reduce the carry propagation delay

● Employ faster gates
● Look-ahead carry (more complex mechanism, yet faster)
● Carry propagate: Pi = AiBi
● Carry generate: Gi = AiBi
● Sum: Si = PiCi
● Carry: Ci+1 = Gi+PiCi
● C0 = Input carry
● C1 = G0+P0C0
● C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
● C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

49
Carry Look-ahead Adder (1/2)

 Logic diagram

Fig.: Logic Diagram of Carry Look-ahead Generator

50
 Carry Look-ahead Adder (2/2)

 4-bit carry-look
ahead adder
● Propagation delay
of C3, C2 and C1 are
equal.

Fig.: 4-Bit Adder with Carry Look-ahead

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 BCD Adder

 BCD digits are valid for decimal numbers 0-9

 Addition of two BCD numbers will generate an output, that
may be greater than 1001 (9).
● In such cases, the BCD number 0110 is added to the result as a
correction step

 When adding two BCD numbers, the maximum result that can
be obtained is:
9 + 9 = 18
● If we include a carry in bit, then the maximum result that can be
obtained is: 19 (10011)
● Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6 needs to
be added to bring them to correct BCD format.

52
 BCD Adder

 4-bits plus 4-bits + x3 x 2 x 1 x 0

+ y3 y 2 y 1 y 0
 Operands and Result: 0 to 9 ────────
Cy S3 S2 S1 S0
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0

0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value

0001 1000 53
 BCD Adder

X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 

+6

54
 BCD Adder

 Correct Binary Adder’s Output (+6)

● If the result is between ‘A’ and ‘F’
● If Cy = 1

S3 S2 S1 S0 Err The function Err is 1 for

all invalid BCD digits, and
0 0 0 0 0 therefore acts as a BCD S1
verifier
1 0 0 0 0
1 1 1 1
S2
1 0 0 1 0 S3
1 0 1 0 1 1 1
1 0 1 1 1 S0
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
55
 BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
Err = S3 S2 + S3 S1 S3 S2 S1 S0

Err If the Err bit is 1 a binary

number 0110 (+6) will be
added to the result to
generate the valid BCD code
0 0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0
56
 Binary Subtractor

Design a combinational circuit for x – y

Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0
57
 Binary Adder/Subtractor
How to build a circuit that performs both addition and subtraction?

 M: Control Signal (Mode) x3 x2 x1 x0 y3 y2 y1 y0 M

● M=0  F = x + y
● M=1  F = x – y

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0

58
 Binary Multiplication

 Similar to decimal multiplication

 Multiplying 2 bits will generate a 1 if both bits are equal to 1, and will be 0
otherwise. Resembles an AND operation
 Multiplying two 2-bit numbers is done as follows:

B1 B0
x A1 A0
----------------
This operation is an
A0B1 A0B0 addition, requires an
A1B1 A1B0 + ADDER
----------------------------------
C3 C2 C1 C0

59
 Binary Multiplication

 Therefore, for multiplying two 2-bit numbers, AND gates and

ADDERS will be sufficient

60
 Binary Multiplication
4-bit by 3-bit binary multiplier
 For J multiplier bits and K
multiplicand bits we need
(J x K) AND gates and
(J − 1) K-bit adders to
produce a product of J+K bits.

 K=4 and J=3, we need 12

AND gates and two 4-bit
adders.

Exercise: Produce a 4-bit

by 4-bt binary multiplier.
61
 Magnitude Comparator
 Compare 4-bit number to 4-bit number
● 3 Outputs: < , = , >
The equality of each pair of bits can be expressed logically with an
exclusive-NOR function.
● Expandable to more number of bits
x A B A B
3 3 3 3 3
A3A2A1A0 B3B2B1B0

x2  A2 B2  A2 B2
Magnitude
x1  A1 B1  A1 B1 Comparator
x0  A0 B0  A0 B0
A<B A=B A>B
( A  B)  x3 x2 x1 x0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
62
 Magnitude Comparator

A3
x3

B3

A2
x2
Logic Symbol
B2

A1 (A<B)
x1

B1

A0
x0 (A>B)

B0
(A=B)
63
 Magnitude Comparator

x7 x6 x 5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

64
 Decoders
 Decoding - the conversion of an n-bit input code to an m-bit
output code with n m  2n such that each valid code word
produces a unique output code
 Circuits that perform decoding are called decoders
 Decoders Extract “Information” from the code
 Here, functional blocks for decoding are
● called n-to-m line decoders, where m 2n, and
● generate 2n (or fewer) SOP for the n input variables

A D0 D1
D0 5 A
1-to-2-Line Decoder 0 1 0
1 0 1 A D1 5 A

(a) (b) 65
 Decoder Examples
A D0 D1
 1-to-2-Line Decoder D0 5 A
0 1 0
1 0 1 A D1 5 A

(a) (b)
A0
 2-to-4-Line Decoder
A1 A0 D0 D 1 D 2 D3
A1
0 0 1 0 0 0 D0 5 A1 A0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A1 A0

(a)
D2 5 A1 A0
 Note that the 2-4-line
made up of 2 1-to-2- D3 5 A1 A0
line decoders and 4 AND gates.
(b)
66
 Decoder Examples

 2-to-4 Line Decoder

Decoder y3
I1
Binary

y2
y1
I0 y0  Note that the 2-
4-line made up of
2 1-to-2- line
decoders and 4
I1 I0 Y3 Y2 Y1 Y0 AND gates.

0 0 0 0 0 1
0 1 0 0 1 0 Y3  I1 I 0 Y2  I1 I 0
1 0 0 1 0 0
Y1  I1 I 0 Y0  I1 I 0
1 1 1 0 0 0
67
 Decoder Examples

 Binary Decoder Only one

● Example: 2-bit Binary Number lamp will
turn on

0 1
x1 0
Binary
x0 0 Decoder 0
0

68
 Decoders

 3-to-8 Line Decoder Y7  I 2 I1 I 0

Y6  I 2 I1 I 0
Y7 Y5  I 2 I1 I 0
Y6
Y5 Y4  I 2 I1 I 0
Decoder
Binary

I2 Y4 Y3  I 2 I1 I 0
I1 Y3
I0 Y2 Y2  I 2 I1 I 0
Y1 Y1  I 2 I1 I 0
Y0
Y0  I 2 I1 I 0

I2
I1
I0
69
 Decoders with enable

 Enabling permits an input signal to pass through to an output

 Disabling blocks an input signal from passing through to an
output, replacing it with a fixed value
 The value on the output depends on the enable
● When disabled, EN=0 output will be 0
● When enabled, EN=1 output will be x(input will pass)

X
F
EN
(a)

X
F
EN 70
 Decoders with enable

 “Enable” Control Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y 0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
71
 Decoders with enable

 A decoder with an enable input is referred to as a

decoder/demultiplexer.
 The truth table of demultiplexer is the same with decoder.
A B

D0
Demultiplexer D1
E
D2
D3

72
3-to-8 decoder with enable implement
the 4-to-16 decoder

73
 Exercise

 Draw the logic diagram of a 2-to-4-line decoder using NOR

gates only, include an enable input.

Solution

74
 Implementation of a Full Adder with a
Decoder
 From the table, we obtain the functions for the combinational circuit in sum of
minterms (SOP):
S(x, y, z) = x’y’z + x’yz’+xy’z’+ xyz
C(x, y, z) = x’yz+xy’z + xyz’ + xyz

75
 Encoders

 Encoding - the opposite of decoding - the conversion of an m-bit

input code to a n-bit output code with n m  2n such that each
valid code word produces a unique output code
 Circuits that perform encoding are called encoders
 An encoder has 2n (or fewer) input lines and n output lines which
generate the binary code corresponding to the input values
 Typically, an encoder converts a code containing exactly one bit
that is 1 to a binary code corresponding to the position in which
the 1 appears.
 An encoder is a circuit that changes a set of signals into a code
● Put “Information” into code

76
Encoder / Decoder Pairs

Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0

77
 Encoder Example

 A decimal-to-BCD encoder
● Inputs: 10 bits corresponding to decimal digits 0 through
9, (D0, …, D9)
● Outputs: 4 bits with BCD codes
● Function: If input bit Di is a 1, then the output (A3, A2,
A1, A0) is the BCD code for i,
 The truth table could be formed, but alternatively, the
equations for each of the four outputs can be obtained
directly.

78
 Encoders Example

 Binary Encoder Only one

● Example: 4-to-2 Binary Encoder switch
should be
activated
at a time

x1
x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
1 0 0 1 1

79
 Encoders Example

 Octal-to-Binary Encoder (8-to-3)

I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2  I 7  I 6  I 5  I 4 I4
Y1
I3
Y1  I 7  I 6  I 3  I 2 I2
I1
Y0  I 7  I 5  I 3  I1 I0 Y0
80
 Priority encoder

 If two inputs are active simultaneously or if no input is active,

the output produces an undefined combination.
● We can establish an input priority to ensure that only one input is
encoded.

 One encoder that can accept all possible combinations of input

values and produce a meaningful result is a priority encoder.

81
 Priority encoder

V=0no valid inputs

V=1valid inputs
 X’s in output columns represent
don’t-care conditions
 X’s in the input columns are
useful for representing a truth
table in condensed form.
Instead of listing all 16
Minterms (SOP) of four
variables.

82
 4-input priority encoder

Implementation
0
0
0
0

x = D 2 + D3
y = D3 + D1D’2
V = D 0 + D 1 + D2 + D 3

83
 Exercise

 Specify the truth table of an octal-to-binary priority encoder. Provide

an output V to indicate that at least one of the inputs is present. The
input with the highest subscript number has the highest priority.
 What will be the value of the four outputs if inputs D2 and D6 are 1 at
the same time?

Solution

84
 Multiplexers

 A multiplexer selects information from an input line and

directs the information to an output line

 A typical multiplexer has n control inputs (Sn -1, … S0)

called selection inputs, 2n information inputs (I2n -1, … I0),
and one output Y

 A multiplexer can be designed to have

m information inputs with m < 2n as
well as n selection inputs

85
Multiplexers

S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
86
 2-to-1 Line Multiplexer

 Since 2 = 21, n = 1 selection inputs

 The single selection variable S has two values:
● S = 0 selects input I0
● S = 1 selects input I1

 The equation:
Y = S I0 + SI1 Decoder
Enabling
Circuits
 The circuit:
I0
Y
S
I1

87
 Multiplexers

 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
 4-to-1 MUX I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S1 S0
S1 S0
88
 Cascading Multiplexers

 Large multiplexers implemented by cascading smaller

ones
8:1
I0 mux
I1 4:1 alternative
I2 mux implementation
I3 2:1
mux Z I0 2:1 8:1
I4 I1 mux mux
I5 4:1
I6 mux I2 2:1
I7 I3 mux 4:1 Z
I4 mux
B C A 2:1
I5 mux
control signals B and C simultaneously choose
one of I0, I1, I2, I3 and one of I4, I5, I6, I7 I6 2:1
I7 mux
control signal A chooses which of the
upper or lower mux's output to gate to Z
C A B
89
 Exercise
 Construct a 16 x1 multiplexer with two 8 x1 and one 2 x1
multiplexers. Use block diagrams

Exercise:- Construct a 16 x1 multiplexer with four 4 x1 and 3 2

x1 multiplexers. Use block diagrams and logical diagrams 90
 Multiplexers as General-purpose Logic

 2n:1 multiplexer implements any function of n

variables
● With the variables used as control inputs and
● Data inputs tied to 0 or 1
● In essence, a lookup table
1 0

 Example:
0 1
1 2
0 3
● F(A,B,C) =A'B'C' + A'BC' + ABC' + ABC 0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0

A B C 91
 Multiplexers as General-purpose Logic
(cont’d)

 2n-1:1 mux can implement any function of n variables

● With n-1 variables used as control inputs and
● Data inputs tied to the last variable or its complement
 Example: F(A,B,C) =A'B'C' + A'BC' + ABC' + ABC
=A'B'(C') + A'B(C') + AB(0) + AB(1)
1 0
0 1
1 2 A B C F
C' 0
0 3 0 0 0 1 C' F
F C' 1
0 4 8:1 MUX 0 0 1 0 4:1 MUX
0 1 0 1 0 2
0 5 C' 1 3
1 6 0 1 1 0 S1 S0
1 7 1 0 0 0 0
S2 S1 S0 1 0 1 0
1 1 0 1 A B
1
1 1 1 1
A B C 92
 Example
Implement F(A, B, C, D)=∑m(1, 3, 4, 11, 12, 13, 14, 15) using 8:1 MUX

93
 DeMultiplexers
• A multiplexer selects information from an output line and directs the information

• Receives information on a single line & transmits it to one of 2n possible output

lines.
Y3
Y2
I DeMUX Y
1

S S Y0
1 0

Y3

Y2
S1 S0 Y3 Y2 Y1 Y0
I
Y1
0 0 0 0 0 I
0 1 0 0 I 0
Y0
1 0 0 I 0 0
S1
1 1 I 0 0 0
S0 94
Multiplexer / DeMultiplexer Pairs

MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
95
DeMultiplexers / Decoders

Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX Y I0 Y1
1
E Y0
S S Y0
1 0

E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

96
 Demultiplexers as General-purpose Logic

 n:2n deMUX implements any function of n variables

● With the variables used as control inputs
● Enable inputs tied to 1 and
● Appropriate minterms (products) summed to form the
function
0 A'B'C'
1 A'B'C demultiplexer generates appropriate
2 A'BC'
3 A'BC minterm based on control signals
“1” 3:8 DEC 4 AB'C' (it "decodes" control signals)
5 AB'C
6 ABC'
7 ABC
S2 S1 S0

A B C

97
 Demultiplexers as General-purpose Logic

 Implement the following functions using Demultiplexers

● F1 = A' B C' D + A' B' C D + A B C D
● F2 = A B C' D’ + A B C 0 A'B'C'D'
1 A'B'C'D
● F3 = (A' + B' + C' + D') 2 A'B'CD' F1
3 A'B'CD
4 A'BC'D'
5 A'BC'D
6 A'BCD'
4:16 7 A'BCD
Enable DeMUX 8 AB'C'D' F2
9 AB'C'D
10 AB'CD'
11 AB'CD
12 ABC'D'
13 ABC'D
14 ABCD'
15 ABCD F3

A BC D
98
 Assignment 2

1. Construct a binary full adder using a multiplexer

2. n

3. Construct a 16 X 1 multiplexer by using five 4x 1 multiplexers. Use block diagrams

4. Implement the following Boolean function with a 4 x 1 multiplexer:
F (A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 15)
5. Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary
number. Implement the circuit using exclusive-OR gates.

Submission Deadline: January 25, 2018 99