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    Module Multi4

    Uploaded by

    Aman Kumar
    This document contains code for a 4-input multiplexer module and test bench. The multiplexer module uses a case statement to output one of its four inputs (a, b, c, d) based on the values of the 2-bit input A. The test bench applies different input patterns to A to sequentially output a, b, then c. It also applies sample inputs to the other ports.

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    Module Multi4

    Uploaded by

    Aman Kumar
    11 views2 pages
    This document contains code for a 4-input multiplexer module and test bench. The multiplexer module uses a case statement to output one of its four inputs (a, b, c, d) based on the values of the 2-bit input A. The test bench applies different input patterns to A to sequentially output a, b, then c. It also applies sample inputs to the other ports.

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    This document contains code for a 4-input multiplexer module and test bench. The multiplexer module uses a case statement to output one of its four inputs (a, b, c, d) based on the values of the 2-bit input A. The test bench applies different input patterns to A to sequentially output a, b, then c. It also applies sample inputs to the other ports.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    11 views2 pages

    Module Multi4

    Uploaded by

    Aman Kumar
    This document contains code for a 4-input multiplexer module and test bench. The multiplexer module uses a case statement to output one of its four inputs (a, b, c, d) based on the values of the 2-bit input A. The test bench applies different input patterns to A to sequentially output a, b, then c. It also applies sample inputs to the other ports.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    module multi4(

    input [1:0]A,
    input a,
    input b,
    input c,
    input d,
    output reg O
    );
    always@(a or b or c or d or A)
    begin
    case(A)
    2'b00 : O<=a;
    2'b01 : O<=b;
    2'b10 : O<=c;
    2'b11 : O<=d;
    endcase
    end

    endmodule

    Test Bench
    module multi44;

    // Inputs
    reg [1:0] A;
    reg a;
    reg b;
    reg c;
    reg d;
    // Outputs
    wire O;

    // Instantiate the Unit Under Test (UUT)


    multi4 uut (
    .A(A),
    .a(a),
    .b(b),
    .c(c),
    .d(d),
    .O(O)
    );
    initial begin
    // Initialize Inputs
    A = 0;
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    #5 A = 1;
    #2 b = 1;
    #5 A = 2;
    #2 c = 1;
    #20 $finish;
    end
    endmodule
    Multiplexer Using And Gate
    module multiandgate(
    input A,
    input B,
    input C,
    input D,
    input S1,
    input S2,
    output O
    );
    assign S1n = ~S1;
    assign S2n = ~S2;
    assign y1 = A &(S1n & S2n);
    assign y2 = B &(S1n & S2);
    assign y3 = C &(S1 & S2n);
    assign y4 = D &(S1 & S2);
    assign O = y1 | y2 | y3 | y4;
    endmodule

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