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Verilog Lab File

1. The document describes designing 4-bit loadable up/down counters using Verilog HDL with if-else statements, case conditional modules, and casez conditional modules. Test benches are created to check the functionality. 2. A 4-bit asynchronous ripple carry counter is designed using D flip-flops. A test bench is written to validate the counter. 3. A 4-bit synchronous ripple carry counter is designed using behavioral modeling of T flip-flops. A test bench simulates and verifies the counter design.

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Harshita Anand
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122 views11 pages

Verilog Lab File

1. The document describes designing 4-bit loadable up/down counters using Verilog HDL with if-else statements, case conditional modules, and casez conditional modules. Test benches are created to check the functionality. 2. A 4-bit asynchronous ripple carry counter is designed using D flip-flops. A test bench is written to validate the counter. 3. A 4-bit synchronous ripple carry counter is designed using behavioral modeling of T flip-flops. A test bench simulates and verifies the counter design.

Uploaded by

Harshita Anand
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
Download as pdf or txt
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EL525 – Digital Design using HDL and FPGA

LAB_10
Aim: To perform following tasks in Verilog HDL.
1. (i) Design 4-bit loadable up/down binary counter using
(a) if-else statements
(b) case conditional module
(c) casez conditional module
(ii) Write a test-bench to check functionality of the module in 1(i).
Verilog HDL:
1. If-else statements:

RTL View of the Schematic:


2. Case conditional module:

RTL View of the Schematic:

3. Casez conditional module:


RTL View of the schematic:

Test-Bench:
module tb_counter;
// Inputs
reg [3:0] loaddata;
reg reset;
reg clk;
reg load;
reg updown;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
counter uut (
.loaddata(loaddata),
.reset(reset),
.clk(clk),
.load(load),
.updown(updown),
.count(count)
);
initial begin
// Initialize Inputs
loaddata = 0;
reset = 0;
clk = 0;
load = 0;
updown = 0;
end
always #1 clk=~clk;
initial begin
// Wait 100 ns for global reset to finish
#100;
loaddata=4'b0110;
reset=1'b1;
load=1'b0;
updown=1'b1;
#100;
loaddata=4'b0110;
reset=1'b0;
load=1'b1;
updown=1'b1;
#100;
loaddata=4'b0110;
reset=1'b0;
load=1'b0;
updown=1'b0;
#100;
loaddata=4'b0110;
reset=1'b0;
load=1'b0;
updown=1'b1;
#100;
loaddata=4'b0111;
reset=1'b0;
load=1'b1;
updown=1'b0;
end
endmodule

Simulation Results:
2. (i) Design a 4–bit asynchronous ripple carry counter in Verilog HDL as shown
in Fig. 1.

The T flip-flops in Fig. 1 are to be instantiated and are designed using D flip-flop
as shown in Fig. 2.

(ii) Write test bench to validate the functionality of ripple carry counter
designed in 2(i).
Verilog HDL Code:
TestBench:
module vtf2;
// Inputs
reg tin;
reg reset;
reg clock;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
rcc2 uut (
.q(q),
.tin(tin),
.reset(reset),
.clock(clock)
);
always
begin
#5 clock=~clock;
end
initial begin
// Initialize Inputs
#7 tin = 1;
clock = 0;
reset = 1;
#5 reset=0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule

RTL View of the Schematic:

Simulation Results:
3. (i) Design a 4–bit synchronous ripple carry counter in Verilog HDL as shown
in Fig. 3.

The T flip-flops in Fig. 3 are to be designed using behavioral level modeling as


shown in Fig. 4. t, clock, reset are inputs, q is output of T_ff module.

Verilog HDL Code:


TestBench:

module rcconlinetf;
// Inputs
reg tin;
reg reset;
reg clock;
// Outputs
wire [3:0] q;
wire out;
// Instantiate the Unit Under Test (UUT)
rcconline uut (
.q(q),
.tin(tin),
.out(out),
.reset(reset),
.clock(clock)
);
always
begin
#5 clock=~clock;
end
initial begin
// Initialize Inputs
#7 tin = 1;
clock = 0;
#8 reset = 1;
#5 reset=0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule

Simulation Results:

CONCLUSION:
The equivalence of the counter output waveforms imply similar operation
although, asynchronous design employed here, is supposedly slower than the
synchronous design implemented here.
Also, casex and casez cover more boundary cases than case, thus, increasing
the ease of creating the cases in more concise manner.

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