Questa Sim User PDF
Questa Sim User PDF
Questa Sim User PDF
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Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operational Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Simulation Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Basic Steps for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Files and Map Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
What is a Library? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mapping the Logical Work to the Physical Work Directory . . . . . . . . . . . . . . . . . . . . . 65
Step 1 — Create Work and Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Step 2 — Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Step 3 — Optimize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Step 4— Load the Design for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Step 5 — Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Step 6 — Debug the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
General Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Startup Variable Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Here-Document Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O Redirection Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Basic Command Line Editing and Navigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Supported Commands for Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Saving Batch Mode Simulation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Output Redirection With vsim -batch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Capturing Raw stdout in C/C++ Batch Mode Simulation . . . . . . . . . . . . . . . . . . . . . . . . 78
Simulator Control Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Default stdout Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Tool Statistics Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Controlling the Display of Statistics Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Definition of an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Graphic Interface Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Installation Directory Pathnames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Where to Find Questa SIM Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Deprecated Features, Commands, and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 2
Protecting Your Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Encryption Envelopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Creating Encryption Envelopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Protection Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
The `include Compiler Directive (Verilog only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Compiling with +protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The Runtime Encryption Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Language-Specific Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Usage Models for Protecting Verilog Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Delivering IP Code with Undefined Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Delivering IP Code with User-Defined Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Usage Models for Protecting VHDL Source Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Using the vhencrypt Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Proprietary Source Code Encryption Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Using Proprietary Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Protecting Source Code Using -nodebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Encryption Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Encryption and Encoding Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
How Encryption Envelopes Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Using Public Encryption Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Using the Mentor Graphics Public Encryption Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 3
Optimizing Designs with vopt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Optimization Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Three-Step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Two-Step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Using vopt and the -O Optimization Control Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . 131
Inlining and the Implications of Coverage Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Preserving Object Visibility for Debugging Purposes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Conflicts in Accessibility When Using Both +acc and +noacc . . . . . . . . . . . . . . . . . . . . . 134
Negation Arguments and Resolution with vopt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Priorities for Resolving Conflicting Control Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Using an External File to Control Visibility Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Creating Specialized Designs for Parameters and Generics . . . . . . . . . . . . . . . . . . . . . . . . 136
Increase Visibility to Retain Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Optimization of Parameters and Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Preoptimizing Regions of Your Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Simulating Designs with Multiple Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Extracting Visibility Requirements for PDUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Using Configurations with Preoptimized Verilog Design Units . . . . . . . . . . . . . . . . . . . . 142
Using Configurations with Preoptimized VHDL Design Units . . . . . . . . . . . . . . . . . . . . . 143
Resolving Preoptimized Design Unit Loading Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Alternate Optimization Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Creating Locked Libraries for Multiple-User Simulation Environments . . . . . . . . . . . . . . 147
Optimizing Liberty Cell Libraries for Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Preserving Design Visibility with the Learn Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Chapter 4
Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
What are Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
What are the Benefits of Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Project Conversion Between Simulator Versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Getting Started with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Open a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Add Source Files to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Compile the Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Change Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Auto-Generate the Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Grouping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Simulate a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
The Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Creating a Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Organizing Projects with Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Adding a Project Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Set File Properties and Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
File Compilation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Convert Pathnames to Softnames for Location Mapping. . . . . . . . . . . . . . . . . . . . . . . . . 176
Setting Custom Double-click Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Access Projects from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 5
Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Design Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Design Unit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Working Library Versus Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Working with Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Creating a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Library Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Library Window Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Map a Logical Name to a Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Mapping a Library with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Mapping a Library from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Modify the modelsim.ini Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Move a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Setting Up Libraries for Group Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Chapter 6
VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Basic VHDL Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Compilation and Simulation of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Creating a Design Library for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Compilation of a VHDL Design—the vcom Command . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Simulation of a VHDL Design—the vsim Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Usage Characteristics and Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Differences Between Supported Versions of the VHDL Standard. . . . . . . . . . . . . . . . . . . 205
Naming Behavior of VHDL for Generate Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Foreign Language Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Simulator Resolution Limit for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Default Binding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Delta Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
The TextIO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Syntax for File Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
STD_INPUT and STD_OUTPUT Within Questa SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
TextIO Implementation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Alternative Input/Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
The TEXTIO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Input Stimulus to a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
VITAL Usage and Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
VITAL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
VITAL 1995 and 2000 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
VITAL Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Compiling and Simulating with Accelerated VITAL Packages . . . . . . . . . . . . . . . . . . . . . 222
Compiler Options for VITAL Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
VHDL Utilities Package (util) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Modeling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Examples of Different Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Effects on Performance by Canceling Scheduled Events . . . . . . . . . . . . . . . . . . . . . . . . . . 236
VHDL Access Object Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Terminology and Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
VHDL Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Default Behavior—Logging and Debugging Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Logging and Debugging Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Chapter 7
Verilog and SystemVerilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Supported Variations in Source Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
for Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Naming Macros with Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Basic Verilog Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Verilog Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Creating a Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Invoking the Verilog Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Verilog Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Parsing SystemVerilog Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Recognizing SystemVerilog Files by File Name Extension . . . . . . . . . . . . . . . . . . . . . . 252
Initializing enum Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Library Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SystemVerilog Multi-File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Declarations in Compilation Unit Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Macro Definitions and Compiler Directives in Compilation Unit Scope . . . . . . . . . . . . 257
Verilog-XL Compatible Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Arguments Supporting Source Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Verilog-XL uselib Compiler Directive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Verilog Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Configurations and the Library Named work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Verilog Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Name Visibility in Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Initializing Registers and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Initialization Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Initializing with Specific Values — Enabled During Compilation . . . . . . . . . . . . . . . . . 267
Initializing with Specific Values — Enabled During Optimization. . . . . . . . . . . . . . . . . 267
Initializing with Random Values — Enabled During Compilation . . . . . . . . . . . . . . . . . 268
Initializing with Random Values — Enabled During Optimization . . . . . . . . . . . . . . . . 268
Recording Initialization Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Verilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Simulator Resolution Limit (Verilog). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Modules Without Timescale Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Multiple Timescale Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Choosing the Resolution for Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Event Ordering in Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Event Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Controlling Event Queues with Blocking or Non-Blocking Assignments. . . . . . . . . . . . 276
Debugging Event Order Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Hazard Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Hazard Detection and Optimization Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Signal Segmentation Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Negative Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Chapter 8
SystemC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Supported Platforms and Compiler Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Building gcc with Custom Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Usage Flow for SystemC-Only Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Recommendations for using sc_main at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Simulating with sc_main at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Creating Shared Object Files for SystemC Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Binding to Verilog or SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Limitations of Bind Support for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Distributing SystemC IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Compiling SystemC Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Creating a Design Library for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Exporting All Top-Level SystemC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Invoking the SystemC Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Distributed sccom Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Compiling Optimized and/or Debug Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Specifying an Alternate g++ Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Verifying Compiler Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Maintaining Portability Between OSCI and the Simulator . . . . . . . . . . . . . . . . . . . . . . . . 424
Using sccom in Addition to the Raw C++ Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Rules for sccom Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Rules for Using Raw g++ to Compile Non-SystemC C/C++ Code . . . . . . . . . . . . . . . . . 426
Chapter 9
Mixed-Language Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Basic Mixed-Language Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Different Compilers with Common Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Case Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Hierarchical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Access Limitations in Mixed-Language Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
The SystemVerilog bind Construct in Mixed-Language Designs . . . . . . . . . . . . . . . . . . . . . 486
Syntax of bind Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Allowed Bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Hierarchical References to a VHDL Object from a Verilog/SystemVerilog Scope. . . . . . 488
Mapping of Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Optimization with SystemVerilog Bind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Port Mapping with VHDL and Verilog Enumerated Types . . . . . . . . . . . . . . . . . . . . . . . . 490
VHDL Instance Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Limitations to Bind Support for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Optimizing Mixed Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Simulator Resolution Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Runtime Modeling Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Hierarchical References to SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Hierarchical References In Mixed HDL and SystemC Designs. . . . . . . . . . . . . . . . . . . . . 499
Signal Connections Between Mixed HDL and SystemC Designs . . . . . . . . . . . . . . . . . . . 500
Mapping Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Verilog and SystemVerilog to VHDL Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
VHDL To Verilog and SystemVerilog Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Verilog or SystemVerilog and SystemC Signal Interaction And Mappings . . . . . . . . . . . 514
VHDL and SystemC Signal Interaction and Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
VHDL Instantiating Verilog or SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Verilog/SystemVerilog Instantiation Criteria Within VHDL. . . . . . . . . . . . . . . . . . . . . . . 530
Component Declaration for VHDL Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . 530
vgencomp Component Declaration when VHDL Instantiates Verilog . . . . . . . . . . . . . . . 531
Modules with Bidirectional Pass Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Modules with Unnamed Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Verilog or SystemVerilog Instantiating VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
VHDL Instantiation Criteria Within Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Entity and Architecture Names and Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Named Port Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Generic Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Sharing User-Defined Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Using a Common VHDL Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Using a Common SystemVerilog Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
SystemC Instantiating Verilog or SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Verilog Instantiation Criteria Within SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
SystemC Foreign Module (Verilog) Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Chapter 10
Advanced Simulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Checkpointing and Restoring Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Checkpoint File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Checkpoint Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Controlling Checkpoint File Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
The Difference Between Checkpoint/Restore and Restart . . . . . . . . . . . . . . . . . . . . . . . . . 583
Using Macros with Restart and Checkpoint/Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Checkpointing Foreign C Code That Works with Heap Memory . . . . . . . . . . . . . . . . . . . 584
Checkpointing a Running Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Simulating with an Elaboration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Why an Elaboration File? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Creating an Elaboration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Loading an Elaboration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Modifying Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Using PLI or FLI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
X Propagation in Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
RTL X-Optimism Removal by xprop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Controlling the X Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
X Propagation Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
X Propagation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Limitations and Restrictions on xprop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Chapter 11
Recording and Viewing Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Transaction Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
What is a Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About the Source Code for Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About Transaction Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Viewing Transactions in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Transaction Viewing Commonalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Viewing Transaction Objects in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Viewing Transactions in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Retroactive Recording and Transaction Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Selecting Transactions or Streams in the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . 613
Customizing Transaction Appearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Customizing Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Customizing Appearance of Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Viewing a Transaction in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Viewing a Transaction in the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Debugging Transactions with Tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transactions in Designs with Questa Verification IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transaction Recording Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transaction Recording Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Names of Streams and Substreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Stream Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Transaction UIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Attribute Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Multiple Uses of the Same Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Anonymous Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Definition of Relationship in Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
The Life-cycle of a Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Transaction Handles and Memory Leaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Transaction Recording Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Recording Transactions in Verilog and VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Verilog Recorded Transaction Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Valid Verilog Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Recording Transactions in SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Initializing SCV and Creating WLF Database Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Creating Transaction Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Writing SCV Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
SCV API Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
SCV Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
CLI Debugging Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Verilog and VHDL API System Task Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
add_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
add_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
add_relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
begin_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
create_transaction_stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
delete_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
end_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
free_transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Chapter 12
Verifying Designs with
Questa Verification IP Library Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
What is Questa Verification IP? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
What is a Questa Verification IP Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Questa Verification IP Transaction Viewing in the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Questa Verification IP Objects in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Arrays in Questa Verification IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Viewing Questa Verification IP Transactions in the Wave Window . . . . . . . . . . . . . . . . . 665
What the Colors Mean in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Appearance of Concurrent Transactions in the Wave Window . . . . . . . . . . . . . . . . . . . . . 668
Questa Verification IP Arrays in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Color and Questa Verification IP Arrays in Wave Window. . . . . . . . . . . . . . . . . . . . . . . . 670
Viewing Questa Verification IP Transactions in Objects Window . . . . . . . . . . . . . . . . . . 671
Viewing Questa Verification IP Transactions in List Window . . . . . . . . . . . . . . . . . . . . . 672
Questa Verification IP Transaction Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Debugging Using Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Questa Verification IP Transaction Details in Transaction View Window . . . . . . . . . . . . 678
The Transaction View Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
The Transaction Stream Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Updating Contents of the Transaction Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Chapter 13
Recording Simulation Results With Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Saving a Simulation to a WLF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Saving at Intervals with Dataset Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Saving Memories to the WLF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
WLF File Parameter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Limiting the WLF File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Opening Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Dataset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Structure Window Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Managing Multiple Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Managing Multiple Datasets in the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Managing Multiple Datasets from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Restricting the Dataset Prefix Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Collapsing Time and Delta Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Virtual Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Virtual Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Virtual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Virtual Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Virtual Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Chapter 14
Waveform Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Wave Window Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Objects You Can View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Adding Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Inserting Signals in a Specific Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Adding Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Editing Cursor Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Jump to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Syncing All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Linking Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Shortcuts for Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Two Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Enable Two Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Additional Mouse Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Expanded Time in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Expanded Time Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Recording Expanded Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Viewing Expanded Time Information in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . 720
Customizing the Expanded Time Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . 723
Expanded Time Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Menu Selections for Expanded Time Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Toolbar Selections for Expanded Time Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Command Selection of Expanded Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Switching Between Time Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Expanding and Collapsing Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Expanded Time with examine and Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Zooming the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Zooming with the Menu, Toolbar and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Saving Zoom Range and Scroll Position with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . . 729
Editing Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Searching in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Searching for Values or Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Search with the Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Using the Expression Builder for Expression Searches . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Saving an Expression to a Tcl Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Searching for a Particular Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Evaluating Only on Clock Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Filtering the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Formatting the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Setting Wave Window Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Hiding/Showing Path Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Double-Click Behavior in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Setting the Timeline to Count Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Formatting Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Chapter 15
Schematic Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Schematic Window Usage Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Live Simulation Schematic Debug Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Post Simulation Schematic Debug Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Two Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Features of the Incremental View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Common Tasks for Schematic Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Adding Objects to the Incremental View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Display a Structural Overview in the Full View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Exploring the Schematic Connectivity of the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Investigating Connectivity Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Limiting the Schematic Display of Readers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Controlling the Schematic Display of Redundant Buffers and Inverters . . . . . . . . . . . . . 813
Tracking Your Path Through the Design with Highlighting . . . . . . . . . . . . . . . . . . . . . . 814
Folding and Unfolding Instances in the Incremental View . . . . . . . . . . . . . . . . . . . . . . . . 815
Using Abstract Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Exploring Designs with the Embedded Wave Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Tracing Events in the Incremental View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Tracing the Schematic Source of an Unknown State (StX) . . . . . . . . . . . . . . . . . . . . . . . . 825
Finding Objects by Name in the Schematic Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Saving and Restoring the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Annotating with Sticky Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Chapter 16
Debugging with the Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Dataflow Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Dataflow Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Live Simulation Debug Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Post-Simulation Debug Flow Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Create the Post-Sim Debug Database. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Use the Post-Simulation Debug Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Common Tasks for Dataflow Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Add Objects to the Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Exploring the Connectivity of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Analyzing a Scalar Connected to a Wide Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Control the Display of Readers and Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
Controlling the Display of Redundant Buffers and Inverters. . . . . . . . . . . . . . . . . . . . . . 854
Track Your Path Through the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
Explore Designs with the Embedded Wave Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
Tracing Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Tracing the Source of an Unknown State (StX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
Finding Objects by Name in the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
Automatically Tracing All Paths Between Two Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Dataflow Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Symbol Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
User-Defined Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Current vs. Post-Simulation Command Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Dataflow Window Graphic Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
What Can I View in the Dataflow Window? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
How is the Dataflow Window Linked to Other Windows? . . . . . . . . . . . . . . . . . . . . . . . . 867
How Can I Print and Save the Display? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
Save a .eps File and Printing the Dataflow Display from UNIX . . . . . . . . . . . . . . . . . . . 869
Print from the Dataflow Display on Windows Platforms . . . . . . . . . . . . . . . . . . . . . . . . 869
Configure Page Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
How Do I Configure Window Options? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Chapter 17
Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
Opening Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Changing File Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Chapter 18
Using Causality Traceback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Creating a Database for Causality Traceback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Initiating Causality Traceback from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Using the find drivers Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Command Line Options for Setting Report Destination . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Command Line Options for Text Report Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Post-sim Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Initiating Causality Traceback from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Trace to the First Sequential Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Initiating the Trace from the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Initiating the Trace from the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Initiating the Trace from the Objects or Schematics Windows . . . . . . . . . . . . . . . . . . . . 914
Tracing to the Immediate Driving Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Tracing to the Root Cause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Chapter 19
Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Overview of Code Coverage Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Language and Datatype Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Usage Flow for Code Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Specifying Coverage Types for Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Union of Coverage Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Rules for Applying Coverage with cover and nocover. . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Enabling Simulation for Code Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Saving Code Coverage in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Saving Coverage Using the UVM Test Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Coverage Auto-save Coverstore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Code Coverage in the UCDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Code Coverage in the Graphic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Understanding Unexpected Coverage Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Code Coverage Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Statement Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Branch Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Branch Coverage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Case and Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
AllFalse Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Missing Branches in VHDL and Clock Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Condition and Expression Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Cond and Exp Coverage Collection Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Reporting Condition and Expression Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
FEC Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
FEC Report Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
FEC and Short-circuiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Exclusions and FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Legacy FEC Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
UDP Coverage Details and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
VHDL Condition and Expression Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Verilog/SV Condition and Expression Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Toggle Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Toggle Coverage and Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
VHDL Toggle Coverage Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Verilog/SV Toggle Coverage Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Toggle Ports Only Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Viewing Toggle Coverage Data in the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . 972
Understanding Toggle Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Specifying Toggle Coverage Statistics Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Chapter 20
Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
FSM Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
FSM Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
FSM Multi-State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Collecting FSM Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Reporting Coverage Metrics for FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Viewing FSM Information in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
FSM Coverage Metrics Available in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Advanced Command Arguments for FSMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Recognized FSM Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
FSM Recognition Info Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
FSM Coverage Text Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Chapter 21
Verification with Assertions and Cover Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Overview of Assertions and Cover Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Assertion Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Using Assert Directive Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
SystemVerilog Bind Construct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Processing Assume Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Configuring Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Enabling Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Enabling Memory and Performance Profiling Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Configuring Message Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Setting Break Severity for Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Enabling/Disabling Assertion Failure and Pass Logging. . . . . . . . . . . . . . . . . . . . . . . . . 1062
Setting Assertion Failure Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Setting Assertion Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Changing the Default Configuration of Cover Directives . . . . . . . . . . . . . . . . . . . . . . . . 1065
Other Configuration Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Simulating Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Maintaining Assertion Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Analyzing Assertions and Cover Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Viewing Assertions in the Assertions Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Viewing Cover Directives in the Cover Directives Window . . . . . . . . . . . . . . . . . . . . . . 1075
Viewing Memory Profile Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Viewing Assertions and Cover Directives in the Wave Window . . . . . . . . . . . . . . . . . . 1077
Utilizing GUI Display Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Comparing Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Saving Metrics to the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Excluding Assertions and Cover Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Creating Assertion Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Chapter 22
Verification with Functional Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
Functional Coverage Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Functional Coverage Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Guidelines for Functional Coverage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Controlling Functional Coverage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Chapter 23
Verification with Constrained
Random Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Verification Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Building Constrained Random Test Benches on SystemVerilog Classes . . . . . . . . . . . . . . . 1173
Generating New Random Values with randomize(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Attributes Of Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Syntax and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Size Constraints for Random Dynamic Arrays with randomize() . . . . . . . . . . . . . . . . . . 1176
Debugging randomize() Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Chapter 24
Coverage and Verification Management in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Coverage and Verification Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
A Flow for Verification of Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
What is the Unified Coverage Database? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Calculation of Total Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Where to Find Coverage Totals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Coverage Binning and Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Coverage Aggregation in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Coverage Calculation in the Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Coverage Calculation in the Tracker Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Coverage and Simulator Use Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Coverage View Mode and the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Running Tests and Collecting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Collecting and Saving Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Name Selection for Test UCDB Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Saving Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Rerunning Tests and Executing Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Understanding Stored Test Data in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Test Attribute Records in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Predefined Attribute Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Managing Test Data in UCDBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
Merging Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
Higher Performance Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
Merging with the vcover merge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
Matching the Paths of Corresponding Coverage Items . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
Merging Using a Master UCDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Parallel Merge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Requirements for Parallel Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
The Parallel Merge Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Options Used for Building the Merge List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Distribution of Files into Parallel Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Warnings During Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Information Not Perfectly Preserved During Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Multiple Test Data Records with Same Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Merging and Source Code Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
Modifying UCDBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
About the Merge Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
Chapter 25
C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Supported Platforms and gdb Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Setting Up C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Running C Debug from a DO File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
Stepping in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
Quitting C Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Finding Function Entry Points with Auto Find bp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Identifying All Registered Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Enabling Auto Step Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Auto Find bp Versus Auto Step Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Chapter 26
Profiling Performance and Memory Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
Introducing Performance and Memory Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
Profile Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
Getting Started with the Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
Enabling the Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
Handling Large Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
Enabling the Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Collecting Memory Allocation and Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Turning Profiling Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Running the Profiler on Windows with FLI/PLI/VPI Code . . . . . . . . . . . . . . . . . . . . . . . . 1279
Interpreting Profiler Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Viewing Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
Ranked Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
Design Units Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Calltree Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Structural Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Viewing Profile Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
Integration with Source Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Analyzing C Code Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Searching Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Reporting Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Enabling or Disabling Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
Levels of Capacity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Coarse-grain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Fine-grain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Enabling Fine-Grain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Opening the Capacity Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Displaying Capacity Data in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
Writing a Text-Based Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
Reporting Capacity Analysis Data From a UCDB File . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Examining Memory Usage for Assertions and Cover Directives. . . . . . . . . . . . . . . . . . . . 1300
Chapter 27
Signal Spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Signal Spy Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
Chapter 28
Monitoring Simulations with JobSpy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
Basic JobSpy Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
Set JOBSPY_DAEMON Environment Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
Start the JobSpy Daemon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
Set the JOBSPY_DAEMON Variable as a Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
Running JobSpy from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
Simulation Commands Available to JobSpy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
Running the JobSpy GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Starting Job Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Invoking Simulation Commands in Job Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Interactive Job Session Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
View Commands and Pathnames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
Viewing Results During Active Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
Viewing Waveforms from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
Licensing and Job Suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
Checkpointing Jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
Connecting to Load-Sharing Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335
Checkpointing with Load-Sharing Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Configuring LSF for Checkpointing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Configuring Flowtracer for Checkpointing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Configuring Grid Engine for Checkpointing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
Chapter 29
Generating Stimulus with Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
Getting Started with the Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
Using Waveform Editor Prior to Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
Using Waveform Editor After Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
Accessing the Create Pattern Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
Creating Waveforms with Wave Create Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
Editing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
Selection and Zoom Percentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
Auto Snapping of the Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Stretching and Moving Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Simulating Directly from Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Exporting Waveforms to a Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
Driving Simulation with the Saved Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
Chapter 30
Standard Delay Format (SDF) Timing Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
Specifying SDF Files for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Instance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
SDF Specification with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Compiling SDF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
Simulating with Compiled SDF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
VHDL VITAL SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
SDF to VHDL Generic Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Resolving Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Verilog SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
$sdf_annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
SDF to Verilog Construct Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
Retain Delay Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Optional Edge Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Optional Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Rounded Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Interconnect Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Specifying the Wrong Instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Matching a Single Timing Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Mistaking a Component or Module Name for an Instance Label. . . . . . . . . . . . . . . . . . . . 1374
Forgetting to Specify the Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Reporting Unannotated Specify Path Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Chapter 31
Value Change Dump (VCD) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
Creating a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Four-State VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Extended VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
VCD Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Checkpoint/Restore and Writing VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Using Extended VCD as Stimulus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Simulating with Input Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Replacing Instances with Output Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . 1384
Port Order Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
VCD Commands and VCD Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Using VCD Commands with SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
Compressing Files with VCD Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
VCD File from Source to Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
VHDL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
Chapter 32
Tcl and DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
Tcl Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Tcl Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
If Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
set Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Command Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Command Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Multiple-Line Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Evaluation Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Tcl Relational Expression Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Variable Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Questa SIM Replacements for Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Simulator State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Referencing Simulator State Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Special Considerations for the now Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Reading Variable Values From the INI File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
List Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Simulator Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
Simulator Tcl Time Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Time Conversion Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Time Relations Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Tcl Time Arithmetic Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
Creating DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
Using Parameters with DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Deleting a File from a .do Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Making Script Parameters Optional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Breakpoint Flow Control in Nested DO files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Useful Commands for Handling Breakpoints and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Error Action in DO File Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
Using the Tcl Source Command with DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
The Tcl Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
The Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
The Chooser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
Tcl Debugger Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
TclPro Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
Appendix A
modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
Organization of the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
Making Changes to the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
Editing modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
Overriding the Default Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
The Runtime Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
AcceptLowerCasePragmaOnly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
AccessObjDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
AddPragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
AmsStandard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
AppendClose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
AssertFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
AssertionActiveThreadMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
AssertionActiveThreadMonitorLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
AssertionCover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
AssertionDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
AssertionEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
AssertionEnableVacuousPassActionBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
AssertionFailAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
AssertionFailLocalVarLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
AssertionFailLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
AssertionLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
AssertionPassLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
AssertionThreadLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
AssertionThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
ATVStartTimeKeepCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
AutoExclusionsDisable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
AutoLibMapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
BatchMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
BatchTranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
BindAtCompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
BreakOnAssertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
CheckPlusargs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
CheckpointCompressMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
CheckSynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
ClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
CodeCoverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
CodeLinkAutoLoad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
CommandHistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
CompilerTempDir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
ConcurrentFileLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
CoverAtLeast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
CoverCells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
CoverClkOptBuiltins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
CoverConstruct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
CoverCountAll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
CoverDeglitchOn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
CoverDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
CoverEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
CoverExcludeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
CoverFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
CoverLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
CoverLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
CoverMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
CoverOpt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
CoverREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
CoverRespectHandL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
CoverReportCancelled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
CoverShortCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
CoverSub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
CoverThreadLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
CoverThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
CoverUDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
CoverWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
CppInstall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
CppOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
CppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
CreateDirForFileAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
CreateLib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
CvgZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
DatasetSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
DefaultForceKind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
DefaultLibType. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
DefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
DefaultRadixFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
DefaultRestartOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
DelayFileOpen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527
displaymsgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
DpiCppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
DpiOutOfTheBlue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
DumpportsCollapse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
EmbeddedPsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
EnableDpiSosCb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
EnableSVCoverpointExprVariable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
EnableTypeOf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
EnumBaseInit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
ErrorFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
Explicit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
ExtendedToggleMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
fatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
FecCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
FecUdpEffort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
FlatLibPageSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
FlatLibPageDeletePercentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
FlatLibPageDeleteThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
floatfixlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
ForceSigNextIter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
ForceUnsignedIntegerToVHDLInteger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
FsmImplicitTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
FsmResetTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
FsmSingle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
FsmXAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
GCThreshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
GCThresholdClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
GenerateFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
GenerateLoopIterationMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
GenerateRecursionDepthMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
GenerousIdentifierParsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
GlobalSharedObjectList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
GlobalSharedObjectsList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Hazard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
ieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
IgnoreError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
IgnoreFailure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
IgnoreNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
IgnorePragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
ignoreStandardRealVector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568
IgnoreSVAError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
IgnoreSVAFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
IgnoreSVAInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
IgnoreSVAWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
IgnoreVitalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573
IgnoreWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
ImmediateContinuousAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
IncludeRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
InitOutCompositeParam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
IterationLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
LargeObjectSilent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
LargeObjectSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
LibrarySearchPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
MaxReportRhsCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583
MaxReportRhsSVCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
MaxSVCoverpointBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
MaxSVCoverpointBinsInst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
MaxSVCrossBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
MaxSVCrossBinsInst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
MessageFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
MessageFormatBreak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
MessageFormatBreakLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
MessageFormatError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
MessageFormatFail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
MessageFormatFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
MessageFormatNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
MessageFormatWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
MixedAnsiPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
modelsim_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
MsgLimitCount. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
msgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
mtiAvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
mtiOvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
mtiPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
mtiUPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
mtiUvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
MultiFileCompilationUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
MvcHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
NoCaseStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
NoDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
NoDeferSubpgmCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
NoIndexCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
NoOthersStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
NoRangeCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
NoVital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
NoVitalCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
NumericStdNoWarnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
OldVHDLConfigurationVisibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
OldVhdlForGenNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
OnFinish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
OnFinishPendingAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Optimize_1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
osvvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
ParallelJobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
PathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
PedanticErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
PliCompatDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
PreserveCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
PrintSimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
PrintSVPackageLoadingAttribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
PslOneAttempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
PslInfinityThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
RequireConfigForAllDefaultBinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
RunLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Sc22Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
ScalarOpts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
SccomLogfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
SccomVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
ScEnableScSignalWriteCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
ScMainFinishOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
ScMainStackSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
ScStackSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
ScShowIeeeDeprecationWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
ScTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
ScvPhaseRelationName . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
SeparateConfigLibrary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Show_BadOptionWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Show_Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Show_PslChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Show_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Show_VitalChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Show_Warning1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Show_Warning2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Show_Warning3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
Show_Warning4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Show_Warning5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
ShowConstantImmediateAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
ShowFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
ShowUnassociatedScNameWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
ShowUndebuggableScTypeWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
ShutdownFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
SignalForceFunctionUseDefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
SignalSpyPathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
SimulateAssumeDirectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
SimulateImmedAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
SimulatePSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
SimulateSVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
SmartDbgSym. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
SolveACTMaxOps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
SolveACTMaxTests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
SolveACTRetryCount. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
SolveArrayResizeMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
SolveBeforeErrorSeverity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
SolveEngine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
SolveFailDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
SolveFailDebugMaxSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
SolveFailSeverity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
SolveGraphMaxEval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
SolveGraphMaxSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
SolveIgnoreOverflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683
SolveRev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
SolveTimeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
SparseMemThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
StackTraceDepth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
Stats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689
std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
std_developerskit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
StdArithNoWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
suppress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694
SuppressFileTypeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
Sv_Seed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
sv_std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
SVAPrintOnlyUserMessage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
SVCovergroupGetInstCoverageDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
SVCovergroupGoal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
SVCovergroupGoalDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
SVCovergroupMergeInstancesDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
SVCovergroupPerInstanceDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
SVCovergroupSampleInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
SVCovergroupStrobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
SVCovergroupStrobeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
SVCovergroupTypeGoal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
SVCovergroupTypeGoalDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
SVCovergroupZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
SVCoverpointAutoBinMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
SVCoverpointExprVariablePrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
SVCoverpointWildCardBinValueSizeWarn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
SVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
SVCrossNumPrintMissingDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
SvExtensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
SVFileSuffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Svlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
SVPrettyPrintFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
SvRandExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
SyncCompilerFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
ToggleCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
ToggleDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
ToggleFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
ToggleMaxFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
ToggleMaxIntValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
ToggleMaxRealValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
ToggleNoIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
TogglePackedAsVec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
TogglePortsOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
ToggleVHDLRecords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
ToggleVlogEnumBits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
ToggleVlogIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
ToggleVlogReal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
ToggleWidthLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
TranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
UCDBFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
UCDBTestStatusMessageFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
UdpCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
UnattemptedImmediateAssertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
UnbufferedOutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
UndefSyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
UpCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
UserTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
UseScv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
UseSVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
UseUvmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
UVMControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
Veriuser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
VHDL93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
VhdlSeparatePduPackage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
VhdlVariableLogging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
vital2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
vlog95compat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
VoptFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
WarnConstantChange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
WaveSignalNameWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
WildcardFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
WildcardSizeThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
WildcardSizeThresholdVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
WLFCacheSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
WLFCollapseMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
WLFCompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
WLFDeleteOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
WLFFileLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
WLFFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
WLFOptimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
WLFSaveAllRegions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773
WLFSimCacheSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
WLFSizeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775
WLFTimeLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
WLFUpdateInterval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
WLFUseThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
WrapColumn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
WrapMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
WrapWSColumn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
XpropAssertionLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
Commonly Used modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Common Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Hierarchical Library Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
Creating a Transcript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
Using a Startup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Turn Off Assertion Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Turn Off Warnings from Arithmetic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Force Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
Appendix B
Location Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Referencing Source Files with Location Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
Using Location Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
Pathname Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
How Location Mapping Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Appendix C
Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793
Message System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
Getting More Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Message Severity Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Syntax Error Debug Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Suppression of Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800
Error Messages from the sccom Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Enforcing Strict 1076 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Appendix D
Questa Verification IP Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
Accessing 60000 Series Error Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
Why Series 50000 Errors Occur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812
Concepts Involved in the Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
Transaction Types and Time Queue ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
Parents and Children . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Generation and Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Communication Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Deleted Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
TLM and WLM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Understanding the ‘Time Queue’ ID Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
Viewing the Time Queue ID Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
The Time Queue ID Number Reported in Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
TQ Id Related Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820
Understanding ‘Parents’ and ‘Children’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
Parent/Child Relationship Related Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
Understanding Generation and Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
Generation/Recognition Related Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
Understanding Deletions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Deletion Related Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Understanding Communication Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Activated Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Uni-directional Transmission of Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832
Appendix E
Verilog Interfaces to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
GCC Compiler Support for use with C Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Registering PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
Registering VPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1849
Registering DPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
DPI Use Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
DPI and the vlog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
Deprecated Legacy DPI Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
When Your DPI Export Function is Not Getting Called . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
Troubleshooting a Missing DPI Import Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
Simplified Import of Library Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
Optimizing DPI Import Call Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
DPI Arguments of Parameterized Datatypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
Making Verilog Function Calls from non-DPI C Models . . . . . . . . . . . . . . . . . . . . . . . . . 1858
Calling C/C++ Functions Defined in PLI Shared Objects from DPI Code . . . . . . . . . . . . 1858
PLI Catalog Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
PLI Catalog (PCAT) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
PCAT File for Controlling Access Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
PCAT File with PLI Autocompile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
PLI Catalog File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
PLI Catalog Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Using a PCAT File for Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Using a PCAT File with PLI Autocompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
Compiling and Linking C Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
For all UNIX Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
Windows Platforms — C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871
Linux Platforms — C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872
Compiling and Linking C++ Applications for Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
For PLI/VPI only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
Windows Platforms — C++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
Appendix F
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Files Accessed During Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
Expansion of Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
Creating Environment Variables in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Library Mapping with Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Referencing Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Removal of Temporary Files (VSOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
Appendix G
Third-Party Model Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Synopsys SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
VHDL SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Enabling the VHDL SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Creating Foreign Architectures with sm_entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
sm_entity Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
SmartModel Vector Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
Command Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
SmartModel Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
Memory Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Verilog SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Documentation for Questa SIM is intended for users of Linux and Microsoft Windows. For
more complete information on current support for Questa SIM, refer to the Installation and
Licensing Guide.
Not all versions of Questa SIM are supported on all platforms.
What is a Library?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Resource Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mapping the Logical Work to the Physical Work Directory. . . . . . . . . . . . . . . . . . . . . . 65
What is a Library?
A library is a location on your file system where Questa SIM stores data to be used for
simulation. Questa SIM uses one or more libraries to manage the creation of data before the data
is needed for simulation. A library also helps to streamline simulation invocation.
You can use libraries in the following ways.
• As a local working library that contains the compiled version of your design
• As a resource library
Resource Libraries
A resource library is typically unchanging, and serves as a parts source for your design. You can
create your own resource libraries, or they may be supplied by another design team or a third
party (for example, a silicon vendor).
Examples of resource libraries:
to a single Verilog module, Questa SIM recompiles only that module, rather than all modules in
the design.
Related Topics
Working Library Versus Resource Libraries
Library Window Contents
Working with Design Libraries
Verilog Resource Libraries
VHDL Resource Libraries
Creating a Library
Use braces ({}) for cases where the path contains multiple items that need to be escaped, such as
spaces in the pathname or backslash characters. For example:
Prerequisites
• Know the paths to the directories that contain your design files and resource libraries.
• Start Questa SIM
Procedure
1. Select File > Change Directory to open the Browse For Folder dialog box.
2. Navigate to the directory where your source files are located.
3. Create the Logical Work Library with the vlib command in one of the following ways:
• Enter the vlib command in the a UNIX shell or the Transcript window:
vlib work
Results
Creates a library named work, places it in the current directory and displays the work library in
the Structure window (Figure 1-2).
Figure 1-2. Work Library
Related Topics
Working Library Versus Resource Libraries
Working with Design Libraries
Map a Logical Name to a Design Library
VHDL VHDL units are compiled in the order they appear on the
command line. For VHDL, the order of compilation is
important — you must compile any entities or
configurations before an architecture that references
them. Projects may assist you in determining the compile
order. For example:
Results
By default, compilation results are stored in the work library. (Figure 1-3)
Figure 1-3. Compiled Design
Related Topics
Verilog Compilation
Compilation and Simulation of VHDL
Auto-Generate the Compile Order
Compiling SystemC Files
Prerequisites
• Create the work library and map required resource libraries to the work library. Refer to
Step 1 — Create Work and Resource Libraries for more information.
• Compile the design. Refer to Step 2 — Compile the Design.
Procedure
1. Enter the following command on the command line:
vopt top -o topopt
2. where:
• top is the name of the compiled top level module.
• -o topopt specifies a name for the optimized version of the design.
Related Topics
Optimizing Designs with vopt
Prerequisites
• Create the work library and map required resource libraries to the work library. Refer to
Step 1 — Create Work and Resource Libraries for more information.
• Compile the design. Refer to Step 2 — Compile the Design.
Procedure
1. Enter the following command on the command line:
vsim testbench globals
2. where testbench and globals are the two top level modules.
Results
After the simulator loads the top-level modules, it iteratively loads the instantiated modules and
UDPs in the design hierarchy, linking the design together by connecting the ports and resolving
hierarchical references.
Note
You can incorporate actual delay values to the simulation by applying standard delay format
(SDF) back-annotation files to the design.
Related Topics
Specifying SDF Files for Simulation
• add wave
• bp
• force
• run
• step
Related Topics
Startup
vsim
Here-Document Flow
You can use the “here-document” technique to enter a string of commands in a UNIX shell or
Windows command window. You invoke vsim and redirect standard input using the
exclamation character (!) to initiate and terminate a sequence of commands.
The following is an example of the “here-document” technique:
log -r *
run 100
do test.do
quit -f
!
The file test.do can run until completion or contain commands that return control of the
simulation to the command line and wait for user input. You can also use this technique to run
multiple simulations.
where “counter” is the design top, “infile” represents a script containing various Questa SIM
commands, and the angle brackets (< >) are redirection indicators.
Use the batch_mode command to verify that you are in Command Line Mode. stdout returns
“1” if you specify batch_mode while you are in Command Line Mode (vsim -c) or Batch Mode
(vsim -batch).
The following series of commands results in a transcript file that can be used for command input
if top is re-simulated (remove the quit -f command from the transcript file if you want to remain
in the simulator).
vsim -c top
transcript on
force clk 1 50, 0 100 -repeat 100
run 500
run @5000
quit -f
You should rename a transcript file that you intend to use as a DO file. If you do not rename the
file, Questa SIM will overwrite it the next time you run vsim. Also, simulator messages are
already commented out with the pound sign (#), but any messages generated from your design
(and subsequently written to the transcript file) will cause the simulator to pause. A transcript
file that contains only valid simulator commands will work fine; comment out anything else
with a pound sign.
Refer to Creating a Transcript File for more information about creating, locating, and saving a
transcript file.
Related Topics
Default stdout Messages
Stats
vsim command
Controlling the Display of Statistics Messages
Batch Mode
Batch Mode is an operational mode that provides the user with the ability to perform
simulations without invoking the GUI. The simulations are executed via scripted files from a
Windows command prompt or UNIX shell and do not provide for interaction with the design
during simulation. Data from the simulation run is typically sent to stdout and may be redirected
to a log file.
Simulating with Batch Mode can yield faster simulation times especially for simulations that
generate a large amount of textual output. Refer to Saving Batch Mode Simulation Data for
information about saving transcript data.
Multi-threaded C text output is not well synchronized with HDL text output. Refer to Capturing
Raw stdout in C/C++ Batch Mode Simulation for more information.
The commands supported within a DO file script for Batch Mode simulation are similar to those
available for Command Line Mode (vsim -c) however, not all commands or command options
are supported by vsim -batch. Refer to the Commands chapter in the Reference Manual to see
which commands can be used with vsim -batch.
1. Specifying vsim -batch with scripted simulations via the -do “<command_string>” |
<do_file_name> argument. Running vsim -batch with output redirection is
recommended as it yields the best simulation performance. Refer to Output Redirection
With vsim -batch for more information.
2. Enabling the BatchMode modelsim.ini variable. If this variable is set to 1, vsim runs as if
the vsim -batch option were specified. If this variable is set to 0 (default), vsim runs as if
the vsim -i option were specified. Transcript data is sent to stdout by default. You can
automatically create a log file by enabling the BatchTranscriptFile modelsim.ini
variable.
Note
You will receive a warning message if you specify vsim -batch with the -c, -gui, or
the -i options and -c, -gui, and -i will be ignored. If you enable the BatchMode
variable, the variable is ignored if you specify the -batch, -c, -gui, or -i options to vsim.
where “outfile” represents a script containing various Questa SIM commands, and the angle
bracket (>) is the output redirection indicator.
vsim -batch top -do "run -all; quit -f" > vsim.log
In addition, simulator behavior is controlled by a number of Tcl variables. Refer to the table
below for the list of default Tcl variables.
Related Topics
modelsim.ini Variables
9 # Region: /top/pads
10 # run -all
11 # 0: Z=1, AVSS=0
12 # quit -f
13 # End time: 18:06:45 on May 13,2014, Elapsed time: 0:00:00
14 # Errors: 0, Warnings: 1
Modes can be set for a specific feature or globally for all features. To add or subtract a mode for
a specific feature, specify using the plus (+) or minus (-) character with the feature, for example,
vsim -stats=cmd+verbose,perf+list. To add or subtract a mode globally for all features, specify
the modes in a comma-separated list, for example, Stats=time,perf,list,-verbose. You cannot
specify global and feature specific modes together.
For example,
• Enable the display of Start, End, and Elapsed time as well as a message count summary.
Echoing of the command line is disabled
vcom -stats=time,-cmd,msg
• The first -stats option is ignored. The none option disables all default settings and then
enables the perf option.
vlog -stats=time,cmd,msg -stats=none,perf
Note
Not all Message Statistics Types or Message Mode Types are available with each
command. Refer to the command description for more information.
Definition of an Object
Because Questa SIM supports a variety of design languages (SystemC, Unified Power Format
(UPF), PSL, Verilog, VHDL, and SystemVerilog), the word “object” is used to refer to any
valid design element in those languages, whenever a specific language reference is not needed.
Figure 1-6 summarizes the language constructs that an object can refer to.
Standards Supported
Standards documents are sometimes informally referred to as the Language Reference Manual
(LRM). This standards listed here are the complete name of each manual. Elsewhere in this
manual the individual standards are referenced using the IEEE Std number.
The following standards are supported for the Questa SIM products:
• VHDL —
o IEEE Std 1076-2008, IEEE Standard VHDL Language Reference Manual.
Questa SIM supports the VHDL 2008 standard features with a few exceptions. For
detailed standard support information see the vhdl2008 technote available at
Assumptions
Using the Questa SIM product and its documentation is based on the following assumptions.
• You are familiar with how to use your operating system and its graphical interface.
• You have a working knowledge of the design languages. Although Questa SIM is an
excellent application to use while learning HDL concepts and practices, this document is
not written to support that goal.
• You have worked through the appropriate lessons in the Questa SIM Tutorial and are
familiar with the basic functionality of Questa SIM. You can find the Questa SIM
Tutorial by choosing Help from the main menu.
Text Conventions
The table below lists the text conventions used in this manual.
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The following tables indicate the version in which the item was superseded and the new item
that replaces it, where applicable.
Questa SIM’s encryption solution allows IP authors to deliver encrypted IP code for a wide
range of EDA tools and design flows. You can, for example, make module ports, parameters,
and specify blocks publicly visible while keeping the implementation private.
Questa SIM supports VHDL, Verilog, and SystemVerilog IP code encryption by means of
protected encryption envelopes. VHDL encryption is defined by the IEEE Std 1076-2008,
section 24.1 (titled “Protect tool directives”) and Annex H, section H.3 (titled “Digital
envelopes”). Verilog encryption is defined by IEEE Std 1364-2005, section 28; and
SystemVerilog encryption is defined by the IEEE Std 1800-2012, section 34 (both sections are
titled “Protected envelopes”). The digital envelopes usage model, as presented in Annex H
section H.3 of these standards, is the recommended methodology for users of VHDL’s `protect
and Verilog's `pragma protect compiler directives. We recommend that you obtain these
specifications for reference.
Questa SIM supports “version 1” of the recommendations from the IEEE P1735-2014 working
group for encryption interoperability between different encryption and decryption tools. It
addresses use model, algorithm choices, conventions, and minor corrections to the HDL
standards to achieve useful interoperability.
The IEEE Std 1735-2014 is a clarification of the separate Verilog and VHDL definitions of
“source protection” and applies to both languages. It addresses the inter-operable (i.e., digital
envelope concept) parts incompletely defined for Verilog and VHDL. It also describes the idea
that “protection” involves encrypting/encoding the original source code into a form using
standard algorithms so that any compliant tool can use this form.
• The first form is a text file that contains a transformed version of the input original plain
text HDL source file.
• The second form is a protected version of the Design Unit(s) that were compiled.
The Questa SIM vencrypt utility for Verilog and SystemVerilog will produce only text files. It
does not compile anything into a library, nor does it process macros or handle the usual Verilog
switches. The Verilog/SystemVerilog compile command, vlog +protect, will produce text files
AND will compile them into the library, AND will process macros (and all the other usual vlog
arguments).
The Questa SIM vhencrypt utility for VHDL works the same as the vencrypt utility (though
VHDL does not have macros). The VHDL compile command, vcom +protect, works the same
as vlog.
Questa SIM also supports using the vcom/vlog -nodebug command to hide the compiled form
of the source code from the user’s point of view.
Encryption Envelopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Compiling with +protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The Runtime Encryption Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Language-Specific Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Proprietary Source Code Encryption Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Encryption Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Encryption Envelopes
Encryption envelopes define a region of textual design data or code to be protected with
protection expressions. The protection expressions specify the encryption algorithm used to
protect the source code, the encryption key owner, the key name, and envelope attributes.
The beginning and ending protection expressions for Verilog/SystemVerilog are `pragma
protect begin and `pragma protect end, respectively.
The beginning and ending protection expressions for VHDL are `protect BEGIN
PROTECTED and `protect END PROTECTED, respectively.
The encryption envelope may contain the code to be encrypted or it may contain `include
compiler directives that point to files containing the code to be encrypted.
Symmetric and asymmetric keys can be combined in encryption envelopes to provide the safety
of asymmetric keys with the efficiency of symmetric keys (see Encryption and Encoding
Methods). Encryption envelopes can also be used by the IP author to produce encrypted source
files that can be safely decrypted by multiple authors. For these reasons, encryption envelopes
are the preferred method of protection.
Procedure
1. Enclose the code to be encrypted within protection directives; or, enclose the names of
the files that contain the code to be encrypted within protection directives.
2. Compile your code with Questa SIM encryption utilities.
• Use the vencrypt command for Verilog and SystemVerilog design code.
• Use the vhencrypt command for VHDL design code.
• Or, use the vcom/vlog +protect command.
3. The flow diagram for creating encryption envelopes is shown in Figure 2-1.
Examples
In Example 2-2 the Verilog design data to be encrypted follows the `pragma protect begin
expression and ends with the `pragma protect end expression. If the design data had been
written in VHDL, the data to be protected would follow a `protect begin expression and would
end with a `protect end expression.
assign err = 0;
initial
begin
$dump_all_vpi;
$dump_tree_vpi(test_dff4);
$dump_tree_vpi(test_dff4.d4);
$dump_tree_vpi("test_dff4");
$dump_tree_vpi("test_dff4.d4");
$dump_tree_vpi("test_dff4.d", "test_dff4.clk", "test_dff4.q");
$dump_tree_vpi("test_dff4.d4.d0", "test_dff4.d4.d3");
$dump_tree_vpi("test_dff4.d4.q", "test_dff4.d4.clk");
end
endmodule
nand #5
g1(l1,preset,l4,l2),
g2(l2,l1,clear,clk),
g3(l3,l2,clk,l4),
g4(l4,l3,clear,d),
g5(q,preset,l2,qbar),
g6(qbar,q,clear,l3);
endmodule
`pragma protect end
In Example 2-3, the design data is contained in three files - diff.v, prim.v, and top.v. This
example shows how to configure the encryption envelope so the entire contents of diff.v, prim.v,
and top.v are encrypted.
`include diff.v
`include prim.v
`include top.v
endmodule
`endcelldefine
For a more technical explanation, see How Encryption Envelopes Work and The `include
Compiler Directive (Verilog only).
Protection Expressions
The encryption envelope contains a number of `pragma protect (Verilog/SystemVerilog) or
`protect (VHDL) expressions.
The following protection expressions are expected when creating an encryption envelope:
• data_method — defines the encryption algorithm that will be used to encrypt the
designated source text. Questa SIM supports the following encryption algorithms: des-
cbc, 3des-cbc, aes128-cbc, aes256-cbc, blowfish-cbc, cast128-cbc, and rsa.
• key_keyowner — designates the owner of the encryption key.
• key_keyname — specifies the keyowner’s key name.
• key_method — specifies an encryption algorithm that will be used to encrypt the key.
Note
The combination of key_keyowner and key_keyname expressions uniquely identify
a key. The key_method is required with these two expressions to complete the
definition of the key.
Note
Encryption envelopes cannot be nested. A `pragma protect begin/end pair cannot
bracket another `pragma protect begin/end pair.
initial begin
a <= b;
b <= c;
end
and the file we want to encrypt, top.v, contains the following source code:
module top;
`pragma protect begin
`include "header.v"
`pragma protect endendmodule
then, when we use the vlog +protect command to compile, the source code of the header file
will be encrypted. If we could decrypt the resulting work/top.vp file it would look like:
module top;
`pragma protect begin
initial begin
a <= b;
b <= c;
end
`pragma protect end
endmodule
When using the vencrypt compile utility (see Delivering IP Code with Undefined Macros), any
`include statements will be treated as text just like any other source code and will be encrypted
with the other Verilog/SystemVerilog source code. So, if we used the vencrypt utility on the
top.v file above, the resulting work/top.vp file would look like the following (if we could
decrypt it):
module top;
`protect
`include "header.v"
`endprotect
endmodule
When you use vlog +protect to generate encrypted files, the original source files must all be
complete Verilog or SystemVerilog modules or packages. Compiler errors will result if you
attempt to perform compilation of a set of parameter declarations within a module. (See also
Compiling with +protect.)
You can avoid such errors by creating a dummy module that includes the parameter
declarations. For example, if you have a file that contains your parameter declarations and a file
that uses those parameters, you can do the following:
module dummy;
`protect
`include "params.v" // contains various parameters
`include "tasks.v" // uses parameters defined in params.v
`endprotect
endmodule
Then, compile the dummy module with the +protect switch to generate an encrypted output file
with no compile errors.
After compilation, the work library will contain encrypted versions of params.v and tasks.v,
called params.vp and tasks.vp. You may then copy these encrypted files out of the work
directory to more convenient locations. These encrypted files can be included within your
design files; for example:
module main
'include "params.vp"
'include "tasks.vp"
...
To illustrate, suppose the author wants to modify the following VHDL sample file so the
encrypted model can be decrypted and simulated by both Questa SIM and by a hypothetical
company named XYZ inc.
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-2"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
library ieee;
use ieee.std_logic_1164.all;
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
The author does this by writing a key block for each decrypting tool. If XYZ publishes a public
key, the two key blocks in the IP source code might look like the following:
The encrypted code would look very much like the sample file, with the addition of another key
block:
Questa SIM uses its key block to determine the encrypted session key and XYZ Incorporated
uses the second key block to determine the same key. Consequently, both implementations
could successfully decrypt the code.
Note
The IP owner is responsible for obtaining the appropriate key for the specific tool(s)
protected IP is intended for, and should validate the encrypted results with those tools to
ensure his IP is protected and will function as intended in those tools.
When +protect is used with vcom or vlog, encryption envelope expressions are
transformed into decryption envelope expressions and decryption content expressions.
Source text within encryption envelopes is encrypted using the specified key and is
recorded in the decryption envelope within a data_block. The new encrypted file is
created with the same name as the original unencrypted file but with a ‘p’ added to the
filename extension. For Verilog, the filename extension for the encrypted file is .vp; for
SystemVerilog it is .svp, and for VHDL it is .vhdp. This encrypted file is placed in the
current work library directory.
2. You can designate the name of the encrypted file using the +protect=<filename>
argument with vcom or vlog as follows:
vlog +protect=encrypt.vp encrypt.v
Examples
Example 2-4 shows the resulting source code when the Verilog IP code used in Example 2-2 is
compiled with vlog +protect.
In this example, the `pragma protect data_method expression designates the encryption
algorithm used to encrypt the Verilog IP code. The key for this encryption algorithm is also
encrypted – in this case, with the RSA public key. The key is recorded in the key_block of the
protected envelope. The encrypted IP code is recorded in the data_block of the envelope.
Questa SIM allows more than one key_block to be included so that a single protected envelope
can be encrypted by Questa SIM then decrypted by tools from different users.
• a Source window will not display the design units’ source code
• a Structure window will not display the internal structure
• the Objects window will not display internal signals
• the Processes window will not display internal processes
Procedure
1. The IP author creates code that contains undefined macros and `directives.
2. The IP author creates encryption envelopes (see Encryption Envelopes) to protect
selected regions of code or entire files (see Protection Expressions).
3. The IP author uses Questa SIM’s vencrypt utility to encrypt Verilog and SystemVerilog
code contained within encryption envelopes. Macros are not pre-processed before
encryption so macros and other `directives are unchanged.
The vencrypt utility produces a file with a .vp or a .svp extension to distinguish it from
non-encrypted Verilog and SystemVerilog files, respectively. The file extension may be
changed for use with simulators other than Questa SIM. The original file extension is
preserved if the -d <dirname> argument is used with vencrypt, or if a `directive is used
in the file to be encrypted.
With the -h <filename> argument for vencrypt the IP author may specify a header file
that can be used to encrypt a large number of files that do not contain the `pragma
protect (or proprietary `protect information - see Proprietary Source Code Encryption
Tools) about how to encrypt the file. Instead, encryption information is provided in the
<filename> specified by -h <filename>. This argument essentially concatenates the
header file onto the beginning of each file and saves the user from having to edit
hundreds of files in order to add in the same `pragma protect to every file. For
example,
vencrypt -h encrypt_head top.v cache.v gates.v memory.v
concatenates the information in the encrypt_head file into each Verilog file listed. The
encrypt_head file may look like the following:
`pragma protect data_method = "aes128-cbc"
`pragma protect author = "IP Provider"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-1"
`pragma protect encoding = (enctype = "base64")
`pragma protect begin
Notice, there is no `pragma protect end expression in the header file, just the header
block that starts the encryption. The `pragma protect end expression is implied by the
end of the file.
4. The IP author delivers encrypted IP with undefined macros and `directives.
5. The IP user defines macros and `directives.
6. The IP user compiles the design with vlog.
7. The IP user simulates the design with Questa SIM or other simulation tools.
Procedure
1. The IP author creates proprietary code that contains user-defined macros and `directives.
2. The IP author creates encryption envelopes with `pragma protect expressions to protect
regions of code or entire files. See Encryption Envelopes and Protection Expressions.
3. The IP author uses the +protect argument for the vlog command to encrypt IP code
contained within encryption envelopes. The `pragma protect expressions are ignored
unless the +protect argument is used during compile. (See Compiling with +protect.)
The vlog +protect command produces a .vp or a .svp extension for the encrypted file to
distinguish it from non-encrypted Verilog and SystemVerilog files, respectively. The
file extension may be changed for use with simulators other than Questa SIM. The
original file extension is preserved if a `directive is used in the file to be encrypted. For
more information, see Compiling with +protect.
4. The IP author delivers the encrypted IP.
5. The IP user simulates the code like any other file.
When encrypting source text, any macros without parameters defined on the command
line are substituted (not expanded) into the encrypted file. This makes certain macros
unavailable in the encrypted source text.
Questa SIM takes every simple macro that is defined with the compile command (vlog)
and substitutes it into the encrypted text. This prevents third party users of the encrypted
blocks from having access to or modifying these macros.
Note
Macros not specified with vlog via the +define+ option are unmodified in the
encrypted block.
For example, the code below is an example of a file that might be delivered by an IP
provider. The filename for this module is example00.sv
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "Mentor Graphics Corporation"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "MGC-VERIF-SIM-RSA-2"
`pragma protect author = "Mentor", author_info = "Mentor_author"
`pragma protect begin
`timescale 1 ps / 1 ps
`define FOO 0
$display("FOO is defined as: ", `FOO);
$display("reg IPPROTECT has the value: ", `IPPROTECT );
end
`else
initial begin
$display("ifdef defined as false");
end
`endif
endmodule
This creates an encrypted file called encrypted00.sv. We can then compile this file with
a macro override for the macro “FOO” as follows:
vlog +define+FOO=99 encrypted00.sv
The macro FOO can be overridden by a customer while the macro IPPROTECT retains
the value specified at the time of encryption, and the macro IPPROTECT no longer
exists in the encrypted file.
• IP authors may use `protect directives to create an encryption envelope (see Encryption
Envelopes) for the VHDL code to be protected and use Questa SIM’s vhencrypt utility
to encrypt the code. The encrypted IP code can be delivered to IP customers for use in a
wide range of EDA tools and design flows. See Using the vhencrypt Utility.
• IP authors may use `protect directives to create an encryption envelope (see Encryption
Envelopes) for the VHDL code to be protected and use Questa SIM’s default encryption
and decryption actions. The IP code can be delivered to IP customers for use in a wide
range of EDA tools and design flows. See Using Questa SIM Default Encryption for
VHDL.
• IP authors may use `protect directives to create an encryption envelope for VHDL code
and select encryption methods and encoding other than Questa SIM’s default methods.
See User-Selected Encryption for VHDL.
• IP authors may use “raw” encryption and encoding to aid debugging. See Using raw
Encryption for VHDL.
• IP authors may encrypt several parts of the source file, choose the encryption method for
encrypting the source (the data_method), and use a key automatically provided by
Questa SIM. See Encrypting Several Parts of a VHDL Source File.
• IP authors can use the concept of multiple key blocks to produce code that is secure and
portable across different simulators. See Portable Encryption for Multiple Tools.
The usage models are illustrated by examples in the sections below.
Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK directive.
concatenates the information in the encrypt_head file into each VHDL file listed. The
encrypt_head file may look like the following:
`protect data_method = "aes128-cbc"
`protect author = "IP Provider"
`protect encoding = (enctype = "base64")
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_method = "rsa"
`protect key_keyname = "MGC-VERIF-SIM-RSA-2"
`protect KEY_BLOCK
`protect begin
Notice, there is no `protect end expression in the header file, just the header block that
starts the encryption. The `protect end expression is implied by the end of the file.
4. The IP author delivers encrypted IP.
5. The IP user compiles the design with vcom.
6. The IP user simulates the design with Questa SIM or other simulation tools.
Examples
Using Questa SIM Default Encryption for VHDL
Suppose an IP author needs to make a design entity, called IP1, visible to the user so the user
can instantiate the design, but the author wants to hide the architecture implementation from the
user. In addition, suppose that IP1 instantiates entity IP2, which the author wants to hide
completely from the user. The easiest way to accomplish this is to surround the regions to be
protected with `protect begin and `protect end directives and let Questa SIM choose default
actions. For this example, all the source code exists in a single file, example1.vhd:
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect begin
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
The IP author compiles this file with the vcom +protect command as follows:
The compiler produces an encrypted file, example1.vhdp which looks like the following:
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect BEGIN_PROTECTED
`protect version = 1
`protect encrypt_agent = "Model Technology", encrypt_agent_info = "DEV"
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-2"
`protect key_method = "rsa"
`protect encoding = ( enctype = "base64" )
`protect KEY_BLOCK
<encoded encrypted session key>
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" , bytes = 224 )
`protect DATA_BLOCK
<encoded encrypted IP>
`protect END_PROTECTED
When the IP author surrounds a text region using only `protect begin and `protect end, Questa
SIM uses default values for both encryption and encoding. The first few lines following the
`protect BEGIN_PROTECTED region in file example1.vhdp contain the key_keyowner,
key_keyname, key_method and KEY_BLOCK directives. The session key is generated into the
key block and that key block is encrypted using the “rsa” method. The data_method indicates
that the default data encryption method is aes128-cbc and the “enctype” value shows that the
default encoding is base64.
Alternatively, the IP author can compile file example1.vhd with the command:
Here, the author does not supply the name of the file to contain the protected source. Instead,
Questa SIM creates a protected file, gives it the name of the original source file with a 'p' placed
at the end of the file extension, and puts the new file in the current work library directory. With
the command described above, Questa SIM creates file work/example1.vhdp. (See Compiling
with +protect.)
The IP user compiles the encrypted file work/example1.vhdp the ordinary way. The +protect
switch is not needed and the IP user does not have to treat the .vhdp file in any special manner.
Questa SIM automatically decrypts the file internally and keeps track of protected regions.
If the IP author compiles the file example1.vhd and does not use the +protect argument, then the
file is compiled, various `protect directives are checked for correct syntax, but no protected file
is created and no protection is supplied.
Questa SIM’s default encryption methods provide an easy way for IP authors to encrypt VHDL
designs while hiding the architecture implementation from the user. It should be noted that the
results are only usable by Questa SIM tools.
-- Both the entity "ip2" and its architecture "a" are completely protected
`protect data_method = "aes128-cbc"
`protect encoding = ( enctype = "base64" )
`protect key_keyowner = "Mentor Graphics Corporation"
`protect key_keyname = "MGC-VERIF-SIM-RSA-2"
`protect key_method = "rsa"
`protect KEY_BLOCK
`protect begin
library ieee;
use ieee.std_logic_1164.all;
entity ip2 is
...
end ip2;
architecture a of ip2 is
...
end a;
`protect end
The data_method directive indicates that the encryption algorithm “aes128-cbc” should be used
to encrypt the source code (data). The encoding directive selects the “base64” encoding method,
and the various key directives specify that the Mentor Graphic key named “MGC-VERIF-SIM-
RSA-2” and the “RSA” encryption method are to be used to produce a key block containing a
randomly generated session key to be used with the “aes128-cbc” method to encrypt the source
code. See Using the Mentor Graphics Public Encryption Key.
end example3_ent;
If (after compiling the entity) the example3_arch.vhd file were compiled using the command:
begin
end arch;
`protect END_PROTECTED========== End of file work/example3_arch.vhdp
Notice that the protected file is very similar to the original file. The differences are that `protect
begin is replaced by `protect BEGIN_PROTECTED, `protect end is replaced by `protect
END_PROTECTED, and some additional encryption information is supplied after the BEGIN
PROTECTED directive.
See Encryption and Encoding Methods for more information about raw encryption and
encoding.
entity ex4_ent is
end ex4_ent;
begin -- ex4_arch
end ex4_arch;
entity ex4_ent is
end ex4_ent;
begin -- ex4_arch
end ex4_arch;
The encrypted example4.vhdp file shows that an IP author can encrypt both declarations and
statements. Also, note that the signal assignment
is not protected. This assignment compiles and simulates even though signal s2 is protected. In
general, executable VHDL statements and declarations simulate the same whether or not they
refer to protected objects.
Note
While Questa SIM supports both `protect and `pragma protect encryption directives, these
two approaches to encryption are incompatible. Code encrypted by one type of directive
cannot be decrypted by another.
The usage flow for delivering IP with the Mentor Graphics proprietary `protect compiler
directive is as follows:
Procedure
1. The IP author protects selected regions of Verilog or SystemVerilog IP with the `protect
/ `endprotect directive pair. The code in `protect / `endprotect encryption envelopes
has all debug information stripped out. This behaves exactly as if using
vlog -nodebug=ports+pli
except that it applies to selected regions of code rather than the whole file.
2. The IP author uses the vlog +protect command to encrypt IP code contained within
encryption envelopes. The `protect / `endprotect directives are ignored by default
unless the +protect argument is used with vlog.
Once compiled, the original source file is copied to a new file in the current work
directory. The vlog +protect command produces a .vp or a .svp extension to distinguish
it from other non-encrypted Verilog and SystemVerilog files, respectively. For example,
top.v becomes top.vp and cache.sv becomes cache.svp. This new file can be delivered
and used as a replacement for the original source file. (See Compiling with +protect.)
Note
The vencrypt utility may be used if the code also contains undefined macros or
`directives, but the code must then be compiled and simulated with Questa SIM.
You can use vlog +protect=<filename> to create an encrypted output file, with the
designated filename, in the current directory (not in the work directory, as in the default
case where [=<filename>] is not specified). For example:
vlog test.v +protect=test.vp
If the filename is specified in this manner, all source files on the command line will be
concatenated together into a single output file. Any `include files will also be inserted
into the output file.
Caution
`protect and `endprotect directives cannot be nested.
If errors are detected in a protected region, the error message always reports the first line
of the protected block.
Note
The -nodebug argument encrypts entire files. The `protect compiler directive allows you to
encrypt regions within a file. Refer to Compiler Directives for details.
Procedure
1. Compile VHDL files to be encrypted with the vcom -nodebug command.
2. Compile Verilog/SystemVerilog files to be encrypted with the vlog -nodebug command.
When you compile with -nodebug, all source text, identifiers, and line number
information are stripped from the resulting compiled object, so Questa SIM cannot
locate or display any information of the model except for the external pins.
You can access the design units comprising your model via the library, and you may
invoke vsim directly on any of these design units to see the ports. To restrict even this
access in the lower levels of your design, you can use the following -nodebug options
when you compile:
Note
Do not use the =ports option on a design without hierarchy, or on the top level of a
hierarchical design. If you do, no ports will be visible for simulation. Rather,
compile all lower portions of the design with -nodebug=ports first, then compile the top
level with -nodebug alone.
Design units or modules compiled with -nodebug can only instantiate design units or
modules that are also compiled -nodebug.
Do not use -nodebug=ports when the parent is part of a vopt -pdu (black-box) flow or for
mixed language designs, especially for Verilog modules to be instantiated inside VHDL.
Encryption Reference
The Encryption Reference includes important information about encryption and encoding
methods, details on how encryption envelopes work, how to use public encryption keys, and
how to use the Mentor Graphics public encryption key.
Encryption and Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
How Encryption Envelopes Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Using Public Encryption Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Using the Mentor Graphics Public Encryption Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Symmetric Encryption
For symmetric encryption, security of the key is critical and information about the key must be
supplied to Questa SIM. Under certain circumstances, Questa SIM will generate a random key
for use with a symmetric encryption method or will use an internal key.
• des-cbc
• 3des-cbc
• aes128-cbc
• aes192-cbc
• aes256-cbc
• blowfish-cbc
• cast128-cbc
The default symmetric encryption method Questa SIM uses for encrypting IP source code is
aes128-cbc.
Asymmetric Encryption
For asymmetric encryption, the public key is openly available and is published using some form
of key distribution system. The private key is secret and is used by the decrypting tool, such as
Questa SIM. Asymmetric methods are more secure than symmetric methods, but take much
longer to encrypt and decrypt data.
rsa
This method is only supported for specifying key information, not for encrypting IP source code
(i.e., only for key methods, not for data methods).
For testing purposes, Questa SIM also supports raw encryption, which doesn't change the
protected source code (the simulator still hides information about the protected region).
All encryption algorithms (except raw) produce byte streams that contain non-graphic
characters, so there needs to be an encoding mechanism to transform arbitrary byte streams into
portable sequences of graphic characters which can be used to put encrypted text into source
files. The encoding methods supported by Questa SIM are:
• uuencode
• base64
• raw
Base 64 encoding, which is technically superior to uuencode, is the default encoding used by
Questa SIM, and is the recommended encoding for all applications.
Raw encoding must only be used in conjunction with raw encryption for testing purposes.
5. The encrypting tool uses this information to encrypt and encode the session key into a
KEY_BLOCK. The occurrence of a KEY_BLOCK in the source code tells the
encrypting tool to generate an encryption envelope.
6. The decrypting tool reads each KEY_BLOCK until it finds one that specifies a key it
knows about. It then decrypts the associated KEY_BLOCK data to determine the
original session key and uses that session key to decrypt the IP source code.
Note
VHDL encryption requires that the KEY_BLOCK (the sequence of key_keyowner,
key_keyname, and key_method directives) end with a `protect KEY_BLOCK
directive.
For VHDL:
`protect key_keyowner="Acme"
`protect key_keyname="AcmeKeyName"
`protect key_public_key
MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQCnJfQb+LLzTMX3NRARsv7A8+LV5SgMEJCvI
f9Tif2emi4z0qtp8E+nX7QFzocTlClC6Dcq2qIvEJcpqUgTTD+mJ6grJSJ+R4AxxCgvHYUwoT
80Xs0QgRqkrGYxW1RUnNBcJm4ZULexYz8972Oj6rQ99n5e1kDa/eBcszMJyOkcGQIDAQAB
This defines a new key named “AcmeKeyName” with a key owner of “Acme.” The data block
following key_public_key directive is an example of a base64 encoded version of a public key
that should be provided by a tool vendor.
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAtNA6tJ1tV/cXF4K5mL4s
4KCuTKWSbN/BnJJ6elRTWr2+s5Baaul0ctIX/3KYzpITmG9ph/4uZBs+jV5DAC+9
WRZQDc11JdIlRi04dEx/bGVbfPs3pdTPFZjA6gfegdW03ZNhjaJChTwEoXL1xIGP
oodJyhX9r1DoxU2lWB19vpwI5Geygh6pYgkPXb0aQzLh6hyUBhH9yMN6eV+imBbO
eax8ZCO6Gz2CJq3ebS/JoMYrikgcIEf6kVhIOiB9LluTp6TZlSd8ilwPhQmfXWH2
w4CaIpN8kADaVHnDWIdqqHlGf3cNQrlWj6FnFpSam6PjmWp5ZD4Jt6UNJxEoKEsn
gwIDAQAB
For Verilog and SystemVerilog applications, copy and paste the entire Mentor Graphics key
block, as follows, into your code:
Caution
The encryption key will not work if extraneous characters or spaces of any type are inserted
during copy and paste operations.
The vencrypt utility will recognize the Mentor Graphics public key. If vencrypt is not used, you
must use the +protect switch with the vlog command during compile.
For VHDL applications, copy and paste the entire Mentor Graphics key block, as follows, into
your code:
The vhencrypt utility will recognize the Mentor Graphics public key. If vhencrypt is not used,
you must use the +protect switch with the vcom command during compile.
Example 2-1 illustrates the encryption envelope methodology for using this key in Verilog/
SystemVerilog. With this methodology you can collect the public keys from the various
companies whose tools process your IP, then create a template that can be included into the files
you want encrypted. During the encryption phase, a symmetric "session key" is created for each
block of HDL source being encrypted. This session key itself is encrypted and encoded using
each public key found in the pragmas that form the encryption envelope that contain the block.
Example 2-1. Using the Mentor Graphics Public Encryption Key in Verilog/
SystemVerilog
//
// Copyright 1991-2009 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
TERMS.
//
module dff (q, d, clear, preset, clock); output q; input d, clear, preset,
clock; reg q;
endmodule
`endcelldefine
Questa SIM, by default, performs built-in optimizations on your design to maximize simulator
performance. These optimizations yield performance improvements over non-optimized runs.
The optimizations will limit the visibility of design objects, but you can increase visibility of
any objects for debugging purposes, as described in the section "Preserving Object Visibility for
Debugging Purposes."
The command that performs global optimizations in Questa SIM is called vopt. This chapter
discusses the vopt functionality, the effects of optimization on your design, and how to
customize the application of vopt to your design. For more information on syntax and usage of
this command, refer to vopt in the Reference Manual.
Optimization Flows
There are two basic flows that you can use to control optimizations for your simulation run.
• Three-Step Flow — where you perform compilation, optimization, and simulation in
three separate steps.
• Two-Step Flow — where you perform compilation and simulation in two separate steps
and optimization is implicitly run prior to simulation.
Note
It is recommended that you use the three-step flow for optimizing and simulating your
design. Because this flow includes explicit use of the vopt command, you can take
advantage of its numerous arguments to apply fine-grained control of the optimization step.
The three-step flow also allows you to reuse optimized images, which saves redundant
optimization time for unchanged designs. Further, these images can reside in a separate library.
Unless you have a specific situation that requires a more simplified flow and are aware of its
limitations, you should use the three-step flow.
Three-Step Flow
The three-step flow includes using the vopt command, which provides you with the most
control over the optimization process.
The steps for this flow consist of the following Questa SIM commands:
The three-step flow allows you to use Questa SIM for several purposes including:
• Preoptimized design units (PDU) — Reduce the amount of time necessary for future
optimization and simulation runs by preoptimizing (black-boxing) regions of your
design using the -pdu argument, as described in the section "Preoptimizing Regions of
Your Design."
• Performing a simulation for debug — Preserve the highest level of visibility by
specifying the +acc argument to vopt. For example:
vlog -work <required_files>
vopt +acc top -o dbugver
vsim dbugver
• Performing a simulation for regression — Reduce the amount of visibility because you
are not as concerned about debugging. For example:
vlog -work <required_files>
vopt top -o optver
vsim optver
Note
The filename must not contain capital letters or any character that is illegal for your
operating system, For example, on Windows you cannot use backslash (\).
Two-Step Flow
The two-step flow omits explicitly use of the vopt command, although you can perform design
optimizations using existing scripts because vsim automatically performs optimization.
Note
In most cases, it is recommended that you use the Three-Step Flow for optimizing and
simulating your design. Unless you have a specific situation that requires a more simplified
flow and are aware of its limitations, you should use the three-step flow.
The two steps for this flow consist of the following actions using Questa SIM commands:
The optimization step of vsim loads compiled design units from their libraries and
regenerates optimized code.
b. Simulate — Runs vsim on the optimized design unit.
Because vopt is called implicitly when using the two-step flow, Questa SIM creates an
optimized internal design for simulation. By default, the maximum number of these designs is
set to three, after which vsim execution removes the oldest optimized design and creates a new
one. You can increase this limit by using the -unnamed_designs argument with the vlib
command. Because the vsim command manages unnamed_designs you cannot use the -o
argument in the -voptargs specification to name an optimized design. For example,
vsim mydesign -voptargs="-o myoptdesign" will generate an error message.
Note
The unnamed optimized designs limit may be exceeded if multiple concurrent vsim sessions
are run with the same 'work' library
The following are some examples of how to pass optimization arguments from the vsim
command line:
You can also use the numbered -O arguments on the vcom or vlog command lines to control
optimizations independently from vopt.
The -O0 and -O1 arguments can negatively impact performance and you should only use them
if you are attempting to analyze the behavior of the simulator. If you require increased visibility
for objects that are being optimized out of the simulation, use the vopt +acc functionality
instead.
The -O5 argument enables more aggressive native-code generation which can speed up many
designs, but it can slow down others.
In code coverage flows, you should use the vlog, vcom, and vopt -coveropt argument (or the
CoverOpt modelsim.ini variable) to control visibility and other interactions between
optimization and code coverage collection.
+noacc=a -noassertdebug
+noacc=b -nobitscalar
+noacc=c -nocellaccess
+noacc=f -nofsmdebug
Table 3-1. vopt Arguments for Access Visibility Being Replaced (cont.)
Previously Supported Argument1 Replacement Argument
+noacc=l -nolinedebug
+noacc=s -nosystfoverride
+noacc=u -noprimitiveaccess
+noacc=x -norandmetastable
1. The following values of +acc and +noacc are also deprecated, but they do not have
replacement arguments and are still supported for backward compatibility:
+acc=m, +acc=n, +acc=p, +acc=r, +acc=t, +acc=v
+noacc=m, +noacc=n, +anocc=p, +noacc=r, +noacc=t, +noacc=v
2. Verilog cells only.
The following examples show some common uses of the vopt +acc combination—refer to the
reference page for the vopt command for a description of all values.
• Preserve visibility of all objects in the design by specifying no arguments with +acc:
vopt +acc mydesign -o mydesign_opt
• Preserve visibility of all objects in a specific module by specifying the name of the
module as an argument with +acc:
vopt top +acc+mod1 mydesign -o mydesign_opt
• Preserve access to nets (n), ports (p) and registers (r) for 3 levels downwards from a
specific level of hierarchy in a design (top.netlist1):
vopt top +acc=npr3+top.netlist1 mydesign -o mydesign_opt
The examples in this section assume that you have set the PathSeparator variable to a
period (.) for a Verilog environment.
• Preserve port access to a specific level of hierarchy in a design (top.netlist2):
vopt top +acc=p+top.netlist2 mydesign -o mydesign_opt
• Preserve port access recursively downward from a specific level of hierarchy in a design
(top.netlist2):
vopt top +acc=p+top.netlist2. mydesign -o mydesign_opt
• Preserve visibility for all instances of a particular VHDL design region (ent1):
vopt top +acc=+ent1 mydesign -o mydesign_opt
• Preserve visibility of line numbers (=l) in addition to registers within a specific module:
vopt top +acc=lr+mod1 mydesign -o mydesign_opt
• Preserve visibility of line numbers and registers within a specific module and all
children in that module by adding a period (.) after the module name:
vopt top +acc=lr+mod1. mydesign -o mydesign_opt
• Preserve visibility of all design units whose names match a wildcard specification (glob-
style):
vopt +acc=r+mod?a mydesign -o mydesign_opt
In general, you first identify a region to which a particular argument should be applied. You
might use +cover to specify that initial region. Then, if some part of this region needed to be
excluded from coverage, you would apply the negating argument to that region, which would be
+nocover+<exclusion_region>. Now, there may be some regions to which the +cover argument
needs to be re-applied, in order to negate the removal by the previous +nocover argument. You
can repeat this process to achieve the desired coverage.
You can use the period character (.) after <object> to apply an argument recursively.
Alternatively, you may use +<recursion_level> to apply this argument to a specified number of
levels under this scope, where recursion_level is any integer from 0 to 128 (a value of 128
specifies full recursion).
The first argument states that branch and condition coverage is applied to all the
instances of lib1.du. Then, the second argument states that coverage is not applied to
specific instance inst.
This example assumes that you have set the PathSeparator variable to a period (.) for a Verilog
environment.
• Override — You can override any design parameters and generics with either the -G or
-g arguments to the vopt command (note the case sensitivity). Questa SIM optimizes
your design based on how you have overridden any parameters and generics.
Once you override a parameter or generic in the optimization step, you will not be able
to change its value during the simulation. Therefore, if you attempt to override these
same generics or parameters during the simulation, Questa SIM will ignore those
specifications of -g or -G.
vopt -o opt_top top -G timingCheck=1 -G top/a/noAssertions=0
The Language Reference Manual (LRM), IEEE Std 1800-2005, for SystemVerilog
places some limits on when you cannot override parameters. You will not be able to
override parameters with the -g, -G, or -floatparameters arguments in the following
instances:
o Local parameters (localparam) cannot be overridden.
o You cannot specify a parameter in a generate scope, and if one exists, it should be
treated as a localparam statement.
o No mechanism is provided for overriding parameters declared inside a package or
$unit, and if one exists, it should be treated as a localparam statement.
• Float — You can specify that parameters and generics should remain floating by using
the -floatparameters or -floatgenerics arguments, respectively, to the vopt command.
Questa SIM will optimize your design, retaining any information related to these
floating parameters and generics so that you can override them during the simulation
step.
vopt -o opt_top top -floatparameters+timingCheck+noAssertions
parameter value you may need to simulate. Refer to "Creating Specialized Designs for
Parameters and Generics" for more information.
• Combination — You can combine the use of the -g/-G and -floatparameters/-
floatgenerics arguments with the vopt command to have more control over the use of
parameters and generics for the optimization and simulation steps.
Because the -g/-G and -floatparameters/-floatgenerics arguments allow some use of
wildcards, ambiguities could occur. If, based on specified arguments, a parameter or
generic is considered floating and also is overridden, the override value takes
precedence. For example:
vopt -o opt_top top -floatparameters+timingCheck
-G top/a/noAssertions=0
Refer to the section Preoptimizing Regions of Your Design for more information.
When you are using vopt -pdu, you should associate the optimized name with the original name
using the -o argument. For example:
For the above example, any design that contains an instantiation of the module moda, Questa
SIM runs a design analysis and automatically includes the Preoptimized Design Unit
moda_pdu_opt.
• When you instantiate a region that has been preoptimized (black-boxed), you do not
need to run vopt on the top level module.
• During optimization, Questa SIM does not descend into the PDU, allowing faster
operation. However, parameters passing through and hierarchical references across the
PDU are restricted. You can retain visibility into a PDU by using the -pdusavehierrefs
argument to vopt, but it can reduce simulation performance.
• You will need to manage both the original portion (moda) and its optimized version
(moda_pdu_opt). Specifically, you must not remove the optimized version without also
removing or recompiling the original version.
Simulating Designs with Multiple Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Extracting Visibility Requirements for PDUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Using Configurations with Preoptimized Verilog Design Units . . . . . . . . . . . . . . . . . . . 142
Using Configurations with Preoptimized VHDL Design Units . . . . . . . . . . . . . . . . . . . . 143
Resolving Preoptimized Design Unit Loading Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Prerequisites
• Current working library.
• Assume the following library and file names:
o work
o asic_lib
o cell_lib.v
o netlist.v
o opt_netlist
o tb.v
o test1.v
o test2.v
o opt_tb
o sim.do
Procedure
1. Compile the work and design libraries.
vlib work
vlib asic_lib
7. Compile and optimize a second test and re-simulate without recompiling or optimizing
the PDU netlist.
vlog test2.v
vopt tb -o opt_tb
vsim -c opt_tb -do sim.do
Prerequisites
• In order to ensure that necessary visibility is maintained, run vopt with appropriate
-pduspec values and an acc file that contains all hierarchical references (such as the .acc
file generated by vsim -learn). Refer to Preserving Design Visibility with the Learn
Flow for more information.
Procedure
1. Compile your design.
vlog *.sv
2. Simulate with vsim -learn and full visibility into your design to generate a control file
with instructions for preserving visibility. In this example, creates the file mylearn.acc.
vsim -voptargs="+acc" -learn mylearn top
3. Create the PDU visibility file, dut1.acc. Using the .acc file generated by -learn,
mylearn.acc and the previously compiled “top.” Generates a unified .acc file for the pdu.
vopt top -pduspec+dut1+facc=dut1.acc -f mylearn.acc
4. Create a PDU for dut1_pdu referencing the visibility requirements generated in Step 3.
vopt -pdu -o dut1_pdu dut1 -f dut1.acc
5. Optimize the design with the merged visibility criteria located in mylearn.acc.
vopt -o top_opt top -f mylearn.acc
o top.v
module top;
foo u0();
foo u1();
endmodule
o foo.v
module foo10;
foo_lower #10 u0();
endmodule
module foo20;
foo_lower #20 u0();
endmodule
module foo_lower;
parameter N=99;
initial begin
$display("N=%d", N);
end
endmodule
Procedure
1. Create the work library.
vlib work
3. Create a PDU named foo10_pdu based on the foo10 module in foo.v. Whenever a part
of the design is dependent upon foo10, the simulator will load the PDU foo10_pdu to
speed up the elaboration process.
vopt -pdu foo10 -o foo10_pdu
Results
When the simulator encounters top.u0 it will use foo10 (as defined in the configuration), at
which point, the simulator will use your PDU foo10_pdu (and similarly for top.u1 and foo20).
o top.vhd
entity top is
end top;
o foo.vhd
entity foo_lower is
generic ( N : integer := 99 );
end foo_lower;
entity foo10 is
end foo10;
entity foo20 is
end foo20;
Procedure
1. Creates the work library.
vlib work
3. Creates a Preoptimized Design Unit (black-box) named foo10_pdu based on the foo10
module in foo.vhd. Whenever a part of the design is dependent upon foo10, the
simulator will load the optimized design unit foo10_pdu to speed up the elaboration
process.
vopt -pdu foo10 -o foo10_pdu
Results
When the simulator encounters u0 : foo_comp it will use foo10 (as defined in the
configuration), at which point the simulator will use your Preoptimized Design Unit foo10_pdu
(and similarly for u1 : foo_comp and foo20).
# ** Warning: (vsim-56) The dependency file generated by the "vopt" tool has either
# been removed, is for an older version of the tool or has been corrupted. Normally
# re-running vopt on the design will recreate this file and solve the issue.
# "/tmp/build1/test/libs/cells/post_cell_bb/_deps" - file open failed.
Causes
Possible causes of error message vsim-166:
• Dependent file — A dependent file generated by running vopt could not be found, or it
was generated by an older version of Questa SIM.
• Library Path — The physical path to a library containing a Preoptimized Design Unit
(PDU) no longer points to the library. This can occur in nested PDUs (a PDU containing
a PDU) and is due to a PDU fixing all logical references (including library mappings) to
physical references below it.
Solution
• Dependent file — Rerunning vopt on the design will recreate the PDU and resolve the
issue.
• Library Path — Use soft links to resolve these physical links if necessary.
Procedure
1. Create the library:
vlib work
You must create any optimized designs before locking the library, otherwise the vopt
command will issue the following error:
# ** Fatal: (vopt-1991) Library "\user\design\work" cannot be
modified due to a lock.
Once the library is locked, you will not be able to alter the library in any way; including
the vlib, vcom, vopt, and vdel commands.
You can ensure that the library is locked by using the command, which returns
information about the library, including the following line:
...
# Library locked/unlocked : locked
...
If you need to recompile a design unit or create a new optimized design, you can unlock
the library as follows:
vlib -unlocklib work
Results
This enables schematic viewing and causality analysis using Liberty logic cell definitions. The
following command sequence shows basic usage of a Liberty library:
vlog design.v
vopt -o opt tb -libertyfiles=cells.lib -debugdb ...
vsim -c opt -debugdb ...
These control files allow you to retain information during optimization for the following:
When you specify the -learn argument, where the argument defines the root name
(top_pli_learn) of the generated control files, vsim analyzes your design as well as your
PLI to determine what information needs to be retained during the optimization.
By specifying -voptargs=+acc you are enabling full visibility which allows the learn
flow to analyze your design with full functionality correctness.
Based on this analysis it then creates the following control files and places them in the
current directory:
top_pli_learn.acc
top_pli_learn.ocf
top_pli_learn.ocm
The learn flow is sensitive to the PathSeparator variable in the modelsim.ini file at the
time of creation of the control files. Be sure to use a consistent path separator throughout
this flow.
3. Run the simulation to generate the control files (.acc, .ocf, and .ocm).
run <time_step><time_unit>
When running the simulation, the Learn Flow tracks and records the objects required for
your PLI routines or used for commands executed before or after the run, for which you
need to retain visibility. Use your knowledge of the design and test bench to estimate
how long to run the simulation.
To ensure that the simulator records every possible access, you should run a complete
simulation (run -all).
4. Create an optimized design, retaining the visibility as defined in the control files. You
can determine which type of control file you wish to use. A command line example for
each type include:
vopt -f top_pli_learn.acc -o top_opt
vopt -ocf top_pli_learn.ocf -o top_opt
vopt -ocf top_pli_learn.ocm -o top_opt
The vopt command creates the optimized design, top_opt, and retains visibility to the
objects required by your PLI routines.
5. Simulate the optimized design.
vsim -pli mypli.sl top_opt
This performs the simulation on the optimized design, where you retained visibility to
the objects required by your PLI routines.
Results
The control files for the learn flow are text files that instruct vopt to retain visibility to objects
required by the specified PLI routines. All three file formats are considered to be non-lossy, in
that information about every object touched by the PLI during the -learn run is retained.
• .acc Learn Flow control file — This format (.acc) creates the information in the
traditional +acc format used by the vopt command. However, this format does not allow
for precise targeting of objects that you can get with the .ocf format.
• .ocf Learn Flow control file — This format (.ocf) is the most verbose and precisely
targeted of the three control files. It is suggested that you use this file for situations
where there is sparse access to objects. If you access every object in a module, this file
can get considerably large.
• .ocm Learn Flow control file — This format (.ocm) is similar to the .ocf format, except
that the file is factorized by design unit, which results in a smaller and more easily read
file, but provides less precise targeting.
These files are text-based and can be edited by anyone.
If you want to override the automatic disabling of the optimizations for modules containing PLI,
specify the -no_autoacc argument with the vsim command.
Suppose you want to dump all nets and registers in the entire design, and that you have the
following $dumpvars call in your test bench (no arguments to $dumpvars means to dump
everything in the entire design):
initial $dumpvars;
Then you need to optimize your design as follows to enable net and register access for all
modules in the design:
As another example, suppose you only need to dump nets (n) and registers (r) of a particular
instance in the design (the first argument of 1 means to dump just the variables in the instance
specified by the second argument):
Then you need to optimize your design as follows (assuming testbench.u1 is an instance of the
module design):
Finally, suppose you need to dump everything in the children instances of testbench.u1 (the first
argument of 0 means to also include all children of the instance):
To gain maximum performance, it may be necessary to enable the minimum required access
within the design.
• -sdfmin, -sdfmax, or -sdftyp on the vsim command line in the Two-Step Flow
The following arguments to vopt are useful when your design includes SDF:
• vopt +notimingchecks — Allows you to simulate your gate-level design without taking
into consideration timing checks, giving you performance benefits. For example:
vlog cells.v netlist.v tb.v
vopt tb -o tb_opt -O5 +checkALL +delay_mode_path +notimingchecks \
-debugCellOpt
vsim tb_opt
By default, vopt does not fix the TimingChecksOn generic in Vital models. Instead, it
lets the value float to allow for overriding at simulation time. If you prefer best
performance and no timing checks, use the +notimingchecks argument with vopt.
vopt +notimingchecks topmod
Modules with "(cell)" following their names are optimized cells. For example,
Module: top
Architecture: fast
In this case, the module named “top” was not optimized, and the module named “bottom” was.
Pre-Compiled Libraries
If the source code is unavailable for any of the modules referenced in a design, then you must
search libraries for the pre-compiled modules using the -L or -Lf arguments to the vopt
command. This optimizes pre-compiled modules the same as if the source code is available. The
optimized code for a pre-compiled module is written to the default ‘work’ library.
The vopt command automatically searches libraries specified in the `uselib directive (see
Verilog-XL uselib Compiler Directive). If your design uses `uselib directives exclusively to
reference modules in other libraries, then you do not need to specify library search arguments.
Projects simplify the process of compiling and simulating a design and are a great tool for
getting started with Questa SIM.
What are Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
What are the Benefits of Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Project Conversion Between Simulator Versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Getting Started with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Open a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Add Source Files to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Compile the Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Change Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Auto-Generate the Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Grouping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Simulate a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
The Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Creating a Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Organizing Projects with Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Adding a Project Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Set File Properties and Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
File Compilation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Setting Custom Double-click Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Access Projects from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Note
Compile order is maintained for HDL-only designs.
• Projects remove the necessity to re-establish compiler switches and settings for each
new session. Settings and compiler switches are stored in the project metadata as are
mappings to source files.
• Projects allow you to share libraries without copying files to a local directory. For
example, you can establish references to source files that are stored remotely or locally.
• Projects allow you to change individual parameters across multiple files. In previous
versions you could only set parameters one file at a time.
• Projects enable "what-if" analysis. For example, you can copy a project, manipulate the
settings, and rerun it to observe the new results.
• Projects reload the initial settings from the project .mpf file every time the project is
opened.
Related Topics
Creating a Simulation Configuration
Organizing Projects with Folders
3. Click OK.
Results
A blank Project window opens in the Main window (Figure 4-2)
Figure 4-2. Project Window Detail
and the Add Items to the Project dialog box opens. (Figure 4-3)
Figure 4-3. Add items to the Project Dialog
The name of the current project is displayed at the bottom bar of the Main window.
If you exit Questa SIM with a project open, Questa SIM automatically opens that same project
upon startup.
You can open a different or existing project by selecting File > Open and choosing Project Files
from the Files of type drop-down.
To close a project file, right-click in the Project window and select Close Project. This closes
the Project window but leaves the Library window open. You cannot close a project while a
simulation is in progress.
b. Specify a name, file type, and folder location for the new file.
When you select OK, the file is listed in the Project window. If you double-click the
name of the new file in the Project window a Source editor window will open, allowing
you to create source code.
2. Add an existing file
a. Select Project > Add to Project > Existing File.
Figure 4-5. Add file to Project Dialog
b. OK.
Results
The files are added to the Project window.
Note
You can send a list of all project filenames to the Transcript window by entering the
command project filenames. This command only works when a project is open.
Procedure
Select Compile > Compile All or right click in the Project window and select Compile >
Compile All.
Results
Once compilation is finished, click the Library window, expand the library work by clicking the
“+”, and you will see the compiled design units.
Figure 4-7. Click Plus Sign to Show Design Hierarchy
2. Drag the files into the correct order or use the up and down arrow buttons. Note that you
can select multiple files and drag them simultaneously.
You can display files in the Project window in alphabetical or in compilation order (by clicking
the column headings). Keep in mind that the order you see in the Project window is not
necessarily the order in which the files will be compiled.
Grouping Files
You can group two or more files in the Compile Order dialog so they are sent to the compiler at
the same time. For example, you might have one file with a bunch of Verilog define statements
and a second file that is a Verilog module. You would want to compile these two files together.
Procedure
1. Select the files you want to group.
Figure 4-9. Grouping Files
To ungroup files, select the group and click the Ungroup button.
Simulate a Design
After you have finished compiling the files contained in your design, you are ready to perform
simulation.
To simulate a design, do one of the following.
• Double-click the Name of an appropriate design object (such as a test bench module or
entity) in the Library window.
• Right-click the Name of an appropriate design object and choose Simulate from the
popup menu.
• Choose Simulate > Start Simulation from the main menu to open the Add Simulation
Configuration dialog box (Figure 4-10). Select a design unit in the Design tab. Set other
options in the VHDL, Verilog, Libraries, SDF, and Others tabs. Click OK to start the
simulation.
Figure 4-10. Add Simulation Configuration Dialog Box — Design Tab
A new Structure window, named sim, appears that shows the structure of the active simulation
(Figure 4-11).
At this point you are ready to run the simulation and analyze your results. You often do this by
adding signals to the Wave window and running the simulation for a given period of time. See
the QuestaSIM Tutorial for examples.
Objects
• Column titles
o Name – The name of a file or object.
o Status – Identifies whether a source file has been successfully compiled. Applies
only to VHDL or Verilog files. A question mark means the file hasn’t been compiled
or the source file has changed since the last successful compile; an X means the
compile failed; a check mark means the compile succeeded; a checkmark with a
yellow triangle behind it means the file compiled but there were warnings generated.
o Type – The file type as determined by registered file types on Windows or the type
you specify when you add the file to the project.
o Order – The order in which the file will be compiled when you execute a Compile
All command.
o Modified – The date and time of the last modification to the file.
You can hide or show columns by right-clicking on a column title and selecting or deselecting
entries.
Usage Notes
You can sort the list by any of the five columns. Click on a column heading to sort by that
column; click the heading again to invert the sort order. An arrow in the column heading
indicates which field the list is sorted by and whether the sort order is descending (down arrow)
or ascending (up arrow).
Procedure
1. Add a simulation configuration to the project by doing either of the following:
• Choose Project > Add to Project > Simulation Configuration from the main
menu.
• Right-click the Project window and choose Add to Project > Simulation
Configuration from the popup menu in the Project window.
This displays the dialog box shown in Figure 4-13.
Tip
Similar to a Simulation Configuration, an Optimization Configuration is a named
object that represents an optimized simulation. The procedure for creating and using
it is similar to the steps for Simulation Configuration, with the following differences:
Choose Project > Add to Project > Optimization Configuration.
Specify options in the Add Optimization Configuration dialog box.
6. Click OK
Results
• The simulation configuration is added to the Project window, as shown in Figure 4-14.
• As noted, the name of the new simulation configuration you have added is verilog_sim.
• To load the design, double-click on verilog_sim.
Figure 4-14. Simulation Configuration in the Project Window
2. Specify the Folder Name, the location for the folder, and click OK. The folder will be
displayed in the Project tab.
Examples
For example, when you add a file, you can select which folder to place it in.
If you want to move a file into a folder later on, you can do so using the Properties dialog for the
file. Simply right-click on the filename in the Project window and select Properties from the
context menu that appears. This will open the Project Compiler Settings Dialog (Figure 4-17).
Use the Place in Folder field to specify a folder.
On Windows platforms, you can also just drag-and-drop a file into a folder.
To customize specific files, select the file(s) in the Project window, right click on the file names,
and select Properties. The resulting Project Compiler Settings dialog (Figure 4-18) varies
depending on the number and type of files you have selected. If you select a single VHDL or
Verilog file, you will see the General tab, Coverage tab, and the VHDL or Verilog tab,
respectively.
If you select a SystemC file, you will see only the General tab.
In the General tab, you will see file properties such as Type, Location, and Size. If you select
multiple files, the file properties on the General tab are not listed. Finally, if you select both a
VHDL file and a Verilog file, you will see all tabs but no file information on the General tab.
• If two or more files have different settings for the same option, the checkbox in the
dialog will be "grayed out." If you change the option, you cannot change it back to a
"multi- state setting" without canceling out of the dialog. Once you click OK, Questa
SIM will set the option the same for all selected files.
• If you select a combination of VHDL and Verilog files, the options you set on the
VHDL and Verilog tabs apply only to those file types.
PSL assertions are supported in projects. You can click on the PSL File button in the VHDL and
Verilog tabs of the Project Compiler Settings dialog to add PSL files. Refer to Verification with
Assertions and Cover Directives for additional information.
Project Settings
To modify project settings, right-click anywhere within the Project window and choose Project
Settings from the popup menu. This opens the Project Settings Dialog Box.
The Project Settings Dialog Box allows you to select the compile output you want, the location
map, what to do with source files when you open or close a project, and how the double-click
action of your mouse will operate on specific file types.
Prerequisites
• Under the Location map section of the Project Settings dialog box (Figure 4-19), enable
the checkbox for Convert pathnames to softnames.
Procedure
1. Right-click anywhere within the Project window and select Project Settings
2. Enable the Convert pathnames to softnames within the Location map area of the
Project Settings dialog box (Figure 4-19).
Results
Once enabled, all pathnames currently in the project and any that are added later are then
converted to softnames.
During conversion, if there is no softname in the mgc location map matching the entry, the
pathname is converted in to a full (hardened) pathname. A pathname is hardened by removing
the environment variable or the relative portion of the path. If this happens, any existing
pathnames that are either relative or use environment variables are also changed: either to
softnames if possible, or to hardened pathnames if not.
Related Topics
Using Location Mapping
notepad %f
where the double-click behavior will substitute %f with the filename that was clicked, then
execute the string.
You can also use the project command from the command line to perform common operations
on projects.
VHDL designs are associated with libraries, which are objects that contain compiled design
units. SystemC, Verilog and SystemVerilog designs simulated within Questa SIM are compiled
into libraries as well.
Design Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Working with Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Verilog Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
VHDL Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Importing FPGA Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Protect Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Any number of libraries can be resource libraries during a compilation. You specify which
resource libraries will be used when the design is compiled, and there are rules to specify in
which order they are searched (refer to Verilog Resource Libraries and VHDL Resource
Libraries).
A common example of using both a working library and a resource library is one in which your
gate-level design and test bench are compiled into the working library and the design references
gate-level models in a separate resource library.
Creating a Library
You need to create a working design library before you run the compiler. This can be done from
either the command line or from the Questa SIM graphic interface.
Note
When you create a project, Questa SIM automatically creates a working design library.
Procedure
You have two ways to create a working design library:
• From the Questa SIM prompt or a UNIX/DOS prompt, use the vlib command:
vlib <directory_pathname>
• With the graphic interface, select File > New > Library.
Results
When you click OK, Questa SIM creates the specified library directory and writes a specially-
formatted file named _info into that directory. The _info file must remain in the directory to
distinguish it as a Questa SIM library.
The new map entry is written to the modelsim.ini file in the [Library] section. Refer to
modelsim.ini Variables for more information.
Note
Remember that a design library is a special kind of directory. The only way to create a
library is to use the Questa SIM GUI or the vlib command. Do not try to create libraries
using UNIX, DOS, or Windows commands.
Related Topics
Getting Started with Projects
modelsim.ini Variables
Library Size
The -smartdbgsym option for the vcom and vlog commands helps to reduce the size of
debugging database symbol files generated at compile time from the design libraries. With
-smartdbgsym, most design-units have their debugging symbol files generated on-demand by
vsim.
While using this flow provides significant savings in terms of the number of files in the library
and the overall size of the library, there are a few limitations: code coverage flows cannot
support this option, and there are limitations to `macro support in refresh flows.
Related Topics
vcom and vlog.
The Library window has a popup menu with various commands that you access by clicking
your right mouse button.
• Simulate — Loads and optimizes the selected design unit(s) and opens Structure (sim)
and Files windows. Related command line command is vsim -voptargs+acc.
• Simulate without Optimization — Loads the selected design unit(s) without
optimization. Related command line command is vsim -voptargs+acc.
• Simulate with full Optimization — Loads and optimizes the selected design unit(s).
Related command line command is vsim -vopt.
• Simulate with Coverage — Loads the selected design unit(s) and collects code
coverage data. Related command line command is vsim -coverage.
• Edit — Opens the selected design unit(s) in the Source window; or, if a library is
selected, opens the Edit Library Mapping dialog (refer to Map a Logical Name to a
Design Library).
• Refresh — Rebuilds the library image of the selected library without using source code.
Related command line command is vcom or vlog with the -refresh argument.
• Recompile — Recompiles the selected design unit(s). Related command line command
is vcom or vlog.
• Optimize — Optimizes the selected Verilog design unit(s). Related command line
command is vopt.
• Update — Updates the display of available libraries and design units.
• Create Wave — Opens a Wave window and loads the objects from the selected design
unit(s) as editable waveforms. Related command line command is wave create -pattern
none.
You can use the GUI, a command, or a project to assign a logical name to a design library. You
can also map multiple logical names to the same design library.
2. You may invoke this command from either a UNIX/DOS prompt or from the command
line within Questa SIM.
3. The vmap command adds the mapping to the library section of the modelsim.ini file.
b. Add a library logical name and pathname for the same library under the [Library]
section heading using the syntax. For example:
[Library]
work = /usr/rick/design
my_asic = /usr/rick/design
This would allow you to use either the logical name work or my_asic in a library or
use clause to refer to the same design library.
You can also create a UNIX symbolic link to the library using the host platform
command. For example:
ln -s <directory_pathname> <logical_name>
3. The vmap command can also be used to display the mapping of a logical library name to
a directory. To do this, enter the shortened form of the command:
vmap <logical_name>
Related Topics
modelsim.ini Variables
Move a Library
Individual design units in a design library cannot be moved. An entire design library can be
moved, however, by using standard operating system commands for moving a directory or an
archive.
[library]
asic_lib = /cae/asic_lib
work = my_work
others = /usr/questasim/modelsim.ini
You can specify only one “others” clause in the library section of a given modelsim.ini file.
The “others” clause only instructs the tool to look in the specified modelsim.ini file for a library.
It does not load any other part of the specified file.
If there are two libraries with the same name mapped to two different locations – one in the
current modelsim.ini file and the other specified by the “others” clause – the mapping specified
in the current .ini file will take effect.
vlib work
vlib asiclib
vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2
Note that the first compilation uses the -work asiclib argument to instruct the compiler to place
the results in the asiclib library rather than the default work library.
• Search libraries specified with -Lf arguments for the vlog, vopt, or vsim commands in
the order they appear on the command line.
• Search the library specified in the Verilog-XL uselib Compiler Directive section.
• Search libraries specified with -L arguments for the vlog, vopt, or vsim commands in the
order they appear on the command line.
• Search the work library.
• Search the library explicitly named in the special escaped identifier instance name.
• Search the libraries containing top design units that are not explicitly present in the set
of -L/-Lf options.
Note
The -libverbose argument for the vopt and vsim commands provide verbose messaging
about library search and resolution operations. The -libverbose=prlib option will print out
the -L or -Lf option used to locate each design unit.
Related Topics
SystemVerilog Multi-File Compilation
The normal library search rules do not work in this situation. For example, if you load the
design as follows:
both instantiations of cellX resolve to the lib1 version of cellX. On the other hand, if you specify
-L lib2 -L lib1, both instantiations of cellX resolve to the lib2 version of cellX.
To handle this situation, Questa SIM implements a special interpretation of the expression -L
work. When you specify -L work first in the search library arguments you are directing vsim to
search for the instantiated module or UDP in the library that contains the module that does the
instantiation.
Related Topics
LibrarySearchPath
vlog.
Predefined Libraries
Certain resource libraries are predefined in standard VHDL. The library named std contains the
packages standard, env, and textio, which should not be modified. The contents of these
packages and other aspects of the predefined language environment are documented in the IEEE
Standard VHDL Language Reference Manual, Std 1076.
A VHDL use clause can be specified to select particular declarations in a library or package that
are to be visible within a design unit during compilation. A use clause references the compiled
version of the package—not the source.
By default, every VHDL design unit is assumed to contain the following declarations:
To specify that all declarations in a library or package can be referenced, add the suffix .all to
the library/package name. For example, the use clause above specifies that all declarations in
the package standard, in the design library named std, are to be visible to the VHDL design unit
immediately following the use clause. Other libraries or packages are not visible unless they are
explicitly specified using a library or use clause.
Another predefined library is work, the library where a design unit is stored after it is compiled
as described earlier. There is no limit to the number of libraries that can be referenced, but only
one library is modified during compilation.
Related Topics
The TextIO Package
You may specify a specific design unit name with the -refresh argument to vcom and vlog in
order to regenerate a library image for only that design, but you may not specify a file name.
Procedure
1. From the GUI — Library > Regenerate. Updates the work library.
2. From the command line:
• VHDL design units in a library, use vcom with the -refresh argument. Updates the
work library.
• Verilog design units in a library, use vlog with the -refresh argument. Updates the
work library.
3. Update a different library. — Use either vcom or vlog with the -work <library>
argument to update a different library. For example, if you have a library named mylib
that contains both VHDL and Verilog design units:
vcom -work mylib -refresh
vlog -work mylib -refresh
Related Topics
Library Window Contents
vcom, and vlog.
Procedure
1. Select File > Import > Library to open the Import Library Wizard. (Figure 5-5)
Figure 5-5. Import Library Wizard
This chapter provides basic information on how to use VHDL for Questa SIM simulation.
Basic VHDL Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Compilation and Simulation of VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Usage Characteristics and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
The TextIO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
VITAL Usage and Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
VHDL Utilities Package (util) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Modeling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
VHDL Access Object Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
1. Compile your VHDL code into one or more libraries using the vcom command. Refer to
Compilation of a VHDL Design—the vcom Command for more information.
2. (Optional) Elaborate and optimize your design using the vopt command. Refer to the
chapter Optimizing Designs with vopt for more information.
3. Load your design with the vsim command. Refer to Simulation of a VHDL Design—the
vsim Command.
4. Simulate the loaded design, then debug as needed.
vlib work
Results
Running the vlib command creates a library named work. By default, compilation results are
stored in the work library.
Caution
The work library is actually a subdirectory named work. This subdirectory contains a
special file named _info. Do not create a VHDL library as a directory by using a system
command—always use the vlib command.
Related Topics
Design Libraries
You can simulate a design written with any of the following versions of VHDL:
• 1076-1987
• 1076-1993
• 1076-2002
• 1076-2008
To do so you need to compile units from each VHDL version separately.
The vcom command compiles using 1076 -2002 rules by default; use the -87, -93, or -2008
arguments to compile units written with version 1076-1987, 1076 -1993, or 1076-2008
respectively. You can also change the default by modifying the VHDL93 variable in the
modelsim.ini file (see modelsim.ini Variables for more information).
Note
Only a limited number of VHDL 1076-2008 constructs are currently supported.
Dependency Checking
You must re-analyze dependent design units when you change the design units they depend on
in the library. The vcom command determines whether or not the compilation results have
changed.
For example, if you keep an entity and its architectures in the same source file and you modify
only an architecture and recompile the source file, the entity compilation results will remain
unchanged. This means you do not have to recompile design units that depend on the entity.
The vcom command preserves both uppercase and lowercase letters of all user-defined object
names in a VHDL source file.
Usage Notes
• You can make the vcom command convert uppercase letters to lowercase by either of
the following methods:
o Use the -lower argument with the vcom command.
o Set the PreserveCase variable to 0 in your modelsim.ini file.
• The supplied precompiled packages in STD and IEEE have their case preserved. This
results in slightly different version numbers for these packages. As a result, you may
receive out-of-date reference messages when refreshing to the current release. To
resolve this, use vcom -force_refresh instead of vcom -refresh.
• Mixed language interactions
o Design unit names — Because VHDL and Verilog design units are mixed in the
same library, VHDL design units are treated as if they are lowercase. This is for
compatibility with previous releases. This also to provide consistent filenames in the
file system for make files and scripts.
o Verilog packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion.
o VHDL packages compiled with -mixedsvvh — not affected by VHDL uppercase
conversion; VHDL basic identifiers are still converted to lowercase for compatibility
with previous releases.
o FLI — Functions that return names of an object will not have the original case
unless the source is compiled using vcom -lower. Port and Generic names in the
mtiInterfaceListT structure are converted to lowercase to provide compatibility with
programs doing case sensitive comparisons (strcmp) on the generic and port names.
1. All VHDL names are case-insensitive, so Questa SIM always stores them in the library
in lowercase to be consistent and compatible with older releases.
2. When looking for a design unit in a library, Questa SIM ignores the VHDL case and
looks first for the name in lowercase. If present, Questa SIM uses it.
3. If no lowercase version of the design unit name exists in the library, then Questa SIM
checks the library, ignoring case.
a. If ONE match is found this way, Questa SIM selects that design unit.
b. If NO matches or TWO or more matches are found, Questa SIM does not select
anything.
The following examples demonstrate these rules. Here, the VHDL compiler needs to find a
design unit named Test. Because VHDL is case-insensitive, Questa SIM looks for "test"
because previous releases always converted identifiers to lowercase.
Example 1
Consider the following library:
work
entity test
Module TEST
The VHDL entity test is selected because it is stored in the library in lowercase. The original
VHDL could have contained TEST, Test, or TeSt, but the library always contains the entity as
"test."
Example 2
Consider the following library:
work
Module Test
No design unit named "test" exists, but "Test" matches when case is ignored, so Questa SIM
selects it.
Example 3
Consider the following library:
work
Module Test
Module TEST
No design unit named "test" exists, but both "Test" and "TEST" match when case is ignored, so
Questa SIM does not select either one.
Range and index checks are performed by default when you compile your design. You can
disable range checks (potentially offering a performance advantage) using arguments to the
vcom command. Or, you can use the NoRangeCheck and NoIndexCheck variables in the
[vcom] section of the modelsim.ini file to specify whether or not they are performed. Refer to
modelsim.ini Variables for more information.
Generally, these checks are disabled only after the design is known to be error-free. If you run a
simulation with range checking disabled, any scalar values that are out of range are indicated by
showing the value in the following format: ?(N) where N is the current value. For example, the
range constraint for STD_ULOGIC is 'U' to '-'; if the value is reported as ?(25), the value is out
of range because the type STD_ULOGIC value internally is between 0 and 8 (inclusive). A
similar thing will arise for integer subtypes and floating point subtypes. This generally indicates
that there is an error in the design that is not being caught because range checking was disabled.
Range checks in Questa SIM are slightly more restrictive than those specified by the VHDL
Language Reference Manual (LRM). Questa SIM requires any assignment to a signal to also be
in range whereas the LRM requires only that range checks be done whenever a signal is
updated. Most assignments to signals update the signal anyway, and the more restrictive
requirement allows Questa SIM to generate better error messages.
Subprogram Inlining
Questa SIM attempts to inline subprograms at compile time to improve simulation performance.
This happens automatically and should be largely transparent. However, you can disable
automatic inlining two ways:
mti_inhibit_inline Attribute
You can disable inlining for individual design units (a package, architecture, or entity) or
subprograms with the mti_inhibit_inline attribute. Follow these rules to use the attribute:
• Assign the value true to the attribute for the appropriate scope. For example, to inhibit
inlining for a particular function (for example, "foo"), add the following attribute
assignment:
attribute mti_inhibit_inline of foo : procedure is true;
To inhibit inlining for a particular package (for example, "pack"), add the following
attribute assignment:
attribute mti_inhibit_inline of pack : package is true;
If you have used the vopt command to optimize a VHDL design (see Optimizing Designs with
vopt), you can specify multiple optimized top design modules. For more information about
simulation with multiple optimized design modules, refer to the
<library_name>.<design_unit> argument to vsim.
The following example uses the vsim command to begin simulation on a design unit that has an
entity named my_asic and an architecture named structure:
Timing Specification
The vsim command can annotate a design using VITAL-compliant models with timing data
from an SDF file. You can specify delay by invoking vsim with the -sdfmin, -sdftyp, or -sdfmax
arguments.
The following example uses an SDF file named f1.sdf in the current work directory, and an
invocation of vsim annotating maximum timing values for the design unit my_asic:
By default, the timing checks within VITAL models are enabled (refer to VITAL Usage and
Compliance). You can disable them with the +notimingchecks argument. For example:
If you specify vsim +notimingchecks, the generic TimingChecksOn is set to FALSE for all
VITAL models with the Vital_level0 or Vital_level1 attribute. Setting this generic to FALSE
disables the actual calls to the timing checks along with anything else that is present in the
model's timing check block. In addition, if these models use the generic TimingChecksOn to
control behavior beyond timing checks, this behavior will not occur. This can cause designs to
simulate differently and provide different results.
By default, vopt does not fix the TimingChecksOn generic in VITAL models. Instead, it lets the
value float to allow for overriding at simulation time. If best performance and no timing checks
are desired, +notimingchecks should be specified with vopt.
• Select the appropriate version from the compiler options menu in the GUI
• Invoke vcom using the argument -87, -93, -2002, or -2008.
• Set the VHDL93 variable in the [vcom] section of the modelsim.ini file to one of the
following values:
- 0, 87, or 1987 for 1076-1987
- 1, 93, or 1993 for 1076-1993
- 2, 02, or 2002 for 1076-2002
- 3, 08, or 2008 for 1076-2008
Tip
Refer to Questa SIM Release Notes for the most current and comprehensive description of
differences between supported versions of the VHDL standard.
• VHDL-93 and VHDL-2002 — The only major problem between VHDL-93 and
VHDL-2002 is the addition of the keyword "PROTECTED". VHDL-93 programs which
use this as an identifier should choose a different name.
All other incompatibilities are between VHDL-87 and VHDL-93.
• VITAL and SDF — It is important to use the correct language version for VITAL.
VITAL2000 must be compiled with VHDL-93 or VHDL-2002. VITAL95 must be
compiled with VHDL-87. A typical error message that indicates the need to compile
under language version VHDL-87 is:
"VITALPathDelay DefaultDelay parameter must be locally static"
• Files — File syntax and usage changed between VHDL-87 and VHDL-93. In many
cases vcom issues a warning and continues:
"Using 1076-1987 syntax for file declaration."
In addition, when files are passed as parameters, the following warning message is
produced:
"Subprogram parameter name is declared using VHDL 1987 syntax."
This message often involves calls to endfile(<name>) where <name> is a file parameter.
• Files and packages — Each package header and body should be compiled with the
same language version. Common problems in this area involve files as parameters and
the size of type CHARACTER. For example, consider a package header and body with a
procedure that has a file parameter:
procedure proc1 ( out_file : out std.textio.text) ...
If you compile the package header with VHDL-87 and the body with VHDL-93 or
VHDL-2002, you will get an error message such as:
"** Error: mixed_package_b.vhd(4): Parameter kinds do not conform
between declarations in package header and body: 'out_file'."
But if you (1) have a function that takes an unconstrained array as a parameter, (2) pass
a concatenation expression as a formal argument to this parameter, and (3) the body of
the function makes assumptions about the direction or bounds of the parameter, then you
will get unexpected results. This may be a problem in environments that assume all
arrays have "downto" direction.
• xnor — "xnor" is a reserved word in VHDL-93. If you declare an xnor function in
VHDL-87 (without quotes) and compile it under VHDL-2002, you will get an error
message like the following:
** Error: xnor.vhd(3): near "xnor": expecting: STRING IDENTIFIER
by
"range nul downto 'ÿ' is null" -- range is nul downto y(umlaut)
• bit string literals — In VHDL-87 bit string literals are of type bit_vector. In VHDL-93
they can also be of type STRING or STD_LOGIC_VECTOR. This implies that some
expressions that are unambiguous in VHDL-87 now become ambiguous is VHDL-93. A
typical error message is:
** Error: bit_string_literal.vhd(5): Subprogram '=' is ambiguous.
Suitable definitions exist in packages 'std_logic_1164' and
'standard'.
• VHDL-2008 packages — Questa SIM does not provide VHDL source for VHDL-2008
IEEE-defined standard packages because of copyright restrictions. You can obtain
VHDL source from http://standards.ieee.org//downloads/1076/1076-2008/ for the
following packages:
IEEE.fixed_float_types
IEEE.fixed_generic_pkg
IEEE.fixed_pkg
IEEE.float_generic_pkg
IEEE.float_pkg
IEEE.MATH_REAL
IEEE.MATH_COMPLEX
IEEE.NUMERIC_BIT
IEEE.NUMERIC_BIT_UNSIGNED
IEEE.NUMERIC_STD
IEEE.NUMERIC_STD_UNSIGNED
IEEE.std_logic_1164
IEEE.std_logic_textio
the default names of the blocks in the design hierarchy would be:
This name appears in the GUI to identify the blocks. You should use this name with any
commands when referencing a block that is part of the simulation environment. The format of
the name is based on the VHDL Language Reference Manual P1076-2008 section 16.2.5
Predefined Attributes of Named Entities.
If the type of the generate parameter is an enumeration type, the value within the parenthesis
will be an enumeration literal of that type; such as: g1(red).
In releases prior to the 6.6 series, this default name was controlled by the GenerateFormat
modelsim.ini file variable would have appeared as:
All previously-generated scripts using this old format should work by default. However, if not,
you can use the GenerateFormat and OldVhdlForGenNames modelsim.ini variables to ensure
that the old and current names are mapped correctly.
Note
In Verilog, this representation of time units is referred to as precision or timescale.
1 fs, 10 fs, 100 fs 1 ps, 10 ps, 100 ps 1 ns, 10 ns, 100 ns 1 us, 10 us, 100 us 1 ms, 10 ms, 100 ms
1 s, 10 s, 100 s
Note that you need to take care in specifying a resolution value larger than a delay value in your
design—delay values in that design unit are rounded to the closest multiple of the resolution. In
the example above, a delay of 4 ps would be rounded down to 0 ps.
Default Binding
By default, Questa SIM performs binding when you load the design with the vsim command.
The advantage of this default binding at load time is that it provides more flexibility for compile
order. Namely, VHDL entities do not necessarily have to be compiled before other entities/
architectures that instantiate them.
However, you can force Questa SIM to perform default binding at compile time instead. This
may allow you to catch design errors (for example, entities with incorrect port lists) earlier in
the flow. Use one of these two methods to change when default binding occurs:
• If performing default binding at load time, search the libraries specified with the -Lf
argument to vsim.
• If a directly visible entity has the same name as the component, use it.
• If an entity would be directly visible in the absence of the component declaration, use it.
• If the component is declared in a package, search the library that contained the package
for an entity with the same name.
• If a configuration declaration contains library and use clauses, use them.
If none of these methods are successful, Questa SIM then does the following:
When you specify the RequireConfigForAllDefaultBinding, Questa SIM requires the user to
provide a configuration specification or component configuration in order to bind an entity with
an architecture. You must explicitly bind all components in the design through either
configuration specifications or configurations. If an explicit binding is not fully specified,
defaults for the architecture, port maps, and generic maps will be used as needed.
Delta Delays
Event-based simulators such as Questa SIM may process many events at a given simulation
time. Multiple signals may need updating, statements that are sensitive to these signals must be
executed, and any new events that result from these statements must then be queued and
executed as well. The steps taken to evaluate the design without advancing simulation time are
referred to as "delta times" or just "deltas."
Figure 6-1 illustrates the process for VHDL designs. This process continues until the end of
simulation time.
This mechanism in event-based simulators may cause unexpected results. Consider the
following code fragment:
In this example, there are two synchronous processes, one triggered with clk and the other with
clk2. Consider the unexpected situation of the signals changing in the clk2 process on the same
edge as they are set in the clk process. As a result, the value of inp appears at s1 rather than s0.
During simulation an event on clk occurs (from the test bench). From this event, Questa SIM
performs the "clk2 <= clk" assignment and the process which is sensitive to clk. Before
advancing the simulation time, Questa SIM finds that the process sensitive to clk2 can also be
run. Since there are no delays present, the effect is that the value of inp appears at s1 in the same
simulation cycle.
In order to correct this and get the expected results, you must do one of the following:
The best way to debug delta delay problems is observe your signals in the Wave Window or List
Window. There you can see how values change at each delta time.
If you receive an iteration limit error, first increase the iteration limit and try to continue
simulation. and then try single stepping to attempt to determine which instances in the design
may be oscillating or run the simulation again with the vsim +autofindloop argument.
You can set the iteration limit from the Simulate > Runtime Options menu or by modifying
the IterationLimit variable in the modelsim.ini. See modelsim.ini Variables for more
information on modifying the modelsim.ini file.
If the problem persists, look for zero-delay loops. Run the simulation and look at the source
code when the error occurs. Use the step button to step through the code and see which signals
or variables are continuously oscillating. Two common causes are a loop that has no exit, or a
series of gates with zero delay where the outputs are connected back to the inputs.
USE std.textio.all;
USE std.textio.all;
ENTITY simple_textio IS
END;
For newer versions of IEEE Std 1076, supported syntax for a file declaration is the following:
You can specify a full or relative path as the file_logical_name. For example (VHDL 1987):
Normally, if a file is declared within an architecture, process, or package, the file is opened
when you start the simulator and is closed when you exit from it. If a file is declared in a
subprogram, the file is opened when the subprogram is called and closed when execution
RETURNs from the subprogram.
Alternatively, you can delay the opening of files until the first read or write by setting the
DelayFileOpen variable in the modelsim.ini file. Also, you can control the number of
concurrently open files with the ConcurrentFileLimit variable. These variables help you
manage a large number of files during simulation. See modelsim.ini Variables for more details.
For IEEE Std 1076-1987, TextIO package contains the following file declarations:
For newer versions of IEEE Std 1076, TextIO package contains these file declarations:
In the TextIO package, the WRITE procedure is overloaded for the types STRING and
BIT_VECTOR. These lines are reproduced here:
The error occurs because the argument "hello" could be interpreted as a string or a bit vector,
but the compiler is not allowed to determine the argument type until it knows which function is
being called.
This call is even more ambiguous, because the compiler could not determine, even if allowed to,
whether the argument "010101" should be interpreted as a string or a bit vector.
The WRITE_STRING procedure simply defines the value to be a STRING and calls the
WRITE procedure, but it serves as a shell around the WRITE procedure that solves the
overloading problem. For further details, refer to the WRITE_STRING procedure in the io_utils
package, which is located in the file <install_dir>/questasim/examples/vhdl/io_utils/
io_utils.vhd.
To expand this functionality, Questa SIM supplies hexadecimal routines in the package io_utils,
which is located in the file <install_dir>/questasim/examples/gui/io_utils.vhd. To use these
routines, compile the io_utils package and then include the following use clauses in your VHDL
source code:
use std.textio.all;
use work.io_utils.all;
Dangling Pointers
Dangling pointers are easily created when using the TextIO package, because WRITELINE de-
allocates the access type (pointer) that is passed to it. Following are examples of good and bad
VHDL coding styles:
Based on an ISAC-VASG recommendation the ENDLINE function has been removed from the
TextIO package. The following test may be substituted for this function:
(L = NULL) OR (L’LENGTH = 0)
Note the this function is commented out of the standard TextIO package. This is because the
ENDFILE function is implicitly declared, so you can use it with files of any type, not just files
of type TEXT.
After making these declarations, you then include the identifier for this file ("myinput" in this
example) in the READLINE or WRITELINE procedure call.
<install_dir>/examples/gui/stimulus.vhd
http://www.ieee.org
/vital1995
/vital2000
LIBRARY vital1995;
USE vital1995.vital_primitives.all;
USE vital1995.vital_timing.all;
USE vital1995.vital_memory.all;
Note that if your design uses two libraries—one that depends on vital95 and one that depends on
vital2000—then you will have to change the references in the source code to vital2000.
Changing the library mapping will not work.
Questa SIM VITAL built-ins are generally updated as new releases of the VITAL packages
become available.
VITAL Compliance
A simulator is VITAL-compliant if it implements the SDF mapping and if it correctly simulates
designs using the VITAL packages—as outlined in the VITAL Model Development
Specification. Questa SIM is compliant with IEEE Std 1076.4-2002, IEEE Standard for VITAL
ASIC Modeling Specification. In addition, Questa SIM accelerates the VITAL_Timing,
VITAL_Primitives, and VITAL_memory packages. The optimized procedures are functionally
equivalent to the IEEE Std 1076.4 VITAL ASIC Modeling Specification (VITAL 1995 and
2000).
If you are using VITAL 2.2b, you must turn off the compliance checking either by not setting
the attributes, or by invoking vcom with the argument -novitalcheck.
You can turn off compliance checking for VITAL 1995 and VITAL 2000 as well, but it is
strongly recommended that you leave checking on to ensure optimal simulation.
• Signal q_w is read by the VITAL process but is NOT in the sensitivity list (1076.4
section 6.4.3)
The first two warnings are minor cases where the body of the VITAL 1995 LRM is slightly
stricter than the package portion of the LRM. Since either interpretation will provide the same
simulation results, both of these cases are provided as warnings.
The last warning is a relaxation of the restriction on reading an internal signal that is not in the
sensitivity list. This is relaxed only for the CheckEnabled parameters of the timing checks, and
only if they are not read elsewhere.
You can control the visibility of VITAL compliance-check warnings in your vcom transcript.
To suppress them, use the vcom -nowarn command. For example, vcom -nowarn 6, where the
number 6 represents the warning level to be displayed as part of the warning: ** WARNING:
[6]. You can also add the following line to your modelsim.ini file in the vcom section:
[vcom]
Show_VitalChecksWarnings = 0
behavior process and permits single stepping through the VITAL procedures to debug
your model. Also, all of the VITAL data can be viewed in the Locals or Objects pane.
• -O0 | -O4
Lowers the optimization to a minimum with -O0 (capital oh zero). Optional. Use this to
work around bugs, increase your debugging visibility on a specific cell, or when you
want to place breakpoints on source lines that have been optimized out.
Enable optimizations with -O4 (default).
• -debugVA
Prints a confirmation if a VITAL cell was optimized, or an explanation of why it was
not, during VITAL level-1 acceleration.
library modelsim_lib;
use modelsim_lib.util.all;
get_resolution
The get_resolution utility returns the current simulator resolution as a real number. For
example, a resolution of 1 femtosecond (1 fs) corresponds to 1e-15.
Syntax
resval := get_resolution;
Arguments
None
Return Values
Related functions
• to_real()
• to_time()
Examples
If the simulator resolution is set to 10ps, and you invoke the command:
resval := get_resolution;
init_signal_driver()
The init_signal_driver() utility drives the value of a VHDL signal or Verilog net onto an
existing VHDL signal or Verilog net. This allows you to drive signals or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench).
init_signal_spy()
The init_signal_spy() utility mirrors the value of a VHDL signal or Verilog register/net onto an
existing VHDL signal or Verilog register. This allows you to reference signals, registers, or nets
at any level of hierarchy from within a VHDL architecture (such as a test bench).
signal_force()
The signal_force() utility forces the value specified onto an existing VHDL signal or Verilog
register or net. This allows you to force signals, registers, or nets at any level of the design
hierarchy from within a VHDL architecture (such as a test bench). A signal_force works the
same as the force command when you set the modelsim.ini variable named ForceSigNextIter to
1. The variable ForceSigNextIter in the modelsim.ini file can be set to honor the signal update
event in next iteration for all force types. Note that the signal_force utility cannot issue a
repeating force.
signal_release()
The signal_release() utility releases any force that was applied to an existing VHDL signal or
Verilog register or net. This allows you to release signals, registers, or nets at any level of the
design hierarchy from within a VHDL architecture (such as a test bench). A signal_release
works the same as the noforce command.
to_real()
The to_real() utility converts the physical type time value into a real value with respect to the
current value of simulator resolution. The precision of the converted value is determined by the
simulator resolution.
For example, if you were converting 1900 fs to a real and the simulator resolution was ps, then
the real value would be rounded to 2.0 (that is, 2 ps).
Syntax
realval := to_real(timeval);
Returns
Arguments
Related functions
• get_resolution
• to_time()
Examples
If the simulator resolution is set to ps, and you enter the following function:
then the value returned to realval would be 12990.0. If you wanted the returned value to be in
units of nanoseconds (ns) instead, you would use the get_resolution function to recalculate the
value:
If you wanted the returned value to be in units of femtoseconds (fs), you would enter the
function this way:
to_time()
The to_time() utility converts a real value into a time value with respect to the current simulator
resolution. The precision of the converted value is determined by the simulator resolution. For
example, if you converted 5.9 to a time and the simulator resolution was 1 ps, then the time
value would be rounded to 6 ps.
Syntax
timeval := to_time(realval);
Returns
Arguments
Related functions
• get_resolution
• to_real()
Examples
If the simulator resolution is set to 1 ps, and you enter the following function:
timeval := to_time(72.49);
Modeling Memory
If you want to model a memory with VHDL using signals, you may encounter either of the
following common problems with simulation:
• Memory allocation error, which typically means the simulator ran out of memory and
failed to allocate enough storage.
• Very long times to load, elaborate, or run.
These problems usually result from the fact that signals consume a substantial amount of
memory (many dozens of bytes per bit), all of which must be loaded or initialized before your
simulation starts.
As an alternative, you can model a memory design using variables or protected types instead of
signals, which provides the following performance benefits:
• Reduced storage required to model the memory, by as much as one or two orders of
magnitude
• Reduced startup and run times
• Elimination of associated memory allocation errors
Examples of Different Memory Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Effects on Performance by Canceling Scheduled Events. . . . . . . . . . . . . . . . . . . . . . . . . 236
library ieee;
use ieee.numeric_bit.ALL;
entity test is
end test;
• Example 6-1 contains two VHDL architectures that demonstrate recommended memory
models: style_93 uses shared variables as part of a process, style_87 uses For
comparison, a third architecture, bad_style_87, shows the use of signals.
The style_87 and style_93 architectures work with equal efficiency for this example.
However, VHDL 1993 offers additional flexibility because the RAM storage can be
shared among multiple processes. This example shows a second process that initializes
the memory—you could add other processes to create a multi-ported memory.
• Example 6-2 is a package (named conversions) that is included by the memory model in
Example 6-1.
• Example 6-3 is provided for completeness—it shows protected types using VHDL 2002.
Note that using protected types offers no advantage over shared variables.
Example 6-1. Memory Model Using VHDL87 and VHDL93 Architectures
-------------------------------------------------------------------------
-- Source: memory.vhd
-- Component: VHDL synchronous, single-port RAM
-- Remarks: Provides three different architectures
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.conversions.all;
entity memory is
generic(add_bits : integer := 12;
data_bits : integer := 32);
port(add_in : in std_ulogic_vector(add_bits-1 downto 0);
data_in : in std_ulogic_vector(data_bits-1 downto 0);
data_out : out std_ulogic_vector(data_bits-1 downto 0);
cs, mwrite : in std_ulogic;
do_init : in std_ulogic);
subtype word is std_ulogic_vector(data_bits-1 downto 0);
constant nwords : integer := 2 ** add_bits;
type ram_type is array(0 to nwords-1) of word;
end;
library ieee;
use ieee.std_logic_1164.all;
package conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural;
function natural_to_sulv(n, bits : natural) return
std_ulogic_vector;
end conversions;
if failure then
return 0;
else
return n;
end if;
end sulv_to_natural;
end conversions;
-------------------------------------------------------------------------
-- Source: sp_syn_ram_protected.vhd
-- Component: VHDL synchronous, single-port RAM
-- Remarks: Various VHDL examples: random access memory (RAM)
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sp_syn_ram_protected IS
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk : IN std_logic;
outclk : IN std_logic;
we : IN std_logic;
addr : IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END sp_syn_ram_protected;
BEGIN
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
memory.write(data_in, addr);
END IF;
END IF;
END intarch;
-------------------------------------------------------------------------
-- Source: ram_tb.vhd
-- Component: VHDL test bench for RAM memory example
-- Remarks: Simple VHDL example: random access memory (RAM)
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram_tb IS
END ram_tb;
-------------------------------------------
-- Component declaration single-port RAM
-------------------------------------------
COMPONENT sp_syn_ram_protected
GENERIC (
data_width : positive := 8;
addr_width : positive := 3
);
PORT (
inclk : IN std_logic;
outclk : IN std_logic;
we : IN std_logic;
addr : IN unsigned(addr_width-1 DOWNTO 0);
data_in : IN std_logic_vector(data_width-1 DOWNTO 0);
data_out : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END COMPONENT;
-------------------------------------------
BEGIN
---------------------------------------------------
-- instantiations of single-port RAM architectures.
-- All architectures behave equivalently, but they
-- have different implementations. The signal-based
-- architecture (rtl) is not a recommended style.
---------------------------------------------------
spram1 : entity work.sp_syn_ram_protected
GENERIC MAP (
data_width => 8,
addr_width => 12)
PORT MAP (
inclk => clk,
outclk => clk,
we => we,
addr => addr(11 downto 0),
data_in => data_in1,
data_out => data_sp1);
-------------------------------------------
-- clock generator
-------------------------------------------
clock_driver : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_pd / 2;
LOOP
clk <= '1', '0' AFTER clk_pd / 2;
WAIT FOR clk_pd;
END LOOP;
END PROCESS;
-------------------------------------------
-- data-in process
-------------------------------------------
datain_drivers : PROCESS(data_in)
BEGIN
data_in1 <= std_logic_vector(data_in(7 downto 0));
END PROCESS;
-------------------------------------------
-- simulation control process
-------------------------------------------
ctrl_sim : PROCESS
BEGIN
FOR i IN 0 TO 1023 LOOP
we <= '1';
data_in <= to_unsigned(9000 + i, data_in'length);
addr <= to_unsigned(i, addr'length);
inaddr <= to_unsigned(i, inaddr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';
we <= '0';
addr <= to_unsigned(i, addr'length);
outaddr <= to_unsigned(i, outaddr'length);
WAIT UNTIL clk'EVENT AND clk = '0';
WAIT UNTIL clk'EVENT AND clk = '0';
END LOOP;
ASSERT false
REPORT "### End of Simulation!"
SEVERITY failure;
END PROCESS;
END testbench;
At time 0, process p makes an event for time 10ms. When synch goes to 1 at 10 ns, the event at
10 ms is marked as canceled but not deleted, and a new event is scheduled at 10ms + 10ns. The
canceled events are not reclaimed until time 10ms is reached and the canceled event is
processed. As a result, there will be 500000 (10ms/20ns) canceled but un-deleted events. Once
10ms is reached, memory will no longer increase because the simulator will be reclaiming
events as fast as they are added.
For projected waveforms, the following would behave the same way:
Tip
You can use the examine and the describe commands in the normal manner for variables
and objects displayed in a Questa SIM window.
In general, such designated objects have a limited lifespan, which corresponds to the VHDL
allocator "new." This allocator creates one at a particular time, and the deallocate() procedure
that destroys one at a particular time, as the simulation runs. Each designated object receives its
unique name when the new allocation occurs; the name is unique over the life of the simulation.
• access object — Thus, the term "access object" means the designated object of an access
variable. An access object is created with the VHDL allocator “new,” which returns the
access value. This value is then assigned to an access variable, either in an assignment
statement or an association element in a subprogram call.
• AIID — access instance identifier. Each access object gets a unique identifier, its access
instance identifier, which is unfortunately named in the manner of class instance
identifier (CIID) for SystemVerilog (which is also known as a handle—refer to
SystemVerilog Class Debugging).
• DOID — dynamic object identifier. The name of a VHDL an access object. The terms
DOID and AIID are interchangeable. Access object names have two different forms,
depending on whether or not the vsim-accessobjdebug command is in effect. Refer to
Default Behavior—Logging and Debugging Disabled and Logging and Debugging
Enabled.
• deep logging — If an access variable is logged, then the DOID of any access object that
it points to during the simulation is also logged automatically. Any embedded access
type subelements of an access type are also logged automatically. Similarly, logging an
access object by name (its access instance identifier) will log not only the access object
itself but any embedded access objects (if the outer access object is of a composite type
that contains a subelement of an access type).
• prelogging — The logging of an access object by name, even if you have not declared it
(that is, it does not yet exist at the time an "add log" command is issued but you can still
log it by name). This produces useful results only if you use a DOID (dynamic object
identifier) that matches the name of an access object that will exist at some future
simulation time.
In this example, subtype foo is called the designated subtype, and the base type of the
designated subtype is called the designated type. The designated type of an access type cannot
be a file type or a protected type. Note that composite types cannot contain elements that are of
file types or protected types, so if the designated type of an access type is a composite type, it
will not have any file type or protected type sub-elements.
Limitations
It is not possible to log a variable (access variable or not) that is declared in the declarative
region of a FUNCTION or PROCEDURE. This is not really a limitation of this new access
object debug, but it is a general limitation. Thus, only shared variables and variables that are
declared in a PROCESS declarative region can be logged (whether access variables or not).
The List window can display the value of an access variable, but cannot display the
corresponding access objects.
Currently, while variables of type STD.TEXTIO.LINE can be logged, the access objects, which
will be of type STD.STANDARD.STRING, will not be logged if such a variable is logged.
Thus, "deep logging" of variables of type LINE does not occur.
Optimized designs (those created with the vopt command in either the 2-step or 3-step flow)
may contain access variables with reduced or eliminated visibility. This will affect the ability to
log variables in optimized designs. The recommended approach is to retain complete visibility
of an access variable of interest by judicious use of the vopt accessibility arguments. Otherwise,
attempting to log a diminished-visibility access variable will produce a Warning message
stating that the variable cannot be logged.
You can use and update the value of the access object by using the VHDL keyword “all” as a
suffix to the access variable name.
Examples
• Declare an access variable “v1” that designates some access object. The value of v1 will
display as [10001]. This name is for display only—it cannot be used as input to any
command that expects an object name. However, it is a unique identifier for any access
object that the design may produce. Note that this value replaces any hexadecimal
address-based value that may have been displayed in previous versions of Questa SIM.
• Use variable v1 with the VHDL keyword “all” as an argument to the examine command,
which returns the current value of the access object. This essentially dereferences the
object.
examine v1.all
With logging enabled for a VHDL access variable, display-only names (such as [10001]) take
on a different form, as follows:
Tip
An alternative method would be to use the add wave command with the DOID of the access
object. For example:
Example
An example of a logged access variable in this form:
@ptr@1
Related Topics
Waveform Analysis
Wave Window
Enabled The returned value of the access object will be the logged name that you assigned (as
per Logging and Debugging Enabled).
Tip
You can also use the describe command with an access variable in a similar way as with the
examine command (for example, describe v1.all). This command returns a more qualitative
description of the variable’s characteristics.
Depending on the data type of the access object, you can use the examine command in different
ways to obtain a variety of access object values. In particular, you can use examine to obtain
object values for the following VHDL data types:
• Integer
• String
• Record
The following examples show how to use access variables of these different types to specify
arguments to the examine command, with access object logging disabled and enabled. Each
example uses an access variable named v1, declared as one of these data types, and an access
object named @ptr@1.
Integer
Table 6-1 shows examples of how to use v1 and @ptr@1 as arguments to the examine
command to obtain the current value of the access object, @ptr@1, which is an integer.
Table 6-1. Using the examine Command to Obtain VHDL Integer Data
Command Value Returned with Value Returned with
Logging Disabled Logging Enabled
(vsim -noaccessobjdebug) (vsim -accessobjdebug)
examine v1 [10001] @ptr@1
Table 6-1. Using the examine Command to Obtain VHDL Integer Data (cont.)
Command Value Returned with Value Returned with
Logging Disabled Logging Enabled
(vsim -noaccessobjdebug) (vsim -accessobjdebug)
examine v1.all 5 5
examine @ptr@1 error 5
Here, the current integer value is 5. Note that an error results when attempting to use @ptr@1 as
an examine argument with access object logging disabled.
String
Table 6-2 shows examples of how to use v1 and @ptr@1 as arguments to the examine
command to obtain the current value of the access object, @ptr@1, which is a string.
Table 6-2. Using the examine Command to Obtain VHDL String Data
Command Value Returned with Value Returned with
Logging Disabled Logging Enabled
(vsim -noaccessobjdebug) (vsim -accessobjdebug)
examine v1 [10001] @ptr@1
examine v1.all "abcdef" "abcdef"
examine v1(4) ‘d’ ‘d’
examine v1.all(4) ‘d’ ‘d’
examine @ptr@1 error "abcdef"
examine @ptr@1(4) error ‘d’
Here, the value of the entire string is abcdef. Note that specifying an index of 4 in the string
obtains the fourth character of the string, d. Also, note that an error results when attempting to
use @ptr@1 as an examine argument with access object logging disabled.
Record
A VHDL record is composite data type, consisting of multiple fields (also referred to as
elements) each of which contains its own separate data. Record fields may be of the same or of
different types.
Table 6-3 shows examples of using the examine command on a record object with an integer
field (f1) and a string field (f2).
Table 6-3. Using the examine Command to Obtain VHDL Record Data
Command Value Returned with Value Returned with
Logging Disabled Logging Enabled
(vsim -noaccessobjdebug) (vsim -accessobjdebug)
examine v1 [10001] @ptr@1
examine v1.all {5, "abcdef"} {5, "abcdef"}
examine v1.f1 5 5
examine v1.all.f1 5 5
examine @[email protected] error 5
Here, the current value of integer field f1 is 5, and the current value of string field f2 is abcdef.
Note that an error results when attempting to use @ptr@1 as an examine argument with access
object logging disabled.
Related Topics
describe
examine
This chapter describes how to compile and simulate Verilog and SystemVerilog designs with
Questa SIM.
Standards, Nomenclature, and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Basic Verilog Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
SystemVerilog System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Analog Mixed-Signal for Verilog and SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Sparse Memory Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Unmatched Virtual Interface Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Verilog PLI and SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
SystemVerilog Class Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
OVM-Aware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
UVM-Aware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Questa SIM implements the Verilog and SystemVerilog languages as defined by the following
standards:
Note
Questa SIM supports partial implementation of SystemVerilog IEEE Std 1800-2012.
For release-specific information on currently supported implementation, refer to the
following text file located in the Questa SIM installation directory: <install_dir>/docs/
technotes/sysvlog.note
The standard for SystemVerilog specifies extensions for a higher level of abstraction for
modeling and verification with the Verilog hardware description language (HDL).
This standard includes design specification methods, embedded assertions language, testbench
language including coverage and assertions application programming interface (API), and a
direct programming interface (DPI).
Note
The term “Language Reference Manual” (or LRM) is often used informally to refer
to the current IEEE standard for Verilog or SystemVerilog.
for Loops
Questa SIM allows using Verilog syntax that omits any or all three specifications of a for loop
— initialization, termination, increment. This is similar to allowed usage in C and is shown in
the following examples.
Note
If you use this variation, a suppressible warning (2252) is displayed, which you can change
to an error if you use the vlog -pedanticerrors command.
For example:
`define 11 22
`define q(s) `" s `"
module defineIdent;
string s2 = `q( `11 );
int i = `11;
initial begin
$display("i: %d\n", i);
#10;
$display("s2: %s\n", s2);
end
endmodule
Also, the following compiler directives accept integer names as well as IEEE-1800 Language
Reference Manual macro names:
‘define
‘else
‘elsif
‘endif
‘fdef
‘undefine
1. Compile your Verilog code into one or more libraries using the vlog command. See
Verilog Compilation for details.
2. (Optional) Elaborate and optimize your design using the vopt command. For more
information, refer to Chapter 3, Optimizing Designs with vopt and Optimization
Considerations for Verilog Designs.
3. Load your design with the vsim command. Refer to Verilog Simulation.
4. Simulate the loaded design and debug as needed.
Verilog Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Initializing enum Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Library Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SystemVerilog Multi-File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Verilog-XL Compatible Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Verilog Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Verilog Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Initializing Registers and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Verilog Compilation
Compiling your Verilog design for the first time is a two-step process.
1. Create a working library with the vlib command, or select File > New > Library.
2. Compile the design using the vlog command, or select Compile > Compile.
Alternatively, if you have previously been using NCSim, Questa SIM provides an alternative
flow that combines the compile, optimize, and simulate phases into one command. Refer to the
qverilog command for more information.
For example, the command vlib work creates a library named work. By default
compilation results are stored in the work library.
The work library is actually a subdirectory named work. This subdirectory contains a
special file named _info. Do not create libraries using UNIX commands – always use the
vlib command.
See Design Libraries for additional information on working with libraries.
Procedure
Use the vlog command or the Compile > Compile menu selection to invoke the Verilog
compiler.
As the design compiles, the resulting object code for modules and user-defined
primitives (UDPs) is generated into a library. As noted above, the compiler places
results into the work library by default. You can specify an alternate library with the -
work argument of the vlog command.
The following example shows how to use the vlog command to invoke the Verilog
compiler:
vlog top.v +libext+.v+.u -y vlog_lib
After compiling top.v, vlog searches the vlog_lib library for files with modules with the
same name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u
implies filenames with a .v or .u suffix (any combination of suffixes may be used). Only
referenced definitions are compiled. Compressed SystemVerilog source files (.gz
extension, compressed with zlib) are accepted.
• Any file within the design contains the .sv file extension
• You use the -sv argument with the vlog command
The following examples of the vlog command show how to enable SystemVerilog features and
keywords in Questa SIM:
In the first example, the .sv extension for testbench automatically causes Questa SIM to parse
SystemVerilog keywords. In the second example, the -sv argument enables SystemVerilog
features and keywords.
Keyword Compatibility
One of the primary goals of SystemVerilog standardization has been to ensure full backward
compatibility with the Verilog standard. Questa recognizes all reserved keywords listed in
Table B-1 in Annex B of IEEE Std 1800-2012.
The following reserved keywords have been added since IEEE Std 1800-2009:
If you use or produce SystemVerilog code that uses any identifiers from a previous release in
which they were not considered reserved keywords, you can do either of the following to avoid
a compilation error:
• Use a different set of strings in your design. You can add one or more characters as a
prefix or suffix (such as an underscore, _) to the string, which will cause the string to be
read in as an identifier and not as a reserved keyword.
• Use the SystemVerilog pragmas `begin_keywords and `end_keywords to define regions
where only the older keywords are recognized.
reads in a.v and d.v as a Verilog files and reads in b.sv and c.svh as SystemVerilog files.
By default, Questa SIM instructs the compiler to treat all files within a compilation command
line as separate compilation units (single-file compilation unit mode, which is the equivalent of
using vlog -sfcu).
Questa SIM would group these source files into three compilation units:
• Run vlog -enumfirstinit when compiling and run vsim -enumfirstinit when simulating.
• Set EnumBaseInit = 0 in the modelsim.ini file.
Incremental Compilation
Questa SIM supports incremental compilation of Verilog designs—there is no requirement to
compile an entire design in one invocation of the compiler.
You are not required to compile your design in any particular order (unless you are using
SystemVerilog packages; see Note below) because all module and UDP instantiations and
external hierarchical references are resolved when the design is loaded by the simulator.
Note
Compilation order may matter when using SystemVerilog packages. As stated in the section
Referencing data in packages of IEEE Std 1800-2005: “Packages must exist in order for the
items they define to be recognized by the scopes in which they are imported.”
Incremental compilation is made possible by deferring these bindings, and as a result some
errors cannot be detected during compilation. Commonly, these errors include: modules that
were referenced but not compiled, incorrect port connections, and incorrect hierarchical
references.
Contents of testbench.sv
module testbench;
timeunit 1ns;
timeprecision 10ps;
bit d=1, clk = 0;
wire q;
initial
for (int cycles=0; cycles < 100; cycles++)
#100 clk = !clk;
Contents of design.v:
Questa
SIM> vlog testbench.sv
.
# Top level modules:
# testbench
Questa
SIM> vlog -sv test1.v
.
# Top level modules:
# dut
Note that the compiler lists each module as a top-level module, although, ultimately, only
testbench is a top-level module. If a module is not referenced by another module compiled in
the same invocation of the compiler, then it is listed as a top-level module. This is just an
informative message that you can ignore during incremental compilation.
The message is more useful when you compile an entire design in one invocation of the
compiler and need to know the top-level module names for the simulator. For example,
Now, suppose that you modify the functionality of the or2 module:
The compiler informs you that it skipped the modules top and and2, and compiled or2.
Automatic incremental compilation is intelligent about when to compile a module. For example,
changing a comment in your source code does not result in a recompile; however, changing the
compiler command line arguments results in a recompile of all modules.
Note
Changes to your source code that do not change functionality but that do affect source code
line numbers (such as adding a comment line) will cause all affected modules to be
recompiled. This happens because debug information must be kept current so that Questa SIM
can trace back to the correct areas of the source code.
Library Usage
All modules and UDPs in a Verilog design must be compiled into one or more libraries. One
library is usually sufficient for a simple design, but you may want to organize your modules into
various libraries for a complex design. If your design uses different modules having the same
name, then you need to put those modules in different libraries because design unit names must
be unique within a library.
The following is an example of how to organize your ASIC cells into one library and the rest of
your design into another:
% vlib work
% vlib asiclib
% vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2
Note that the first compilation uses the -work asiclib argument to instruct the compiler to place
the results in the asiclib library rather than the default work library.
Because instantiation bindings are not determined at compile time, you must instruct the
simulator to search your libraries when loading the design. The top-level modules are loaded
from the library named work unless you prefix the modules with the <library>. option. If they
are not found in the work library, they are searched in the libraries specified with -Lf arguments
followed by libraries specified with -L arguments.
Please refer to Library Search Rules for more information on how to search your libraries.
Related Topics
Library Search Rules
Handling Sub-Modules with the Same Name
The vlog command also supports a non-default mode called Multi File Compilation Unit
(MFCU). In MFCU mode, vlog compiles all files on the command line into one compilation
unit. You can invoke vlog in MFCU mode as follows:
See Declarations in Compilation Unit Scope for instructions on how to control vlog's handling
of compilation units.
Note
Compiler directives revert to their default values at the end of a compilation unit.
If a compiler directive is specified as an option to the compiler, this setting is used for all
compilation units present in the current compilation.
+define+<macro_name>[=<macro_text>]
+delay_mode_distributed
+delay_mode_path
+delay_mode_unit
+delay_mode_zero
-f <filename>
+incdir+<directory>
+mindelays
+maxdelays
+nowarn<mnemonic>
+typdelays
-u
Source libraries are searched after the source files on the command line are compiled. If there
are any unresolved references to modules or UDPs, then the compiler searches the source
libraries to satisfy them. The modules compiled from source libraries may in turn have
additional unresolved references that cause the source libraries to be searched again. This
process is repeated until all references are resolved or until no new unresolved references are
found. Source libraries are searched in the order they appear on the command line.
-v <filename>
-y <directory>
+libext+<suffix>
+librescan
+nolibcell
-R [<simargs>]
Related Topics
vlog
`uselib <library_reference>...
-y /h/vendorA +libext+.v
Since the `uselib directives are embedded in the Verilog source code, there is more flexibility in
defining the source libraries for the instantiations in the design. The appearance of a `uselib
directive in the source code explicitly defines how instantiations that follow it are resolved,
completely overriding any previous `uselib directives.
An important feature of ‘uselib is to allow a design to reference multiple modules having the
same name, therefore independent compilation of the source libraries referenced by the `uselib
directives is required.
Each source library should be compiled into its own object library. The compilation of the code
containing the `uselib directives only records which object libraries to search for each module
instantiation when the design is loaded by the simulator.
Because the `uselib directive is intended to reference source libraries, the simulator must infer
the object libraries from the library references. The rule is to assume an object library named
work in the directory defined in the library reference:
dir=<library_directory>
file=<library_file>
The simulator will ignore a library reference libext=<file_extension>. For example, the
following `uselib directives infer the same object library:
‘uselib dir=/h/vendorA
‘uselib file=/h/vendorA/libcells.v
In both cases the simulator assumes that the library source is compiled into the object library:
/h/vendorA/work
The simulator also extends the `uselib directive to explicitly specify the object library with the
library reference lib=<library_name>. For example:
‘uselib lib=/h/vendorA/work
The library name can be a complete path to a library, or it can be a logical library name defined
with the vmap command.
-compile_uselibs Argument
Use the -compile_uselibs argument to vlog to reference `uselib directives. The argument finds
the source files referenced in the directive, compiles them into automatically created object
libraries, and updates the modelsim.ini file with the logical mappings to the libraries.
When using -compile_uselibs, Questa SIM determines into which directory to compile the
object libraries by choosing, in order, from the following three values:
The following code fragment and compiler invocation show how two different modules that
have the same name can be instantiated within the same design:
module top;
`uselib dir=/h/vendorA libext=.v
NAND2 u1(n1, n2, n3);
`uselib dir=/h/vendorB libext=.v
NAND2 u2(n4, n5, n6);
endmodule
This allows the NAND2 module to have different definitions in the vendorA and vendorB
libraries.
uselib is Persistent
As mentioned above, the appearance of a `uselib directive in the source code explicitly defines
how instantiations that follow it are resolved. This may result in unexpected consequences. For
example, consider the following compile command:
Assume that dut.v contains a `uselib directive. Since srtr.v is compiled after dut.v, the `uselib
directive is still in effect. When srtr is loaded it is using the `uselib directive from dut.v to
decide where to locate modules. If this is not what you intend, then you need to put an empty
`uselib at the end of dut.v to “close” the previous `uselib statement.
Verilog Configurations
The Verilog 2001 specification added configurations. Configurations specify how a design is
“assembled” during the elaboration phase of simulation. Configurations actually consist of two
pieces: the library mapping and the configuration itself. The library mapping is used at compile
time to determine into which libraries the source files are to be compiled.
Here is an example of a simple library map file:
Here is an example of a library map file that uses the -incdir argument:
The name of the library map file is arbitrary. You specify the library map file using the -libmap
argument to the vlog command. Alternatively, you can specify the file name as the first item on
the vlog command line, and the compiler reads it as a library map file.
Tip
You can use vlog -mfcu to compile macros for all files in a given testbench. Any macros
already defined before the -libmap argument appears are still defined for use by the -libmap
files. That is, -mfcu macros are applied to the other libraries in library mapping files.
The library map file must be compiled along with the Verilog source files. Multiple map files
are allowed but each must be preceded by the -libmap argument.
The library map file and the configuration can exist in the same or different files. If they are
separate, only the map file needs the -libmap argument. The configuration is treated as any other
Verilog source file.
config cfg;
design top;
instance top.u1 use work.u1;
endconfig
To create a configuration that loads an instance from a library other than the default work
library, do the following:
1. Make sure the library has been created using the vlib command. For example:
vlib mylib
Related Topics
Working Library Versus Resource Libraries
generate
if (p)
integer x = 1;
else
real x = 2.0;
endgenerate
initial $display(x);
endmodule
This example is legal under 2001 rules. However, it is illegal under the 2005 rules and causes an
error in Questa SIM. Under the new rules, you cannot hierarchically reference a name in an
anonymous scope from outside that scope. In the example above, x does not propagate its
visibility upwards, and each condition alternative is considered to be an anonymous scope.
For this example to simulate properly in Questa SIM, change it to the following:
module m;
parameter p = 1;
if (p) begin:s
integer x = 1;
end
else begin:s
real x = 2.0;
end
initial $display(s.x);
endmodule
Because the scope is named in this example (begin:s), normal hierarchical resolution rules apply
and the code runs without error.
In addition, note that the keyword pair generate - endgenerate is optional under the 2005 rules
and are excluded in the second example.
Initialization Concepts
Two important initialization concepts to understand for initializing registers and memories are
“random stability” and “sequential UDPs.”
• Random stability — From run to run, it is reasonable to expect that simulation results
will be consistent with the same seed value, even when the design is recompiled or
different optimization switches are specified.
However, if the design changes in any way, random stability can not be ensured. These
design changes include:
o Changing the source code (except for comment editing).
o Changing parameter values with vopt -G or vsim -G. This forces a different topology
during design elaboration.
o Changing a +define switch such that different source code is compiled.
o Changing design hierarchy of the design units due to the random initial value being
dependent upon the full path name of the instance.
For sequential UDPs, the simulator guarantees repeatable initial values only if the
design is compiled and run with the same vlog, vopt, and vsim options.
Limitations
• The following are not initialized with +initmem or +initreg:
o Variables in dynamic types, dynamic arrays, queues, or associative arrays.
o Unpacked structs, or unpacked or tagged unions.
Requirements
• Prepare your libraries with vlib and vmap as you would normally.
Verilog Simulation
A Verilog design is ready for simulation after it has been compiled with vlog and possibly
optimized with vopt. The simulator may then be invoked with the names of the top-level
modules (many designs contain only one top-level module) or the name(s) you assigned to the
optimized version(s) of the design. Multiple optimized top design modules can be specified.
For more information on Verilog optimizations, see the Chapter, Optimizing Designs with vopt
and the section Optimization Considerations for Verilog Designs. For more information about
simulation with multiple optimized design modules refer to vsim
<library_name>.<design_unit>.
For example, if your top-level modules are “testbench” and “globals”, then invoke the simulator
as follows:
After the simulator loads the top-level modules, it iteratively loads the instantiated modules and
UDPs in the design hierarchy, linking the design together by connecting the ports and resolving
hierarchical references. By default all modules and UDPs are loaded from the library named
work. Modules and UDPs from other libraries can be specified using the -L or -Lf arguments to
vsim (see Library Search Rules for details).
On successful loading of the design, the simulation time is set to zero, and you must enter a run
command to begin simulation. Commonly, you enter run -all to run until there are no more
simulation events or until $finish is executed in the Verilog code. You can also run for specific
time periods (for example, run 100 ns). Enter the quit command to exit the simulator.
`timescale 1 ns / 100 ps
The first number (1 ns) is the time units; the second number (100 ps) is the time precision,
which is the rounding factor for the specified time units. The directive above causes time values
to be read as nanoseconds and rounded to the nearest 100 picoseconds.
Time units and precision can also be specified with SystemVerilog keywords as follows:
timeunit 1 ns
timeprecision 100 ps
-timescale Option
The -timescale option can be used with vlog and vopt to specify the default timescale in effect
during compilation for modules that do not have an explicit `timescale directive. The format of
the -timescale argument is the same as that of the `timescale directive:
-timescale <time_units>/<time_precision>
where <time_units> is <n> <units>. The value of <n> must be 1, 10, or 100. The value of
<units> must be fs, ps, ns, us, ms, or s. In addition, the <time_units> must be greater than or
equal to the <time_precision>.
For example:
Design units that do not have a timescale set in the HDL source, with vlog -timescale, or vopt -
timescale will generate an error similar to the following:
but the error can be suppressed causing vsim to use the simulator time resolution.
Note
For SystemVerilog source files (.sv files), this requires that you use either the -mfcu
argument or the -mfcu=macro argument with the vlog command.
`timescale 1 ns / 100 ps
module foo;
initial
#12.536 $display
The list below shows three possibilities for -t and how the delays in the module are handled in
each case:
• -t not set
The delay is rounded to 12.5 as directed by the module’s ‘timescale directive.
• -t is set to 1 fs
The delay is rounded to 12.5. Again, the module’s precision is determined by the
‘timescale directive. Questa SIM does not override the module’s precision.
• -t is set to 1 ns
The delay will be rounded to 13. The module’s precision is determined by the -t setting.
Questa SIM can only round the module’s time values because the entire simulation is
operating at 1 ns.
Event Queues
Section 11 of IEEE Std 1364-2005 defines several event queues that determine the order in
which events are evaluated.
At the current simulation time, the simulator has the following pending events:
• active events
• inactive events
• non-blocking assignment update events
• monitor events
• future events
o inactive events
o non-blocking assignment update events
The Standard (LRM) dictates that events are processed as follows:
• always@(q) p = q;
The tables below show two of the many valid evaluations of these statements. Evaluation events
are denoted by a number where the number is the statement to be evaluated. Update events are
denoted <name>(old->new) where <name> indicates the reg being updated and new is the
updated value.\
Again, both evaluations are valid. However, in Evaluation 1, clk has a glitch on it; in Evaluation
2, clk does not. This indicates that the design has a zero-delay race condition on clk.
Blocking Assignments
Blocking assignments place an event in the active, inactive, or future queues depending on what
type of delay they have:
Non-blocking assignments should be used only for outputs of flip-flops. This ensures that all
outputs of flip-flops do not change until after all flip-flops have been evaluated. Attempting to
use non-blocking assignments in combinational logic paths to remove race conditions may only
cause more problems. (In the preceding example, changing all statements to non-blocking
assignments would not remove the race condition.) This includes using non-blocking
assignments in the generation of gated clocks.
If written this way, a value on d1 always takes two clock cycles to get from d1 to q2.
If you change clk1 = master and clk2 = clk1 to non-blocking assignments or q2 <= q1 and q1
<= d1 to blocking assignments, then d1 may get to q2 is less than two clock cycles.
Hazard Detection
The -hazards argument for the vsim command detects event order hazards involving
simultaneous reading and writing of the same register in concurrently executing processes.
Questa SIM detects the following kinds of hazards:
• WRITE/WRITE — Two processes writing to the same variable at the same time.
• READ/WRITE — One process reading a variable at the same time it is being written to
by another process. Questa SIM calls this a READ/WRITE hazard if it executed the read
first.
• WRITE/READ — Same as a READ/WRITE hazard except that Questa SIM executed
the write first.
vsim issues an error message when it detects a hazard. The message pinpoints the variable and
the two processes involved. You can have the simulator break on the statement where the
hazard is detected by setting the break on assertion level to Error.
To enable hazard detection you must invoke vlog with the -hazards argument when you compile
your source code and you must also invoke vsim with the -hazards argument when you
simulate.
Note
Enabling -hazards implicitly enables the -compat argument. As a result, using this argument
may affect your simulation results.
class C;
int x;
endclass
C obj;
initial obj.x = 5;
This attempts to initialize a property of obj, but obj has not been constructed. The code is
missing the following:
C obj = new;
To debug a SIGSEGV error, first look in the transcript. Figure 7-1 shows an example of a
SIGSEGV error message in the Transcript window.
The Fatal error message identifies the filename and line number where the code violation
occurred (in this example, the file is top.sv and the line number is 19).
Questa SIM sets the active scope to the location where the error occurred. In the Processes
window, the current process is highlighted (Figure 7-2).
Double-click the highlighted process to open a Source window. A blue arrow will point to the
statement where the simulation stopped executing (Figure 7-3).
Next, look for null values in the Questa SIM Locals window (Figure 7-4), which displays data
objects declared in the local (current) scope of the active process.
The null value in Figure 7-4 indicates that the object handle for obj was not properly
constructed with the new operator.
The negative timing check algorithm is enabled by default. To explicitly enable the algorithm,
use the +delayed_timing_checks with the vsim command. If you want to disable the
functionality, add the +no_autodtc to the vsim command line.
Models that support negative timing check limits must be written properly if they are to be
evaluated correctly. These timing checks specify delayed versions of the input ports, which are
used for functional evaluation. The correct syntax for $setuphold and $recrem is as follows.
$setuphold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
$recrem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Timing Check Syntactical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
$setuphold
The $setuphold check determine whether signals obey the timing constraints.
Usage
$setuphold ( reference_event , data_event , timing_check_limit , timing_check_limit ,
[ notifier ] , [ stamptime_condition ] , [ checktime_condition ] , [ delayed_reference ] ,
[ delayed_data ] ) ;
Arguments
• reference_event
(required) Specifies a transition in a reference signal that establishes the reference time for
tracking timing violations on the data_event. Since $setuphold combines the functionality of
the $setup and $hold system tasks, the reference_event sets the lower bound event for $hold
and the upper bound event for $setup.
• data_event
(required) Specifies a transition of a data signal that initiates the timing check. The
data_event sets the upper bound event for $hold and the lower bound limit for $setup.
• timing_check_limit (both instances are required)
Specifies a constant expression or specparam that specifies the minimum interval between:
First instance
the data_event and the clk_event. Any change to the data signal within this interval
results in a timing violation.
Second instance
the interval between the clk_event and the data_event. Any change to the data signal
within this interval results in a timing violation.
• notifier
(optional) Specifies a register whose value is updated whenever a timing violation occurs.
The notifier can be used to define responses to timing violations.
• stamptime_condition
(optional) Conditions the data_event for the setup check and the reference_event for the
hold check. This alternate method of conditioning precludes specifying conditions in the
reference_event and data_event arguments.
• checktime_condition
(optional) Conditions the data_event for the hold check and the reference_event for the
setup check. This alternate method of conditioning precludes specifying conditions in the
reference_event and data_event arguments.
• delayed_reference
(optional) Specifies a net that is continuously assigned the value of the net specified in the
reference_event. The delay is determined by the simulator and may be nonzero depending
on all the timing check limits.
• delayed_data
(optional) Specifies a net that is continuously assigned the value of the net specified in the
data_event. The delay is determined by the simulator and may be nonzero depending on all
the timing check limits.
$recrem
The $recrem timing check determine whether signals obey the timing constraints.
Usage
$recrem ( reference_event , data_event , timing_check_limit , timing_check_limit ,
[ notifier ] , [ stamptime_condition ] , [ checktime_condition ] , [ delayed_reference ] ,
[ delayed_data ] ) ;
Arguments
• reference_event
(required) Specifies an asynchronous control signal with an edge identifier to indicate the
release from an active state.
• data_event
(required) Specifies a clock or gate signal with an edge identifier to indicate the active edge
of the clock or the closing edge of the gate.
• timing_check_limit (both instances are required)
Specifies a minimum interval between:
First instance — the release of the asynchronous control signal and the active edge of the
clock event. Any change to a signal within this interval results in a timing violation.
Second instance — the active edge of the clock event and the release of the
asynchronous control signal. Any change to a signal within this interval results in a
timing violation.
• notifier
(optional) Specifies a register whose value is updated whenever a timing violation occurs.
The notifier can be used to define responses to timing violations.
• stamptime_condition
(optional) Conditions the data_event for the removal check and the reference_event for the
recovery check. This alternate method of conditioning precludes specifying conditions in
the reference_event and data_event arguments.
• checktime_condition
(optional) Conditions the data_event for the recovery check and the reference_event for the
removal check. This alternate method of conditioning precludes specifying conditions in the
reference_event and data_event arguments.
• delayed_reference
(optional) Specifies a net that is continuously assigned the value of the net specified in the
reference_event. The delay is determined by the simulator and may be nonzero depending
on all the timing check limits.
• delayed_data
(optional) Specifies a net that is continuously assigned the value of the net specified in the
data_event. The delay is determined by the simulator and may be nonzero depending on all
the timing check limits.
The internal timing check algorithm will determine the proper delay values, specifically a
negative hold requires the shifting of your DATA signal and a negative setup requires the
shifting of your CLOCK. In some rare cases, typically due to bad SDF values, the timing check
algorithm can not create convergence. Use the +ntc_warn argument to the vsim command to
receive additional warning messages.
The LRM does not allow for you to specify a reference_event or data_event condition using the
&&& operator and also specify a stamptime_condition or checktime_condition. When this does
occur, the simulator issues a warning and ignores the condition defined in either event. For
example, in the task:
The delayed_reference and delayed_data arguments are provided to ease the modeling of
devices that may have negative timing constraints. The model's logic should reference the
delayed_reference and delayed_data nets in place of the normal reference and data nets. This
ensures that the correct data is latched in the presence of negative constraints. The simulator
automatically calculates the delays for delayed_reference and delayed_data such that the correct
data is latched as long as a timing constraint has not been violated. See Using Delayed Inputs
for Timing Checks for more information.
dCLK is the delayed version of the input CLK and dD is the delayed version of D. This posedge
D-Flipflop module has a negative setup limit of -10 time units, which allows posedge CLK to
occur up to 10 time units before the stable value of D is latched.
Without delaying CLK by 11, an old value for D could be latched. Note that an additional time
unit of delay is added to prevent race conditions.
Because the posedge CLK transition is delayed by the amount of the negative setup limit (plus
one time unit to prevent race conditions) no timing violation is reported and the new value of D
is latched.
However, the effect of this delay could also affect other inputs with a specified timing
relationship to CLK. The simulator is responsible for calculating the delay between all inputs
and their delayed versions. The complete set of delays (delay solution convergence) must
consider all timing check limits together so that whenever timing is met the correct data value is
latched.
To solve the timing checks specified relative to CLK the following delay values are necessary:
Rising Falling
dCLK 31 31
dD 20 20
dRST 0 0
The simulator's intermediate delay solution shifts the violation regions to overlap the reference
events.
Notice that no timing is specified relative to negedge CLK, but the dCLK falling delay is set to
the dCLK rising delay to minimize pulse rejection on dCLK. Pulse rejection that occurs due to
delayed input delays is reported by:
Now, consider the following case where a new timing check is added between D and RST and
the simulator cannot find a delay solution. Some timing checks are set to zero. In this case, the
new timing check is not annotated from an SDF file and a default $setuphold limit of 1, 1 is
used:
As illustrated earlier, to solve timing checks on CLK, delays of 20 and 31 time units were
necessary on dD and dCLK, respectively.
Rising Falling
dCLK 31 31
dD 20 20
dRST 0 0
The simulator's intermediate delay solution is:
But this is not consistent with the timing check specified between RST and D. The falling RST
signal can be delayed by additional 10, but that is still not enough for the delay solution to
converge.
Rising Falling
dCLK 31 31
dD 20 20
dRST 0 10
As stated above, if a delay solution cannot be determined with the specified timing check limits
the smallest negative $setup/$recovery limit is zeroed and the calculation of delays repeated. If
no negative $setup/$recovery limits exist, then the smallest negative $hold/$removal limit is
zeroed. This process is repeated until a delay solution is found.
If a timing check in the design was zeroed because a delay solution was not found, a summary
message like the following will be issued:
Invoking vsim with the +ntc_warn option identifies the timing check that is being zeroed.
Finally consider the case where the RST and D timing check is specified on the posedge RST.
In this case the delay solution converges when an rising delay on dRST is used.
Rising Falling
dCLK 31 31
dD 20 20
dRST 20 10
When performed on the delayed inputs, the violation region between the delayed inputs is:
Although the check is performed on the delayed inputs, the timing check violation message is
adjusted to reference the undelayed inputs. Only the report time of the violation message is
noticeably different between the delayed and undelayed timing checks.
By far the greatest difference between these modes is evident when there are conditions on a
delayed check event because the condition is not implicitly delayed. Also, timing checks
specified without explicit delayed signals are delayed, if necessary, when they reference an
input that is delayed for a negative timing check limit.
Other simulators perform timing checks on the delayed inputs. To be compatible, Questa SIM
supports both methods. By default timing checks are performed on the delayed inputs. This can
be disabled using the +no_autodtc switch.
Related Topics
force
+alt_path_delays
-l <filename>
+maxdelays
+mindelays
+multisource_int_delays
+no_cancelled_e_msg
+no_neg_tchk
+no_notifier
+no_path_edge
+no_pulse_msg
-no_risefall_delaynets
+no_show_cancelled_e
+nosdfwarn
+nowarn<mnemonic>
+ntc_warn
+pulse_e/<percent>
+pulse_e_style_ondetect
+pulse_e_style_onevent
+pulse_int_e/<percent>
+pulse_int_r/<percent>
+pulse_r/<percent>
+sdf_nocheck_celltype
+sdf_verbose
+show_cancelled_e
+transport_int_delays
+transport_path_delays
+typdelays
\/top/dut/03
\/top/dut/03\
Starting in version 6.3, all object names inside the simulator appear identical to their names in
original HDL source files.
Sometimes, in mixed language designs, hierarchical identifiers might refer to both VHDL
extended identifiers and Verilog escaped identifiers in the same fullpath. For example, top/
\VHDL*ext\/\Vlog*ext /bottom (assuming the PathSeparator variable is set to '/'), or
top.\VHDL*ext\.\Vlog*ext .bottom (assuming the PathSeparator variable is set to '.')
Any fullpath that appears as user input to the simulator (such as on the vsim command line, in a
.do file, or on the vopt command line) should be composed of components with valid escaped
identifier syntax.
Note that SDF files are always parsed in “generous mode.” Signal Spy function arguments are
also parsed in “generous mode.”
On the vsim command line, the language-correct escaped identifier syntax should be used for
top-level module names. Using incorrect escape syntax on the command line works in the
incremental/debug flow, but not in the default optimized flow (see Optimizing Designs with
vopt). This limitation may be removed in a future release.
For example,
\n
When a Tcl command is used in the command line interface, the TCL backslash should be
escaped by adding another backslash. For example:
The Verilog identifier, in this example, is \yw[1]. Here, backslashes are used to escape the
square brackets ([]), which have a special meaning in Tcl.
For a more detailed description of special characters in Tcl and how backslashes should be used
with those characters, click Help > Tcl Syntax in the menu bar, or simply open the docs/
tcl_help_html/TclCmd directory in your QuestaSim installation.
Cell Libraries
Mentor Graphics has passed the Verilog test bench from the ASIC Council and achieved the
“Library Tested and Approved” designation from Si2 Labs. This test bench is designed to
ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete
on the way to achieving full ASIC vendor support. As a consequence, many ASIC and FPGA
vendors’ Verilog cell libraries are compatible with Questa SIM Verilog.
The cell models generally contain Verilog “specify blocks” that describe the path delays and
timing constraints for the cells. See Section 14 in the IEEE Std 1364-2005 for details on specify
blocks, and Section 15 for details on timing constraints. Questa SIM Verilog fully implements
specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog-XL
compatible extensions.
Delay Modes
Verilog models may contain both distributed delays and path delays. Distributed delays appear
on primitives, UDPs, and continuous assignments; path delays are the port-to-port delays
specified in specify blocks. These delays interact to determine the actual delay observed. Most
Verilog cells use path delays exclusively, with no distributed delays specified.
The following code shows a simple two-input AND gate cell, where no distributed delay is
specified for the AND primitive.
For cells such as this, the actual delays observed on the module ports are taken from the path
delays. This is typical for most cells, though more complex cells may require nonzero
distributed delays to work properly.
Tip
Delay mode arguments to the vlog command take precedence over delay mode
directives in the source code.
Note that these directives and arguments are compatible with Verilog-XL. However, using these
modes results in behavior that is not clearly defined by the Verilog standard—the delays that are
set to zero can vary from one simulator to another (some simulators zero out only some delays).
Example 7-2 shows the 2-input AND gate cell using a different compiler directive to apply each
delay mode. In particular, Questa SIM does the following:
• The `delay_mode_zero directive sets both the continuous assignment delay (assign #2 c
= b) and the primitive delay (and #3 (y, a,c) ) to zero.
• The `delay_mode_unit directive converts both of these nonzero delays (continuous
assignment and primitive) to 1.
Example 7-2. Delay Mode Directives in a Verilog Cell
The following instances of a 2-input AND gate cell (and2_1, and2_2, and2_3, and2_4) use
compiler directives to apply each delay mode.
`delay_mode_zero
module and2_1(y, a, b);
input a, b;
output y;
wire c;
assign #2 c = b;
`delay_mode_unit
module and2_2(y, a, b);
input a, b;
output y;
wire c;
assign #2 c = b;
`delay_mode_distributed
module and2_3(y, a, b);
input a, b;
output y;
wire c;
assign #2 c = b;
`delay_mode_path
module and2_4(y, a, b);
input a, b;
output y;
wire c;
assign #2 c = b;
Approximating Metastability
The ability to approximate metastability for Verilog gate-level designs is useful for simulating
synchronizer flops used to synchronize inputs from one clock domain to another. It allows a
known random state to be latched when timing between domains is violated.
Without this feature, you need to selectively use a version of the cell that does not generate
unknowns from timing check violations, or disable/force notifiers to override the timing check
violation toggle that introduced unknown states into the circuit.
Standard timing simulation Verilog cells have timing checks with notifier registers. The notifier
registers are inputs to user defined primitives (UDPs), which are coded to generate an unknown
output state when the notifier input changes.
During standard simulation, a timing check violation generates a violation message and the
notifier register value is toggled. The notifier register change causes an evaluation of the UDP
which generates an unknown state.
During metastable approximation the timing check operates as normal. When a timing check
violation occurs, the notifier is toggled and the UDP is evaluated in a manner to approximate
metastability. The metastable UDP evaluation does not generate an unknown state, but rather a
random 1 or 0 logic state.
The metastablity feature is implemented accepting a standard Verilog UDP description and
interpreting it in a non-standard manner as follows.
Usage
To allow metastable approximation simulation, Verilog cells must be optimized (vopt
command) with the proper optimization visibility .
• Most system tasks and functions defined in SystemVerilog IEEE Std 1800-2012
• Several system tasks and functions that are specific to Questa SIM
• Several non-standard, Verilog-XL system tasks
IEEE Std 1800-2012 System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Using the $typename Data Query Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Using the $coverage_* System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Using the $coverage_save System Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Simulator-Specific System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Task and Function Names Without Round Braces ‘()’ . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Verilog-XL Compatible System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
String Class Methods for Matching Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Example Usage
$typename(a, `mtiTypenameExpandAll);
The various form of $typename() output for a parametrized class "vector" which extends
another parametrized class "vector_base", both of which are defined in the module scope
"typename_parameterized_class":
• The coverage numbers reported by Questa SIM differ from the SV system functions due
the fact that the numbers in Questa SIM reports:
o reflect merge/roll-up coverage numbers (i.e. 9 instances of the same assertion is
reported as 1 assertion). These system functions will count each instance separately
(i.e. 9 assertions).
o ignore recursion when the -du argument is used. These system functions allow
recursion with filtering on a design unit.
• The "$coverage_merge(...)" system function is unsupported: if encountered in the code,
Questa SIM issues an 'unsupported' warning message and is ignored.
• The "$coverage_save(...)" system function remains unaltered from its current behavior.
See, Using the $coverage_save System Function.
• The coverage control `SV_COV_CHECK is supported. Currently, the
"$coverage_control(`SV_COV_RESET,...)",
"$coverage_control(`SV_COV_START,...)" and
"$coverage_control(`SV_COV_STOP,...)" system functions are not: they issue an
'unsupported' warning message and otherwise are ignored.
• Currently, only the `SV_COV_ASSERTION coverage type identification is supported.
The `SV_COV_FSM_STATE, `SV_COV_STATEMENT and `SV_COV_TOGGLE
coverage type identifications are currently unsupported.
Example Usage
Check all assertion instances in the entire design to verify one or more has coverage:
Check all assertions on all instances of the module DUT to verify one or more has coverage.
See $coverage_save_mti.
For example:
========
clog2.sv
========
module clog2;
var logic [95:0] i;
initial begin
i = 1'b0;
$display("$clog2(%h) ==> %h", i, $clog2(i));
i = 40'h3X_XXXX_XXXX;
$display("$clog2(%h) ==> %h", i, $clog2(i));
i = 40'hX3_XXXX_XXXX;
$display("$clog2(%h) ==> %h", i, $clog2(i));
i = 40'h3Z_ZZZZ_ZZZZ;
$display("$clog2(%h) ==> %h", i, $clog2(i));
i = 40'hZ3_ZZZZ_ZZZZ;
$display("$clog2(%h) ==> %h", i, $clog2(i));
end
endmodule
================
output for clog2
================
# $clog2(000000000000000000000000) ==> 00000000
# $clog2(000000000000003xxxxxxxxx) ==> 00000026
# $clog2(00000000000000x3xxxxxxxx) ==> 00000028
# $clog2(000000000000003zzzzzzzzz) ==> 00000026
# $clog2(00000000000000z3zzzzzzzz) ==> 00000022
$coverage_save_mti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
$get_initial_random_seed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
$messagelog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
$psprintf() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
$sdf_done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
$stacktrace() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
$wlfdumpvars() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
$coverage_save_mti
The $coverage_save_mti() system function saves only Code Coverage information to a file
during a batch run that typically would terminate with the $finish call.
Syntax
$coverage_save_mti(<filename>, [<instancepath>], [<xml_output>]);
Arguments
none
Description
The $coverage_save() system function is defined in IEEE Std 1800, as explained above in
Using the $coverage_save System Function. The pre-standardization behavior is retained for
backwards-compatibility by the $coverage_save_mti() system function.
The $coverage_save_mti() system function returns a “0” to indicate that the coverage
information was saved successfully or a “-1” to indicate an error (unable to open file, instance
name not found, and so forth.)
If you do not specify <instancepath>, Questa SIM saves all coverage data in the current design
to the specified file. If you do specify <instancepath>, Questa SIM saves data on that instance,
and all instances below it (recursively), to the specified file.
If set to 1, the [<xml_output>] argument specifies that the output be saved in XML format.
$get_initial_random_seed
The $get_initial_random_seed system function returns the value of the initial random seed.
Note
You specify this random seed value by using the -sv_seed argument of the vsim command.
Syntax
$get_initial_random_seed;
Arguments
none
$messagelog
The $messagelog system task allows you to create a message using text and specifiers.
Syntax
$messagelog({"<message>", <value>...}[, ...]);
Arguments
• Task arguments:
o <message> — Your message, enclosed in quotation marks ("), using text and
specifiers to define the output.
o <value> — A scope, object, or literal value that corresponds to the specifiers in the
<message>. You must specify one <value> for each specifier in the <message>.
Specifiers
• Task arguments:
The $messagelog task supports all specifiers available with the $display system task. For
more information about $display, refer to section 17.1 of the IEEE std 1364-2005.
The following specifiers are specific to $messagelog.
Note
The format of these custom specifiers differ from the $display specifiers.
Specifically, “%:” denotes a $messagelog specifier and the letter denotes the type of
specifier.
• %:C — Group/Category
A string argument, enclosed in quotation marks ("). This attribute defines a group or
category used by the message system. If you do not specify %:C, the message system logs
User as the default.
• %:F — Filename
A string argument specifying a simple filename, relative path to a filename, or a full path to
a filename. In the case of a simple filename or relative path to a filename, the simulator
accepts what you specify in the message output, but internally it uses the current directory to
complete these paths to form a full path—this allows the message viewer to link to the
specified file.
If you do not include %:F, the simulator automatically logs the value of the filename in
which the $messagelog is called.
If you do include %:R, %:F, or %:L, or a combination of any two of these, the simulator
does not automatically log values for the undefined specifier(s).
• %:I — Message ID
A string argument. The Message Viewer displays this value in the ID column. This attribute
is not used internally, therefore you do not need to be concerned about uniqueness or
conflict with other message IDs.
• %:L — Line number
An integer argument.
If you do not include %:L, the simulator automatically logs the value of the line number on
which the $messagelog is called.
If you do include %:R, %:F, or %:L, or a combination of any two of these, the simulator
does not automatically log values for the undefined specifier(s).
• %:O — Object/Signal Name
A hierarchical reference to a variable or net, such as sig1 or top.sigx[0]. You can specify
multiple %:O for each $messagelog, which effectively forms a list of attributes of that kind,
for example:
$messagelog("The signals are %:O, %:O, and %:O.",
sig1, top.sigx[0], ar [3].sig);
Description
• Non-printing attributes (~) — You can specify that an attribute value is not to be printed
in the transcripted message by placing the tilde (~) character after the percent (%)
character, for example:
$messagelog("%:~S Do not print the Severity Level", "Warning");
However, the value of %:S is logged for use in the Message Viewer.
• Logging of simulation time — For each call to $messagelog, the simulation time is
logged, however the simulation time is not considered an attribute of the message
system. This time is available in the Message Viewer.
• Minimum field-width specifiers — are accepted before each specifier character, for
example:
%:0I
%:10I
initial begin
wrapper(`__FILE__, `__LINE__);
wrapper(`__FILE__, `__LINE__);
end
endmodule
Examples
• The following $messagelog task:
$messagelog("hello world");
while logging all default attributes, but does not log a category.
while silently logging the severity level of “Note”, and uses a direct reference to the
Verilog scope for the %:R specifier, and does not log any attributes for %:F (filename)
or %:L (line number).
• The following $messagelog task:
$messagelog("%:~V%:S %:C-%:I,%:L: Unexpected AHB interrupt received
in transactor %:R", 1, "Error", "AHB", "UNEXPINTRPT", `__LINE__,
ahbtop.c190);
where the verbosity level (%:V) is “1”, severity level (%:S) is “Error”, the category
(%:C) is “AHB”, and the message identifier (%:I) is “UNEXPINTRPT”. There is a
direct reference for the region (%:R) and the macro ‘__LINE__ is used for line number
(%:L), resulting in no attribute logged for %:F (filename).
$psprintf()
The $psprintf() system function behaves like the $sformat() file I/O task except that the string
result is passed back to the user as the function return value for $psprintf(), not placed in the
first argument as for $sformat(). Thus $psprintf() can be used where a string is valid. Note that
at this time, unlike other system tasks and functions, $psprintf() cannot be overridden by a user-
defined system function in the PLI.
Syntax
$psprintf();
Arguments
none
$sdf_done
This task is a “cleanup” function that removes internal buffers, called MIPDs, that have a delay
value of zero. These MIPDs are inserted in response to the -v2k_int_delay argument for the
vsim command. In general, the simulator automatically removes all zero delay MIPDs.
However, if you have $sdf_annotate() calls in your design that are not getting executed, the
zero-delay MIPDs are not removed. Adding the $sdf_done task after your last $sdf_annotate()
removes any zero-delay MIPDs that have been created.
Syntax
$sdf_done;
Arguments
none
$stacktrace()
This function produces a call stack trace back from the point where the call is made. A
successful $stacktrace() call returns a non-zero value, a failed call returns zero (0).
Syntax
$stacktrace();
Arguments
none
Description
You can specify the depth of the stack frames returned by setting the StackTraceDepth
modelsim.ini variable.
Examples
Example 1—output from $stacktrace
# Call Stack:
# Function class_A::f1 src/pack.sv(10)
# Task class_A::t1 src/pack.sv(13)
# Task class_A::t2 src/pack.sv(17)
# Module top src/test5.sv(35)
$wlfdumpvars()
This Verilog system task specifies variables to be logged in the current simulation's WLF file
(default, vsim.wlf) and is called from within a Verilog design. It is equivalent to the Verilog
system task $dumpvars, except it dumps values to the current simulation's WLF file instead of
a VCD file. While it can not be called directly from within VHDL, it can log VHDL variables
contained under a Verilog scope that is referenced by $wlfdumpvars. The modelsim.ini
variable WildcardFilter will be used to filter types when a scope is logged by $wlfdumpvars.
Multiple scopes and variables are specified as a comma separated list.
Syntax
$wlfdumpvars(<levels>, {<scope> | <variable>}[, <scope> | <variable>]);
Arguments
• <levels>
Specifies the number of hierarchical levels to log, if a scope is specified. Specified as a non-
negative integer.
• <scope>
Specifies a Verilog pathname to a scope, under which all variables are logged.
• <variable>
Specifies a variable to log.
Examples
Log variable "addr_bus" in the current scope
$wlfdumpvars(0, addr_bus);
Log all variables within the scope "alu", and in any submodules
$wlfdumpvars(2, alu);
$wlfdumpvars(1, $root.top.alu.regfile)
The compiler will use the following rules for interpreting task and function names without
round braces:
1. Non class tasks/functions (static or non static) will be interpreted as a search in the scope
of the function and not a function call.
2. Non-static class methods will be treated as a function call.
3. Static class methods will be treated as a lookup in the function scope.
4. Once a function call is made for a hierarchical name, all subsequent function names will
be treated as function calls whether the type of function is static or non-static.
Examples
module top;
class CTest1 ;
string s;
static function CTest1 g();
static CTest1 s = new();
CTest1 t = new();
$display ("hello_static" ) ;
return t;
endfunction
function CTest1 f();
static string s;
CTest1 t = new();
$display ("hello_auto" ) ;
return t;
endfunction
endclass;
CTest1 t1 = new();
initial t1.g.s.f.g.s="hello";
endmodule
t1.g.s.f.g.s
t1.g.s.f().g().s
The first g is treated as a scope lookup, since it is a static function. Since f is an automatic
function, it is treated as a function call. The next g is treated as a function call g() since
according to rule 4, once an automatic function gets called, all subsequent names in the list
which are Function names, whether static or automatic, are treated as function calls.
This system task sets a Verilog net to the specified value. variable is the net to be changed;
value is the new value for the net. The value remains until there is a subsequent driver
transaction or another $deposit task for the same net. This system task operates identically to the
Questa SIM force -deposit command.
$disable_warnings("<keyword>"[,<module_instance>...]);
This system task instructs Questa SIM to disable warnings about timing check violations or
triregs that acquire a value of ‘X’ due to charge decay. <keyword> may be decay or timing.
You can specify one or more module instance names. If you do not specify a module instance,
Questa SIM disables warnings for the entire simulation.
$enable_warnings("<keyword>"[,<module_instance>...]);
This system task enables warnings about timing check violations or triregs that acquire a value
of ‘X’ due to charge decay. <keyword> may be decay or timing. You can specify one or more
module instance names. If you do not specify a module_instance, Questa SIM enables warnings
for the entire simulation.
$system("command");
This system function takes a literal string argument, executes the specified operating system
command, and displays the status of the underlying OS process. Double quotes are required for
the OS command. For example, to list the contents of the working directory on Unix:
$system("ls -l");
Return value of the $system function is a 32-bit integer that is set to the exit status code of the
underlying OS process.
Note
There is a known issue in the return value of this system function on the win32 platform. If
the OS command is built with a cygwin compiler, the exit status code may not be reported
correctly when an exception is thrown, and thus the return code may be wrong. The workaround
is to avoid building the application using cygwin or to use the switch -mno-cygwin in cygwin
on the gcc command line.
$systemf(list_of_args)
This system function can take any number of arguments. The list_of_args is treated exactly the
same as with the $display() function. The OS command that runs is the final output from
$display() given the same list_of_args. Return value of the $systemf function is a 32-bit integer
that is set to the exit status code of the underlying OS process.
Note
There is a known issue in the return value of this system function on the win32 platform. If
the OS command is built with a cygwin compiler, the exit status code may not be reported
correctly when an exception is thrown, and thus the return code may be wrong. The workaround
is to avoid building the application using cygwin or to use the switch -mno-cygwin in cygwin
on the gcc command line.
$test$plusargs("plus argument")
This system function tests for the presence of a specific plus argument on the simulator's
command line. It returns 1 if the plus argument is present; otherwise, it returns 0. For example,
to test for +verbose:
if ($test$plusargs("verbose"))
$display("Executing cycle 1");
creates the directory path nodir_2/nodir_3 and opens the file “testfile” in write mode.
This system task reads commands from the specified filename. The equivalent simulator
command is do <filename>.
$list[(hierarchical_name)]
This system task lists the source code for the specified scope. The equivalent functionality is
provided by selecting a module in the Structure (sim) window. The corresponding source code
is displayed in a Source window.
$reset
This system task resets the simulation back to its time 0 state. The equivalent simulator
command is restart.
$restart("filename")
This system task sets the simulation to the state specified by filename, saved in a previous call
to $save. The equivalent simulator command is restore <filename>.
$save("filename")
This system task saves the current simulation state to the file specified by filename. The
equivalent simulator command is checkpoint <filename>.
$scope(hierarchical_name)
This system task sets the interactive scope to the scope specified by hierarchical_name. The
equivalent simulator command is environment <pathname>.
$showscopes
This system task displays a list of scopes defined in the current interactive scope. The
equivalent simulator command is show.
$showvars
This system task displays a list of registers and nets defined in the current interactive scope. The
equivalent simulator command is show.
• search() — This function searches for a pattern in the string and returns the integer index
to the beginning of the pattern.
search(string pattern);
results assigning the value 1 to integer i because the pattern CDE exists within string str.
• prematch() — This function returns the string before a match, based on the result of the
last match() function call.
prematch();
where index is the integer number of the expression being matched (indexing starts at 0).
For example:
integer i;
string str, patt, str1, str2;
str = "12345ABCDE"
patt = "([0-9]+) ([a-zA-Z .]+)";
i = str.match(patt);
str1 = str.backref(0);
str2 = str.backref(1);
results in assigning the value “12345” to the string str1 because of the match to the
expression “[0-9]+”. It also results in assigning the value “ABCDE” to the string str2
because of the match to the expression “[a-zA-Z .]+”.
You can specify any number of additional Perl expressions in the definition of patt and
then call them using sequential index numbers.
Compiler Directives
Questa SIM Verilog supports all of the compiler directives defined in the IEEE Std 1364, some
Verilog-XL compiler directives, and some that are proprietary.
Many of the compiler directives (such as `timescale) take effect at the point they are defined in
the source code and stay in effect until the directive is redefined or until it is reset to its default
by a `resetall directive. The effect of compiler directives spans source files, so the order of
source files on the compilation command line could be significant. For example, if you have a
file that defines some common macros for the entire design, then you might need to place it first
in the list of files to be compiled.
The `resetall directive affects only the following directives by resetting them back to their
default settings (this information is not provided in the IEEE Std 1364):
`celldefine
‘default_decay_time
`default_nettype
`delay_mode_distributed
`delay_mode_path
`delay_mode_unit
`delay_mode_zero
`protect
`timescale
`unconnected_drive
`uselib
`define QUESTA
`celldefine
`default_nettype
`define
`else
`elsif
`endcelldefine
`endif
`ifdef
‘ifndef
`include
‘line
`nounconnected_drive
`resetall
`timescale
`unconnected_drive
`undef
This directive pair allows you to encrypt selected regions of your source code. The code in
`protect regions has all debug information stripped out. This behaves exactly as if using:
vlog -nodebug=ports+pli
except that it applies to selected regions of code rather than the whole file. This enables usage
scenarios such as making module ports, parameters, and specify blocks publicly visible while
keeping the implementation private.
The `protect directive is ignored by default unless you use the +protect argument to vlog. Once
compiled, the original source file is copied to a new file in the current work directory. The name
of the new file is the same as the original file with a “p” appended to the suffix. For example,
“top.v” is copied to “top.vp”. This new file can be delivered and used as a replacement for the
original source file.
A usage scenario might be that a vendor uses the `protect / `endprotect directives on a module
or a portion of a module in a file named encrypt.v. They compile it with vlog +protect encrypt.v
to produce a new file named encrypt.vp. You can compile encrypt.vp just like any other verilog
file. The protection is not compatible among different simulators, so the vendor must ship you a
different encrypt.vp than they ship to someone who uses a different simulator.
You can use vlog +protect=<filename> to create an encrypted output file, with the designated
filename, in the current directory (not in the work directory, as in the default case where
[=<filename>] is not specified). For example:
If the filename is specified in this manner, all source files on the command line are concatenated
together into a single output file. Any `include files are also inserted into the output file.
If errors are detected in a protected region, the error message always reports the first line of the
protected block.
`include
If any `include directives occur within a protected region, the compiler generates a copy of the
include file with a .vp suffix and protects the entire contents of the include file. However, when
you use vlog +protect to generate encrypted files, the original source files must all be complete
Verilog modules or packages. Compiler errors result if you attempt to perform compilation of a
set of parameter declarations within a module.
You can avoid such errors by creating a dummy module that includes the parameter
declarations. For example, if you have a file that contains your parameter declarations and a file
that uses those parameters, you can do the following:
module dummy;
`protect
`include "params.v" // contains various parameters
`include "tasks.v" // uses parameters defined in params.v
`endprotect
endmodule
Then, compile the dummy module with the +protect switch to generate an encrypted output file
with no compile errors.
After compilation, the work library contains encrypted versions of params.v and tasts.v, called
params.vp and tasks.vp. You may then copy these encrypted files out of the work directory to
more convenient locations. These encrypted files can be included within your design files; for
example:
module main
`include "params.vp"
`include "tasks.vp"
...
Though other simulators have a `protect directive, the algorithm Questa SIM uses to encrypt
source files is different. As a result, even though an uncompiled source file with `protect is
compatible with another simulator, once the source is compiled in Questa SIM, you could not
simulate it elsewhere.
This directive specifies the default decay time to be used in trireg net declarations that do not
explicitly declare a decay time. The decay time can be expressed as a real or integer number, or
as “infinite” to specify that the charge never decays.
`delay_mode_distributed
This directive disables path delays in favor of distributed delays. See Delay Modes for details.
`delay_mode_path
This directive sets distributed delays to zero in favor of path delays. See Delay Modes for
details.
`delay_mode_unit
This directive sets path delays to zero and nonzero distributed delays to one time unit. See
Delay Modes for details.
`delay_mode_zero
This directive sets path delays and distributed delays to zero. See Delay Modes for details.
`uselib
This directive is an alternative to the -v, -y, and +libext source library compiler arguments. See
Verilog-XL uselib Compiler Directive for details.
The following Verilog-XL compiler directives are silently ignored by Questa SIM Verilog.
Many of these directives are irrelevant to Questa SIM Verilog, but may appear in code being
ported from Verilog-XL.
`accelerate
`autoexpand_vectornets
`disable_portfaults
`enable_portfaults
`expand_vectornets
`noaccelerate
`noexpand_vectornets
`noremove_gatenames
`noremove_netnames
`nosuppress_faults
`remove_gatenames
`remove_netnames
`suppress_faults
The following Verilog-XL compiler directives produce warning messages in Questa SIM
Verilog. These are not implemented in Questa SIM Verilog, and any code containing these
directives may behave differently in Questa SIM Verilog than in Verilog-XL.
`default_trireg_strength
`signed
`unsigned
Refer to the QuestaSIM Installation and Licensing Guide for more information on license
features. For information on how to obtain licensing options, visit the Mentor Graphics
SupportNet web page: supportnet.mentor.com/licenses
In particular, support for the wreal net type involves a variety of issues related to analog and
digital signals and data that appear on design connections. This section identifies issues related
to connectivity as it is described in the Verilog family of languages. Specifically, problems arise
from different semantic meanings applied to the same word ("wire") in different standards, and
from using a common word (net, wire, interconnect) in a standard and ascribing to it a well-
defined semantic meaning that differs from the common colloquial understanding.
Questa SIM implements the following extensions to SystemVerilog for real number modeling
with wreal and to support Verilog-AMS netlisters:
• Real number modeling and explicit connectivity of real number models using wreal,
which is a built-in net type. You enable declarations of wreal net type by using the -ams
argument to the vlog command.
• The ability to convert wire objects that are used as structural wires in the sense of
Verilog-AMS into the typeless interconnect nets with the SystemVerilog semantic. You
enable this connection typing by using the -wireasinterconnect argument to the vlog
command.
• A global resolution function for conflicting values on wreal nets. You enable this
resolution function by using the \¬wreal_resolution argument to the vsim command.
AMS Standards and Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Connectivity Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Standards
A standard can be a ratified industry standard, such as those endorsed by IEEE or Accellera, or
it can be a de-facto standard, meaning an implementation that has become so widely used that it
has become equivalent to an endorsed standard in its influence on the industry. In the context of
behavior supported by Questa SIM, the following standards are considered:
When working with analog and mixed-signal designs that use real-number models coded using
wreal, it is common to combine test benches written in SystemVerilog with a DUT that
combines modules written in a combination of Verilog-AMS (the real number models and use
of structural wire) and SystemVerilog or its Verilog subset.
To support this situation, vendors have developed proprietary extensions to handle such
combinations.
Nomenclature
Support for modeling AMS connectivity in the Verilog family of languages is complicated by
the terminology historically associated with design connections and topology.
These issues are essentially problems created by different semantic meanings given to the same
word ("wire") in different standards and by the use of comon words (net, wire, interconnect) in
a standard that have been assigned more formal meaning that may differ from everyday usage.
This particular context is verification of mixed-signal semiconductor designs that use real
number modeling for analog components, which includes technical issues of using the Verilog
HDL family constructs wreal, wire, and interconnect.
Connectivity Terms
In electronic design, the word "wire" is used as an informal term to describe a connection
between pins (analog/SPICE terminology) or ports (digital/HDL terminology) of modules in a
system of connected components. Ideally, when information (signal, data) appears on one end
of a wire, it is instantly available to be observed at the other end without change. Of course,
behavior is less ideal in the physical world, but these non-ideal complications (such as delay and
distortion) are typically introduced at a lower level of abstraction.
Further, connections throughout a design exist beyond just to two ends of a wire—HDLs allow
connections of many component pins/ports. Such a multitude of connections among many
components is informally referred to as a "net" or "interconnect."
In analog (SPICE) modeling and simulation, when multiple physical wires are connected
together, the point of the connection is often called a "node, " where the word node can mean
the entire net.
Historically, descriptions of connectivity have used terms such as wire, net, node, interconnect,
circuit/design structure, and others to colloquially depict the fact that components are connected
together, along with the means of their connectivity. The problem that arises is twofold:
• When the colloquial meaning differs from the specific technical meaning of a given
word.
• When different versions of actual and de-facto standards are implemented.
Signal Type
Real-life signals in systems implemented from electrical components exist at the analog
physical level and are modeled by voltages and currents (as in SPICE or AMS hardware
description languages). At higher levels of abstraction, the details of voltages and currents are
ignored, and simpler modeling representations are used. In HDLs, the signal information that is
carried by the connectivity objects can be represented by many different data types. In Verilog,
the most commonly encountered ones are 4-state logic and real numbers. More detailed
descriptions use signal abstractions that can carry several pieces of data—typically a struct in a
user-defined nettype.
From the Verilog-AMS standard, a wreal net represents a real-valued physical connection
between structural entities that does not store its value. A wreal net can be used for real-valued
nets driven by a single driver, such as a continuous assignment. If no driver is connected to a
wreal net, its value is real zero (0.0). Whereas digital nets have an initial value of ‘Z’ (a 4-state
logic value), wreal nets have an initial value of 0.0
Connectivity Modeling
The issues to be considered in modeling connectivity in an AMS design are described below.
A common case of a behavioral wire is a one that is accessed (written or read) in the behavioral
code of a module, but it includes a wire that is declared (as a port or a local object) but is not
used at all.
• User-Defined Nettype (UDN) — UDN allows a definition of a net type that can carry
arbitrarily complex data using a built-in type (such as real) or a user-defined type (such
as struct). Consequently, UDN is a generalization of the wreal net type from Verilog-
AMS. In order to allow connectivity of models that rely on UDNs, a more generic
connectivity mechanism is needed—the interconnect object (below).
• The interconnect net — An interconnect object is a typeless net that can be used only to
express connections; it cannot be used to express behavior.
• Verilog-AMS wire can carry logic or real values, whereas interconnect can carrry any
type, including built-in types and the types used in a UDN. Thus, a Verilog-AMS
structural wire object can be accessed by a hierarchical reference in a testbench and its
type is known after elaboration.
• SystemVerilog interconnect is an object that cannot take on the type of behavioral
objects that it is connected to (unlike a Verilog-AMS structural wire). Thus, a
SystemVerilog interconnect object cannot be used in any behavioral read or write
access, including using a hierarchical reference.
The most important consequence of this latter distinction is that a Verilog-AMS structural wire
object can be accessed by a hierarchical reference in a test bench, and its type is known after
elaboration. Conversely, a SystemVerilog interconnect object cannot be used in any behavioral
read- or write-access, including using a hierarchical reference to it.
Another consequence of the distinction between using wire and interconnect is that a test bench
that relies on the Verilog-AMS rules of a structural wire cannot be compiled nor optimized
independently of the DUT. This is because a hierarchical reference from the test bench could
turn up to have, after elaboration, either logic or real type. Further, because when using Verilog,
it is difficult to identify the type of a hierarchical reference from its context, the compiler cannot
determine the verification engineer’s intention. This is even if the user "knows" that the
hierarchical reference will "always" end up to be the type (such as logic) unequivocally
associated with a wire net in SystemVerilog.
When a design contains models that use real numbers to represent the behavior of an analog
component, a practical problem arises when using the Cadence AMS netlister. The netlister
relies on the concept of Verilog-AMS structural wire, which, according to the Verilog-AMS
standard and the Cadence wreal extensions, is capable of carrying signals that are either logic
(0,1,X,Z) or real numbers (but not both). The netlister generates modules from schematics for
structure. The netlisted modules use only Verilog implicit net declarations, meaning that the
ports and nets are not declared in the module. Because of the default rules of all Verilog
languages, such objects are implictly declared as wire objects, and when used with a product
compliant with Verilog-AMS, those wires can connect either logic (behavioral wire) or real
(wreal) models.
The extension that Questa SIM implements to support the use of AMS netlisters with
SystemVerilog-based testbenches and DUTs differs from extensions used by the AMS
netlitsters of other vendors. As might be expected, this difference in interpretation leads to some
porting problems.
• Other vendors implemented extensions for connectivity that rely on the older Verilog-
AMS standard. This implementation will allow a hierarchical reference in a test bench to
a Verilog-AMS structural wire. It is not known how such a reference is interpreted when
the structural wire becomes either a wire or wreal depending on what is connected to it
in the DUT.
• Questa SIM has implemented the extensions using the more modern SystemVerilog
concept of interconnect. when the structural wire is converted to the SystemVerilog
interconnect, Based on the SystemVerilog rules, this implementation will not permit a
use of a hierarchical reference to such an object.
Workarounds
There are several possible workarounds to the discrepancies between these implementations:
In addition to real values, wreal can take on two additional states: ‘wrealXState and
‘wrealZState. The value of ‘wrealZState represents a high-impedance disconnection, while
‘wrealXState indicates that the value is unknown. You can declare a variable port of type real
only in SystemVerilog, not in Verilog-AMS. A wreal and a real can connect through a port
connection.
Note
It is not possible to save or checkpoint a simulation that contains wreal declarations.
package mgc_rnm_pkg;
nettype real wreal1driver with MGC_res_wreal1driver;
nettype real wreal4state with MGC_res_wreal4state;
nettype real wrealmin with MGC_res_wrealmin;
nettype real wrealmax with MGC_res_wrealmax;
nettype real wrealsum with MGC_res_wrealsum;
nettype real wrealavg with MGC_res_wrealavg;
endpackage : mgc_rnm_pkg
The following module declares four wires. It reads data from one (a), writes data to another (b),
and instantiates another (c), and ignores another (d).
module top;
wire a, b, c, d;
initial $display (a);
assign b=1;
x inst1 (c)
endmodule
Using vlog -wireasinterconnect means the compiler interprets the wires as SystemVerilog
interconnects. That is, the compiler converts wire objects used as structural wires (per Verilog-
AMS) into the typeless interconnect nets (per the SystemVerilog semantic).
You can then define a simulation module for x in either of two ways—
Hierarchical Availability
This example demonstrates the following:
• The ‘default_netlister pragma specifies that all nets are to be netlisted as wire type,
unless otherwise specified.
• The module mid declares two input ports (a, b) and one output port (c). It also three child
instances that declare these three ports as wires, two additional wires that assume the
default type (d, e), and an interconnect wire (f).
• The module top defines an instance of the mid and attempts to display an instance of the
interconnect wire (f) as a hierarchical reference.
• Three simulation modules instantiate child3 from mid, each with a different method of
specifying a resolution function for f.
‘default_netlister; wire
module mid (input a, b output c);
i1 child1 (a, d, e);
i2 child2 (c, e, f);
i3 child3 (f);
endmodule;
module top;
i11 mid(x, a, b);
initial $display(i1.f);
endmodule
Most operations are available for sparse memories and non-sparse memories alike. You actually
do not need to know whether a memory was sparse or not, except in a few cases which are
documented in "Limitations of Sparse Memories".
You can identify memories as “not sparse” by using the +nosparse switch to vlog or vopt.
Related Topics
SparseMemThreshold
However, you can override this automatic behavior using mti_sparse with a value:
write report -l
Results
The write report command lists summary information about the design, including sparse
memory handling. You would issue this command if you are not certain whether a memory was
successfully implemented as sparse or not. For example, you might add a /*sparse*/
metacomment above a multi-D SystemVerilog memory, which is not supported. In that case,
the simulation will function correctly, but Questa SIM will use a non-sparse implementation of
the memory.
If you are planning to optimize your design with vopt, be sure to use the +acc argument in order
to make the sparse memory visible, thus allowing the write report -l command to report the
sparse memory.
simulation through such a virtual interface, an error results due to dereferencing a null virtual
interface.
However, there are a few situations in which types from such references can participate in the
design without requiring a dereference of the virtual interface pointer. This is extremely rare in
practice, but due to Questa SIMs overall elaboration and simulation flow, it is not possible for
Questa SIM to determine whether such type references will actually be exercised during
simulation. So, for these cases, you can allow vsim to elaborate the design by adding the
following argument to vsim:
vsim -permit_unmatched_virtual_intf
Tip
Important: When using the -permit_unmatched_virtual_intf argument, take care to ensure
that no simulation time operations occur through unmatched virtual interfaces.
Related Topics
vsim
Note
Questa SIM does not support pthread with DPI.
Related Topics
Verilog Interfaces to C
Questa SIM supports the following addition to the SystemVerilog DPI import tasks and
functions (additional support is in bold):
dpi_function_proto ::= function_prototype
Note
While optimization is not necessary for class based debugging, you might want to
use vsim -voptargs=+acc=lprn to enable visibility into your design for RTL
debugging.
The CIID may be used in commands such as examine, describe, add wave, add list.
Note
A CIID is unique for a given simulation. Modifying a design, or running the same design
with different parameters, randomization seeds, or other configurations that change the
order of operations, may result in a class instance changing. For example, @packet@134 in one
simulation run may not be the same @packet@134 in another simulation run if the design has
changed.
myclass var;
initial begin
#10
var = new();
$display( "%t : var = %s", $time, $get_id_from_handle(var) );
end
Results
10 : var = @myclass@1
You can find the correct syntax for the class variable by dragging and dropping the class
variable from the Objects window into the Transcript.
2. Log a class type to create a contiguous record of each instance of that class type from the
time the instance first comes into existence to the time the instance is destroyed with the
log -class command. For example:
log -class sim:/mem_agent_pkg::mem_item
Refer to The Class Instance Identifier for more information about finding and specifying
a class instance identifier.
4. Log a Class Path Expression. Refer to Working with Class Path Expressions for more
information.
In this example, one of the parameters in the descriptive name is also a specialization of a
parameterized class.
# my_foo
# foo2
# /top/mod1/foo
# /top/mod2/foo
In the output, my_foo and foo2 are unique class types. However, the last two entries show that
there are two distinct class types with the name 'foo'; one defined in mod1 and the other in
mod2. To specify an instance of type 'foo', the full path of the specific “foo” is required, for
example @/top/mod2/foo@19.
You can also find the correct syntax for a class type by dragging and dropping the class type
from the Structure window into the Transcript window.
can organize by extended class (default) or by base class. Use it to show all of the relationships
between the classes in your design.
Figure 7-6. Class in the Class Graph Window
Prerequisites
The class debug feature must be enabled to use the Class Instances window. Refer to Enabling
Class Debug for more information.
The Class Instances window is dynamically populated by selecting SystemVerilog classes in the
Structure (sim) window. All currently active instances of the selected class are displayed in the
Class Instances window. Class instances that have not yet come into existence or have been
destroyed are not displayed. Refer to The classinfo Commands for more information about
verifying the current state of a class instance.
Once you have chosen the design unit you want to observe, you can lock the Class Instances
window on that design unit by selecting File > Environment > Fix to Current Context when
the Class Instances window is active.
You can hover the mouse over any class waveform to display information about the class
variable (Figure 7-10).
• Static objects — analysis includes the object count and current memory usage.
• Dynamic objects — analysis includes object count, current memory usage, peak
memory usage, and the time peak memory usage occurred.
Questa SIM collects data as either a coarse-grain analysis (default) or a fine-grain analysis of
memory capacity. The main difference between the two levels is the amount of capacity data
collected. You must enable fine-grain analysis to view count, current and peak memory
allocation for each class type, aggregate information about the class type, including the current
filename and line number where the allocation occurred. Refer to Levels of Capacity Analysis
for more information.
Refer to the Capacity Window and Capacity Analysis sections for more information about
viewing class memory usage. You can also display capacity data in the Wave Window. Refer to
Displaying Capacity Data in the Wave Window for more information.
• allow you to view class properties in the Wave and Watch windows, and return data
about class properties with the examine command. You can see how the class properties
change over time even when class references within the path expression change values.
• may be added to the Wave window even when they do not exist.
• may be expanded inline in the Wave window without having to add class objects to the
Wave window individually.
• may be cast to the legal types for the expression. In the Wave window, the casting
options are restricted to the set of types of objects actually assigned to the references.
• are automatically logged once the expression is added to the Wave window.
Class Path Expression Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Adding a Class Path Expression to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Class Path Expression Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Casting a Class Variable to a Specific Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Class Objects vs Class Path Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Disabling Class Path Expressions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
/top/myref.xarray[2].prop
where
In this case the expression allows you to watch the value of prop even if myref changes to point
to a different class object, or if the reference in element [2] of xarray changes.
Procedure
1. Right-click (RMB) the class variable waveform and select Cast to.
2. RMB over the name/value of the class reference in the Pathnames or the Values Pane of
the Wave window to open a popup menu. Select Cast to > <class_type>. The current
value will have check mark next to it. (Figure 7-15)
Figure 7-15. Casting c1 to c1prime
will add the class path expression to the wave window. The expression will be evaluated
regardless of what class object is referenced by myref.
Using the -obj argument to the add wave command will cause the command to interpret the
expression immediately and add the specific class object to the Wave window instead of the
class path expression. For example:
will add the currently class object and property to the Wave window, in this case,
@[email protected]. @myref@19 is the specific object at the time the command was executed.
Examples
• Conditional breakpoint in dynamic code
bp mem_driver.svh 60 -cond {this.id == 9}
b. Drag and drop the object from the Objects window into the Transcript window.
Questa SIM adds the full path to the command.
examine –handle
{sim:/uvm_pkg::uvm_top.top_levels[0].super.m_env.m_mem_agent.m_driver}
c. Press Enter
Refer to the Step Toolbar section for a complete description of the stepping features.
Examples
• Print the current values of a class instance.
examine /ovm_pkg::ovm_test_top
• Print the unique ID of a specific class instance using the full path to the object.
examine –handle /ovm_pkg::ovm_test_top.i_btn_env
• Print the unique handle of the class object located at the current breakpoint.
examine –handle this
Returns:
# class /questa_uvm_pkg::questa_messagelogger_report_server extends
/uvm_pkg::uvm_report_server
# static /questa_uvm_pkg::questa_messagelogger_report_server
m_q;
# function new;
# static function message_logger;
# function compose_message;
# function process_report;
# static function get;
# static function init;
# endclass
Returns:
class /std::mailbox::mailbox__1
# Queue items;
# int maxItems;
# chandle read_awaiting;
# chandle write_awaiting;
# chandle qtd;
# /std::semaphore read_semaphore;
# /std::semaphore write_semaphore;
# function new;
# task put;
# function try_put;
# task get;
# function try_get;
# task peek;
# function try_peek;
# function post_randomize;
# function pre_randomize;
# function constraint_mode;
# endclass
Calling Functions
The call command calls SystemVerilog static functions, class functions directly from the vsim
command line in live simulation mode and Verilog interface system tasks and system functions.
Tasks are not supported.
Function return values are returned to the vsim shell as a Tcl string. Returns the class instance
ID when a function returns a class reference.
Call a static function or a static 0 time task from the command line.
Examples:
Prerequisites
Specify the -classdebug argument with the vsim command.
Procedure
Enter the classinfo descriptive command for the desired class type.
Examples
• Display the descriptive class type name for /std::mailbox::mailbox__1
classinfo descriptive /std::mailbox::mailbox__1
Returns:
# Class /std::mailbox::mailbox__1 maps to mailbox #(class uvm_phase)
Related Topics
Authoritative and Descriptive Class Type Names
classinfo descriptive
Examples
• Verify the existence of the class instance @mem_item@87
classinfo find @mem_item@87
Returns:
# @mem_item@87 exists
or
# @mem_item@87 not yet created
or
# @mem_item@87 has been destroyed
Related Topics
classinfo find
Examples
• List the currently active instances of the class type mem_item.
Returns:
# @mem_item@140
# @mem_item@139
# @mem_item@138
# @mem_item@80
# @mem_item@76
# @mem_item@72
# @mem_item@68
# @mem_item@64
Related Topics
classinfo instances
Procedure
Enter the classinfo report command at the command line.
classinfo report
Examples
• Create a report of all class instances in descending order in the Total column. Print the
Class Names, Total, Peak, and Current columns. List only the first six lines of that
report.
classinfo report -s dt -c ntpc -m 6
Returns:
# Class Name Total Peak Current
# uvm_pool__11 318 315 315
# uvm_event 286 55 52
# uvm_callback_iter__1 273 3 2
# uvm_queue__3 197 13 10
# uvm_object_string_pool__1 175 60 58
# mem_item 140 25 23
Related Topics
classinfo report
classinfo stats
Examples
• Display the current number of class types, the maximum number, peak number and
current number of all class instances.
classinfo stats
Returns:
# class type count 451
# class instance count (total) 2070
# class instance count (peak) 1075
# class instance count (current) 1058
Related Topics
classinfo stats
Procedure
Enter the classinfo trace command with the desired class instance.
Examples
• Return the first active reference to @my_report_server@1
classinfo trace @my_report_server@1
Returns:
# top.test.t_env.m_rh.m_srvr
Related Topics
classinfo trace
Examples
• Return the inheritance for mem_item.
classinfo ancestry mem_item
Returns:
# class /mem_agent_pkg::mem_item extends /
uvm_pkg::uvm_sequence_item
# class /uvm_pkg::uvm_sequence_item extends /
uvm_pkg::uvm_transaction
# class /uvm_pkg::uvm_transaction extends /uvm_pkg::uvm_object
# class /uvm_pkg::uvm_object extends /uvm_pkg::uvm_void
# class /uvm_pkg::uvm_void
Related Topics
classinfo ancestry
Asking the question [classinfo isa Apple] would return Apple, HoneyCrisp, GoldenDelicious,
and Gravenstein. Asking [classinfo isa Pear] would return Pear, Bosc, and Bartlett. And finally,
[classinfo isa Fruit] would return Fruit, Apple, Pear, HoneyCrisp, GoldenDelicious,
Gravenstein, Bosc, and Bartlett.This command could be useful for determining all the types
extended from a particular methodology sequencer, for example.
Examples
• Find all extensions for the class type mem_item.
classinfo isa mem_item
Returns:
# /mem_agent_pkg::mem_item
# /mem_agent_pkg::mem_item_latency4_change_c
# /mem_agent_pkg::mem_item_latency2_change_c
# /mem_agent_pkg::mem_item_latency6_change_c
# /mem_agent_pkg::mem_item_latency_random_c
Examples
• List the full path of the class types that do not match the pattern *uvm*. The scope and
instance name returned are in the format required for logging classes and when setting
some types of breakpoints,
classinfo types -x *uvm*
Returns:
# /environment_pkg::test_predictor
# /environment_pkg::threaded_scoreboard
# /mem_agent_pkg::mem_agent
# /mem_agent_pkg::mem_config
# /mem_agent_pkg::mem_driver
Related Topics
classinfo types
The default settings for execution of the garbage collector are optimized to balance performance
and memory usage for either mode. The garbage collector executes when one of the following
events occurs depending on the mode:
• After the total of all class objects in memory reaches a specified size in Megabytes.
• At the end of each run command.
• After each step operation.
Procedure
1. To open the Garbage Collector Configuration dialog, select Tools > Garbage Collector
> Configure to open the dialog box.
Figure 7-17. Garbage Collector Configuration
2. The default settings are loaded automatically and set based on whether you have
specified the -classdebug or the -noclassdebug argument with the vsim command.
Related Topics
gc configure
GCThreshold
GCThresholdClassDebug
vsim
OVM-Aware Debug
OVM-aware debugging provides you, the verification or design engineer, with information, at
the OVM abstraction level, that connects you to the OVM base-class library.
Preparing Your Simulation for OVM-Aware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
OVM-Aware Debugging Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
OVM-Aware Debug Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
and the compiler will use the precompiled OVM library (mtiOvm).
• If your OVM requires macros, you must also include the ovm-2.0, or greater, source
files. For example:
vlog top.sv \
+incdir+<install_dir>/verilog_src/ovm-<version>/src/
• If you cannot use the precompiled OVM and need to compile the OVM source
directly, you must specify a +define of OVM_DEBUGGER as follows:
vlog top.sv \
+incdir+<install_dir>/verilog_src/ovm-<version>/src/ \
+define+OVM_DEBUGGER \
<install_dir>/verilog_src/ovm-<version>/src/ovm_pkg.sv
2. Optimization — You can explicitly or implicitly run vopt. There are no special settings
to enable OVM-Aware debugging.
3. Elaboration — You must specify the -OVMdebug switch on the vsim command line.
Note that the switch is case-sensitive. This instructs the simulator to collect debugging
information about your OVM environment.
4. GUI — Display the OVM-aware debugging windows, OVM Globals Window and
OVM Hierarchy Window, by executing the command:
view ovm
You can also display these windows from the View > OVM menu items.
5. Simulation — The OVM Hierarchy window will be empty until the testbench creates the
first OVM environment components. As soon as the simulation enters the OVM build
phase, the OVM structure is built up and the OVM Hierarchy window is populated. You
can enter the OVM build phase by running the simulation to a particular time or by
setting a breakpoint in your design.
Procedure
1. Expand the Blockers tree in the OVM Globals window.
2. Select one of the “Blocker” entries in the tree.
This adds a green arrow to the OVM Hierarchy window indicating the location of the
corresponding element.
3. In the OVM Hierarchy window, continue to expand the tree until the green arrow
disappears and the corresponding element to the blocker is selected. Note also that the
element is also highlighted green if you select any other element of the hierarchy.
4. Right-click on the selected hierarchy element and select “View Sequence Details” for
additional information.
• Any get configuration highlighted in green can be expanded to show the location
that sets the configuration.
Select any matching (green) configuration and your OVM Hierarchy window will
select the corresponding element.
• Any get configuration highlighted in red does not have a matching set configuration.
4. In the OVM Component window expand the Set Configurations tree.
• Any set configuration highlighted in green can be expanded to show the location(s)
that gets the configuration.
Select any matching (green) configuration and your OVM Hierarchy window will
highlight the corresponding elements in green or directly select a single component
that gets that configuration.
• Any set configuration highlighted in red does not have a matching get configuration.
UVM-Aware Debug
UVM-Aware Debug provides you with information at the UVM abstraction level that connects
you to the UVM base-class library. The Questa SIM installation tree includes the latest
qualified, pre-compiled version of the Accellera UVM package library. It also contains a pre-
compiled DPI library necessary for UVM integration into Questa SIM, and a Questa SIM-
specific UVM debugging package called "questa_uvm_pkg". These three pieces work together
to provide not only Questa SIM’s standard UVM support, but also its UVM-Aware debugging
capabilities.
Compiling Your Simulation for UVM-Aware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Simulating With UVM-Aware Debug Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
UVM Information in the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
UVM Transaction Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Setting UVM Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
UVM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
http://verificationacademy.com/topics/verification-methodology
Procedure
Compilation — The most recent UVM library comes pre-compiled with each Questa SIM
installation. It is highly recommended that you use the pre-compiled libraries supplied in the
Questa SIM install tree because it minimizes potential errors during compilation and simulation
startup, and it enables you to use the built-in UVM-Aware Debug capability without any
additional compilation overhead.
a. To use the pre-compiled libraries, your UVM source needs to import the uvm_pkg.
The UVM source is then automatically imported when you compile your UVM
source with a command similar to:vlog
<my_uvm>.sv
b. If you must use a UVM library that is not part of the Questa SIM installation, then
there are a variety of ways to compile it. One flow is outlined below. You will need
to compile the UVM source library and UVM DPI, the Questa SIM UVM-Aware
library, and your UVM testbench source files using the +incdir+ argument to vlog.
For example:
setenv UVM_HOME /absolute/path/to/appropriate/dir
setenv QUESTA_UVM_HOME /<questa_install_dir>/verilog_src/ \
questa_uvm_pkg-1.2
vlog +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv \
$(UVM_HOME)/src/dpi/uvm_dpi.cc -ccflags -DQUESTA
vlog +incdir+$(UVM_HOME)/src +incdir+$(QUESTA_UVM_HOME)/src \
$(QUESTA_UVM_HOME)/src/questa_uvm_pkg.sv
vlog +incdir+$(UVM_HOME)/<path>/<uvm_design_source>
Code Description
Define the $UVM_HOME environment variable to the location of the
UVM kit.
Define the $QUESTA_UVM_HOME variable to the location of
questa_uvm_pkg.sv
Compile the UVM kit
Compile the Questa SIM UVM-Aware library
Compile the UVM testbench source files
Note
If you change the version of UVM that you are using, you will need to recompile
the questa_uvm_pkg.
Besides the Structure window population and the random stability functionality, UVM-Aware
debug has other available features. These are all controlled with the vsim switch -uvmcontrol.
In Questa SIM these include: Message Viewer display of UVM messages, Wave window
viewing of UVM transactions, and automatic transaction logging of sequences.
Questa SIM UVM-aware debug tries not to adversely impact simulation performance, so the
default UVM debug setting is -uvmcontrol=struct, as described below. To enable all of the
features of the questa_uvm_pkg, the -uvmcontrol=all option can be used. The "all" option is
simple to specify but it could enable unnecessary functionality. Consequently, individual
features of vsim -uvmcontrol can be enabled and disabled with a keyword list. You can use any
of the following UVM-Aware arguments to vsim:
all — Enables all UVM-Aware functionality and debug options except disable and verbose.
You must specify verbose separately.
certe — Enables the integration of the elaborated design in the Certe tool. Disables Certe
features when specified as -certe.
disable — Prevents the UVM-Aware debug package from being loaded. Changes the results of
randomized values in the simulator.
msglog — Enables messages logged in UVM to be integrated into the Message Viewer
window. You must also enable WLF message logging by specifying tran or wlf with vsim
-msgmode. Disables message logging when specified as -msglog
none — Turns off all UVM-Aware debug features. Useful when multiple -uvmcontrol options
are specified in a separate script, makefile, or alias and you want to be sure all UVM debug
features are turned off.
struct — (default) Enables UVM component instances to appear in the Structure window.
UVM instances appear under “uvm_root” in the Structure window. Disables Structure window
support when specified as -struct.
trlog — Causes the Questa specific implementation of the UVM Recorder interface to be used
to record transactions. When the UVM automatically records sequences or sequence items, they
will be recorded in the WLF file. These recorded transactions will then be available to be
viewed in the Questa Wave window. Transaction logging is off by default, or can be turned off
explicitly by using '-trlog'.
verbose — Sends UVM debug package information to the transcript. Does not affect
functionality. Must be specified separately.
For more information on the -uvmcontrol option, Refer to the vsim command description in the
Reference Manual.
If you enable UVM message logging integration (via the vsim the -uvmcontrol=all or
uvmcontrol=msglog option) you should also enable the Message Viewing functionality with the
-msgmode option since the default behavior is for messages to only appear in the transcript
window. The -msgmode setting must be set to either "wlf or "both" to have messages populate
the Message Viewer window.
An orthogonal but useful and related feature is the vsim -classdebug feature. Among other
things, it allows class handles to be used on the command line to examine class contents, and
populates the Class Instance browser. For more information on the -classdebug option, Refer to
the vsim command description in the Reference Manual.
In summary, the fullest UVM-aware debug flow is available if vsim is invoked with the
following options:
You can set these vsim options as your default settings by adding them to the [vsim] section of
the modelsim.ini file. For example:
[vsim]
ClassDebug = 1
msgmode = both
UVMControl = struct,msglog,trlog
The red stars in Figure 7-18 indicate design elements created after you elaborate by entering
run 0 on the command line. You can explore the UVM components in your design and drag and
drop the design units into the Objects window, Wave window, Watch window, and more. Refer
to SystemVerilog Class Debugging for more information about viewing class objects.
Stream mode displays any existing transaction streams that exist at or below the UVM
component hierarchy selected in the Structure window. You can drag UVM stream objects into
the Wave window.
Config DB mode displays any configuration database items that are accessible to the UVM
component selected in the Structure window. It displays whether the configuration item is
written to or read as well as the value and type. All of the configuration database items are listed
when the uvm_root component is selected. You can use this window to help debug testbench
name mismatches which can cause failure of the testbench.
Sequences mode displays a list of sequencers and the active sequences running under them for
the currently selected UVM hierarchy.
Processes Window
You can use the Processes window to display a class instance ID and UVM components with
the UVM full name as well as the full path.
Refer to the Message Viewer Window description for more information about working with
objects in the Message Viewer window.
execution of the sequence body() is the recorded transaction for a sequence, and the start_item/
finish_item pair is the recorded transaction for a sequence item. If the body of a sequence
consumes no time, then a zero time transaction will be recorded. If the start_item/finish_item
pair consumes no time, then a zero time transaction will be recorded.
After a UVM transaction has been recorded, it can be viewed in the Wave window.
Procedure
1. The UVM transaction recording automation is implemented in two layers. Both layers
must be enabled in order for transactions to be recorded and viewable in the wave
window.
2. The first layer is the UVM itself. It will automatically call a user defined function named
'do_record' for the sequence or sequence_item. Do_record should be implemented to
record the interesting attributes for the sequence or sequence_item.
For example, you can use the UVM/OVM built-in ‘uvm_record_attribute() macro in
your transactions:
function void do_record(uvm_recorder recorder);
super.do_record(recorder);
Refer to Macros and Expanded Macros for information about viewing macros and
expanded macros in your source code.
3. The second layer is the Questa SIM specific layer which implements the actual
recording into the WLF file. Turn on “recording_detail” in your source.
For example:
uvm_config_db#(int)::set(null, "*", "recording_detail", 1);
Note
This setting is normally set before the UVM component hierarchy is constructed.
For example, in the top level of the testbench, before calling run_test(). The
recording_detail is a configuration variable which is built in to the UVM. It adheres to
all the usual config variable rules.
6. Open the UVM Details window by selecting View > UVM Details or by entering view
uvm details on the command line. Then select the UVM component that contains the
streams you want to view. The transaction streams are automatically loaded into the
UVM Details window.
7. Drag and drop the transaction streams you want to view from the UVM Details window
into the Wave window or choose Add > Wave to add the transaction stream to the Wave
window. Run the simulation and view the results in the Wave window (Figure 7-25).
Figure 7-25. UVM Transaction Streams in Wave Window
Examples
The following command breaks the simulation run on line 104 of file envA.sv.
The simulation breaks on line 104 if the 'this' pointer was representing the UVM component
"uvm_test_top.e1.a" as determined by a UVM get_full_name() function call.
bp in <function_name>
Examples
bp in /uvm_pkg::uvm_component::set_config_int -cond {this == @myunit@1}
bp in /mem_agent_pkg::mem_seq5::body
UVM Commands
Questa SIM provides a number of commands for use with UVM test benches.
For example:
uvm_test_top.middle.bottom0.my_obj
Finally, a UVM object may be referenced by the hierarchical path the simulator maps the UVM
object into within the sim:/uvm_root context (where the simulator collects all of the
dynamically-allocated UVM components). This hierarchical simulation path will be similar to a
UVM path, except that path delimiters will match the simulator's path delimiter settings, and
some component names may be slightly changed to use Verilog escaped identifiers if the
component names do not conform to Verilog naming rules. This type of path will be referred to
as a "simulation path". For example, a simulation path would look like, "sim:/uvm_root/
uvm_test_top/middle/bottom0.my_obj".
Any sub-command that accepts a UVM object handle parameter will always first look into the
current context to find that object. If the object does not exist in the current context, then the
parameter string will be parsed to determine if it contains a hierarchy specification as described
above. In all cases it will first check to see if the path is a class instance id string. If it is not, then
by default it will scan the path as a UVM-style path name. The default can be changed to be
simulation-style path names with the uvm mapmode command. Finally, even when the path
name mapping mode is in the default UVM-style mode, it still can accept simulation-style paths
if they start with a "sim:/uvm_root" prefix.
This chapter describes how to compile and simulate SystemC designs with Questa SIM. Questa
SIM implements the SystemC language based on the Open SystemC Initiative (OSCI) proof-of-
concept SystemC simulator. The default suupported version of SystemC is the IEEE 1666-2011
standard, SystemC-2.3.1. Release 2.3.1 of SystemC includes Release 2.0.3 of Transaction Level
Modeling (TLM) code. It is recommended that you obtain the OSCI functional specification or
the latest version of the IEEE Std 1666-2011, IEEE Standard SystemC Language Reference
Manual.
To enable SystemC-2.2 (IEEE 1666-2005 standard), you can use the Sc22Mode modelsim.ini
variable or the -sc22 argument for the sccom, vopt, and vsim commands. The -sc22 argument
should be used with the sccom command during both compile and link steps, and then used
again in the vopt step and in the vsim step to enable SystemC-2.2.
In addition to the functionality described in the OSCI specification, Questa SIM for SystemC
includes the following features:
Table 8-3 shows how to specify a SystemC kernel (either 2.3.1 or 2.2) and a compiler version
using the sccom, vopt, and vsim commands with the -sc22 and -cppinstall options. The -sc22
and -cppinstall options must be used with sccom for compiling and linking, as well as with vopt
for optimization and vsim for simulation.
For example, if the platform for your Questa SIM installation uses SystemC-2.3.1 as its default,
but you want to use SystemC-2.2 and the alternate gcc-4.3.3 compiler (gcc-4.5.0 is default for
SystemC-2.2), then you would enter the following commands:
When using a custom gcc, Questa SIM requires that you build the custom gcc with several
specific configuration options. These vary on a per-platform basis, as shown in the following
table:
• sjlj-exceptions or setjump longjump exceptions do not work with SystemC. It can cause
problems with catching exceptions thrown from SC_THREAD and SC_CTHREAD.
• Always build the compiler with --disable-sjlj-exceptions and never with --enable-sjlj-
exceptions.
• binutils-2.17 and binutils-2.18 do not work. Do not attempt to use those on win32
atleast.
If you do not have a GNU binutils2.16 assembler and linker, you can use the as and ld
programs. They are located inside the gcc in directory:
<install_dir>/lib/gcc-lib/<gnuplatform>/<ver>
The location of the as and ld executables has changed since gcc-3.4. For all gcc-4.x releases, as
and ld are located in:
<install_dir>/libexec/gcc/<gnuplatform>/<ver>
By default Questa SIM also uses the following options when configuring built-in gcc:
• --disable-nls
• --enable-languages=c,c++
These are not mandatory, but they do reduce the size of the gcc installation.
1. Create and map the working design library with the vlib and vmap statements, as
needed.
2. If you are simulating sc_main() as the top-level, skip to Step 3. Also, refer to
“Recommendations for using sc_main at the Top Level,” below.
If you are simulating a SystemC top-level module instead, then modify the SystemC
source code to export the top level SystemC design unit(s) using the
SC_MODULE_EXPORT macro. Refer to “Modifying SystemC Source Code” for
information and examples on how to convert sc_main() to an equivalent module.
3. Analyze the SystemC source using the sccom command, which invokes the native C++
compiler to create the C++ object files in the design library. Optionally, you can
distribute the compile of multiple source files across multiple machines.
See Using sccom in Addition to the Raw C++ Compiler for information on when you
are required to use sccom as opposed to another C++ compiler.
4. Perform a final link of the C++ source using sccom -link, and -sc22 if running SystemC
2.2. This process creates a shared object file in the current work library which will be
loaded by vsim at runtime.
You must rerun sccom -link before simulation if any new sccom compiles were
performed.
5. Load the design into the simulator using the standard Questa SIM vsim command.
6. Run the simulation using the run command, which you enter at the VSIM> command
prompt.
7. Debug the design using Questa SIM GUI features, including the Source and Wave
windows.
Recommendations for using sc_main at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Simulating with sc_main at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
int
sc_main(int, char*[])
{
design_top t1 = new design_top("t1");
sc_start(-1);
delete t1;
return 1;
}
sc_start(-1) in the OSCI simulator means that the simulation is run until the time it is
halted by sc_stop(), or because there were no future events scheduled at that time. The
sc_start(-1) in means that sc_main() is yielding to the Questa SIM simulator until the
current simulation session finishes.
• Avoid sc_main() going out of scope — Since sc_main() is run as a thread, it must not go
out of scope or delete any simulation objects while the current simulation session is
running. The current simulation session is active unless a quit, restart, sc_stop, $finish,
or assert is executed, or a new design is loaded. To avoid sc_main() from going out of
scope or deleting any simulation objects, sc_main() must yield control to the Questa
SIM simulation kernel before calling any delete and before returning from sc_main. In
Questa SIM, sc_start(-1) gives control to the Questa SIM kernel until the current
simulation session is exited. Any code after the sc_start(-1) is executed when the current
simulation ends.
int
sc_main(int, char*[])
{
top t1("t1");
top* t2 = new top("t2");
sc_signal<int> reset("reset");
t1.reset(reset);
t2->reset(reset);
sc_start(100, SC_NS); <-------- 1st part executed during
construction. yield to the
kernel for 100 ns.
return 1;}
If the run command specified at the simulation prompt before ending the current
simulation session exceeds the cumulative sc_start() times inside sc_main(), the
simulation continues to run on design elements instantiated both by sc_main() and
outside of sc_main(). For example, in this case, if sc_main() instantiates an sc_clock, the
clock will continue to tick if the simulation runs beyond sc_main().
On the other hand, if the current simulation ends before the cumulative sc_start() times
inside sc_main, the remainder of the sc_main will be executed before quitting the
current simulation session if the ScMainFinishOnQuit variable is set to 1 in the
modelsim.ini file. If this variable is set to 0, the remainder of sc_main will not executed.
The default value for this variable is 1. One drawback of not completely running
sc_main() is that memory leaks might occur for objects created by sc_main. Also, it is
possible that simulation stimulus and execution of the test bench will not complete, and
thus the simulation results will not be valid.
• sc_cycle(sc_time) is deprecated in SystemC 2.2. A suggested alternative to sc_cycle is
sc_start(sc_time). In case of a cycle accurate design, this will yield the same behavior.
Questa SIM will always convert sc_cycle() to sc_start() with a note.
• sc_initialize() is also deprecated in SystemC 2.2. The replacement for sc_initialize() is
sc_start(SC_ZERO_TIME). Questa SIM treats sc_initialize() as
sc_start(SC_ZERO_TIME).
• Questa SIM treats sc_main() as a top-level module and creates a hierarchy called
sc_main for it. Any simulation object created by sc_main() will be created under the
sc_main hierarchy in Questa SIM. For example, for the sc_main() described above, the
following hierarchy will be created:
/
|
|-- sc_main
|
|-- t1
|-- t2
|-- reset
The name() method for all objects created under the sc_main hierarchy will contain the
sc_main scope name. If applied to vsim, the -noscmainscopename argument will strip
the sc_main scope name from the names returned by the name() method.
Procedure
1. To simulate in Questa SIM using sc_main() as the top-level in your design:
2. Run vsim with sc_main as the top-level module:
vsim -c sc_main
3. Explicitly name all simulation objects for mixed-language designs, or to enable debug
support of objects created by sc_main(). Pass the declared name as a constructor
arguments, as follows:
sc_signal<int> sig("sig");
top_module* top = new top("top");
Tip
: For SystemC-only designs, the simulation runs even if debug support is not
enabled. Mixed language designs, however, will not elaborate if explicit naming is
not performed in sc_main(). Questa SIM issues an error message to this effect.
4. Optionally, override the default stack size (10Mb) for sc_main() in the modelsim.ini file:
ScMainStackSize 1 Gb
Consider the following scenario: You have a SystemC file which is used in all of your tests,
common.cpp, and then you have test-specific SystemC files, such as test1.cpp, test2.cpp, etc.
The following procedure is an example of how you can manage your tests and common code.
Prerequisites
• Must be running Questa SIM 6.6a or higher.
Procedure
1. Create a library for your intermediate shared object:
vlib common
6. Link the test specific object files with the shared object in each of the test libraries:
sccom -link -libshared common -lib test1 -work test1
sccom -link -libshared common -lib test2 -work test2
where -libshared specifies the location of the intermediate shared object, -lib specifies
the library that contains the compiled object files, and -work specifies the location of the
final systemc.so.
7. Run the tests:
vsim -lib work1 top
vsim -lib work2 top
Note
To run the above steps with SystemC-2.2 instead of the default SystemC-2.3.1, use
the
-sc22 argument in each of the steps.
Distributing SystemC IP
This section describes several methods you can use to distribute your SystemC IP for others to
use in a Questa SIM environment.
One requirement is that you, the IP provider, must distribute the IP library for each major
release version (such as 10.2 or 10.3). Patch releases (such as 10.1b or 10.2a) are mostly
backward compatible, and therefore do not require you to recompile libraries with each patch.
However, sometimes the SystemC header files may be modified. In such situations, you must
distribute a recompiled library for a patch release.
where you distribute the archived library archive_file_name to IP users. However, you
should note that there will not be any debug information generated for the IP.
• Distribute IP as shared libraries
To create a shared library perform the following actions:
vlib <work library>
sccom <options> <source files>
sccom -linkshared -work <work_library>
o If you are distributing a SystemC test shared library that was created using the
-linkshared or -link arguments with the sccom command, the -nodebug argument
needs to be specified during the compile time and link time. For example,
Linkshared flow
sccom -nodebug <source files>
sccom -nodebug -linkshared -work <work_library>
Compiling and linking a SystemC design using the -nodebug argument with the sccom
command will only affect the debug visibility of the objects in the GUI. This will not
affect the simulation results in any way.
The Questa SIM SystemC libraries may contain third-party software, including open source
software. Please see the "Third-Party Software for Questa and ModelSim Products"
documentation for licensing terms. If you distribute your SystemC IP to others, you will be
required to meet the licensing terms of the third-party software included in the Questa SIM
SystemC libraries, as well as the licensing terms provided to you by Mentor Graphics. Should
you have further questions about your obligations, please seek legal advice.
This creates a library named work. By default, compilation results are stored in the work
library.
The work library is actually a subdirectory named work. This subdirectory contains a special
file named _info.
Note
Do not create libraries using UNIX commands—always use the vlib command.
See vlib and Design Libraries for additional information on working with libraries.
Since it is natural for simulators to elaborate design-unit(s) as tops, it is recommended that you
use design units as your top-level rather than relying on sc_main based elaboration and
simulation. There are a few limitations and requirements for running a sc_main() based
simulation.
If you have a sc_main() based design and would like to convert it to a design-unit based one, a
few modifications must be applied to your SystemC source code. To see example code
containing the code modifications detailed in Modifying SystemC Source Code, see Code
Modification Examples.
Related Topics
sccom command
Additionally, you can distribute the compilation process to multiple cores across multiple
machines by specifying the -machines <hosts.txt> option along with the -j <value> option. You
can also specify a maximum number of processes for a particular machine specified in the hosts
file. All host machines specified must be accessible from the machine where the sccom
command is run.
Related Topics
sccom command
This approach is useful if you are running a design in regression mode, or creating a library (.a)
from the object files (.o) created by sccom, to be linked later with the SystemC shared object.
Related Topics
sccom command
CppPath /u/abc/gcc-4.2.1/bin/g++
SC_CTOR(mytop)
: mysig("mysig"),
mod("mod")
{
mod.outp(mysig);
}
};
SC_MODULE_EXPORT(top);
sc_start(100, SC_NS);
}
#endif
• Its pre-processor output is different from the last time it was successfully compiled (see
Note below). This includes changes in included header files and to the source code itself.
• You invoke sccom with a different set of command-line options that have an impact on
the gcc command line. Preserving all settings for the gcc command ensures that Questa
SIM re-compiles source files when a different version of gcc is used or when a platform
changes.
Note
Pre-processor output is used because it prevents compilation on a file with the
following types of changes:
Example
The following example shows how to compile a SystemC design with automatic incremental
compilation.
1. Run sccom -incr on three files and re-link all compiled files in the design.
% sccom -incr top.cpp and2.cpp or2.cpp
Model Technology ModelSim SE sccom DEV compiler 2003.05 Mar 2 2008
Exported modules:
top
% sccom -incr -link
Model Technology ModelSim SE sccom DEV compiler 2003.05 Mar 2 2008
2. After changing functional content of the top module, re-compile and re-link.
% sccom -incr top.cpp and2.cpp or2.cpp
Model Technology ModelSim SE sccom DEV compiler 2003.05 Mar 2 2008
Exported modules:
top
Note
You must compile all included libraries (using -lib) with -incr for automatic incremental
compilation to work in linking mode. Failing to do so generates an error.
Limitations
• Automatic incremental compile is only supported for source files compiled with sccom.
Questa SIM does not track files for changes if they are compiled directly using a C++
compiler.
• Physically moving the library that holds a shared object forces re-creating that shared
object next time. This applies only to the directories holding the shared object, not to the
libraries that hold object files.
• If the SystemC source file includes a static library, then any change in that static library
will not cause Questa SIM to recompile the source file.
• If a design file consists of more than one SystemC module, changing even one module
causes Questa SIM to recompile the entire source file (and all the modules contained in
it), regardless of whether the other modules were changed or not.
• Automatic incremental archiving is not supported (if you use the -archive argument, the
-incr argument has no effect).
For example, assume you have the following templatized SystemC module:
You can specialize the module by setting T = int, thereby removing the template, as follows:
Or, alternatively, you could write a wrapper to be used over the template module:
SC_MODULE_EXPORT(modelsim_top);
Use of Extensions
You must include the declaration of all types (for which you want extensions to be generated) in
a header file.
2. Creates a C++ file (.cpp) that includes all the header files that have all the type
declarations and define a global variable for each type you want to extend.
Result: The C++ file for the above type looks like this:
#include "test.h"
packet_t pack;
4. Run the sccom -dumpscvext command to dump SCV extensions for all the types for
whom global variables have been defined in the C++ file.
sccom -dumpscvext mypacket.cpp
where mypacket.cpp is the name of the C++ file containing global variable definitions.
Result: The generated extensions are displayed in stdout (similar to the way scgenmod
dumps a foreign module declaration).
Note
You must define global variables for all types for which extensions need to be
generated. The sccom -dumpscvext command will cause an error out if it cannot find
any global variables defined in the supplied C++ file.
The command also automatically inserts the following header in mypacket.cpp with the
generated extensions:
#ifndef TYPENAME_H
#define TYPENAME_H
#include "scv.h"
<generated extensions>
#endif
Note
If extensions are generated for more than one type, the type name of the first type
will be used as TYPENAME in the ifndef preprocessor.
Related Topics
SCV Extensions for User-specified Types
/* SystemC type */
struct packet_t {
sc_uint<8> addr;
sc_uint<12> data;
};
SCV_EXTENSIONS(packet_t) {
public:
scv_extensions< sc_uint<8> > addr;
scv_extensions< sc_uint<12> > data;
SCV_EXTENSIONS_CTOR(packet_t) {
SCV_FIELD(addr);
SCV_FIELD(data);
}
};
Example 8-3. Generating SCV Extensions for a Class without Friend (Private
Data Not Generated)
/* SystemC type */
class restricted_t {
public:
sc_uint<8> public_data;
private:
sc_uint<8> private_data;
};
SCV_EXTENSIONS(restricted_t) {
public:
scv_extensions< sc_uint<8> > public_data;
SCV_EXTENSIONS_CTOR(restricted_t) {
SCV_FIELD(public_data);
}
};
Example 8-4. Generating SCV Extensions for a Class with Friend (Private Data
Generated)
/* SystemC type */
class restricted_t {
friend class scv_extensions<restricted_t>;
public:
sc_uint<8> public_data;
private:
sc_uint<8> private_data;
};
SCV_EXTENSIONS(restricted_t) {
public:
scv_extensions< sc_uint<8> > public_data;
scv_extensions< sc_uint<8> > private_data;
SCV_EXTENSIONS_CTOR(restricted_t) {
SCV_FIELD(public_data);
SCV_FIELD(private_data);
}
};
Enums
Note the following set of rules for generating a SCV extensions for enumerated types.
/* SystemC type */
SCV_ENUM_EXTENSIONS(instruction_t) {
public:
SCV_ENUM_CTOR(instruction_t) {
SCV_ENUM(ADD);
SCV_ENUM(SUB);
}
};
Named Constraints
The open SCV API supports the following macros for creating constraint data expression
initializers data member fields of a user-defined constraint, based on a derivation of class
scv_constraint_base:
#define SCV_CONSTRAINT(expr)
#define SCV_SOFT_CONSTRAINT(expr)
The first defines a hard constraint and the second defines a soft constraint.
The following example shows a user-defined constraint that uses these macros in the SCV
constraint constructor macro, SCV_CONSTRAINT_CTOR().
SCV_CONSTRAINT_CTOR( EtherFrameConstraintT ){
printf( "Start initializing EtherFrameConstraint ...\n" );
SCV_CONSTRAINT( Type() == (SDF_BYTE << 8 | SDF_BYTE) );
SCV_CONSTRAINT( DestAddr() != SrcAddr() );
SCV_CONSTRAINT( DestAddr() < 0xffLL ); // Limit to 48 bits
SCV_CONSTRAINT( SrcAddr() < 0xffLL ); // Limit to 48 bits
}
};
To augment these macros, the following macro allows a constraint field to be named:
class scv_constraint_expr {
public:
typedef enum { HARD, SOFT } scv_constraint_type;
scv_constraint_expr(
const char* name, scv_constraint_type type, scv_expression e,
const char* file = "unknown", int line = 0 );
void disable();
void enable();
bool is_disabled() const;
};
When the constraint is created, the file name and line # are captured in the class
scv_constraint_expr object so that it can be provided later to parts of the internal SCV
implementation for reporting purposes, such as error messages. You can do this by referencing
the ANSI C FILE and LINE directives at the point where the name constraint is constructed.
Accessors ::name(), ::file(), and ::line() are provided to class scv_constraint_expr as shown
above to provide this information for messaging, if needed.
class scv_constraint_base {
...
public:
...
bool disable_constraint( const char* name );
bool enable_constraint( const char* name );
...
};
You can use these methods to enable or disable any named constraint field in a user-defined
constraint object derived from class scv_constraint_base. The implementation of class
scv_constraint_base can use names as lookup keys to an internal table of class
scv_constraint_expr objects. Once looked up, you can call the ::enable() or ::disable() method
on those objects appropriately.
Further, you can constrain this randomization of vector size simply by calling
vector_size.keep_only() on the ::vector_size member of the scv_extensions< vector > class. The
::keep_only() method can be given a range of values that size can assume.
Further, you can constrain this randomization simply by calling vector_size.keep_only() on the
::vector_size member of the scv_extensions< T[N] > class. The ::keep_only() method can be
given a range of values that size can assume.
Multiple optimized top design modules can be specified. For more information about simulation
with multiple optimized design modules refer to vsim <library_name>.<design_unit>.
For example, use the vsim command to begin simulation on a design named top:
vsim top
When the GUI appears (as shown in Figure 8-1), you can expand the hierarchy of the design to
view the SystemC modules. SystemC objects are denoted by green icons (see Design Object
Icons and Their Meanings for more information).
To simulate from a command shell without using the GUI, invoke vsim with the -c argument:
vsim -c <top_level_module>
Tip
If you want to run a design with sc_main() as the top level, refer to Recommendations for
using sc_main at the Top Level.
Running Simulation
Run the simulation using the run command or choose one of the Simulate > Run selections
from the main menu.
Two related yet distinct concepts are involved with determining the simulation resolution: the
SystemC time unit and the simulator resolution. The following table describes the concepts, lists
the default values, and defines the methods for setting/overriding the values.
Available settings for both time unit and resolution are: 1x, 10x, or 100x of fs, ps, ns, us, ms, or
sec.
You can view the current simulator resolution by invoking the report command with the
simulator state option.
When deciding what to set the simulator’s resolution to, you must keep in mind the relationship
between the simulator’s resolution and the SystemC time units specified in the source code. For
example, with a time unit usage of:
sc_wait(10, SC_PS);
a simulator resolution of 10ps would be fine. No rounding off of the ones digits in the time units
would occur. However, a specification of:
sc_wait(9, SC_PS);
would require you to set the resolution limit to 1ps in order to avoid inaccuracies caused by
rounding.
Note
If you have a design in which some state-based code must be placed in the constructor,
destructor, or the elaboration callbacks, you can use the mti_IsVoptMode() function to
determine if the elaboration is being run by vopt. You can use this function to prevent vopt from
executing any state-based code.
The following virtual functions should be used to initialize and clean up state-based code, such
as logfiles or the VCD trace functionality of SystemC. They are virtual methods of the
following classes: sc_port_base, sc_module, sc_channel, and sc_prim_channel. You can think
of them as phase callback routines in the SystemC language:
• before_end_of_elaboration () — Called after all constructors are called, but before port
binding.
1. Constructors
2. before_end_of_elaboration ()
3. end_of_elaboration ()
4. start_of_simulation ()
5. end_of_simulation ()
6. Destructors
Usage of Callbacks
The start_of_simulation() callback is used to initialize any state-based code. The
corresponding cleanup code should be placed in the end_of_simulation() callback. These
callbacks are called by vsim only during simulation and thus are safe.
Related Topics
SCV Extensions for User-specified Types
Types
bool, sc_bit short, unsigned short
sc_logic long, unsigned long
sc_bv<width> sc_bigint<width>
sc_lv<width> sc_biguint<width>
sc_int<width> sc_ufixed<W,I,Q,O,N>
sc_uint<width> short, unsigned short
sc_fix long long, unsigned long long
sc_fix_fast float
sc_fixed<W,I,Q,O,N> double
sc_fixed_fast<W,I,Q,O,N> enum
sc_ufix pointer
sc_ufix_fast array
sc_ufixed class
sc_ufixed_fast struct
sc_signed union
sc_unsigned ac_int
char, unsigned char ac_fixed
int, unsigned int
port is a channel derived from an sc_prim_channel. If it is, you can add the macro
MTI_SC_PORT_ENABLE_DEBUG to the channel class’ public declaration area, as shown in
this example:
{
...
public:
MTI_SC_PORT_ENABLE_DEBUG
};
The number of elements must match for vectors; specific indexes are ignored.
sccom mytop -g
Or, if you plan to use it every time you run the compiler, you can specify it in the modelsim.ini
file with the CppOptions variable. See the modelsim.ini Variables for more information.
The source code debugger, C Debug, is automatically invoked when the design is compiled for
debug in this way.
Figure 8-2 shows an example of how to set breakpoints in a Source window (Line 59) and
single-step through your SystemC/C++ source code.
Note
To disallow source annotation, use the -nodbgsym argument for the sccom command. This
disables the generation of symbols for the debugging database in the library.
By default, auto-stepping out of the library for debugging is enabled, which means stepping into
the library is not allowed (cdbg allow_lib_step off). So, if you step into a library function,
execution will automatically return to your code.
cdbg allow_lib_step on
Now, execution will not automatically step out from library functions, but it will step into the
library code.
The allow_lib_step argument to the cdbg command takes a value of "on" or "off."
You can also perform this action in the GUI by selecting Tools > CDebug > Allow lib step
from the menus (Figure 8-3).
For example, assume that the debugger has stepped to a library function call. If this were the
only library function call in the current line, execution would go the next line in your code
(there would be no need for the “step out” action). However, if there are more function calls in
the current line, execution comes back to the same line, and the next 'step -over' operation goes
to the next line in your code. So the debugging operation always stays in your code, regardless
of where it steps.
NOTE: You can also set breakpoints by opening a file in source window and clicking on
a line number.
3. Load the design by entering the vsim command. Questa SIM automatically stops after
loading the shared library and sets all the constructor breakpoints. You can set additional
constructor breakpoints here.
4. The run -continue command elaborates the design and stops the simulation at the
constructor breakpoint.
5. You can also set destructor breakpoints using these same steps in either the Cdebug Init
mode or the Automated Constructor breakpoint flow; or, after the design is loaded. If
you set destructor breakpoints before loading the design, then Questa SIM keeps all the
breakpoints enabled even after design is loaded.
Results
When you set a destructor breakpoint, Questa SIM automatically sets up in Stop on quit mode
(see Debugging Functions when Quitting Simulation). The debugger will stop at the breakpoint
after you issue the quit -f command in Questa SIM. This allows you to step through and
examine the code. Run the run -continue command when you have finished examining the C
code.
Because the Stop on quit mode is set up, when simulation completes, Questa SIM
automatically quits C-debugger and the GUI (whether or not a C breakpoint was hit and you
return to the VSIM> prompt).
Related Topics
bp
Naming Requirements
In order to make a global viewable for debugging purposes, the name given must match the
declared signal name.
An example:
sc_signal<bool> clock("clock");
For statics to be viewable, the name given must be fully qualified, with the module name and
declared name, as follows:
<module_name>::<declared_name>
For example, the static data member "count" is viewable in the following code excerpt:
SC_MODULE(top)
{
static sc_signal<float> count; //static data member
....
}
In the case of the above examples, the debugging statements for examining "top/count" (a static)
and "clock" (a global) would be:
is equivalent to:
sc_signal <sc_lv<3>> a;
for debug purposes. Questa SIM shows one signal - object "a" - in both cases.
The following aggregate would appear in the Wave window as shown in Figure 8-5:
module **mod_inst;
mod_inst = new module*[2];
mod_inst[0] = new module("mod_inst[0]");
mod_inst[1] = new module("mod_inst[1]");
Limitations
• The instance names of modules containing dynamic arrays must match the
corresponding C++ variables, such as “mod_inst[0]” and “mod_inst[1]” in the example
above. If not named correctly, the module instances simulate correctly, but are not
debuggable.
• For sc_foreign_module arrays, if [] in the name is desired, please use the extended
identifier syntax to name the module. For example:
foreign_module **foreign_module_inst;
foreign_module_inst = new foreign_module*[2];
foreign_module_inst[0] = new foreign_module
("\\foreign_module_inst[0]\\");
foreign_module_inst[1] = new foreign_module
("\\foreign_module_inst[1]\\");
Viewing FIFOs
Context: SystemC objects
In Questa SIM, the values contained in an sc_fifo appear in a definite order. The top-most or
left-most value is always the next to be read from the FIFO. Elements of the FIFO that are not in
use are not displayed.
Example of a signal where the FIFO has five elements:
# examine f_char
# {}
VSIM 4> # run 10
VSIM 6> # examine f_char
# A
VSIM 8> # run 10
VSIM 10> # examine f_char
# {A B}
VSIM 12> # run 10
VSIM 14> # examine f_char
# {A B C}
VSIM 16> # run 10
VSIM 18> # examine f_char
# {A B C D}
VSIM 20> # run 10
VSIM 22> # examine f_char
# {A B C D E}
VSIM 24> # run 10
VSIM 26> # examine f_char
# {B C D E}
VSIM 28> # run 10
VSIM 30> # examine f_char
# {C D E}
VSIM 32> # run 10
VSIM 34> # examine f_char
# {D E}
The Questa SIM tool detects and displays SystemC memories. A memory is defined as any
member variable of a SystemC module which is defined as an array of the following type:
1. Use the member function mti_set_typename and apply it to the modules. Pass the
actual derived class name to the function when an instance is constructed, as shown in
Example 8-7.
SC_MODULE(top) {
base_mod* inst;
SC_CTOR(top) {
if (some_condition) {
inst = new d1_mod("d1_inst");
inst->mti_set_typename("d1_mod");
} else {
inst = new d2_mod("d2_inst");
inst->mti_set_typename("d2_mod");
}
}
};
Tip
: In this example, the class names are simple names, which may not be the case if the
type is a class template with lots of template parameters. Look up the name in
<work>/moduleinfo.sc file, if you are unsure of the exact names.
Here is the code for which the above SC_MODULE was modified:
sc_signal<int> base_sig;
int base_var;
...
};
sc_signal<int> d1_sig;
int d1_var;
...
};
sc_signal<int> d2_sig;
int d2_var;
...
};
SC_MODULE(top) {
base_mod* inst;
SC_CTOR(top) {
if (some_condition)
inst = new d1_mod("d1_inst");
else
inst = new d2_mod("d2_inst");
}
};
In this unmodified code, the sccom compiler could only see the declarative region of a module,
so it thinks "inst" is a pointer to the "base_mod" module. After elaboration, the GUI would only
show "base_sig" and "base_var" in the Objects window for the instance "inst."
You really wanted to see all the variables and signals of that derived class. However, since you
didn’t associate the proper derived class type with the instance "inst", the signals and variables
of the derived class are not debuggable, even though they exist in the kernel.
The solution is to associate the derived class type with the instance, as shown in the modified
SC_MODULE above.
The custom debug interface provides debug support for the following SystemC objects (T is a
user defined type, or a user-defined channel or port):
• T
• sc_signal<T>
• sc_fifo<T>
• tlm_fifo<T>
• sc_in<T>
• sc_out<T>
• sc_inout<T>
Debugging Instructions
To provide custom debug for any object:
1. Register a callback function — one for each instance of that object — with the
simulator. Specify the maximum length of the string buffer to be reserved for an object
instance. See Registration and Callback Function Syntax.
2. The simulator calls the callback function, with the appropriate arguments, when it needs
the latest value of the object.
The registration function can be called from the phase callback function
before_end_of_elaboration(), or anytime before this function during the elaboration
phase of the simulator.
3. The Questa SIM simulator passes the callback function a pre-allocated string of a length
specified during registration. The callback function must write the value of the object in
that string, and it must be null terminated (\0).
4. The Questa SIM simulator takes the string returned by the callback function as-is and
displays it in the Objects window, Wave window, and CLI commands (such as
examine). The describe command on custom debug objects simply reports that the
object is a custom debug object of the specified length.
The macro used to register an object for debugging is
SC_MTI_REGISTER_CUSTOM_DEBUG. Occasionally, Questa SIM fails to register an
object because it determines that the object cannot be debugged. In such cases, an error message
is issued to that effect. If this occurs, use the
SC_MTI_REGISTER_NAMED_CUSTOM_DEBUG to both name and register the object for
debugging.
void SC_MTI_REGISTER_CUSTOM_DEBUG
(void* obj, size_t value_len,
mtiCustomDebugCB cb_func);
void SC_MTI_REGISTER_NAMED_CUSTOM_DEBUG
(void* obj, size_t value_len,
mtiCustomDebugCB cb_func, const char* name);
Callback:
class myclass {
private:
int x;
int y;
public:
void get_string_value(char format_str, char* mti_value);
size_t get_value_length();
...
};
SC_MODULE(test) {
myclass var1;
myclass* var2;
SC_CTOR(test) {
SC_MTI_REGISTER_CUSTOM_DEBUG(
&var1,
var1.get_value_length(),
mti_myclass_debug_cb);
SC_MTI_REGISTER_CUSTOM_DEBUG(
var2,
var2->get_value_length(),
mti_myclass_debug_cb);
}
};
sc_signal, sc_fifo and tlm_fifo of type T and Associated Ports would be:
SC_MODULE(test) {
sc_signal<myclass> sig1;
sc_signal<myclass> *sig2;
sc_fifo<myclass> fifo;
SC_CTOR(test) {
myclass temp;
SC_MTI_REGISTER_CUSTOM_DEBUG(
&sig1,
temp.get_value_length(),
mti_myclass_debug_cb);
SC_MTI_REGISTER_CUSTOM_DEBUG(
sig2,
temp.get_value_length(),
mti_myclass_debug_cb);
SC_MTI_REGISTER_CUSTOM_DEBUG(
&fifo,
temp.get_value_length(),
mti_myclass_debug_cb);
}
};
By registering the primitive channel sc_signal<T> for custom debug, any standard port
connected to it (sc_in<T>, sc_out<T>, sc_inout<T>, sc_fifo_in<T>, and so forth) automatically
is available for custom debug. It is illegal to register any built-in ports for custom debug
separately.
Please see the section on variables of type T in Example 8-8 for more details on the registration
and callback mechanism for such objects.
You have two choices available to you for making user defined ports debuggable:
In this case, you may not separately register the port for custom debug.
• Specific port registration
Register the port separately for custom debug. To do this, simply register the specific
port, without using the macro. The callback and registration mechanism is the same as a
variable of type T.
Any port object registered for custom debug is treated as a variable of a user defined type.
Please see Example 8-8, variables of type T, for more details on the registration and callback
mechanism for such objects.
Channels and ports of this category are supported for debug natively in Questa SIM. Questa
SIM treats them as variables of type T. These channels and ports can be registered for custom
debug. The registration and callback mechanism is the same as for a variable of type T, as
shown in Example 8-8 above.
• Any test bench code inside sc_main() should be moved to a process, normally an
SC_THREAD process.
• All C++ variables in sc_main(), including SystemC primitive channels, ports, and
modules, must be defined as members of sc_module. Therefore, initialization must take
place in the SC_CTOR. For example, all sc_clock() and sc_signal() initializations must
be moved into the constructor.
Table 8-9 shows a simple example of how to convert sc_main to a module that you can
elaborate with the vsim command.
Here, you would use the following run command for the modified code as the equivalent to the
sc_start(100, SC_NS) statement in the original OSCI code:
run 100 ns
Table 8-10 shows a slightly more complex conversion that illustrates the use of sc_main() and
signal assignments, and how you would get the same behavior using Questa SIM.
{ {
reset.write(1);
wait(5, SC_NS);
reset.write(0);
wait(100, SC_NS);
reset.write(1);
wait(5, SC_NS);
reset.write(0);
wait(100, SC_NS);
sc_stop();
}
SC_MODULE_EXPORT(new_top);
Table 8-11 shows a conversion that modifies a design using an SCV transaction database.
Questa SIM requires that you create the transaction database before calling the constructors on
the design subelements.
Take care to preserve the order of functions called in sc_main() of the original code.
You cannot place subelements in the initializer list, since the constructor body must be executed
prior to their construction. Therefore, you must make the subelements as pointer types by
creating them with "new" in the SC_CTOR() module.
• The run command in Questa SIM is equivalent to sc_start(). In the SystemC simulator,
sc_start() runs the simulation for the duration of time specified by its argument. In
Questa SIM the run command runs the simulation for the amount of time specified by its
argument.
• The sc_cycle(), and sc_start() functions are not supported in Questa SIM.
• The default name for sc_object() is bound to the actual C object name. However, this
name binding only occurs after all sc_object constructors are executed. As a result, any
name() function call placed inside a constructor will not pick up the actual C object
name.
• The value returned by the name() method prefixes OSCI-compliant hierarchical paths
with "sc_main", which is Questa SIM's implicit SystemC root object. For example, for
the following example code:
#include "systemc.h"
SC_MODULE(bloc)
{
SC_CTOR(bloc) {}
};
SC_MODULE(top)
{
bloc b1 ;
SC_CTOR(top) : b1("b1") { cout << b1.name() << endl ; }
};
and Questa
SIM returns:
sc_main.top_i.b1
Fixed-Point Types
Contrary to OSCI, Questa SIM compiles the SystemC kernel with support for fixed-point types.
If you want to compile your own SystemC code to enable that support, you must first define the
compile time macro SC_INCLUDE_FX.
• Enter the g++/aCC argument -DSC_INCLUDE_FX on the sccom command line, such
as:
sccom -DSC_INCLUDE_FX top.cpp
• Add a define statement to the C++ source code before the inclusion of the systemc.h, as
shown below:
#define SC_INCLUDE_FX
#include "systemc.h"
Algorithmic C Datatype Support
Questa SIM supports native debug for the Algorithmic-C data types ac_int and ac_fixed. The
Algorithmic C data types are used in Catapult C Synthesis, a tool that generates optimized RTL
from algorithms written as sequential ANSI-standard C/C++ specifications. These data types
are synthesizable and run faster than their SystemC counterparts sc_bigint, sc_biguint, sc_fixed
and sc_ufixed.
To use these data types in the simulator, you must obtain the datatype package and specify the
path containing the Algorithmic C header files with the -I argument on the sccom command
line:
To enable native debug support for these datatypes, you must also specify the
-DSC_INCLUDE_MTI_AC argument on the sccom command line.
Native debug is only supported for Version 1.2 and above. If you do not specify
-DSC_INCLUDE_MTI_AC, the GUI displays the C++ layout of the datatype classes.
To enable support for cin, the design source files must be compiled with -DUSE_MTI_CIN
sccom option. For example:
getinput(cin);
A workaround for this case, the source code needs to be modified as shown below:
void getinput()
{
int input_data;
...
cin >> input_data;
..
}
getinput();
ModelSim includes the header files and exmaples from the OSCI SystemC TLM (Transaction
Level Modeling) Library, Release 2.0.3. The TLM library can be used with simulation, and
requires no extra arguments or files. TLM objects are not debuggable, with the exception of
tlm_fifo.
Experimental Features
This release of SystemC contains the "Proof of Concept" simulator for the IEEE 1666-2011
SystemC standard that is provided by Accellera Systems Initiative. Each release of SystemC
also contains experimental features. By default, these features are not enabled in the default
library configuration.
The experimental features of SystemC 2.3.1 are listed below and are not supported by Questa
SIM for this release. By default, they are not enabled.
Caution
Do not build the SystemC library using the
SC_ENABLE_SIMULATION_PHASE_CALLBACKS and
SC_ENABLE_SIMULATION_PHASE_CALLBACKS_TRACING defines
(which enable this unsupported feature).
• sc_argc() — Returns the number of arguments specified on the vsim command line with
the -sc_arg argument. This function can be invoked from anywhere within SystemC
code.
• sc_argv() — Returns the arguments specified on the vsim command line with the
-sc_arg argument. This function can be invoked from anywhere within SystemC code.
Example:
int argc;
const char * const * argv;
argc = sc_argc();
argv = sc_argv();
These are the only SystemC types that have construction time parameters. The default size for
these types is 32. If you require values other than the default parameters, you need to read this
section.
If you are using one of these types in a SystemC signal, port, fifo, or an aggregate of one of
these (such as an array of sc_signal), you cannot pass the size parameters to the type. This is a
limitation imposed by the C++ language. Instead, SystemC provides a global default size (32)
that you can control.
For sc_signed and sc_unsigned, you need to use the two objects, sc_length_param and
sc_length_context, and you need to use them in an unusual way. If you just want the default
vector length, simply do this:
SC_MODULE(dut) {
sc_signal<sc_signed> s1;
sc_signal<sc_signed> s2;
SC_CTOR(dut)
: s1("s1"), s2("s2")
{
}
}
For a single setting, such as using five-bit vectors, your module and its constructor would look
like the following:
SC_MODULE(dut) {
sc_length_param l;
sc_length_context c;
sc_signal<sc_signed> s1;
sc_signal<sc_signed> s2;
SC_CTOR(dut)
Notice that the constructor initialization list sets up the length parameter first, assigns the length
parameter to the context object, and then constructs the two signals. You DO pass the name to
the signal constructor, but the name is passed to the signal object, not to the underlying type.
There is no way to reach the underlying type directly. Instead, the default constructors for
sc_signed and sc_unsigned reach out to the global area and get the currently defined length
parameter—the one you just set.
If you need to have signals or ports with different vector sizes, you need to include a pair of
parameter and context objects for each different size. For example, the following uses a five-bit
vector and an eight-bit vector:
SC_MODULE(dut) {
sc_length_param l1;
sc_length_context c1;
sc_signal<sc_signed> s1;
sc_signal<sc_signed> s2;
sc_length_param l2;
sc_length_context c2;
sc_signal<sc_signed> u1;
sc_signal<sc_signed> u2;
SC_CTOR(dut)
: l1(5), c1(l1), s1("s1"), s2("s2"),
l2(8), c2(l2), u1("u1"), u2("u2")
{
}
}
With simple variables of this type, you reuse the context object. However, you must have the
extra parameter and context objects when you are using them in a constructor-initialization list
because the compiler does not allow repeating an item in that list.
The four fixed-point types that use construction parameters work exactly the same way, except
that they use the objects sc_fxtype_contxt and sc_fxtype_params to do the work. Also, there are
more parameters you can set for fixed-point numbers. Assuming you want to set only the length
of the number and the number of fractional bits, the following example is similar to the
preceding example, modified for fixed-point numbers:
SC_MODULE(dut) {
sc_fxtype_params p1;
sc_fxtype_contxt c1;
sc_signal<sc_fix> s1;
sc_signal<sc_fix> s2;
sc_fxtype_params p2;
sc_fxtype_contxt c2;
sc_signal<sc_ufix> u1;
sc_signal<sc_ufix> u2;
SC_CTOR(dut)
: p1(5,0), c1(p1), s1("s1"), s2("s2"),
p2(8,5), c2(p2), u1("u1"), u2("u2")
{
}
}
You may have one or more threads needing a larger stack size. If so, call the SystemC function
set_stack_size() and adjust the stack to accommodate your needs. Note that you can ask for too
much stack space and have unexplained behavior as well.
/home/cmg/newport2_systemc/chip/vhdl/work/systemc.so: symbol
_Z28host_respond_to_vhdl_requestPm:
Missing Definition
If the undefined symbol is a C function in your code or a library you are linking with, be sure
that you declared it as an extern "C" function:
This should appear in any header files include in your C++ sources compiled by sccom. It tells
the compiler to expect a regular C function; otherwise the compiler decorates the name for C++
and then the symbol can't be found.
Also, be sure that you actually linked with an object file that fully defines the symbol. You can
use the "nm" utility on Unix platforms to test your SystemC object files and any libraries you
link with your SystemC sources. For example, assume you ran the following commands:
sccom test.cpp
sccom -link libSupport.a
If there is an unresolved symbol and it is not defined in your sources, it should be correctly
defined in any linked libraries:
Missing Type
When you get errors during design elaboration, be sure that all the items in your SystemC
design hierarchy, including parent elements, are declared in the declarative region of a module.
If not, sccom ignores them.
For example, consider a design containing SystemC over VHDL. The following declaration of a
child module "test" inside the constructor module of the code is not allowed and will produce an
error:
SC_MODULE(Export)
{
SC_CTOR(Export)
{
test *testInst;
testInst = new test("test");
}
};
The error results from the fact that the SystemC parse operation will not see any of the children
of "test". Nor will any debug information be attached to it. Thus, the signal has no type
information and cannot be bound to the VHDL port.
The solution is to move the element declaration into the declarative region of the module.
To resolve the error, recompile the design using sccom. Make sure any include paths read by
sccom do not point to a SystemC 2.2 or 2.3.1 installation. By default, sccom automatically
picks up the Questa SIM SystemC header files.
and
The first command ensures that your SystemC object files are seen by the linker before the
library "liblocal.a" and the second command ensures that "liblocal.a" is seen first. Some linkers
can look for undefined symbols in libraries that follow the undefined reference while others can
look both ways. For more information on command syntax and dependencies, see sccom.
work/sc/gensrc/test_ringbuf.o: In function
`test_ringbuf::clock_generator(void)':
This error arises when the same global symbol is present in more than one .o file. There are two
common causes of this problem:
Text in .h files is included into .cpp files by the C++ preprocessor. By the time the compiler sees
the text, it's just as if you had typed the entire text from the .h file into the .cpp file. So an .h file
included into two .cpp files results in lots of duplicate text being processed by the C++ compiler
when it starts up. Include guards are a common technique to avoid duplicate text problems.
If an .h file has an out-of-line function defined, and that .h file is included into two .c files, then
the out-of-line function symbol will be defined in the two corresponding .o files. This leads to a
multiple symbol definition error during sccom -link.
To solve this problem, add the "inline" keyword to give the function "internal linkage." This
makes the function internal to the .o file, and prevents the function's symbol from colliding with
a symbol in another .o file.
For free functions or variables, you could modify the function definition by adding the "static"
keyword instead of "inline", although "inline" is better for efficiency.
Sometimes compilers do not honor the "inline" keyword. In such cases, you should move your
function(s) from a header file into an out-of-line implementation in a .cpp file.
Questa SIM allows you to simulate designs that are written in VHDL, SystemC, Verilog, and
SystemVerilog. While design units must be entirely of one language type, any design unit may
instantiate other design units from another language. Any instance in the design hierarchy may
be a design unit from another language without restriction.
In addition, Questa SIM supports a procedural interface between SystemC and SystemVerilog,
so you may make calls between these languages at the procedural level.
For SystemC designs with HDL instances — Create a SystemC foreign module
declaration for all Verilog/SystemVerilog and VHDL instances. For more information
on this declaration, refer to SystemC Foreign Module (Verilog) Declaration or SystemC
Foreign Module (VHDL) Declaration.
For Verilog/SystemVerilog/VHDL designs with SystemC instances — Export any
SystemC instances that will be directly instantiated by the other language using the
SC_MODULE_EXPORT macro. Instantiate exported SystemC modules as you would
instantiate any Verilog/SystemVerilog/VHDL module or design unit.
For VHDL with Verilog instances — Do not use vlog -nodebug=ports during
compilation of the Verilog modules because VHDL will not have the necessary access
to the port information.
For binding Verilog design units to VHDL or Verilog design units — See “The
SystemVerilog bind Construct in Mixed-Language Designs.” When using bind in
compilation unit scope, use the -cuname argument with the vlog command (see Separate
Bind Statements in the Compilation Unit Scope).
For binding Verilog design units to VHDL or Verilog design units or SystemC modules
— See “The SystemVerilog bind Construct in Mixed-Language Designs.” When using
bind in compilation unit scope, use the -cuname argument with the vlog command (see
Separate Bind Statements in the Compilation Unit Scope).
3. For designs containing SystemC — Link all objects in the design using sccom -link.
4. Elaborate and optimize your design using the vopt command. See Optimizing Mixed
Designs.
5. Simulate the design with the vsim command.
6. Run and debug your design.
Case Sensitivity
Note that VHDL and Verilog observe different rules for case sensitivity.
• VHDL is not case-sensitive. For example, clk and CLK are regarded as the same name
for the same signal or variable.
• Verilog (and SystemVerilog) are case-sensitive. For example, clk and CLK are regarded
as different names that you could apply to different signals or variables.
Caution
VHDL is not case sensitive, so when you run vcom -mixedsvvh to compile the
VHDL package to use in Verilog or SystemVerilog, it silently converts all names in
the package to lower case (for example, InterfaceStage becomes interfacestage).
Because Verilog and SystemVerilog are case-sensitive, when you run the vlog compiler,
it looks for InterfaceStage in the compiled VHDL package but will not find it because it
does not match interfacestage (which is what vcom -mixedsvvh produced).
This means that you must write anything in a VHDL package that SystemVerilog uses in
lower case in the SystemVerilog source code, regardless of the upper/lower case used in
the VHDL source code.
Hierarchical References
Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you to
make hierarchical references from VHDL to VHDL. Currently, these references can cross
Verilog boundaries, but they must begin and end in VHDL.
Note
The target of an external name must be a VHDL object. The location of the VHDL external
name declaration must be in VHDL but the actual path can start anywhere. This only applies
to the absolute path name because the relative path name starts at the enclosing concurrent
scope where the external name occurs.
The external names syntax allows references to be made to signals, constants, or variables, as
follows:
external_pathname <=
absolute_pathname | relative_pathname | package_pathname
Notice that the standard requires the entire syntax be enclosed in double angle brackets, << >>.
It also requires that you specify the type of the object you are referencing.
To use this capability, use the vcom command to compile your VHDL source for the IEEE
1076-2008 syntax as follows:
Note
Indexing and slicing of the name appears outside of the external name and is not part of the
external path name itself. For example: << signal u1.vector : std_logic_vector>>(3) instead
of << signal u1.vector(3): std_logic>>
The order of elaboration for Verilog to Verilog references that cross VHDL boundaries does not
matter. However, the object referenced by a VHDL external name must be elaborated before it
can be referenced.
SystemVerilog binds in VHDL scopes are translated to “equivalent” VHDL so that any
restrictions on VHDL external names apply to the hierarchical references in the bind statement
(that is, the target must be a VHDL object.) Because binds are done after all other instances
within a scope, there should be no ordering issues.
• control_foreign_signal()
• observe_foreign_signal()
For more information on the use of control and observe, refer to “Hierarchical References In
Mixed HDL and SystemC Designs”.
This bind statement creates an instance of the assertion module inside the target VHDL entity/
architecture or SystemC module with the specified instance name and port connections. When
the target is a VHDL entity, the bind instance is created under the last compiled architecture.
Note that the instance being bound cannot contain another bind statement. In addition, a bound
instance can make hierarchical reference into the design.
Allowed Bindings
The following list provides examples of bindings you can make.
• Bind to all instances of a VHDL entity.
bind e bind_du inst(p1, p2);
• Bind to an instance where the instance path includes a for generate scope.
bind test.dut/forgen__4/inst1 bind_du inst(p1, p2);
Supported Objects
The only VHDL object types that can be referenced are: signals, shared variables, constants,
and generics not declared within processes. VHDL functions, procedures, and types are not
supported, and you cannot read VHDL process variables.
VHDL signals are treated as Verilog wires. You can use hierarchical references to VHDL
signals in instances and left-hand sides of continuous assignments, which can be read any place
a wire can be read and used in event control. Blocking assignments, non-blocking assignments,
force, and release are not supported for VHDL signals.
VHDL shared variables can be read anywhere a Verilog reg can be read. VHDL variables do
not have event control on them, therefore hierarchical references to VHDL shared variables
used in event control are an error by default. The statement @(vhdl_entity.shared_variable) will
never trigger. Because of this, you cannot use hierarchical references to VHDL shared variables
in instance port maps.
You can use non-blocking assignments and blocking assignments on VHDL shared variables.
VHDL constant and generics can be read anywhere. Questa SIM treats them similarly to
Verilog parameters. The one exception is that they should not be used where constant
expressions are required. In addition, VHDL generics cannot be changed by a defparam
statement.
Supported Types
The following VHDL data types are supported for hierarchical references:
Complex types like records are supported if there exists a matching type in the language
generated with the -mixedsvvh switch for either the vcom or vlog commands.
Mapping of Types
All SystemVerilog data types supported at the SystemVerilog-VHDL boundary are supported
while binding to VHDL target scopes. This includes hierarchical references in actual
expressions if they terminate in a VHDL scope. These data-types follow the same type-mapping
rules followed at the SystemVerilog-VHDL mixed-language boundary for direct instantiation.
All the types supported at the SystemC-SystemVerilog mixed language boundary are also
supported when binding to a SystemC target. Please refer to Verilog or SystemVerilog and
SystemC Signal Interaction And Mappings for a complete list of all supported types.
Related Topics
Mapping Data Types
Related Topics
Optimizing Designs with vopt
This kind of port mapping between VHDL enum and Verilog vector is only allowed when the
Verilog is instantiated under VHDL through the bind construct and is not supported for normal
instances.
Table 9-1 shows the allowed VHDL types for port mapping to SystemVerilog port vectors.
The following steps show how to follow the same type-sharing rules, which are applicable for
direct instantiations at the SystemVerilog-VHDL mixed-language boundary (refer to Sharing
User-Defined Types).
--/*----------pack.vhd---------------*/
package pack is
type fsm_state is(idle, send_bypass,
load0,send0, load1,send1, load2,send2,
load3,send3, load4,send4, load5,send5,
load6,send6, load7,send7, load8,send8,
load9,send9, load10,send10,
load_bypass, wait_idle);
end package;
The following procedure shows how to use this at the mixed-language boundary of
SystemVerilog and VHDL.
1. Compile this package using the -mixedsvvh argument for the vcom command:
vcom -mixedsvvh pack.vhd
2. Make the package available to the design in either of the following ways:
o Include this package in your VHDL target, like a normal VHDL package:
use work.pack.all;
...
signal int_state : fsm_state;
signal nxt_state : fsm_state;
...
3. Assume you want to implement functional coverage of the VHDL finite state machine
states. With Questa SIM, you can bind any SystemVerilog functionality, such as
functional coverage, into a VHDL object. To do this, define the following covergroup in
SystemVerilog:
...
covergroup sm_cvg @(posedge clk);
coverpoint int_state
{
bins idle_bin = {idle};
bins load_bins = {load_bypass, load0, load9, load10};
bins send_bins = {send_bypass, send0, send9, send10};
bins others = {wait_idle};
option.at_least = 500;
}
coverpoint in_hs;
in_hsXint_state: cross in_hs, int_state;
endgroup
sm_cvg sm_cvg_c1 = new;
...
4. As with monitoring VHDL components, you create a wrapper containing the bind
statement to connect the SystemVerilog Assertions to the VHDL component:
module interleaver_binds;
...
// Bind interleaver_props to a specific interleaver instance
// and call this instantiate interleaver_props_bind
bind interleaver_m0 interleaver_props interleaver_props_bind (
// connect the SystemVerilog ports to VHDL ports (clk)
// and to the internal signal (int_state)
.clk(clk), ..
.int_state(int_state)
);
...
endmodule
5. Use either of the following to perform the actual binding in Questa SIM:
o instantiation
o loading of multiple top modules into the simulator with the vsim command:
vsim interleaver_tester interleaver_binds
Related Topics
Sharing User-Defined Types
Example 9-2. Using the Bind Statement with VHDL Component and
SystemVerilog Assertion
Consider the following VHDL code that uses nested generate statements:
The following SystemVerilog program (SVA) uses a cover directive to define the assertion:
To tie the SystemVerilog cover directive to the VHDL component, you can use a wrapper
module such as the following:
module sva_wrapper;
bind test.top__2.second__1.q // Bind a specific instance
SVA // to SVA and call this
sva_bind // instantiation sva_bind
( .a(A), .b(B), .c(C) ); // Connect the SystemVerilog ports to
// VHDL ports (A, B and C)
endmodule
You can instantiate sva_wrapper in the top level or simply load multiple top modules into the
simulator:
vlib work
vlog *.sv
vcom *.vhd
vsim test sva_wrapper
This binds the SystemVerilog program, named SVA, to the specific instance defined by the
generate and configuration statements.
Tip
: You can control the format of generate statement labels by using the GenerateFormat
variable in the modelsim.ini file.
Note that when the bind statement is in the compilation unit scope, the bind becomes effective
only when $unit package gets elaborated by vsim. In addition, the package gets elaborated only
when a design unit that depends on that package gets elaborated. As a result, if you have a file in
a compilation unit scope that contains only bind statements, you can compile that file by itself,
but the bind statements will never be elaborated. A warning to this effect is generated by the
vlog command if bind statements are found in the compilation unit scope.
The -cuname argument for vlog gives a user-defined name to a specified compilation $unit
package (which, in the absence of -cuname, is some internally generated name). You must
provide this named compilation unit package as the top-level design unit with the vsim
command in order to force elaboration.
Tip
: If you are using the vlog -R or qverilog commands to compile and simulate the design,
Questa SIM handles this binding issue automatically.
The vlog -cuname argument is used only in conjunction with the vlog -mfcu argument, which
instructs the compiler to treat all files within a compilation command line as a single
compilation unit.
Example 9-3 shows how to use vlog -cuname and -mfcu arguments to elaborate a bind
statement contained in its own file.
Example 9-3. Using vlog -cuname and -mfcu Arguments to Ensure Proper
Elaboration
Consider the following SystemVerilog module, called checker.sv, that contains an assertion for
checking a counter:
Next, bind that assertion module to the following counter module named counter.sv.
using the bind statement contained separately in a file named bind.sv, which will reside in the
compilation unit scope.
This statement instructs Questa SIM to create an instance of checker in the target module,
counter.sv.
module testbench;
reg clk, reset;
wire [15:0] cnt;
counter #(16) inst(clk, reset, cnt);
initial
begin
clk = 1'b0;
reset = 1'b1;
#500 reset = 1'b0;
#1000 $finish;
end
always #50 clk = ~clk;
endmodule
If the bind.sv file is compiled by itself (vlog bind.sv), you will receive a Warning like this one:
** Warning: 'bind' found in a compilation unit scope that either does not
contain any design units or only contains design units that are
instantiated by 'bind'. The 'bind' instance will not be elaborated.
To fix this problem, use the -cuname argument with the vlog command, as follows:
If the root is SystemC, then SystemC rules are used (see SystemC Time Unit and Simulator
Resolution for details).
In the case of a mixed-language design with multiple tops, the following algorithm is used:
• If VHDL or SystemC modules are present, then the Verilog resolution is ignored. An
error is issued if the Verilog resolution is finer than the chosen one.
• If VHDL modules are present, then the Verilog resolution is ignored. An error is issued
if the Verilog resolution is finer than the chosen one.
• If both VHDL and SystemC are present, then the resolution is chosen based on which
design unit is elaborated first. For example:
vsim sc_top vhdl_top -do vsim.do
The above scheduling semantics are required to satisfy the HDL LRM. All processes triggered
by an event on an HDL signal shall wake up at the end of the current delta.
For a signal chain that crosses the language boundary, this means that processes on the SystemC
side get woken up one delta later than processes on the HDL side. Consequently, one delta of
skew will be introduced between such processes. However, if the processes are communicating
with each other, correct system behavior will still result.
The argument (const char* name) is a full hierarchical path to an HDL signal or port. These
functions always return “true” for all cases (even if the call failed). However, an error is issued
if the call could not be completed due to any reason. See tables for Verilog/SystemVerilog
(Data Type Mapping from SystemC to Verilog or SystemVerilog) and VHDL (Data Type
Mapping Between SystemC and VHDL) to view a list of types supported at the mixed language
boundary. If it is a supported boundary type, it is supported for hierarchical references.
Note
SystemC control/observe always return “true” for all cases (even if the call failed).
Control
When a SystemC signal calls control_foreign_signal() on an HDL signal, the HDL signal is
considered a fanout of the SystemC signal. This means that every value change of the SystemC
signal is propagated to the HDL signal. If there is a pre-existing driver on the HDL signal which
has been controlled, the value of the HDL signal is the resolved value of the existing driver and
the SystemC signal. This value remains in effect until a subsequent driver transaction occurs on
the HDL signal, following the semantics of the force -deposit command.
Observe
When a SystemC signal calls observe_foreign_signal() on an HDL signal, the SystemC signal
is considered a fanout of the HDL signal. This means that every value change of the HDL signal
is propagated to the SystemC signal. If there is a pre-existing driver on the SystemC signal
which has been observed, the value is changed to reflect that of the HDL signal. This value
remains in effect until a subsequent driver transaction occurs on the SystemC signal, following
the semantics of the force -deposit command.
Example
SC_MODULE(test_ringbuf)
{
sc_signal<bool> observe_sig;
sc_signal<sc_lv<4> > control_sig;
SC_CTOR(test_ringbuf)
{
ring_INST = new ringbuf("ring_INST", "ringbuf");
.....
observe_sig.observe_foreign_signal("/test_ringbuf/ring_INST/block1_INST/
buffers(0)");
control_sig.control_foreign_signal("/test_ringbuf/ring_INST/block1_INST/
sig");
}
};
The scv_connect() API is provided by the SystemC Verification Standard and is defined as
follows:
where
Supported Types
The scv_connect() function supports all datatypes supported at the SystemC-HDL
mixed-language boundaries. Refer to the tables for Verilog/SystemVerilog (Data Type Mapping
from SystemC to Verilog or SystemVerilog) and VHDL (Data Type Mapping Between
SystemC and VHDL) to view a list of types supported at the mixed language boundary. If it is a
supported boundary type, it is supported for hierarchical references.
A VHDL instantiation of Verilog may associate VHDL signals and values with Verilog ports
and parameters. Likewise, a Verilog instantiation of VHDL may associate Verilog nets and
values with VHDL ports and generics.
The following sections describe data type mappings for mixed-language designs in Questa SIM:
Verilog Parameters
The type of a Verilog parameter is determined by its initial value.
For more information on using Verilog bit type mapping to VHDL, refer to the Usage Notes
under “VHDL Instantiation Criteria Within Verilog.”
Note
Note that you can use the wildcard syntax convention (.*) when instantiating Verilog ports
where the instance port name matches the connecting port name and their data types are
equivalent.
The vl_logic type is an enumeration that defines the full state set for Verilog nets, including
ambiguous strengths. The bit and std_logic types are convenient for most applications, but the
vl_logic type is provided in case you need access to the full Verilog state set. For example, you
may wish to convert between vl_logic and your own user-defined type. The vl_logic type is
defined in the vl_types package in the pre-compiled verilog library. This library is provided in
the installation directory along with the other pre-compiled libraries (std and ieee). The vl_logic
type is defined in the following file installed with Questa SIM:
<install_dir>/vhdl_src/verilog/vltypes.vhd
Verilog States
Verilog states are mapped to std_logic and bit as follows:
When a scalar type receives a real value, the real is converted to an integer by truncating the
decimal portion.
Type time is treated specially: the Verilog number is converted to a time value according to the
‘timescale directive of the module.
Physical and enumeration types receive a value that corresponds to the position number
indicated by the Verilog number. In VHDL this is equivalent to T'VAL(P), where T is the type,
VAL is the predefined function attribute that returns a value given a position number, and P is
the position number.
• Verilog-Style Declarations
• SystemVerilog-Style Declarations
• Miscellaneous Declarations
Verilog-Style Declarations
This category is for all parameters that are defined using a Verilog-style declaration. This style
of declaration does not have a type or range specification, so the type of these parameters is
inferred from the final value that gets assigned to them.
For example:
// SystemVerilog
parameter p1 = 10;
-- VHDL
inst1 : entity work.svmod generic map (p1 => integer'(20));
inst2 : entity work.svmod generic map (p1 => real'(2.5));
inst3 : entity work.svmod generic map (p1 => string'("Hello World"));
inst3 : entity work.svmod generic map (p1 => bit_vector'("01010101"));
Component Instantiation
For Verilog-style declarations, Questa SIM allows you to override the default type of the
generic in your component declarations.
For example:
// SystemVerilog
parameter p1 = 10;
-- VHDL
component svmod
generic (p1 : std_logic_vector(7 downto 0));
end component;
...
inst1 : svmod generic map (p1 => "01010101");
SystemVerilog-Style Declarations
This category is for all parameters that are defined using a SystemVerilog-style declaration.
This style of declaration has an explicit type defined, which does not change based on the value
that gets assigned to them.
For example:
// SystemVerilog
parameter int p1 = 10;
-- VHDL
inst1 : entity work.svmod generic map (p1 => integer'(20)); -- OK
-- inst2 : entity work.svmod generic map (p1 => real'(3.5)); -- ERROR
-- inst3 : entity work.svmod generic map (p1 => string'("Hello World"));
-- ERROR
inst4 : entity work.svmod generic map (p1 => bit_vector'("010101010101"));
-- OK
Component Instantiation
Questa SIM allows only the VHDL equivalent type of the type of the SystemVerilog parameter
in the component declaration. Using any other type will result in a type-mismatch error.
For example:
// SystemVerilog
parameter int p1 = 10;
-- VHDL
component svmod
generic (p1 : bit_vector(7 downto 0));
end component;
...
inst1 : svmod generic map (p1 => "01010101");
In addition to the mapping in Table 9-10, Questa SIM handles sign specification while
overriding SystemVerilog parameters from VHDL in accordance with the following rules:
• A Verilog parameter with a range specification, but with no type specification, shall
have the range of the parameter declaration and shall be unsigned. The sign and range
shall not be affected by value overrides from VHDL.
• A Verilog parameter with a signed type specification and with a range specification shall
be signed and shall have the range of its declaration. The sign and range shall not be
affected by value overrides from VHDL.
Miscellaneous Declarations
The following types of parameter declarations require special handling, as described below.
For example:
parameter p1;
Because no default value is specified, you must specify an overriding parameter value in every
instantiation of the parent SystemVerilog module inside VHDL. Questa SIM will consider it an
error if these parameters are omitted during instantiation.
For example:
// SystemVerilog
parameter p1;
-- VHDL
inst1 : entity work.svmod generic map (p1 => integer'(20)); -- OK
inst2 : entity work.svmod generic map (p1 => real'(3.5)); -- OK
inst3 : entity work.svmod generic map (p1 => string'("Hello World"));
-- OK
Component Instantiation
It is your responsibility to define a type of generics corresponding to untyped SystemVerilog
parameters in their component declarations. Questa SIM will issue an error if an untyped
SystemVerilog parameter is omitted in the component declaration.
The vgencomp command will dump a comment instead of the type of the generic,
corresponding to an untyped parameter, and prompt you to put in your own type there.
For example:
// SystemVerilog
parameter p1;
-- VHDL
component svmod
generic (p1 : bit_vector(7 downto 0) := "00000000" );
end component;
...
inst1 : svmod generic map (p1 => "01010101");
For example:
module mb;
logic [3:0] i,o;
ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int
endmodule
You can leave this type of parameter OPEN in entity instantiation, or omit it in component
instantiation. However, if you want to override such a parameter, you can do so by applying
your own data type and value (component declaration), or by using an unambiguous actual
value (direct entity instantiation). If a parameter with no default value or compile-time
non-constant default value is defined using SystemVerilog-style declarations, the corresponding
generic on the VHDL side will have a data type, but no default value. You can also leave such
generics OPEN in entity instantiations, or omit them in component instantiations. But if you
want to override them from VHDL, you can do so in a way similar to the Verilog-Style
Declarations described above—except that the data type of the overriding VHDL actual must be
allowed for mapping with the Verilog formal (refer to Table 9-10 for a list of allowed
mappings).
1. User-defined SystemC channels and ports derived from built-in SystemC primitive channels
and ports can be connected to HDL signals. The built-in SystemC primitive channel or port
must be already supported at the mixed-language boundary for the derived class connection to
work.
A SystemC sc_out port connected to an HDL signal higher up in the design hierarchy is treated
as a pure output port. A read() operation on such an sc_out port might give incorrect values. Use
an sc_inout port to do both read() and write() operations.
Table 9-12 shows the correspondence of SystemC data types to SystemVerilog data types.
6. The number of elements in the SystemC signal array and the SV unpacked array must match; and the
type of SystemC signal array must be compatible with the type of the element of the SV unpacked array.
1. Refer to enum, struct, and union at SystemC-SystemVerilog Mixed-Language Boundary for more
information on these complex types.
2. Unpacked and tagged unions are not supported at the SystemC-SystemVerilog mixed language
boundary.
3. Classes, multi-dimensional arrays, unpacked/tagged unions, strings and handles are not supported
for SystemC control/observe.
• The number of elements in the SystemC signal array and the Verilog/SystemVerilog
array is the same.
• Mapping between the type of SystemC signal array and the type of the element of the
Verilog/SystemVerilog array is permitted at the SystemC-Verilog/SystemVerilog
boundary.
Note
SystemC signal arrays are supported only for cases where Verilog/SystemVerilog
instantiates a SystemC module—not vice versa.
Enumerations
A SystemVerilog enum may be used at the SystemC-SystemVerilog language boundary if it
meets the following criteria:
• Base type of the SystemVerilog enum must be int (32-bit 2-state integer).
• The value of enum elements are not ambiguous and are equal to the value of the
corresponding value of enum elements on the SystemC side. Enums with different
strings are allowed at the language boundary as long as the values on both sides are
identical.
• SystemVerilog enums with 'range of enumeration elements' are allowed provided the
corresponding enum is correctly defined (manually) on the SystemC side.
• The type of all elements of the union/structure is one of the supported types.
• The type of the corresponding elements of the SystemC union/structure follow the
supported type mapping for variable ports on the SystemC-SystemVerilog language
boundary. See Channel and Port Type Mapping for mapping information.
• The number and order of elements in the definition of structures on SystemVerilog and
SystemC side is the same. For unions, the order of elements may be different, but the
number of elements must be the same.
• Union must be packed and untagged. While both packed and unpacked structures are
supported, only packed unions are supported at the SystemC-SystemVerilog language
boundary.
Port Direction
Verilog port directions are mapped to SystemC as shown in Table 9-14. Note that you can use
the wildcard syntax convention (.*) when instantiating Verilog ports where the instance port
name matches the connecting port name and their data types are equivalent.
A SystemC sc_out port connected to an HDL signal higher up in the design hierarchy is treated
as a pure output port. A read() operation on such an sc_out port might give incorrect values. Use
an sc_inout port to do both read() and write() operations.
Table 9-20. Mapping Between SystemC sc_signal and VHDL Types (cont.)
SystemC VHDL
sc_bv<W> bit_vector(W-1 downto 0)
sc_lv<W> std_logic_vector(W-1 downto 0)
sc_bv<32>, integer
sc_lv<32>
sc_bv<64>, real
sc_lv<64>
sc_int<W>, bit_vector(W-1 downto 0)
sc_uint<W> std_logic_vector(W -1 downto 0)
sc_bigint<W>, sc_biguint<W> bit_vector(W-1 downto 0)
std_logic_vector(W-1 downto 0)
sc_fixed<W,I,Q,O,N>, bit_vector(W-1 downto 0)
sc_ufixed<W,I,Q,O,N> std_logic_vector(W-1 downto 0)
sc_fixed_fast<W,I,Q,O,N>, bit_vector(W-1 downto 0)
sc_ufixed_fast<W,I,Q,O,N> std_logic_vector(W-1 downto 0)
1sc_fix, bit_vector(WL-1 downto 0)
1sc_ufix std_logic_vector(WL- 1 downto 0)
1sc_fix_fast, bit_vector(WL-1 downto 0)
1sc_ufix_fast std_logic_vector(WL- 1 downto 0)
2sc_signed, bit_vector(WL-1 downto 0)
2sc_unsigned std_logic_vector(WL- 1 downto 0)
char, unsigned char bit_vector(7 downto 0)
std_logic_vector(7 downto 0)
short, unsigned short bit_vector(15 downto 0)
std_logic_vector(15 downto 0)
int, unsigned int bit_vector(31 downto 0)
std_logic_vector(7 downto 0)
long, unsigned long bit_vector(31 downto 0)
std_logic_vector(31 downto 0)
long long, unsigned long long bit_vector(63 downto 0)
std_logic_vector(63 downto 0)
Table 9-20. Mapping Between SystemC sc_signal and VHDL Types (cont.)
SystemC VHDL
float bit_vector(31 downto 0)
std_logic_vector(31 downto 0)
double bit_vector(63 downto 0)
std_logic_vector(63 downto 0)
real
struct record
enum enum
record3 record
element_declaration
{element_declaration}
end record
[ record_type_simple_name ]
signal array4 type signal_name
array (constraint_definition) of
signal_type
Not supported on language boundary Multi-dimensional array
(no equivalent SystemC type)
pointer Not supported on language boundary
(no equivalent VHDL type)
class Not supported on language boundary
(no equivalent VHDL type)
union Not supported on language boundary
(no equivalent VHDL type)
bit_fields Not supported on language boundary
(no equivalent VHDL type)
Not supported on language boundary access
(no equivalent SystemC type)
Not supported on language boundary protected
(no equivalent SystemC type)
1. WL (word length) is the total number of bits used in the type. It is specified during
runtime. To make a port of type sc_fix, sc_ufix, sc_fix_fast, or sc_ufix_fast of word
length other than the default(32), you must use sc_fxtype_params and sc_fxtype_context
to set the word length. For more information, see Construction Parameters for SystemC
Types in 2.2.
2. To make a port of type sc_signed or sc_unsigned of word length other than the default
(32), you must use sc_length_param and sc_length_context to set the word length. For
more information, see Construction Parameters for SystemC Types in 2.2.
3. Including nested records.
4. SystemC signal arrays are supported only for cases where VHDL instantiates a
SystemC module—not vice versa.
Type Checking—Records
Two records at the SystemC-VHDL mixed-language boundary will be equivalent if all of the
following conditions hold true:
• The number and order of elements in the definition of records on VHDL and SystemC
side is the same.
• Size of each field of one record is exactly same as the size of the corresponding field in
the second record.
• Type of each field of both the records is supported at the SystemC-VHDL boundary.
• Mapping between corresponding field types is permitted at the SystemC-VHDL
boundary.
Type Checking—Enums
Two enumerated types at the SystemC-VHDL mixed-language boundary will be equivalent if
all of the following conditions hold true for them:
• The number of elements in the SystemC signal array and the VHDL array is the same.
• Mapping between the type of SystemC signal array and the type of the element of the
VHDL array is permitted at the SystemC-VHDL boundary.
Note
SystemC signal arrays are supported only for cases where VHDL instantiates a
SystemC module—not vice versa.
Note
VHDL constants are supported for port connections at a VHDL-SystemC boundary.
SystemC type sc_logic is mapped to VHDL std_logic states as shown in Table 9-25:
• std_logic
• std_logic_vector
Optionally, you can choose one of the following:
Questa SIM converts Verilog identifiers to VHDL 1076-1993 extended identifiers in three
cases:
The default value of the generic is the same as the parameter's initial value. For example:
• Port Clause
The vgencomp command generates a port clause if the module has ports. A
corresponding VHDL port is defined for each named Verilog port.
You can set the VHDL port type to bit, std_logic, or vl_logic. If the Verilog port has a
range, then the VHDL port type is bit_vector, std_logic_vector, or vl_logic_vector. If
the range does not depend on parameters, then the vector type will be constrained
accordingly, otherwise it will be unconstrained. For example:
Configuration declarations are allowed to reference Verilog modules in the entity aspects of
component configurations. However, the configuration declaration cannot extend into a Verilog
instance to configure the instantiations within the Verilog module.
In all other cases, the following warning is issued at elaboration and the simulation of the
Verilog port may produce incorrect results if the design actually drives in both directions across
the port:
** Warning: (vsim-3011) testfile(4): [TRAN] - Verilog net 'n' with bidirectional tran primitives
might not function correctly when connected to a VHDL signal.
If you use the port solely in a unidirectional manner, then you should explicitly declare it as
either input or output (whichever matches the direction of the signal flow).
Note that a[3:0] is considered to be unnamed even though it is a full part-select. A common
mistake is to include the vector bounds in the port list, which has the undesired side effect of
making the ports unnamed (which prevents you from connecting by name even in an all-Verilog
design).
Most modules having unnamed ports can be easily rewritten to explicitly name the ports, thus
allowing the module to be instantiated from VHDL. Consider the following example:
Here is the same module rewritten with explicit port names added:
Empty Ports
Verilog modules may have “empty” ports, which are also unnamed, but they are treated
differently from other unnamed ports. If the only unnamed ports are empty, then the other ports
may still be connected to by name, as in the following example:
Although this module has an empty port between ports a and b, the named ports in the module
can still be connected to or from VHDL.
Usage Notes
Passing a parameter values from Verilog or SystemVerilog to a VHDL generic of type std_logic
is slightly different than other VHDL types. Note that std_logic is defined as a 9-state
enumerated type, as follows:
TYPE std_ulogic IS (
‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘0’, -- Forcing 0
‘1’, -- Forcing 1
‘Z’, -- High Impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- Don’t care
);
To be able to correctly set the VHDL generic to any of the nine states, you must set the value in
the Verilog instance to the element (positional) value in the std_logic enum that corresponds to
the std_logic value (that is, the position not the value itself). For example, to set the generic to a
‘U’, use 1’b0, to set it to an “X”, use 1’b1, to set it to ‘0’, use 2’b10.
Note that this only applies to std_logic types—for std_logic_vector you can simply pass the
value as you would normally expect.
For example, the following VHDL entity shows the generics of type std_logic:
entity ent is
generic (
a : std_logic;
b : std_logic ;
c : std_logic
) ;
module test ;
// here we will pass 0 to a, 1 to b and z to c
ent #(2’b10, 2’b11, 3’b100) u_ent ())
endmodule
Note that this does not pass the value but the positional number corresponding to the element
value in the std_logic enum.
Alternatively, you can use std_logic_vector for the generics, and you can simply pass the value
as normal.
\mylib.entity(arch) u1 (a, b, c) ;
\mylib.entity u1 (a, b, c) ;
\entity(arch) u1 (a, b, c) ;
If the escaped identifier takes the form of one of the above and is not the name of a design unit
in the work library, then the instantiation is broken down as follows:
• library = mylib
Generic Associations
Generic associations are provided via the module instance parameter value list. List the values
in the same order that the generics appear in the entity. Parameter assignment to generics is not
case sensitive.
The defparam statement is not allowed for setting generic values.
SDF Annotation
A mixed VHDL/Verilog design can also be annotated with SDF.
Related Topics
SDF for Mixed VHDL and Verilog Designs
import vh_pack::vh_type
Because VHDL is case-insensitive, design units, variables and constants will be converted to
lower-case.
If you use mixed-case identifiers with its original case in your SystemVerilog code, design
compilation will fail because SystemVerilog is case sensitive. For example, if your VHDL
package contains an identifier named myPacketData the compiler will convert it to
mypacketdata. Therefore, if you use myPacketData in your SystemVerilog code, compilation
would fail due to a case mismatch. Because of this, it is suggested that everything in the shared
package should be lower-case to avoid these mismatch issues.
In order to import a VHDL package into SystemVerilog, you must compile it using the
-mixedsvvh argument with the vcom command (refer to Usage Notes, below).
Note
The following types must be defined in a common package if you want to use them at the
SystemVerilog-VHDL boundary:
• Records
• Enumerations
• One-dimensional array of bit, std_logic, std_ulogic, integer, natural, positive, real &
time
• Multi-dimensional arrays and array of arrays of all supported types
• Subtypes of all supported types
• Alias of records, enums and arrays only
• Types (static ranges only)
Questa SIM supports VHDL constants of all types currently supported at the VHDL-
SystemVerilog mixed language boundary as shown in Table 9-5.
Deferred constants are not supported. Only static expressions are supported as constant values.
Usage Notes
When using a common VHDL package at a SystemVerilog-VHDL boundary, compile the
VHDL package with the -mixedsvvh argument with the vcom command, as follows:
Example
Consider the following VHDL package that you want to use at a SystemVerilog-VHDL
boundary:
--/*----------pack.vhd---------------*/
package pack is
type st_pack is record
a: bit_vector (3 downto 0);
b: bit;
c: integer;
end record;
constant c : st_pack := (a=>"0110", b=>'0', c=>4);
end package;
You must compile this package with the -mixedsvvh argument for vcom:
Import this package into the SystemVerilog design, as if it were a SystemVerilog package.
--/*------VHDL_entity--------*/
use work.pack.all;
entity top is
end entity;
architecture arch of top is
component bot
port(in1 : in st_pack;
in2 : bit_vector(1 to c.c);
out1 : out st_pack);
end component;
begin
end arch;
/*------SV_file--------*/
import pack::*; // including the VHDL package in SV
module bot(input st_pack in1, input bit [1:c.c] in2, output st_pack out1);
endmodule
use work.sv_pack.sv_type
In order to include a SystemVerilog package in VHDL, you must compile it using the
-mixedsvvh argument of the vlog command (refer to Usage Notes, below).
Note
You must use the vcom -mixedsvvh option when compiling the common package, and the
following types must be defined in a common package if you want to use them at the
SystemVerilog-VHDL boundary:
• Strucures
• Enumerations with base type as 32-bit 2-state integer
• Multi-dimensional arrays of all supported types
Usage Notes
When using a common SystemVerilog package at a SystemVerilog-VHDL boundary, you
should compile the SystemVerilog package with the -mixedsvvh argument of the vlog
command, as follows:
When you compile a SystemVerilog package with -mixedsvvh, the package can be included in
a VHDL design as if it were defined in VHDL itself.
Note
If you do not specify b, s, or v with -mixedsvvh, the default treatment of data types is
applied.
Example
The following SystemVerilog package contains a type named st_pack, which you want to use at
the SystemVerilog-VHDL mixed-language boundary.
/*----------pack.sv---------------*/
package pack;
typedef struct {
bit [3:0] a;
bit b;
} st_pack;
endpackage
To use this package (and type) at a SystemVerilog-VHDL boundary, you must compile it using
vlog -mixedsvvh:
You can now include this package (st_pack) in the VHDL design, as if it were a VHDL
package:
--/*------VHDL_file--------*/
use work.pack.all; -- including the SV package in VHDL
entity top is
end entity;
/*------SV Module--------*/
import pack::*;
• Run scgenmod, a utility that automatically generates your foreign module declaration
(much like vgencomp generates a component declaration).
• Modify your SystemC source code manually.
After you have analyzed the design, you can generate a foreign module declaration by using
scgenmod as follows:
scgenmod mod1
where mod1 can be any name of a Verilog module. A foreign module declaration for the
specified module is written to stdout.
• Contains ports corresponding to Verilog ports. These ports must be explicitly named in
the constructor initializer list of the foreign module.
• Must not contain any internal design elements such as child instances, primitive
channels, or processes.
• Must pass a secondary constructor argument denoting the module’s HDL name to the
sc_foreign_module base class constructor. For Verilog, the HDL name is simply the
Verilog module name corresponding to the foreign module, or [<lib>].<module>.
• Allows inclusion of parameterized modules. Refer to Parameter Support for SystemC
Instantiating Verilog for details.
Example 9-4. SystemC Instantiating Verilog - 1
The SystemC foreign module declaration for the above Verilog module is:
counter dut("dut");
where the constructor argument (dut) is the instance name of the Verilog module.
Another variation of the SystemC foreign module declaration for the same Verilog module
might be:
Refer to SystemC Foreign Module (Verilog) Declaration for information regarding the creation
of sc_foreign_module.
If you create your foreign module manually (see Guidelines for Manual Creation of Foreign
Module Declaration), you must also pass the parameter information to the sc_foreign_module
constructor. If you use scgenmod to create the foreign module declaration, the parameter
information is detected in the HDL child and is incorporated automatically.
Following Example 9-4, the following parameter information would be passed to the SystemC
foreign module declaration:
Verilog module:
parameter integer_param = 4;
parameter real_param = 2.9;
parameter str_param = "ERROR";
...
endmodule
SC_MODULE(top) {
SC_CTOR(top)
{
const char* generic_list[3];
generic_list[0] = strdup("integer_param=16");
generic_list[1] = strdup("real_param=2.6");
generic_list[2] = strdup("str_param=\"Hello\"");
Verilog module:
parameter counter_size = 4;
...
endmodule
SC_MODULE(top) {
counter<20> counter_inst_1;
// Instantiates counter with counter_size = 20
counter counter_inst_2;
// Instantiates counter with default counter_size = 4
SC_CTOR(top)
: counter_inst_1(cinst_1, "work.counter"),
counter_inst_2(cinst_2, "work.counter")
{}
};
Verilog module:
parameter counter_size = 4;
parameter real_param = 2.9;
parameter str_param = "ERROR";
...
endmodule
SC_MODULE(top) {
SC_CTOR(top)
{
const char* generic_list[2];
generic_list[0] = strdup("real_param=2.6");
generic_list[1] = strdup("str_param=\"Hello\"");
//
// The integer parameter override is already passed as template
// argument. Pass the overrides for the non-integer parameters
// using the foreign module constructor arguments.
//
counter_inst_1 = new counter<20>("c_inst", "work.counter", 2, \
generic_list);
#include "transceiver.h"
SC_MODULE_EXPORT(transceiver);
Questa SIM supports passing parameters with a bit range, and types: int, real, and string.
Named parameter association must be used for all Verilog/SystemVerilog modules that
instantiate SystemC.
The first argument to sc_get_param defines the parameter name, the second defines the
parameter value. For retrieving string values, Questa SIM also provides a third optional
argument, format_char. It is used to specify the format for displaying the retrieved string. The
format can be ASCII (“a” or “A”), binary (“b” or “B”), decimal (“d” or “D”), octal (“o” or “O”),
or hexadecimal (“h” or “H”). Binary is the default. These functions return a 1 if successful,
otherwise they return a 0.
Alternatively, you can use the following forms of the above functions in the constructor
initializer list:
The following ring buffer example includes all the files necessary for simulation.
// test_ringbuf.v
-------------------------------------------------------------------------
// ringbuf.h
#ifndef INCLUDED_RINGBUF
#define INCLUDED_RINGBUF
#include <systemc.h>
#include "control.h"
...
SC_MODULE(ringbuf)
{
public:
// Module ports
sc_in clock;
...
...
SC_CTOR(ringbuf)
: clock("clock"),
...
...
{
int int_param = 0
if (sc_get_param(“int_param”, int_param))
cout << “int_param” << int_param << end1;
std::string str_param;
str_param = sc_get_string_param(“str_param”, ‘a’, &is_successful);
if (is_successful)
cout << “str_param=” << str_param.c_str() << end1;
str::string reg_param;
if (sc_get_param(“reg_param”, ‘b’))
cout << “reg_param=” << reg_param.c_str() << end1;
~ringbuf() {}
};
#endif
------------------------------------------------------------------------
// ringbuf.cpp
#include "ringbuf.h"
SC_MODULE_EXPORT(ringbuf);
vlib work
sccom ringbuf.cpp
vlog test_ringbuf.v
sccom -link
vsim test_ringbuf
# int_param=4
# real_param=2.6
# str_param=Hello World
# reg_param=001100xz
scgenmod mod1
where mod1 is any name of a VHDL entity. A foreign module declaration for the specified
entity is written to stdout.
• Names of fields of the SystemC structure/enum must be same as those on the VHDL
side.
• The data types of fields in the SystemC structure must follow the same type conversion
(mapping) rules as normal ports.
• Additional dummy functions (operator<<, sc_trace, operator== functions) must be
generated along with the structure definition.
• Contains ports corresponding to VHDL ports. These ports must be explicitly named in
the constructor initializer list of the foreign module.
• Must not contain any internal design elements such as child instances, primitive
channels, or processes.
• Must pass a secondary constructor argument denoting the module’s HDL name to the
sc_foreign_module base class constructor. For VHDL, the HDL name can be in the
format [<lib>.]<primary>[(<secondary>)] or [<lib>.]<conf>.
• Can contain generics, which are supported for VHDL instantiations in SystemC designs.
See Generic Support for SystemC Instantiating VHDL for more information.
Example 9-11. SystemC Design Instantiating a VHDL Design Unit
entity counter is
port (count : buffer bit_vector(8 downto 1);
clk : in bit;
reset : in bit);
end;
end only;
The SystemC foreign module declaration for the above VHDL module is:
counter(sc_module_name nm)
: sc_foreign_module(nm, "work.counter(only)"),
clk("clk"),
reset("reset"),
count("count")
{}
};
counter dut("dut");
If you create your foreign module manually (see Guidelines for Manual Creation in VHDL),
you must also pass the generic information to the sc_foreign_module constructor. If you use
scgenmod to create the foreign module declaration, the generic information is detected in the
HDL child and is incorporated automatically.
Following Example 9-11, the generic information passed to the SystemC foreign module
declaration is shown below. The generic parameters passed to the constructor are shown in
magenta color:
VHDL entity:
entity counter is
generic(
integer_gen : integer := 4,
real_gen : real := 0.0,
str_gen : string);
port(
clk : in std_logic;
count : out std_logic_vector(7 downto 0));
end counter;
SC_MODULE(top) {
SC_CTOR(top)
{
const char* generic_list[3];
generic_list[0] = strdup("integer_param=16");
generic_list[1] = strdup("real_param=2.6");
generic_list[2] = strdup("str_param=\"Hello\"");
VHDL entity:
entity counter is
generic(counter_size : integer := 4);
port(
clk : in std_logic;
count : out std_logic_vector(counter_size - 1 downto 0));
end counter;
counter<20> counter_inst_1;
// Instantiates counter with counter_size = 20
counter counter_inst_2;
// Instantiates counter with default counter_size = 4
SC_CTOR(top)
: counter_inst_1(cinst_1, "work.counter"),
counter_inst_2(cinst_2, "work.counter")
{}
};
VHDL entity:
entity counter is
generic(counter_size : integer := 4);
port(
clk : in std_logic;
count : out std_logic_vector(counter_size - 1 downto 0));
end counter;
};
SC_MODULE(top) {
SC_CTOR(top)
{
const char* generic_list[2];
generic_list[0] = strdup("real_param=2.6");
generic_list[1] = strdup("str_param=\"Hello\"");
//
// The integer parameter override is already passed as template
// argument. Pass the overrides for the non-integer parameters
// using the foreign module constructor arguments.
//
counter_inst_1 = new counter<20>("c_inst", "work.counter", 2, \
generic_list);
• std_logic
• std_logic_vector
Questa SIM converts the SystemC identifiers to VHDL 1076-1993 extended identifiers in three
cases:
#include "transceiver.h"
SC_MODULE_EXPORT(transceiver);
The sccom -link command collects the object files created in the work library, and uses them to
build a shared library (.so) in the current work library. If you have changed your SystemC
source code and recompiled it using sccom, then you must run sccom -link before invoking
vsim. Otherwise your changes to the code are not recognized by the simulator.
Procedure
1. Add registration macros to the declarative region of the SystemC module. The macros
are:
• SC_GENERIC_INT(<generic_name>, <default_value>);
<default_value> must be an integer literal
• SC_GENERIC_REAL(<generic_name>, <default_value>);
<default_value> must be a real literal
• SC_GENERIC_STRING(<generic_name>, <default_value>);
<default_value> must be a string literal enclosed in double quotes (“).
For all macros, <default_value> must be a constant literal value. You cannot use
variables, constants, signals or other generics.
You can use these macros multiple times to register multiple generics.
2. Add initializer macros to the initializer list of your SystemC module’s constructor
section. The macros are:
• SC_INIT_GENERIC_INT(<generic_name>)
• SC_INIT_GENERIC_REAL(<generic_name>)
• SC_INIT_GENERIC_STRING(<generic_name>)
These macros will retrieve the correct generic value from the Verilog or VHDL parent
module.
You can use these macros multiple times to initialize multiple generics.
3. (optional) Use a flag “<generic_name>_valid” to ensure the validity of a generic’s
value. This is most useful when you use a generic in a conditional block to create
underlying hierarchy. If you do not test for this validity, or continue to simulation with
invalid information, you could receive the following warning.
# ** Warning: (vsim-6663)
Instance '/test_ringbuf/ring_INST/block1_COPY' created during
elaboration in vsim has not been created during elaboration in vopt.
It is likely that the instantiation statement corresponding to this
instance is dependent on the value of a generic propagated to
SystemC from HDL. Please check to see that the SystemC hierarchy
created in vsim is correct.
SC_MODULE(example)
{
public:
SC_GENERIC_INT(generic_int, 0);
SC_GENERIC_REAL(generic_real, 0.0);
SC_GENERIC_STRING(generic_boolean, "true");
SC_CTOR(example)
: SC_INIT_GENERIC_INT(generic_int),
SC_INIT_GENERIC_REAL(generic_real),
SC_INIT_GENERIC_STRING(generic_boolean)
{
if (generic_int_valid) {
block1_COPY = new control("block1_COPY", "control", 3,
generic_list_1);
block1_COPY->clock(clock);
block1_COPY->reset(reset);
}
}
~example() {}
};
The SystemVerilog LRM describes the details of a DPI C import and export interface. This
document describes how to extend the same interface to include SystemC and C++ in general.
The import and export keywords used in this document are in accordance with SystemVerilog
as described in the SystemVerilog LRM. An export function or task is defined in
SystemVerilog, and is called by C or SystemC. An import task or function is defined in
SystemC or C, and is called from SystemVerilog.
Definition of Terms
The following terms are used in this section.
• C++ import function
A C++ import function is defined as a free floating C++ function, either in the global or
some private namespace. A C++ import function must not have any SystemC types as
formal arguments. This function must be made available in the SystemC shared library.
• SystemC Import Function
A SystemC import function must be available in the SystemC shared library, and it can
be either of the following:
o A free-floating C++ function, either in the global or private namespace, with formal
arguments of SystemC types.
Global Functions
A global function can be registered using the API below:
• the name of the function, which can be different than the actual function name. This
name must match the SystemVerilog import declaration. No two functions registered
using this API can have the same name: it creates an error if they do.
• a function pointer to the registered function. On successful registration, this function
will return a 0. A non-zero return status means an error.
Example 9-16. Global Import Function Registration
A macro like the one shown below is provided to make the registration even more simple. In
this case the ASCII name of the function will be identical to the name of the function in the
source code.
SC_DPI_REGISTER_CPP_FUNCTION(scGlobalImport);
In the SystemVerilog code, the import function needs to be defined with a special marker
(“DPI-SC”) that tells the SystemVerilog compiler that this is an import function defined in the
SystemC shared library. The syntax for calling the import function remains the same as
described in the SystemVerilog LRM.
For the SystemC import function shown in Example 9-16, the SystemVerilog import
declaration is as follows:
import mti_scdpi::*;
import "DPI-SC" context function int scGlobalImport(
input sc_logic a, output sc_lv[8:0] b);
Example 9-18 shows how to register a global function by introducing a dummy module
specifically for the purpose of the registration.This lets you do the registration in the procedural
context anytime before the import function is used.
/*Thistop-levelSystemCmoduledoesnothingbutregisterDPI-SCimports
*/
SC_MODULE(dpi_sc_import)
{
SC_CTOR(dpi_sc_import)
{
SC_DPI_REGISTER_CPP_FUNCTION(scGlobalImport);
.............
}
~dpi_sc_import() {};
};
SC_MODULE_EXPORT(dpi_sc_import)
Please refer to Module Member Functions and Calling SystemVerilog Export Tasks / Functions
from SystemC for more details on the SystemC import and export task or function declaration
syntax.
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION(<function_name>, <func_ptr>);
Example:
SC_MODULE(top) {
void sc_func() {
}
SC_CTOR(top) {
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION(“sc_func”, &top::sc_func);
}
};
Note that in the above case, since the registration is done from the module constructor, the
module pointer argument might be redundant. However, the module pointer argument will be
required if the macro is used outside a constructor.
To register a member function from a function that is not a member of the module, the
following registration function must be used:
• The first argument is the name of the function, which can be different than the actual
function name.
This is the name that must be used in the SystemVerilog import declaration.
• The second argument is a reference to the module instance where the function is
defined.
It is illegal to pass a reference to a class other than a class derived from sc_module and
will lead to undefined behavior.
• The third argument is a function pointer to the member function being registered.
On successful registration, this function will return a 0. A non-zero return status means
an error.
For example, the member function run() of the module “top” in the example above can be
registered as follows:
SC_MODULE(top) {
void sc_task() {
SC_CTOR(top) {
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("sc_task", &top::sc_task);
sc_dpi_set_stack_size(1000000); // set stack size to be 1Mbyte.
}
}
For the C++ functions declared as SystemVerilog import functions, you do not need to set the
stack size.
Registration of static member functions is identical to the registration of global functions using
the API sc_dpi_register_cpp_function().
Only one copy of the overloaded member functions is supported as a DPI import, as DPI can
only identify the import function by its name, not by the function parameters.
To enable the registration of member functions, the SystemC source file must be compiled with
the -DMTI_BIND_SC_MEMBER_FUNCTION macro.
and
scSetScopeByName() expects the full hierarchical name of a valid SystemC scope as the input.
The hierarchical name must use the Verilog-style path separator. The previous scope
hierarchical name before setting the new scope will be returned.
scGetScopeName() returns the current SystemC scope for next member import function call.
Since both routines are predefined in Questa SIM built-in package mti_scdpi, you need to
import this package into the proper scope where the two routines are used, using the following
statement:
import mti_scdpi::*;
//test.cpp:
SC_MODULE(scmod)
{
void cppImportFn();
SC_CTOR(scmod)
{
........
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("cppImportFn",
&scmod::cppImportFn);
......
}
};
//test.sv:
module top();
string prev_sc_scope;
string curr_sc_scope;
endmodule
The function declaration must use the SystemC type package, similar to the following:
import mti_scdpi::*;
function int Export(input sc_logic a, output sc_bit b);
The syntax for calling an export function from SystemC is the same as any other C++ function
call.
The SystemC data type names have been treated as special keywords. Avoid using these
keywords for other purposes in your SystemVerilog source files.
The table below shows how each of the SystemC type will be represented in SystemVerilog.
This table must be followed strictly for passing arguments of SystemC type. The SystemVerilog
typedef statements, listed in the middle column of Table 9-29, are automatically imported
whenever the mti_scdpi package is imported.
According to the table above, a SystemC argument of type sc_uint<32> will be declared as
sc_uint[31:0] in SystemVerilog “DPI-SC” declaration. Similarly, sc_lv<9> would be
sc_lv[8:0]. to enable the fixed point datatypes, the SystemC source file must be compiled with -
DSC_INCLUDE_FX.
For fixed-point types the left and right indexes of the SystemVerilog vector can lead to a
negative number. For example, sc_fixed<3,0> will translate to sc_fixed[0-1:0-3] which is
sc_fixed[-1:-3]. This representation is used for fixed-point numbers in the Questa SIM tool, and
must be strictly followed.
For the SystemC types whose size is determined during elaboration, such as sc_signed and
sc_unsigned, a parameterized array must be used on the SystemVerilog side. The array size
parameter value, on the SystemVerilog side, must match correctly with the constructor
arguments passed to types such as sc_signed and sc_unsigned at SystemC elaboration time.
Examples
An export declaration with arguments of SystemC type:
import mti_scdpi::*;
function int Export(input sc_logic a, input sc_int[8:0] b);
import mti_scdpi::*;
import "DPI-SC" context function int scGlobalImport(
input sc_logic a, output sc_lv[8:0] b);
The same typedefs supported for SystemC types as arguments to DPI-SC can be members of
structures.
Example — SystemVerilog
The following structure declaration defines a group of five simple variables: direction, flags,
data, addr, token_number. The name of the structure is defined as packet_sv.
typedef struct {
sc_bit direction;
sc_bv[7:0] flags;
sc_lv[63:0] data;
bit[63:0] addr;
int token_number;
} packet_sv;
You can then use this structure (packet_sv) as a datatype for arguments of DPI-SC, just like any
other variable. For example:
Example — SystemC
An equivalent structure containing corresponding members of SystemC types are available on
the SystemC side of the design. The following structure declaration defines a group of five
simple variables: direction, flags, data, addr, token_number. The name of the structure is
defined as packet_sc.
typedef struct {
sc_bit direction;
sc_bv<8> flags;
sc_lv<64> data;
svBitVecVal addr[SV_PACKED_DATA_NELEMS(64)];
int token_number;
} packet_sc;
You can then use this structure (packet_sc) as a data-type for arguments of DPI-SC, just like
any other variable. For example:
where dpilib1, dpilib2 and dpilib3 are the logical names of SystemVerilog libraries previously
compiled.
An example of a complete compile flow for compiling with multiple libraries is as follows:
// SystemC source file compilations that may include all of the above
three header files.
sccom scmod.cpp
----------------------------------------
hello.cpp:
#include "systemc.h"
#include "sc_dpiheader.h"
SC_MODULE(hello)
{
void call_verilog_task();
void sc_func();
SC_CTOR(hello)
{
SC_THREAD(call_verilog_task);
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("sc_func", &hello::sc_func);
}
~hello() {};
};
void hello::sc_func()
{
printf("hello from sc_func().
}
void hello::call_verilog_task()
{
svSetScope(svGetScopeFromName("top"));
for(int i = 0; i < 3; ++i)
{
verilog_task();
}
}
SC_MODULE_EXPORT(hello);
----------------------------------------
Compilation:
vlog -sv hello.v
sccom -DMTI_BIND_SC_MEMBER_FUNCTION hello.cpp
sccom -link
vsim -c -do "run -all; quit -f" top
Questa SIM allows you to use advanced simulation techniques to control and speed the
simulation process.
Checkpointing and Restoring Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Simulating with an Elaboration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
X Propagation in Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Checkpoint Exclusions
There are a few items upon which checkpoint/restore does not work.
You cannot checkpoint/restore the following:
• state of macros
• changes made with the command-line interface (such as user-defined Tcl commands)
• state of graphical user interface windows
• toggle statistics
• SystemC designs
If you use the foreign interface, you will need to add additional function calls in order to use
checkpoint/restore. See the Foreign Language Interface Reference Manual or Verilog
Interfaces to C for more information.
3. You can also control checkpoint compression using the modelsim.ini file in the [vsim]
section (use the same 0 or 1 switch):
[vsim]
CheckpointCompressMode = <switch>
The situation is similar for using checkpoint/restore without quitting Questa SIM; that is,
doing a checkpoint and later in the same session doing a restore of the earlier checkpoint. The
restore does not touch the state of the macro interpreter so you may also do checkpoint and
restore commands within macros.
vlog when.v
vsim -c when -do "do when.do"
onbreak {
echo "Resume macro at $now"
resume
}
quietly set continueSim 1
quietly set whenFired 0
quietly set checkpointCntr 0
when { needToSave = 1 } {
echo "when Stopping to allow checkpoint at $now"
set whenFired 1
stop
}
while {$continueSim} {
run -all
if { $whenFired} {
set whenFired 0
echo "Out of run command. Do checkpoint here"
checkpoint cpf.n[incr checkpointCntr].cpt
}
}
module when;
reg clk;
reg [3:0] cnt;
reg needToSave;
initial
begin
needToSave = 0;
clk = 0;
cnt = 0;
#1000;
$display("Done at time %t", $time);
$finish;
end
One restriction of elaboration files is that they must be created and used in the same
environment. The same environment means the same hardware platform, the same OS and
patch version, and the same version of any PLI/FLI code loaded in the simulation.
1. If timing for your design is fixed, include all timing data when you create the elaboration
file (using the -sdf<type> instance=<filename> argument). If your timing is not fixed
in a Verilog design, you will need to use $sdf_annotate system tasks. Note that use of
$sdf_annotate causes timing to be applied after elaboration.
2. Apply all normal vsim arguments when you create the elaboration file. Some arguments
(primarily related to stimulus) may be superseded later during loading of the elaboration
file (see Modifying Stimulus below).
3. Load the elaboration file along with any arguments that modify the stimulus (see
below).
Note
Elaboration files can be created in command-line mode only. You cannot create an
elaboration file while running the Questa SIM GUI.
Examples
The vsim arguments listed below can be used with -load_elab to affect the simulation.
+<plus_args>
-32
-64
+autofindloop
-c, -i, -batch, or -gui
-do <do_file>
-f
-filemap_elab <HDLfilename>=<NEWfilename>
-l <log_file>
-quiet
-stats
-suppress
-sv_seed <integer> | random
-trace_foreign <level>
+UVM_TESTNAME
-ucdbteststatusmsgfilter
-vcdread <filename>
-vcdstim <filename>
-wlf <filename>
Modification of an argument that was specified at elaboration file creation, in most cases,
causes the previous value to be replaced with the new value. Usage of the -quiet argument at
elaboration load causes the mode to be toggled from its elaboration creation setting.
All other vsim arguments must be specified when you create the elaboration file, and they
cannot be used when you load the elaboration file.
Note
The elaboration file must be loaded under the same environment in which it was created.
The same environment means the same hardware platform, the same OS and patch version,
the same version of any PLI/FLI code loaded in the simulation, and the same release of Questa
SIM.
Modifying Stimulus
A primary use of elaboration files is to simulate the same design multiple times using a different
stimulus.
Procedure
The following techniques allow you to modify the stimulus for each simulation run.
• Use the change command to modify parameters or generic values. This affects
values only—it has no effect on triggers, compiler directives, or generate statements
that reference either a generic or parameter.
• Note that because the elaborated image is already created, the vsim -g and vsim -G
arguments are ignored for simulation.
FLI models that don't support checkpoint/restore may work if simulated with the
-elab_defer_fli argument. When used in tandem with -elab, -elab_defer_fli defers calls to the
FLI model's initialization function until elaboration file load time. Deferring FLI initialization
skips the FLI checkpoint/restore activity (callbacks, mti_IsRestore(), ...) and may allow these
models to simulate correctly. However, deferring FLI initialization also causes FLI models in
the design to be initialized in order with the entire design loaded. FLI models that are sensitive
to this ordering may still not work correctly even if you use -elab_defer_fli.
See the vsim command for details on -elab, -elab_cont, -elab_defer_fli, -compress_elab,
-filemap_elab, and -load_elab.
Upon first simulating the design, use vsim -elab <filename> <library_name.design_unit> to
create an elaboration file that will be used in subsequent simulations.
In subsequent simulations you simply load the elaboration file (rather than the design) with
vsim -load_elab <filename>.
To change the stimulus without recording, recompiling, and reloading the entire design, Questa
SIM allows you to map the stimulus file (or files) of the original design unit to an alternate file
(or files) with the -filemap_elab switch. For example, the VHDL code for initiating stimulus
might be:
If the alternate stimulus file is named, say, alt_vectors, then the correct syntax for changing the
stimulus without recording, recompiling, and reloading the entire design is as follows:
X Propagation in Simulation
The xprop functionality within Questa SIM serves to make RTL simulation behavior close to
silicon behavior. The difference in behavior is mainly due to the handling of 'X' values. So, in
certain cases it makes RTL more pessimistic by considering 'X', while in other cases it makes
RTL more optimistic by eliminating 'X'. The main advantage of this technology is to find
hidden issues in the early stages of verification (at RTL level).
When considering X values, it is instructive to recall that there is no real X value in silicon. X
means the value is either 1 or 0, but the simulator doesn't know which one is correct at the
moment. Typically an un-initialized register will power-up in ether the 0 or 1 state, but that
value cannot be predicted, so in simulation we use X to represent that state. Consider the
following scenario:
if (en)
q = d1;
else
q = d2;
If “en” goes ‘X’ then RTL semantic considers it false and executes the else branch of the if
statement. However, in actual hardware, any of two branches can be executed. In some cases,
this RTL x-optimism can hide some potential bugs.
If 'sel' goes 'X' then the RTL semantic would assign 'x' value to 'out' irrespective of the value of
'a' and 'b'. However, in actual hardware if 'a' and 'b' are equal then 'out' should take the value of
either of 'a' or 'b'. Due to this RTL x-pessimism a great deal of engineering time can be lost
debugging the cause of a pessimistic X, only to find out that there is no actual design problem.
By default, Questa SIM identifies certain x-scenarios in the design, similar to those outlined
above, which can cause RTL-silicon mismatches. It then modifies them to make the simulation
more silicon compatible (i.e. x-pessimistic/x-optimistic).
This removal process can be understood by taking the following if-else construct:
if (en)
q = d1;
else
q = d2;
Here, xprop checks for 'X' values on existing ‘if’ conditions and pessimistically drives all the
writers to 'X' value. The modification can be thought of as wrapping a conditional branching
statement with an immediate assertion that checks for X. That being the case, the example
above would be treated as:
• pass mode (“vopt -xprop,mode=pass”) — checks for ‘X’ values on all branches and
drives the writers to ‘X’.
• resolve mode (default: “vopt -xprop,mode=resolve”) — evaluates all possible output
values from all branches: if values are the same, that value drives the output. If any of
the values is different, then the output is driven to ‘X’.
• trap mode (“vopt -xprop,mode=trap”) — if any assertion value goes ‘X’, then only
assertion messages are output; the simulation behavior is unaffected.
Unreachable branches can be removed using an additional parameter (“vopt -
xprop,mode=pass|resolve|trap,optmode”). When this is used, xprop does not consider output
values from unreachable (dead/optimized) branches.
Application:
1. within a module:
(*xprop_off = "TRUE"*)
module module_name
……
endmodule
2. within a process:
(*xprop_off="TRUE"*)
process begin
…….
end
WRITE Example:
Assertion Message:
READ Example:
Assertion Message:
X Propagation Examples
Examples of X propagation can be divided into two categories; RTL x-optimism examples and
RTL x-pessimism examples.
You can find additional examples within the install directory at:
<install_dir>/examaples/xprop/
if (en)
q = d1;
else
q = d2;
Table 10-2 describes the resolve and pass output for 'q' for various values of inputs
Table 10-2. If-else - Outputs with pass and resolve xprop Settings
en d1 d2 pass resolve RTL Silicon
Simulation
x 0 0 x 0 0 0
x 1 0 x x 0 ?
x 0 1 x x 1 ?
x 1 1 x 1 1 1
if (reset)
q = 0;
else if(set)
q = 1;
else if(en)
q = d;
Table 10-3. Latch - Outputs with pass and resolve xprop Settings
reset set en d q(t-1) pass resolve RTL Sim Silicon
x x x 0 0 x 0 0 0
x x x 0 1 x x 0 ?
x x x 1 0 x x 1 ?
Table 10-3. Latch - Outputs with pass and resolve xprop Settings (cont.)
reset set en d q(t-1) pass resolve RTL Sim Silicon
x x x 1 1 x 1 1 1
RTL X-Pessimism Examples
Example 10-3. Array-index Pessimism
Reg [1:0]arr;
q = arr[idx];
If 'idx' goes x, then RTL simulation assigns 'x' value to q irrespective of values stored in
different bits of the vector 'arr'. However in silicon, if all the bits of 'arr' are same then q takes a
valid value.
Table 10-5. assign mux - Outputs with pass and resolve xprop Setting
sel a b pass resolve RTL-sim Silicon
x 1 1 x 1 x 1
x 1 0 x x x ?
x 0 1 x x x ?
x 0 0 x 0 x 0
case (en)
1'b1: q = d1;
1'b0: q = d2;
Table 10-6 describes the resolve and pass output for 'q' for various values of inputs.
Table 10-6. Case Statements - Outputs with pass and resolve xprop Settings
en d1 d2 pass resolve RTL Silicon
Simulation
x 0 0 x 0 x 0
x 1 0 x x x ?
x 0 1 x x x ?
x 1 1 x 1 x 1
if (reset)
q = 0;
else if(set)
q = 1;
else if(clk)
q = d;
Table 10-7. Flip-Flop - Outputs with pass and resolve xprop Settings
reset set clk d q(t-1) pass resolve RTL Silicon
Simulation
x x x 0 0 x 0 0 0
x x x 0 1 x x 0 ?
x x x 1 0 x x 1 ?
x x x 1 1 x 1 1 1
The following Questa features are disabled when vopt -xprop is applied:
• Coverage
• Advanced debug
• Multi-core simulation
If the -xprop vopt argument is used with any of above features, vopt issues the following error
and exits:
If coverage is enabled during the compilation of source files, then vopt ignores the coverage.
This chapter discusses transactions in Questa SIM: what they are, how to successfully record
them, and how to view them in the GUI.
Transaction Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
What is a Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About the Source Code for Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About Transaction Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Viewing Transactions in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Transaction Viewing Commonalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Viewing Transaction Objects in the Structure Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Viewing Transactions in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Retroactive Recording and Transaction Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Selecting Transactions or Streams in the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . 613
Customizing Transaction Appearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Viewing a Transaction in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Viewing a Transaction in the Objects Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Debugging Transactions with Tcl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transactions in Designs with Questa Verification IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transaction Recording Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transaction Recording Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Names of Streams and Substreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Stream Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Transaction UIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Attribute Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Multiple Uses of the Same Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Anonymous Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Definition of Relationship in Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
The Life-cycle of a Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Transaction Handles and Memory Leaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Transaction Recording Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Recording Transactions in Verilog and VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Verilog Recorded Transaction Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Valid Verilog Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Recording Transactions in SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Initializing SCV and Creating WLF Database Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Creating Transaction Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Writing SCV Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
SCV API Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Transaction Background
Some concepts are inherent to understanding transactions.
What is a Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About the Source Code for Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
About Transaction Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
What is a Transaction?
A transaction is a statement of what the design is doing between one time and another during a
simulation run. It is as simple as it is powerful.
While the definition of a transaction may be simple, the word “transaction” itself can be
confusing because of its association with Transaction Level Modeling (TLM). In TLM, design
units pass messages across interfaces and these messages are typically called transactions.
• transaction — An abstract statement, logged in the WLF file, of what the design was
doing at a specific time. The designer writes a transaction in the source code, which is
then logged into the WLF file during simulation. Often, transactions represent packets of
data moving around between design objects. Transactions allow users to debug and
monitor the design at any level of abstraction.
As written in the source code, a transaction at a minimum consists of:
• a name
• a start time
• an end time
With that alone, you could record the transitions of a state machine, summarize the activity on a
bus, and so forth. Additionally, transactions may have user-defined attributes, such as address,
data, status, and so on.
Related Topics
Viewing Transactions in the GUI
Selecting Transactions or Streams in the Wave Window
See “Verilog and VHDL API System Task Reference” for the Questa SIM Verilog API
recording syntax.
Related Topics
Viewing Transactions in the GUI
Selecting Transactions or Streams in the Wave Window
Concurrent transactions appear in the Wave window as they are recorded, either as:
The simulator automatically logs the transactions, making them available for immediate
viewing in the GUI. Transactions are best viewed in the Wave window. See Viewing
Transactions in the GUI for procedural details.
Icon Element
Transaction Stream
Substream
Attributes
Parallel transactions
Phase transactions
Concurrent (overlapping)
transactions
Parallel Transactions
The simulator creates a separate substream for each transaction so that they are distinct from
each other in the view. Expanding the substream reveals the attributes on those transactions.
Concurrent transaction instances are drawn overlapping, with a vertical offset, so that each
instance can be seen.
Tip
Substream Creation — Generally, you have no direct control over the creation of
substreams; they are created for you during simulation as needed. The rule for substream
creation is: A transaction is placed on the first substream that has no active transaction and does
not have any transaction in the future of the one being logged.
For example, consider that a busRead transaction may have several steps or phases. Each of
these could be represented as a smaller, concurrent transaction and would appear on a second
substream. However, you can indicate that these are phase transactions, and by doing so, you
instruct the tool to draw them specially, as shown in Figure 11-1. Concurrent transaction
instances are drawn overlapping, with a vertical offset, so that each instance can be seen.
Related Topics
Viewing Transactions in the GUI
Selecting Transactions or Streams in the Wave Window
Figure 11-2 shows several streams, one of which has eight sub-streams.
Transaction streams are dynamic objects under the control of the design. During simulation, the
design may define new streams, define new transaction kinds, overlap transactions or create
phase transactions, add special attributes of all kinds, and so forth. In response, the simulator
actively re-creates the objects in the GUI to reflect the most recent changes.
Dynamic changes are always additive: once an element is added to a stream, it remains there in
all views. In post-simulation debug, all elements are shown as if they existed from the beginning
of the simulation run. For both interactive and post-simulation debug, elements that did not exist
at a particular simulation time are shown as if the "nolog" command had been used; their values
are "No_Data".
Related Topics
Viewing Transactions in the GUI
Related Topics
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Viewing a Transaction in the List Window
Viewing a Transaction in the Objects Window
3. Select the plus icon next to streams having objects beneath them to reveal substreams
and/or any attributes.
Results
The icon for a transaction stream is a four-point star in the color of the source language for the
region in which the stream is found (SystemC - green, Verilog - light blue, VHDL - dark blue).
In the waveform pane, transactions appear as boxes surrounding all the visible values for that
transaction. Here's an example of a transaction on a stream with only one sub-stream where the
stream is shown in its expanded and collapsed forms:
Figure 11-3. Viewing Transactions and Attributes
Each box represents an “instance” of a transaction on the stream. The horizontal line drawn
between the first and second transaction indicates a period of either no activity OR a period in
which logging has been disabled; there is no way to know which is the case.
When there are concurrent, parallel transactions, the stream shows concurrent values which are
drawn overlapping with a vertical offset, so that each instance can be seen. Expanding the
stream reveals the sub-streams, separating the transactions neatly, as in Figure 11-4. Each sub-
stream may expand to reveal attributes or phase sub-streams. When you select a transaction
instance, all related transactions are also highlighted, as can also be seen in Figure 11-4.
Figure 11-5 shows a simple transaction stream that includes simple, user-defined address and
data attributes:
Figure 11-5. Transaction in Wave Window - Viewing
The top row of a transaction is the name of the transaction. When the transaction stream is
expanded, as in Figure 11-5, additional rows are revealed that represent attributes of the
transaction.
Tip
For SystemC begin/end attributes — If a begin end attribute was declared by the generator,
but the value was not defined, the value appears as “Undefined” in the GUI.
Related Topics
Viewing Transactions in the GUI
Retroactive Recording and Transaction Display
Viewing a Transaction in the List Window
Viewing a Transaction in the Objects Window
For example, a stream could have logging disabled between T1 and T2 and still record a
transaction in that period using retroactive logging after time T2. A transaction is always
entirely logged or not logged.
Related Topics
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Viewing a Transaction in the List Window
Viewing a Transaction in the Objects Window
Viewing Options
• Selecting transactions or streams with the mouse:
o Select an individual transaction: left click on the transaction. When you select a
transaction, any substreams of that transaction are selected also.
Left click while holding down the SHIFT key to select multiple transactions/
streams.
o Select a transaction stream: left click on the transaction name in the object name area
of the Wave window.
• Selecting and Viewing Related Transactions
a. Select a single transaction.
b. Right mouse click to bring up pop-up menu with the following choices:
• Select Related — to select a transaction to which the current transaction is
pointing.
• Select Relating — to select a transaction that is pointing to the current
transaction.
• Select Chain — to select all related and relating transactions for the current
transaction. Use this to select an entire causal chain.
• Select Meta — to select all related and relating transactions for the current
transaction. Use this to select any existing branches for the relationship.
Selecting any of these items brings up a submenu which lists all relationship names that
apply.
These pop-up menu items are grayed out if more than one transaction is selected.
For information on how to record relations, see “Specifying Relationships” (SC) and
“Specifying Relationships” (Verilog/VHDL).
Related Topics
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Viewing a Transaction in the List Window
Customizing Color
Customizing the color in the Wave window overrides colors during simulation (set with
add_color() in the design).
You can change the color of one or more transactions or streams using the GUI or the tr color
command.
Note
Whether the color is specified using add_color() or in the Wave window, the color name
specified is interpreted by Tcl and the local window manager at debug time. For example,
“red” can appear different from machine to machine, depending on whether or not a system is
performing gamma correction.
Procedure
1. Right-click a transaction or stream name to open a popup menu.
2. Select Transaction Properties to open the Transaction-Stream Properties dialog box
(Figure 11-6).
The element, transaction or entire stream of transactions changes to the chosen color.
Related Topics
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Customizing Transaction Appearance
4. Select the attribute from the list of visible attributes and select:
• Show — to display currently hidden attributes in stream
• Hide — to hide attribute from view in the stream
• Up — to move attribute up in the stream up
• Down — to move down
• Default — to restore original view
5. Apply makes the changes, leaving the dialog box open; OK applies the changes and
exits.
Related Topics
tr order
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Selecting Transactions or Streams in the Wave Window
Procedure
1. Run simulation on a design containing transactions.
vsim top; run -all
Results
When transactions are present in the List window, new rows are written to the List window any
time a transaction's state changes. Specifically, rows are printed when a transaction starts or
ends and when any attribute changes state, which can occur between time steps or deltas.
Figure 11-8. Transactions in List Window
This example shows List output for a stream showing two transaction kinds. Each has a begin
attribute, a special attribute and an end attribute in the style of SCV.
ns /top/abc/busMon
delta
0 +0 <Inactive>
1 +0 <Inactive>
1 +0 <Inactive>
1 +0 {busRead 1 <Inactive> <Inactive>}
3 +0 {busRead 1 100 <Inactive>}
3 +0 {busRead 1 100 10}
3 +0 <Inactive>
4 +0 <Inactive>
4 +0 <Inactive>
4 +0 <Inactive>
4 +0 {busWrite 2 <Inactive> <Inactive>}
6 +0 {busWrite 2 200 <Inactive>}
6 +0 {busWrite 2 200 20}
6 +0 <Inactive>
7 +0 <Inactive>
7 +0 <Inactive>
7 +0 <Inactive>
7 +0 {busRead 3 <Inactive> <Inactive>}
9 +0 {busRead 3 300 <Inactive>}
9 +0 {busRead 3 300 30}
9 +0 <Inactive>
In this example, you can see the same time/delta repeating as changes are made to the
transaction. For example, at 1(0) a busRead begins with the begin attribute set to the value "1".
At time 3(0), the end attribute value "100" arrives. On the next line, also at time 3(0), the special
attribute's value of "10" arrives. On the next line the transaction has ended. This is followed by
a number of lines showing the "<Inactive>" state as the various attributes change state
internally.
Related Topics
tr order
Viewing Transactions in the GUI
Viewing Transactions in the Wave Window
Viewing Transaction Objects in the Structure Window
2. Open the Objects window, if not open by default: View > Objects.
Results
Streams appear in the Objects window as simple or composite signals, depending on the
complexity of transactions that have been defined for the stream. The icon for a transaction
stream is a four pointed star in the color of source language for the region in which the stream is
found (SystemC - green, Verilog - light blue, VHDL - dark blue).
Figure 11-9. Transactions in Objects Window
Related Topics
Selecting Transactions or Streams in the Wave Window
Viewing Transaction Objects in the Structure Window
Viewing Transactions in the Wave Window
<stream>.<substream>[<substream...].<attribute>
Questa SIM generates the names of sub streams. The name is the first character of the
parent stream's name followed by a number. Sub-stream numbering starts at zero.
set subStream “s0”
Once you have set the stream, substream, and attribute names, you can access the variable value
at any specified time. A sample examine command using the attribute in the above example
might be:
exa –t 30 $streamName.$subStream.$attributeName
You can place commands such as these into a Tcl script and use it to parse the WLF database.
Related Topics
Names of Streams and Substreams
The basic steps for recording transactions can be summarized in Figure 11-10.
The SystemC tasks and Verilog API calls used in these steps are listed in Table 11-1.
Table 11-1. System Tasks and API for Recording Transactions (cont.)
Action SystemC - Verilog/VHDL -
System Task Used Questa SIM API Used
Specify relationships between ::add_relation() add_relation
transactions — Optional. or
SC - See Specifying Relationships begin_transaction
V - See Specifying Relationships
Specify begin and/or end times of ::begin_transaction() and begin_transaction
transactions — Optional. ::end_transaction() and
SC - See Specifying Transaction Start and end_transaction
End Times
V - See Specifying Transaction Start and
End Times
Control database logging — Optional. log / nolog and log / nolog
See Stream Logging ::set_recording()
For SCV specific limitations and implementation details, see: SCV Limitations
Read these guidelines prior to recording transactions for a general understanding of recording
transactions for viewing in Questa SIM:
Anonymous streams are not allowed. Stream names may be any legal C, Verilog or VHDL
identifier. If the name includes white-space or is not a legal C identifier, it should be an escaped
or extended identifier or you will get a warning at run time. The simulator issues a warning for a
non-standard name.
You can also specify a relative path, using the tool to search upward from the calling region in
the hierarchy as determined automatically by the simulator. The region where a transaction
stream appears is determined according to the placement of the call to create the stream
($create_transaction_stream, create_transaction_stream or scv_tr_stream). For most designs,
the transaction stream is placed just where you would want it to be. However, for some
SystemVerilog and OVM class-based designs, the placement may not be appropriate. In these
cases, full path specifications are usually safest.
Substream Names
The tool names substreams automatically. The name of any substream is the first character of
the parent’s name followed by a simple index number. The first substream has the index zero. If
the parent stream has a non-standard name, such as one that starts with a numeral or a space,
you may have difficulty with debug.
Related Topics
Transaction Recording Guidelines
Stream Logging
Transaction UIDs
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
Stream Logging
By default, when your design creates a stream, logging is enabled for that stream providing that
the logging is enabled at the simulation time when the design calls ::begin_transaction(). The
effective start time of the transaction (the time passed by the design as a parameter to ::begin
transaction()) does not matter.
For example, a stream could have logging disabled between T1 and T2 and still record a
transaction in that period using retroactive logging after time T2. A transaction is always
entirely logged or entirely ignored. You can disable the logging on transaction streams with the
nolog command.
There is no way in the simulator to distinguish a stream whose logging has been disabled from
one that is merely inactive.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Transaction UIDs
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
Transaction UIDs
Each transaction, when created during simulation, is assigned a 64-bit serial number. This serial
number, along with the logical name of the dataset in which the transaction exists, comprises the
transaction’s UID (unique identifier). Within the simulation run, this number is unique.
The “tr uid” and “tr color” commands use the UID to specify a specific transaction within a
particular dataset in which it exists. UIDs also allow for any transaction to refer to any other
transaction.
Use examples:
The first example represents a transaction in the current simulation, since “sim” is always the
name of the current simulation dataset. The second example is a transaction from a WLF file
opened with the logical name “myData”.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
Attribute Type
On any single transaction stream, Questa SIM associates an attribute name with a data type.
Attempts to overload an attribute name are not recommended; in most cases, Questa SIM will
issue an error. The only exception is that the same attribute name on two different sub-streams
of a stream may be overloaded.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Transaction UIDs
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Transaction UIDs
Attribute Type
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
Anonymous Attributes
Questa SIM requires every transaction attribute to have a name. It is possible to neglect the
name in the SCV and Verilog/VHDL APIs for transaction recording, however. The simulator
resolves the problem by inventing a name for the attribute.
SCV — an attribute is anonymous if the name is the empty string or the name is a NULL
pointer. The simulator uses the data type to choose a new name as follows:
• If the type is a struct or class, the simulator constructs an attribute for each field or
member, using the field or member name as the name of each attribute.
• If the type is anything other than a string or class, the simulator uses the type name (for
example, "short", "float", etc.) as the name for the attribute.
Verilog/VHDL — an attribute is anonymous if the name parameter is ignored or is an empty
string. The simulator chooses a name as follows:
• If the value of the attribute is passed through a variable, the simulator uses the name of
the variable as the name for the attribute.
• If the value of the attribute is passed as a literal or the return value from a function, the
simulator uses the type name of the value as the name for the attribute.
In any language, if the simulator finds an attribute already exists with the same name and type
as the one it is creating, it will re-use that attribute.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Transaction UIDs
Attribute Type
Multiple Uses of the Same Attribute
Definition of Relationship in Transactions
...
$add_relation(hSrc, hTgt, "child");
the relationship is created for hSrc such that “hSrc” claims the child relationship to “hTgt”.
When this relationship is recorded, a counter relationship is automatically recorded on “hTgt” to
indicate that “hSrc” is claiming the child relationship with “hTgt”.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
The Life-cycle of a Transaction
Transaction Handles and Memory Leaks
• Attributes and relations can be added during the entire life-cycle, not just between the
start and end times for the transaction, so long as you have a valid handle to the
transaction. A valid handle is one whose returned value is non-zero. See “Valid Verilog
Handles” for information about how to detect errors.
• You can enable or disable logging of transactions anytime during the life-cycle,
regardless of start and end times.
• A transaction stays in memory until its handle is released. Transaction handles should be
freed as soon as possible, to minimize use of memory buffering and the retroactive WLF
channels. Verilog and VHDL designs must use the free_transaction() task explicitly for
every transaction.
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Transaction UIDs
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
Transaction Handles and Memory Leaks
Related Topics
Transaction Recording Guidelines
Names of Streams and Substreams
Stream Logging
Transaction UIDs
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
Definition of Relationship in Transactions
The Life-cycle of a Transaction
The recording APIs for Verilog and VHDL are a bit simpler than the SCV API. Specifically, in
Verilog and VHDL:
• There is no database object as there is in SCV; the database is always WLF format (a
.wlf file).
• There is no concept of begin and end attributes All attributes are recorded with the
system task $add_attribute() or add_attribute.
• Your design code must free the transaction handle once the transaction is complete and
all use of the handle for relations or attribute recording is complete. (In most cases,
SystemC designs ignore this step since SCV frees the handle automatically.)
For a full example of recorded Verilog transactions with comments, see Verilog Recorded
Transaction Code Example.
Prerequisites
• Understand the rules governing transaction recording. See the section entitled
Transaction Recording Guidelines for details.
• For VHDL, the design must include the transaction recording package supplied with
Questa SIM. You can find this in the modelsim_lib library.
library modelsim_lib;
use modelsim_lib.transactions.all;
Note
This procedure is based on the Verilog API. The VHDL API is very similar.
Procedure
1. Defining a transaction stream
Use $create_transaction_stream() to create one or more stream objects.
module top;
integer hStream
initial begin
hStream = $create_transaction_stream("stream", "transaction");
.
.
end
.
.
endmodule
This example code declares the stream stream in the current module. The stream is part
of the WLF database and the stream will appear as an object in the GUI. The stream will
be logged.
In some OVM or other class-based designs, you may want to specify stream a full path
to the location where you wish to the stream to appear. See “Full or Relative Pathnames”
for more information.
2. Starting a Transaction
Use $begin_transaction, providing:
• a valid handle to a transaction stream
• a variable to hold the handle of the transaction itself
integer hTrans;
.
.
hTrans = $begin_transaction(hstream, "READ");
In this example, we begin a transaction named "READ" on the stream already created.
The $begin_transaction system function accepts other parameters to specify: the start
time for the transaction, and any relationship information, including its designation as a
phase transaction (see “Phase / Child Transactions”). See Verilog and VHDL API
System Task Reference for syntax details.
The return value is the handle for the transaction. It is needed to end the transaction or
record attribute.
3. Recording an Attribute
Optional. Use the $add_attribute system task and provide:
• the handle of the transaction being recorded
• the name for the attribute
• a variable that holds the attribute value
integer address;
.
.
$add_attribute(hTrans, address, "addr");
Be aware that nothing prevents the design from setting the same attribute many times
during the transaction. However, Questa SIM records only the last value of the attribute
prior to the end of the transaction. Once the design uses an attribute, it becomes a
permanent attribute of the parent stream from that time onward. Thus, it shows up as an
element of all subsequent transactions, even if it is unused.
4. Ending a Transaction
Submit a call to $end_transaction and provide the handle of the transaction:
$end_transaction(hTrans);
This ends the specified transaction, though it does not invalidate the transaction handle.
The handle is still valid for calls to record attributes and to define relations between
transactions. As with $begin_transaction(), there are optional parameters for this system
task. See Verilog and VHDL API System Task Reference for details.
5. Specifying Relationships
See “Definition of Relationship in Transactions”. To specify a relationship between
transactions, you must provide:
• two valid transaction handles: one for the source, one for the target
• a <name> for the relation (one signifying the relationship of the <source> to the
<target>). Questa SIM captures the name and uses it to record to pointers, one from
the source instance to the target instance, and one from the target to the source. In the
examples below, the name chosen to represent the relationship is “successor”.
This method is valid any time the design has two valid transaction handles.
See “Definition of Relationship in Transactions” and “Selecting Transactions or
Streams in the Wave Window” for more information.
6. Specifying Transaction Start and End Times
To specify a start and/or end time for any transaction, pass the start and end times as
parameters to $begin_transaction() and $end_transaction(). The time must be the current
simulation time or earlier. See “Transaction Recording Guidelines” for information on
valid start and end times.
7. Freeing the Transaction Handle
Tip
To avoid memory leakage: You must explicitly free all transaction handles in your
design. This is a requirement for Verilog, SystemVerilog and VHDL) recording. See
“Transaction Handles and Memory Leaks”.
a. Ensure that the transaction is complete AND all use of the handle for recording
attributes and relations has been completed.
b. Submit a call to $free_transaction, providing the handle of the transaction being
freed.
$free_transaction(hTrans);
initial begin
stream = $create_transaction_stream("Stream");
#10;
tr = $begin_transaction(stream, "Tran1");
$add_attribute(tr, 10, "beg");
$add_attribute(tr, 12, "special");
$add_attribute(tr, 14, "end");
#4;
$end_transaction(tr);
$free_transaction(tr);
end
endmodule
Related Topics
Recording Transactions in Verilog and VHDL
Verilog and VHDL API System Task Reference
Valid Verilog Handles
The SCV API is a bit more involved than the Verilog or VHDL recording APIs. Specific
differences for the SCV API are as follow:
• In SCV, you must create a database object that is tied to a WLF file.
• The concept of begin and end attributes is unique to SCV. In Verilog and VHDL, all
attributes are recorded with a single system task: add_attribute().
• Transaction handles are freed automatically in SCV.
For a full example of recorded SCV transactions with comments, see “SCV API Code
Example”.
Prerequisites
• Understand the material in the section entitled “Transaction Recording Guidelines” to
understand the basic rules and guidelines for recording transactions.
• Be aware of the limitations for recording transactions in SCV. See “SCV Limitations”.
Procedure
1. Initialize SCV and the MTI extensions for transaction recording and debug.
a. Create a database tied to WLF.
b. Provide SCV extensions, for user-defined types used with attributes.
2. Create transaction generators.
3. Write the transactions.
Related Topics
Initializing SCV and Creating WLF Database Object
Creating Transaction Generators
Verilog Recorded Transaction Code Example
Writing SCV Transactions
1. Enter scv_startup() in the design code — this initializes the SCV library.
2. Enter scv_tr_wlf_init() in the design code — this creates the database tied to WLF,
allowing transactions to then be written to specific database objects in the code.
3. Enter database object(s) — you can create many objects, or create one and specify it as
the default object. All database objects are contained the same WLF file.
/* Initialize SCV: */
scv_startup();
if (txdb != NULL)
scv_tr_db::set_default_db(txdb);
return txdb;
}
• name argument to scv_tr_db() — All databases are tied to the WLF file once the user
calls scv_tr_wlf_init().
• sc_time_unit argument to scv_tr_db() when the database is a WLF database — The
time unit of the database is specified by the overall simulation time unit.
Related Topics
Creating Transaction Generators
Writing SCV Transactions
Recording Transactions in SystemC
For specific details on providing SCV extensions, refer to the SystemC Verification Standard
Specification, Version 1.0e.
Related Topics
Initializing SCV and Creating WLF Database Object
Writing SCV Transactions
SCV API Code Example
Recording Transactions in SystemC
SCV Limitations
Procedure
1. Defining a transaction stream
Before you can record a transaction, you must define the stream onto which the
transaction will be written. In SCV, streams are tied to a specific database so that all
transactions on them are written into that database only. Usually, the code declares the
stream as a member of the module that will use it. Then, it must call the constructor,
passing the stream's name and database as parameters. For example:
SC_MODULE(busModel)
{
| public:
scv_tr_db *txdb;
scv_tr_stream busStream;
SC_CTOR(busModel) :
txdb(init_recording()),
busStream( "busModel", "**TRANSACTOR**")
{
}
}
This example code declares the database and stream objects. In the module constructor,
it initializes the database by calling the setup routine (defined in “Initializing SCV and
Creating WLF Database Object”). It initializes the stream object with its display name
and a string indicating the stream kind. The database is presumed to be the default,
though the example could have been explicit and passed "txdb" as a third parameter.
The name of the stream must be passed as a parameter. Questa SIM treats it as a path
name. This defines where the stream will appear in the design during debug. Each
stream lives in a design region: either the instance in which it was declared or an
instance specified in the constructor parameters.
If the string is a simple name such as "busRead", Questa SIM assumes the stream is to
be created in the current scope, usually the instance of the module. If the string is a
partial path such as "dut/bus/busRead", Questa SIM will try to find parent region "dut/
bus" as the home for the stream. If the string is a full path, such as "/top/dut/bus/
busRead", Questa SIM tries to find the exact region "/top/dut/bus". For full and partial
paths, the region specified must exist or you will receive a runtime error.
If you specify a stream that already exists, returns a handle to the same stream even
though the design will have two different scv_tr_stream objects.
For more specific details on writing a transaction, refer to the “SystemC Verification
Standard Specification, Version 1.0e”.
2. Defining a transaction kind (This step is Optional.)
In SCV, each transaction is defined by a generator object, which is a template for a
transaction. The generator:
• Specifies the name of the transaction. Anonymous transactions are not allowed.
• Specifies optional begin and end attributes. Begin and end attributes are part of the
generator for that kind. They are treated as part of each instance of that transaction.
First, the code must declare each generator, usually in the module in which it will be
used. Any begin and end attribute types must be provided as template parameters. Then,
the generator must be constructed, usually in the constructor initialization list of the
parent module:
SC_MODULE(busModel)
{
public:
scv_tr_db *txdb;
scv_tr_stream busStream;
scv_tr_generator<busAddrAttr, busDataAttr> busRead;
SC_CTOR(busModel) :
txdb(init_recording()),
busStream( "busModel", "**TRANSACTOR**"),
busRead("busRead", busStream)
{
}
}
Special attributes are not part of the original transaction generator: they are
afterthoughts. Record special attributes by:
a. Define the attribute type.
b. Modify a specific transaction instance through the transaction handle using the
scv_tr_handle::record_attribute() routine.
Example:
if (status != BUS_OK) {
errorAttr err;
err.code = status;
txh.record_attribute(err);
}
Nothing prevents a design from setting the same special attribute many times during the
transaction. However, the Questa SIM simulator records only the last value of the
attribute prior to the end of the transaction.
For greater detail on recording special attributes, refer to the SystemC Verification
Standard Specification, Version 1.0e.
5. Recording Phase Transactions
Phase transactions are unique to Questa SIM. If recorded, they appear as transactions
within their parent transaction. The SCV specification does not describe this kind of
transaction, but Questa SIM can record it. Any transaction may have phases, including
another phase transaction. To record phase transactions:
a. Specify mti_phase as the relation name in a call to ::begin_transaction().
You can also specify your own relation name for phases by modifying the value of
the variable ScvPhaseRelationName in the modelsim.ini from “mti_phase” to
something else, such as “child”. This variable applies to recording only; once a
phase is recorded in a WLF file, it is drawn as a phase, regardless of the setting of
this variable.
b. Provide an appropriate parent transaction handle in a call to ::begin_transaction().
6. Specifying Transaction Start and End Times
To specify a start and/or end time for any transaction, pass the start and end times as
parameters to ::begin_transaction() and ::end_transaction(). The time must be the
current simulation time or earlier. See “Retroactive Recording / Start and End Times”
and “Start and End Times for Phase Transactions”.
7. Ending a Transaction
To end transactions in your SystemC code:
a. Set the value for the end attribute.
In both these examples, the design specifies that the current transaction is a “successor”
to the previous transaction.
Related Topics
Initializing SCV and Creating WLF Database Object
SCV API Code Example
Recording Transactions in SystemC
SC_MODULE(tx)
{
public:
scv_tr_db *txdb; /* a handle to a transaction database */
scv_tr_stream *stream; /* a handle to a transaction stream */
generator *gen; /* a handle to a transaction generator */
SC_CTOR(tx)
{
SC_THREAD(initialize);
SC_THREAD(thread);
}
SC_MODULE(top)
{
public:
tx *a;
SC_CTOR(top)
{
a = new tx("tx");
}
};
SC_MODULE_EXPORT(top);
Related Topics
Initializing SCV and Creating WLF Database Object
Creating Transaction Generators
Writing SCV Transactions
SCV Limitations
Recording Transactions in SystemC
SCV Limitations
You can record transactions in only one WLF file at a time.
The SCV API routines allow you to create and use multiple databases, however — if the chosen
database is WLF — all databases are aliased to the same WLF file. Once created, you may load
multiple WLF files that contain transactions into Questa SIM for viewing and debugging.
add_attribute
This system task adds an attribute to a transaction.
Usage
Verilog
$add_attribute(transaction, value, attribute_name)
VHDL
add_attribute(transaction, value, attribute_name)
Arguments
• Task arguments
Return Values
Nothing
Related Topics
Recording Transactions in Verilog and VHDL
Attribute Type
Multiple Uses of the Same Attribute
Anonymous Attributes
add_color
This system task is used to specify color on a per-transaction basis. Sets the color from within
the design, using information available to the design, to highlight different kinds of commands,
error conditions, etc..
Usage
Verilog
$add_color(transaction, color)
VHDL
add_color(transaction, color)
Arguments
• Task arguments.
Return Values
Nothing
Related Topics
Customizing Color
add_relation
This system task adds a relation from the source transaction to the target transaction.
Usage
Verilog
$add_relation(source_transaction, target_transaction, relationship_name)
VHDL
add_relation(source_transaction, target_transaction, relationship_name)
Arguments
• Task arguments.
Return Values
Nothing
Related Topics
Recording Transactions in Verilog and VHDL
Definition of Relationship in Transactions
begin_transaction
This system task begins a transaction on the specified stream. The transaction handle must be
saved for use in other transaction API calls. $begin_transaction() or begin_transaction() is used
to start all transactions. The optional fourth parameter allows you to specify a parent
transaction, making the new transaction a phase transaction of the parent.
Usage
Verilog
$begin_transaction(stream, transaction_name, begin_time, parent_transaction)
VHDL
begin_transaction(stream, transaction_name, begin_time, parent_transaction)
Arguments
• Task arguments
Return Values
Description
A handle returned by $begin_transaction() or begin_transaction() will be non-zero unless there
is an error. The error is reported to the transcript.
Related Topics
Recording Transactions in Verilog and VHDL
The Life-cycle of a Transaction
Valid Verilog Handles
create_transaction_stream
This system task creates a transaction stream that can be used to record transactions. The stream
handle must be saved for use in other transaction API calls.
Usage
Verilog
$create_transaction_stream(stream_name, stream_kind)
VHDL
create_transaction_stream(stream_name, stream_kind)
Arguments
• Task arguments
Return Values
Description
A handle returned by $create_transaction_stream() or create_transaction_stream() will be non-
zero unless there is an error. The error is reported to the transcript.
Related Topics
Recording Transactions in Verilog and VHDL
About Transaction Streams
Names of Streams and Substreams
Stream Logging
Valid Verilog Handles
delete_transaction
This system task removes a transaction from the transaction database. The transaction is not
recorded in the WLF file.
Usage
Verilog
$delete_transaction(transaction)
VHDL
delete_transaction(transaction)
Arguments
• Argument names
Return Values
Nothing
Related Topics
Recording Transactions in Verilog and VHDL
Valid Verilog Handles
end_transaction
This system task ends the specified transaction. Ending the transaction simply sets the end-time
for the transaction and may be done only once. However, if free is not specified, the transaction
handle is still valid for use in recording relations and attributes until a call to $free_transaction()
or free_transaction().
Usage
Verilog
$end_transaction(transaction, end_time, free)
VHDL
end_transaction(transaction, end_time, free)
Arguments
• Task arguments.
Return Values
Nothing
Related Topics
Recording Transactions in Verilog and VHDL
The Life-cycle of a Transaction
free_transaction
This system task frees a transaction. This call allows the memory allotted for this transaction to
be freed. The handle will no longer be valid. Attributes can no longer be recorded for the
transaction. Relations can no longer be made with the transaction.
Tip
You must free all transaction handles in your design. This is a requirement specific to
Verilog and VHDL recording. If a handle is not freed, the result is a memory leak in the
simulation.
Usage
Verilog
$free_transaction(transaction)
VHDL
free_transaction(transaction)
Arguments
• Task arguments
Return Values
Nothing
Related Topics
The Life-cycle of a Transaction
This chapter provides a brief introduction to Questa Verification IP transactions in Questa SIM,
and discusses additional features of the Questa SIM GUI available when simulating a model
that includes Questa Verification IP(s).
What is Questa Verification IP?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
What is a Questa Verification IP Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Questa Verification IP Transaction Viewing in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . 662
Questa Verification IP Transaction Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
the address and data transfers. It is also referenced by a higher level transaction, “Burst
Transfer.” Note that “Burst Transfer” can consist of multiple “Transfer” transactions. Signals
are always represented at the lowest level of abstraction.
In the example shown in Figure 12-1, a “Transfer” transaction is related to the “Address” and
“Data” transactions that communicate the address and data information for that transfer. These
transactions in turn are related to the individual signals which communicate the equivalent
information across the bus. Questa Verification IPs maintain these relationships, allowing for
simulation and debugging across the different levels of abstraction.
The term “parent” describes a related transaction at a higher level of abstraction, and “child”
describes a related transaction or signal at a lower level of abstraction. Each transaction may
have many related child or parent transactions. In Figure 12-1, the “Transfer” transaction has
two children: a “Address” transaction and a “Data” transaction. It also has one parent: “Burst
Transfer” transaction. Each Burst Transfer transaction can have multiple “Transfer”
transactions as children.
Related Topics
Questa Verification IP Arrays in the Wave Window
Questa Verification IP Objects in the GUI
Color and Questa Verification IP Arrays in Wave Window
Arrays in Questa Verification IP
The MVC_Message and MVC_Transaction objects represent higher level transactions (see
Figure 12-1 for an example) that can be related to other MVC_Stripe, MVC_Message and
MVC_Transaction objects. MVC_Stripe objects are always the lowest level transaction, having
a direct relationship to a set of signals.
Questa Verification IP objects can be viewed in the Wave window, where they are drawn as
transaction streams or signals. Table 12-1 includes a description of the various objects and how
they appear.
Related Topics
Questa Verification IP Transaction Viewing in the GUI
Questa Verification IP arrays can have multiple dimensions. For example, one component
might contain a two-by-two array of MVC_Message objects. This results in a single object in
the GUI. Consider the following array in the objects window (as shown in Figure 12-2).
Selecting the array’s expand button reveals the two rows of the array. The “Kind” field for the
array displays the Questa Verification IP kind (“MVC_Message”) and the size of the array
(“[2][2]”).
The level below the array (txStreamArray) is that of the two sub-arrays (0 and 1). These are the
rows of the parent array, each of which has the correct name for an array element, and its kind
field indicates the size of the sub-array. Expanding the sub-arrays reveals the leaf streams of the
array, whose “Kind” fields do not contain any index values. Expand buttons on “leaf” streams
indicate that they have sub-streams or attributes.
Related Topics
Questa Verification IP Objects in the GUI
2. Enable logging for the desired object(s). Objects must be explicitly logged for
transaction viewing. Logging the object(s) results in the objects being recorded in the
.wlf file, allowing them to be viewed post-simulation. To log Questa Verification IP
objects, you can:
• Add transactions to the Wave window by dragging and dropping them into the
window. Alternatively, you can use a add wave CLI command, such as:
add wave /top/interface/read_id
• To log all OVM/UVM sequence Questa Verification IP transactions (i.e., only the
transactions in the Questa Verification IP protocol stack with sequence items) use
the -mvcovm switch:
add wave -mvcovm -r /*
log -mvcovm -r /*
4. Within the Wave window, navigate to the portion of the design containing the Questa
Verification IP component or protocol.
a. Additional Steps for the viewing of completed transactions
5. Additional Steps for the viewing of completed transactions
By default, only recognized transactions that have become used as legal protocol are
logged, which may prevent the transaction instances of interest from being logged soon
enough to observe an issue. To enable the logging of transaction instances that have
been recognized as completed (which may later become used or deleted), please follow
these additional steps:
a. Add the required transaction to the Wave window.
b. Right-click on the transaction name.
You can select any number of transaction streams to enable the logging of completed
transaction instances for those additional transaction streams.
c. Select “Transaction Properties” from the pop-up menu.
d. Select the “Questa VIP Logging” tab.
e. Click the “Deletion Logging Enabled” box to display deleted transaction instances.
f. Click the “State Logging Enabled” box to log the State History of transaction
instances.
g. Click OK.
h. Run the simulation - all completed transactions now appear on the Wave window.
Results
Transactions within Questa Verification IP components appear in the Wave window, as shown
in Table 12-3. For information on the colors of transactions, see “What the Colors Mean in the
Wave Window”.
For example, in Figure 12-3, the color shown in the transaction objects allows us to determine
that a read transaction was started by a TLM master. This resulted in the Questa Verification IP
generating a setup_phase transaction and a number of xxx_cycle messages, which in turn
resulted in some pin level activity. This caused an RTL slave to issue a response which was
recognized by the Questa Verification IP up into a response_phase message (through the
xxx_cycle messages), and finally back into the read transaction.
This basic color scheme is modified slightly for arrays of Questa Verification IP objects. See
“Color and Questa Verification IP Arrays in Wave Window” for more information.
Related Topics
About Transaction Streams
Questa Verification IP Transaction Debug
What is a Questa Verification IP Transaction?
You can see that all of the other instances on the four “leaf” streams are either activated (purple)
or generated (green) (see Table 12-2 for color descriptions).
Now, these colors are NOT reflected up to the parent arrays: the parent arrays are black. This is
due to the fact that it is typical to have paired elements in an array to separate outgoing and
incoming traffic, and it is not feasible to mix the colors symbolizing this pairing in any
straightforward way. Thus, arrays are always drawn in black, unless an error occurs in one or
more element.
Related Topics
What the Colors Mean in the Wave Window
Questa Verification IP Transaction Debug
Procedure
1. Ensure the model containing the Questa Verification IP protocol is loaded. For example:
vsim top
2. With the Objects window open (View > Objects), select the top level SystemVerilog
interface in the Questa Verification IP.
Results
The objects in that interface appear in the Objects window, similar to those in Figure 12-7.
Related Topics
Viewing Questa Verification IP Transactions in the Wave Window
Questa Verification IP Transaction Debug
Viewing Questa Verification IP Transactions in List Window
Prerequisites
Before you can view Questa Verification IP objects in the Questa SIM GUI, you must have
loaded the design containing the library protocols. For information on how to hook up the
protocols to your design, refer to the “Questa Verification IP Library Data Book” available from
SupportNet at http://supportnet.mentor.com.
Procedure
1. Ensure the model containing the Questa Verification IP protocol is loaded. For example:
vsim top
2. With the List window open (View > List), select the top level SystemVerilog interface
in the Questa Verification IP.
Results
The objects in that interface appear in the List window, similar to those in Figure 12-8.
Figure 12-8. Questa Verification IP Objects in List Window
When transactions are present in the list window, rows are written any time a transaction’s state
changes:
• when a transaction starts or ends
• when any attribute changes state
In Figure 12-8 above, there is an internal attribute (not shown) changing state and causing extra
rows to be drawn.
Questa Verification IP arrays display the value of every element.
Related Topics
Viewing Questa Verification IP Transactions in the Wave Window
This simple way of viewing relationships between the different transaction abstraction levels
and the signals allows very rapid movement between levels of abstraction when debugging. For
example, on an interface that allows multiple outstanding requests, you could select the data
signal at a certain point in time, and immediately see the transaction that the data is part of. This
provides you with information such as the address, requesting master, burst type, and so forth,
without needing to carefully trace back along the signals.
Note
IMPORTANT — For the highlighting of Transaction/Wire relationships to function
properly, all Questa Verification IP transactions in the protocol hierarchy (from the top level
transactions down to the stripes) must be logged to WLF (as described in the section Viewing
Questa Verification IP Transactions in the Wave Window).
Transaction viewing and navigation for Questa Verification IP transactions are the same as for
any transaction in Questa SIM.
Related Topics
Viewing Transactions in the Wave Window
Selecting Transactions or Streams in the Wave Window
What the Colors Mean in the Wave Window
Objects
• GUI elements
o Main Pane — The main pane displays the Questa Verification IP instance content,
consisting of items and values displayed in two columns. The items are:
• Type — The type of Questa Verification IP transaction instance.
• Name — The name of the transaction instance.
• TQ id— A serial number for instances on the same stream. (This is not the same
as the UID, which is a unique ID assigned by the Questa SIM simulator).
• Main State — Identifies how the transaction instance came into existence.
• Sub State — Identifies the phase of life the instance has reached.
Note
The “State History” for a transaction stream should only be enabled to assist in
the debug of QuestaSim 50000 series errors due to the additional consumption of
simulation resources when enabled.
Related Topics
Viewing Transactions in the Wave Window
Selecting Transactions or Streams in the Wave Window
The Transaction Stream Window
Objects
• GUI elements
o Main Pane — The main pane displays the Questa Verification IP transaction stream
content, consisting of items and values displayed in two columns. The items are:
• Name — The name of the transaction stream.
• Count — The number of transaction instances in the stream.
o Instances Tab — The lower pane contains a list of instances, and their parameter
values that have occurred for the transaction stream. The parameter values displayed
for the transaction stream are:
• Start Time - Start time of the transaction instance.
• End Time - End time of the transaction instance.
• Tag - The name of the transaction stream instance.
• TQ_id - A serial number for instances on the same stream. (This is not the same
as the UID, which is a unique ID assigned by the ModelSim simulator).
• Main State - Identifies how the transaction instance came into existence.
• Sub State - Identifies the phase of life the instance has reached.
• Trace_state - The greatest severity trace message reported for the instance from
“none”, “continue”, note”, “warning”, “error” and “halt”.
• Trace_num - QuestaSim 60000 series error message number reported for a
Questa Verification IP protocol. For more information, see “Accessing 60000
Series Error Documentation”.
• Attribute data for all the transaction instances from the stream. You can save this
attribute data to a file named <stream_name>.csv by selecting File > Save.
Related Topics
Viewing Transactions in the Wave Window
Related Topics
Viewing Transactions in the Wave Window
Selecting Transactions or Streams in the Wave Window
Questa Verification IP Objects in the GUI
This chapter describes how to save the results of a Questa SIM simulation and use them in your
simulation flow. In general, any recorded simulation data that has been loaded into Questa SIM
is called a dataset.
One common example of a dataset is a wave log format (WLF) file. In particular, you can save
any Questa SIM simulation to a wave log format (WLF) file for future viewing or comparison to
a current simulation. You can also view a wave log format file during the currently running
simulation.
A WLF file is a recording of a simulation run that is written as an archive file in binary format
and used to drive the debug windows at a later time. The files contain data from logged objects
(such as signals and variables) and the design hierarchy in which the logged objects are found.
You can record the entire design or choose specific objects.
A WLF file provides you with precise in-simulation and post-simulation debugging capability.
You can reload any number of WLF files for viewing or comparing to the active simulation.
You can also create virtual signals that are simple logical combinations or functions of signals
from different datasets. Each dataset has a logical name to indicate the dataset to which a
command applies. This logical name is displayed as a prefix. The current, active simulation is
prefixed by “sim:” WLF datasets are prefixed by the name of the WLF file by default.
Figure 13-1 shows two datasets in the Wave window. The current simulation is shown in the top
pane along the left side and is indicated by the “sim” prefix. A dataset from a previous
simulation is shown in the bottom pane and is indicated by the “gold” prefix.
The simulator resolution (see Simulator Resolution Limit (Verilog) or Simulator Resolution
Limit for VHDL) must be the same for all datasets you are comparing, including the current
simulation. If you have a WLF file that is in a different resolution, you can use the wlfman
command to change it.
If you then run a new simulation in the same directory, the vsim.wlf file is overwritten with the
new results.
If you want to save the WLF file and not have it be overwritten, select the Structure tab and then
select File > Save. Or, you can use the -wlf <filename> argument to the vsim command or the
dataset save command.
Also, datasets can be saved at intervals, each with unique filenames, with the dataset snapshot
command. See “Saving at Intervals with Dataset Snapshot” for GUI instructions.
Note
If you do not use either the dataset save or dataset snapshot command, you must end a
simulation session with a quit or quit -sim command in order to produce a valid WLF file.
If you do not end the simulation in this manner, the WLF file will not close properly, and Questa
SIM may issue the error message “bad magic number” when you try to open an incomplete
dataset in subsequent sessions. If you end up with a damaged WLF file, you can try to repair it
using the wlfrecover command.
3. Select Tools > Dataset Snapshot to open the Dataset Snapshot dialog box
(Figure 13-2).
4. Select Enabled for the Dataset Snapshot State.
5. Set the simulation time or the wlf file size.
6. Choose whether the snapshot will contain only data since previous snapshot or all
previous data.
7. Designate the snapshot directory and file.
8. Choose whether to replace the existing snapshot file or use an incrementing suffix if a
file by the same name exists.
9. Click the OK button to create the dataset snapshot.
Figure 13-2. Dataset Snapshot Dialog Box
You can customize the datasets either to contain all previous data, or only the data since
the previous snapshot. You can also set the dataset to overwrite previous snapshot files,
or increment the names of the files with a suffix.
2. It you want to use wildcards, then you will need to remove memories from the
WildcardFilter list. To see what is currently in the WildcardFilter list, use the following
command:
set WildcardFilter
If “Memories” is in the list, reissue the set WildcardFilter command with all items in the
list except “Memories.” For details, see Using the WildcardFilter Preference Variable.
Note
For post-process debug, you can add the memories into the Wave or List windows
but the Memory List window is not available.
• WLF Cache Size— Specify the size in megabytes of the WLF reader cache. WLF reader
cache size is zero by default. This feature caches blocks of the WLF file to reduce
redundant file I/O. If the cache is made smaller or disabled, least recently used data will
be freed to reduce the cache to the specified size.
• WLF Collapse Mode—WLF event collapsing has three settings: disabled, delta, time:
o When disabled, all events and event order are preserved.
o Delta mode records an object's value at the end of a simulation delta (iteration) only.
Default.
o Time mode records an object's value at the end of a simulation time step only.
• WLF Compression— Compress the data in the WLF file.
• WLF Delete on Quit— Delete the WLF file automatically when the simulation exits.
Valid for current simulation dataset (vsim.wlf) only.
• WLF File Lock — Control overwrite permission for the WLF file.
• WLF Filename— Specify the name of the WLF file.
• WLF Indexing— Write additional data to the WLF file to enable fast seeking to specific
times. Indexing makes viewing wave data faster, however performance during
optimization will be slower because indexing and optimization require significant
memory and CPU resources. Disabling indexing makes viewing wave data slow unless
the display is near the start of the WLF file. Disabling indexing also disables
optimization of the WLF file but may provide a significant performance boost when
archiving WLF files. Indexing and optimization information can be added back to the
file using wlfman optimize. Defaults to on.
• WLF Optimization— Write additional data to the WLF file to improve draw
performance at large zoom ranges. Optimization results in approximately 15% larger
WLF files.
• WLFSimCacheSize— Specify the size in megabytes of the WLF reader cache for the
current simulation dataset only. This makes it easier to set different sizes for the WLF
reader cache used during simulation and those used during post-simulation debug. If
WLFSimCacheSize is not specified, the WLFCacheSize settings will be used.
• WLF Size Limit— Limit the size of a WLF file to <n> megabytes by truncating from
the front of the file as necessary.
• WLF Time Limit — Limit the size of a WLF file to <t> time by truncating from the
front of the file as necessary.
A WLF file contains event, header, and symbol portions. The size restriction is placed on the
event portion only. When Questa SIM exits, the entire header and symbol portion of the WLF
file is written. Consequently, the resulting file will be larger than the size specified with -
wlfslim. If used in conjunction with -wlftlim, the more restrictive of the limits takes precedence.
The WLF file can be limited by time with the WLFTimeLimit simulation control variable in the
modelsim.ini file or with the -wlftlim switch for the vsim command. Either method specifies the
duration of simulation time for WLF file recording. The duration specified should be an integer
of simulation time at the current resolution; however, you can specify a different resolution if
you place curly braces around the specification. For example,
sets the duration at 5000 nanoseconds regardless of the current simulator resolution.
The time range begins at the current simulation time and moves back in simulation time for the
specified duration. In the example above, the last 5000ns of the current simulation is written to
the WLF file.
If used in conjunction with -wlfslim, the more restrictive of the limits will take effect.
The -wlfslim and -wlftlim switches were designed to help users limit WLF file sizes for long or
heavily logged simulations. When small values are used for these switches, the values may be
overridden by the internal granularity limits of the WLF file format. The WLF file saves data in
a record-like format. The start of the record (checkpoint) contains the values and is followed by
transition data. This continues until the next checkpoint is written. When the WLF file is limited
with the -wlfslim and -wlftlim switches, only whole records are truncated. So if, for example,
you are were logging only a couple of signals and the amount of data is so small there is only
one record in the WLF file, the record cannot be truncated; and the data for the entire run is
saved in the WLF file.
You can disable this functionality with the vsim -nowlfopt switch, which you may want to do if
you are performing several simulations with logging at the same time.You can also control this
behavior with the WLFUseThreads variable in the modelsim.ini file.
Opening Datasets
Questa SIM allows you to open existing datasets.
Procedure
To open a dataset, do one of the following:
• Select File > Open to open the Open File dialog box and set the “Files of type” field
to Log Files (*.wlf). Then select the .wlf file you want and click the Open button.
• Select File > Datasets to open the Dataset Browser; then click the Open button to
open the Open Dataset dialog box (Figure 13-3).
• Use the dataset open command to open either a saved dataset or to view a running
simulation dataset: vsim.wlf. Running simulation datasets are automatically updated.
The Open Dataset dialog box includes the following options:
o Dataset Pathname — Identifies the path and filename of the WLF file you want
to open.
o Logical Name for Dataset — This is the name by which the dataset will be
referred. By default this is the name of the WLF file.
Dataset Structure
Each dataset you open creates a structure tab in the Main window. The tab is labeled with the
name of the dataset and displays a hierarchy of the design units in that dataset.
The graphic below shows three structure tabs: one for the active simulation (sim) and one each
for two datasets (test and gold).
If you have too many tabs to display in the available space, you can scroll the tabs left or right
by clicking the arrow icons at the bottom right-hand corner of the window.
You can hide or show columns by right-clicking a column name and selecting the name on the
list.
2. From the Dataset Browser you can open a selected dataset, save it, reload it, close it,
make it the active dataset, or rename it.
Procedure
1. You can specify a different dataset name as an optional qualifier to the vsim -view
switch on the command line using the following syntax:
-view <dataset>=<filename>
For example:
vsim -view foo=vsim.wlf
Questa SIM designates one of the datasets to be the active dataset, and refers all names
without dataset prefixes to that dataset. The active dataset is displayed in the context
path at the bottom of the Main window. When you select a design unit in a dataset’s
Structure window, that dataset becomes active automatically. Alternatively, you can use
the Dataset Browser or the environment command to change the active dataset.
2. Design regions and signal names can be fully specified over multiple WLF files by using
the dataset name as a prefix in the path. For example:
sim:/top/alu/out
view:/top/alu/out
golden:.top.alu.out
Dataset prefixes are not required unless more than one dataset is open, and you want to
refer to something outside the active dataset. When more than one dataset is open,
Questa SIM will automatically prefix names in the Wave and List windows with the
dataset name. You can change this default by selecting:
• List Window active: List > List Preferences; Window Properties tab > Dataset Prefix
pane
• Wave Window active: Wave > Wave Preferences; Display tab > Dataset Prefix
Display pane
3. Questa SIM also remembers a “current context” within each open dataset. You can
toggle between the current context of each dataset using the environment command,
specifying the dataset without a path. For example:
env foo:
sets the active dataset to foo and the current context to the context last specified for foo.
The context is then applied to any unlocked windows.
The current context of the current dataset (usually referred to as just “current context”) is
used for finding objects specified without a path.
4. You can lock the Objects window to a specific context of a dataset. Being locked to a
dataset means that the pane updates only when the content of that dataset changes. If
locked to both a dataset and a context (such as test: /top/foo), the pane will update only
when that specific context changes. You specify the dataset to which the pane is locked
by selecting File > Environment.
Table 13-3. vsim Arguments for Collapsing Time and Delta Steps
vsim argument effect modelsim.ini setting
-nowlfcollapse All events for each logged signal are WLFCollapseMode = 0
recorded to the WLF file in the exact order
they occur in the simulation.
Table 13-3. vsim Arguments for Collapsing Time and Delta Steps (cont.)
vsim argument effect modelsim.ini setting
-wlfcollapsedelta Each logged signal which has events during WLFCollapseMode = 1
a simulation delta has its final value recorded
to the WLF file when the delta has expired.
Default.
-wlfcollapsetime Same as delta collapsing but at the timestep WLFCollapseMode = 2
granularity.
When a run completes that includes single stepping or hitting a breakpoint, all events are
flushed to the WLF file regardless of the time collapse mode. It’s possible that single stepping
through part of a simulation may yield a slightly different WLF file than just running over that
piece of code. If particular detail is required in debugging, you should disable time collapsing.
Virtual Objects
Virtual objects are signal-like or region-like objects created in the GUI that do not exist in the
Questa SIM simulation kernel.
Virtual objects are indicated by an orange diamond as illustrated by Bus1 in Figure 13-6:
Virtual Signals
Virtual signals are aliases for combinations or subelements of signals written to the WLF file by
the simulation kernel. They can be displayed in the Objects, List, Watch, and Wave windows,
accessed by the examine command, and set using the force command.
You can create virtual signals using the Wave or List > Combine Signals menu selections or
by using the virtual signal command. Once created, virtual signals can be dragged and dropped
from the Objects pane to the Wave, Watch, and List windows. In addition, you can create virtual
signals for the Wave window using the Virtual Signal Builder (refer to Using the Virtual Signal
Builder).
Virtual signals are automatically attached to the design region in the hierarchy that corresponds
to the nearest common ancestor of all the elements of the virtual signal. The virtual signal
command has an -install <region> option to specify where the virtual signal should be installed.
This can be used to install the virtual signal in a user-defined region in order to reconstruct the
A virtual signal can be used to reconstruct RTL-level design buses that were broken down
during synthesis. The virtual hide command can be used to hide the display of the broken-down
bits if you don't want them cluttering up the Objects window.
If the virtual signal has elements from more than one WLF file, it will be automatically installed
in the virtual region virtuals:/Signals.
Virtual signals are not hierarchical – if two virtual signals are concatenated to become a third
virtual signal, the resulting virtual signal will be a concatenation of all the scalar elements of the
first two virtual signals.
The definitions of virtuals can be saved to a DO file using the virtual save command. By default,
when quitting, Questa SIM will append any newly-created virtuals (that have not been saved) to
the virtuals.do file in the local directory.
If you have virtual signals displayed in the Wave or List window when you save the Wave or
List format, you will need to execute the virtuals.do file (or some other equivalent) to restore the
virtual signal definitions before you re-load the Wave or List format during a later run. There is
one exception: “implicit virtuals” are automatically saved with the Wave or List format.
Virtual Functions
Virtual functions behave in the GUI like signals but are not aliases of combinations or elements
of signals logged by the kernel. They consist of logical operations on logged signals and can be
dependent on simulation time.
Virtual functions can be displayed in the Objects, Wave, and List windows and accessed by the
examine command, but cannot be set by the force command.
The result type of a virtual function can be any of the types supported in the GUI expression
syntax: integer, real, boolean, std_logic, std_logic_vector, and arrays and records of these types.
Verilog types are converted to VHDL 9-state std_logic equivalents and Verilog net strengths are
ignored.
Virtual functions are also implicitly created by Questa SIM when referencing bit-selects or part-
selects of Verilog registers in the GUI, or when expanding Verilog registers in the Objects,
Wave, or List window. This is necessary because referencing Verilog register elements requires
an intermediate step of shifting and masking of the Verilog “vreg” data structure.
Virtual Regions
User-defined design hierarchy regions can be defined and attached to any existing design region
or to the virtuals context tree. They can be used to reconstruct the RTL hierarchy in a gate-level
design and to locate virtual signals. Thus, virtual signals and virtual regions can be used in a
gate-level design to allow you to use the RTL test bench.
To create and attach a virtual region, use the virtual region command.
Virtual Types
User-defined enumerated types can be defined in order to display signal bit sequences as
meaningful alphanumeric names. The virtual type is then used in a type conversion expression
to convert a signal to values of the new type. When the converted signal is displayed in any of
the windows, the value will be displayed as the enumeration string corresponding to the value of
the original signal.
To create a virtual type, use the virtual type command.
The Wave window is the most commonly used tool for analyzing and debugging your design
after simulation. It displays all signals in your design as waveforms and signal values and
provides a suite of graphical tools for debugging.
Wave Window Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Objects You Can View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Adding Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Inserting Signals in a Specific Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Working with Cursors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Adding Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Editing Cursor Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Jump to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Syncing All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Linking Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Shortcuts for Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Two Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Expanded Time in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Expanded Time Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Recording Expanded Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Viewing Expanded Time Information in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . 720
Customizing the Expanded Time Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . 723
Expanded Time Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Switching Between Time Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Expanding and Collapsing Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Expanded Time with examine and Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Zooming the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Zooming with the Menu, Toolbar and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Saving Zoom Range and Scroll Position with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . . 729
Editing Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Searching in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Searching for Values or Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Search with the Expression Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Filtering the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Formatting the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Setting Wave Window Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
For more information about the graphic features of the Wave window, see the Wave Window
section of the GUI Reference Manual.
• insert — (default) Places new object(s) above the Insertion Pointer Bar.
• append — Places new object(s) below the Insertion Pointer Bar.
• top — Places new object(s) at the top of the Wave window.
• end — Places new object(s) at the bottom of the Wave window.
Prerequisites
There must be at least one signal in the Wave window.
Procedure
1. Click on the vertical white bar on the left-hand side of the active Wave window to select
where signals should be added. (Figure 14-2)
2. Your cursor will change to a double-tail arrow and a green bar will appear. Clicking in
the vertical white bar next to a signal places the Insertion Point Bar below the indicated
signal. Alternatively, you can Ctrl+click in the white bar to place the Insertion Point Bar
below the indicated signal.
Figure 14-2. Insertion Point Bar
3. Select an instance in the Structure (sim) window or an object in the Objects window.
4. Use the hot key Ctrl+w to add all signals of the instance or the specific object to the
Wave window in the location of the Insertion Point Bar.
Related Topics
Insertion Point Bar and Pathname Pane.
Table 14-2 summarizes common cursor actions you can perform with the icons in the toolbox,
or with menu selections.
The Toggle leaf names <-> full names icon allows you to switch from displaying full
pathnames (the default) to displaying leaf or short names in the Pathnames Pane. You can also
control the number of path elements in the Wave Window Preferences dialog. Refer to Hiding/
Showing Path Hierarchy.
The Edit grid and timeline properties icon opens the Wave Window Properties dialog box to
the Grid & Timeline tab (Figure 14-3).
• The Grid Configuration selections allow you to set grid offset, minimum grid spacing,
and grid period. You can also reset these grid configuration settings to their default
values.
• The Timeline Configuration selections give you change the time scale. You can display
simulation time on a timeline or a clock cycle count. If you select Display simulation
time in timeline area, use the Time Units dropdown list to select one of the following as
the timeline unit:
fs, ps, ns, us, ms, sec, min, hr
Note
The time unit displayed in the Wave window (default: ns) does not reflect the
simulation time that is currently defined.
The current configuration is saved with the wave format file so you can restore it later.
• The Show frequency in cursor delta box causes the timeline to display the difference
(delta) between adjacent cursors as frequency. By default, the timeline displays the delta
between adjacent cursors as time.
Adding Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Editing Cursor Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Jump to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Syncing All Active Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Linking Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Shortcuts for Working with Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Two Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Adding Cursors
To add cursors when the Wave window is active you can do one of the following.
Procedure
1. Click the Insert Cursor icon.
2. Choose Add > To Wave > Cursor from the menu bar.
3. Press the “A” key while the mouse pointer is located in the cursor pane.
4. Right click in the cursor pane and select New Cursor @ <time> ns to place a new
cursor at a specific time.
2. From the Cursor Properties dialog box, alter any of the following properties:
• Cursor Name — the name that appears in the Wave window.
• Cursor Time — the time location of the cursor.
• Cursor Color — the color of the cursor.
• Locked Cursor Color — the color of the cursor when it is locked to a specific time
location.
• Lock cursor to specified time — disables relocation of the cursor.
Related Topics
Debug Toolbar Tab.
The Now cursor is always locked to the current simulation time and it is not manifested as a
graphical object (vertical cursor bar) in the Wave window.
Cursor 1 is located at time zero. Clicking anywhere in the waveform display moves the Cursor
1 vertical cursor bar to the mouse location and makes this cursor the selected cursor. The
selected cursor is drawn as a bold solid line; all other cursors are drawn with thin lines.
2. When all active cursors are synced, moving a cursor in one window will automatically
move the active cursors in all opened Wave windows to the same time location. This
option is also available by selecting Wave > Cursors > Sync All Active Cursors in the
menu bar when a Wave window is active.
Linking Cursors
Cursors within the Wave window can be linked together, allowing you to move two or more
cursors together across the simulation timeline. You simply click one of the linked cursors and
drag it left or right on the timeline. The other linked cursors will move by the same amount of
time.
Procedure
1. You can link all displayed cursors by right-clicking the time value of any cursor in the
timeline, as shown in Figure 14-6, and selecting Cursor Linking > Link All.
2. You can link and unlink selected cursors by selecting the time value of any cursor and
selecting Cursor Linking > Configure to open the Configure Cursor Links dialog
(Figure 14-7).
Figure 14-7. Configure Cursor Links Dialog
Select Tools > Window Preferences when the Wave window is a stand-alone, undocked
window.
• You can position a cursor without snapping by dragging a cursor in the cursor pane
below the waveforms.
You can return to standard Wave Window behavior by selecting Wave > Mouse Mode > and
choosing one of the other menu picks or by selecting a different button in the Debug Toolbar
Tab.
The zoom amount is displayed at the mouse cursor. A zoom operation must be more than 10
pixels to activate.
To zoom with the scroll-wheel of your mouse, hold down the Ctrl key at the same time to scroll
in and out. The waveform pane will zoom in and out, centering on your mouse cursor.
The expanded time function makes these intermediate values visible in the Wave window.
Expanded time shows the actual order in which objects change values and shows all transitions
of each object within a given time step.
change at any one event time. Object values and the exact order which they change can
be saved in the .wlf file.
• Expanded Time — the Wave window feature that expands single simulation time steps
to make them wider, allowing you to see object values at the end of each delta cycle or at
each event time within the simulation time.
• Expand — causes the normal simulation time view in the Wave window to show
additional detailed information about when events occurred during a simulation.
• Collapse — hides the additional detailed information in the Wave window about when
events occurred during a simulation.
You can choose not to record event time or delta time information to the .wlf file by using the
-wlfcollapsetime argument with vsim, or by setting WLFCollapseMode to 2. This will prevent
detailed debugging but may reduce the size of the .wlf file and speed up the simulation.
Figure 14-8. Waveform Pane with Collapsed Event and Delta Time
Figure 14-9 shows the Waveform pane and the timescale from the Cursors pane after expanding
simulation time at time 3ns. The background color is blue for expanded sections in Delta Time
mode and green for expanded sections in Event Time mode.
In Delta Time mode, more than one object may have an event at the same delta time step. The
labels on the time axis in the expanded section indicate the delta time steps within the given
simulation time.
In Event Time mode, only one object may have an event at a given event time. The exception to
this is for objects that are treated atomically in the simulator and logged atomically.
The individual bits of a SystemC vector, for example, could change at the same event time.
Labels on the time axis in the expanded section indicate the order of events from all of the
objects added to the Wave window. If an object that had an event at a particular time but it is not
in the viewable area of the Waveform panes, then there will appear to be no events at that time.
Depending on which objects have been added to the Wave window, a specific event may
happen at a different event time. For example, if s3 shown in Figure 14-9, had not been added to
the Wave window, the result would be as shown in Figure 14-10.
Now the first event on s2 occurs at event time 3ns + 2 instead of event time 3ns + 3. If s3 had
been added to the Wave window (whether shown in the viewable part of the window or not) but
was not visible, the event on s2 would still be at 3ns + 3, with no event visible at 3ns + 2.
Figure 14-11 shows an example of expanded time over the range from 3ns to 5ns. The expanded
time range displays delta times as indicated by the blue background color. (If Event Time mode
is selected, a green background is displayed.)
Figure 14-11. Waveform Pane with Expanded Time Over a Time Range
When scrolling horizontally, expanded sections remain expanded until you collapse them, even
when scrolled out of the visible area. The left or right edges of the Waveform pane are viewed
in either expanded or collapsed sections.
Expanded event order or delta time sections appear in all panes when multiple Waveform panes
exist for a Wave window. When multiple Wave windows are used, sections of expanded event
or delta time are specific to the Wave window where they were created.
For expanded event order time sections when multiple datasets are loaded, the event order time
of an event will indicate the order of that event relative to all other events for objects added to
that Wave window for that object’s dataset only. That means, for example, that signal sim:s1
and gold:s2 could both have events at time 1ns+3.
Note
The order of events for a given design will differ for optimized versus unoptimized
simulations, and between different versions of Questa SIM. The order of events will be
consistent between the Wave window and the List window for a given simulation of a particular
design, but the event numbering may differ. See Expanded Time Viewing in the List Window.
You may display any number of disjoint expanded times or expanded ranges of times.
Related Topics
Debug Toolbar Tab.
Procedure
1. Select Tools > Edit Preferences from the menus. This opens the Preferences dialog.
2. Select the By Name tab.
3. Scroll down to the Wave selection and click the plus sign (+) for Wave.
4. Change the values of the Wave Window variables waveDeltaBackground and
waveEventBackground.
Select Delta Time Mode or Event Time Mode from the appropriate menu according to
Table 14-6 to have expanded simulation time in the Wave window show delta time steps or
event time steps respectively. Select Expanded Time Off for standard behavior (which is the
default).
modes from the menu bar or command line also results in the appropriate resetting of these three
buttons. The "Expanded Time Off" button is selected by default.
In addition, there are four buttons in the Debug Toolbar Tab for expanding and collapsing
simulation time.
• The “Expand All Time” button expands simulation time over the entire simulation time
range, from time 0 to the current simulation time.
• The “Expand Time At Active Cursor” button expands simulation time at the simulation
time of the active cursor.
• The “Collapse All Time” button collapses simulation time over entire simulation time
range.
• The “Collapse Time At Active Cursor” button collapses simulation time at the
simulation time of the active cursor.
Related Topics
Debug Toolbar Tab.
Use the wave expand mode command to select which mode is used to display expanded time in
the wave window. This command also results in the appropriate resetting of the three toolbar
buttons.
Procedure
Use the following procedure:
• seetime — The -event <event> option to the seetime command behaves in the same
manner as the -delta <delta> option.
Zoom Mode
change mouse pointer to zoom mode; see below
Zoom Out 2x
zoom out by a factor of two from current view
Zoom Full
zoom out to view the full range of the simulation from time
0 to the current time
To zoom with the mouse, first enter zoom mode by selecting View > Zoom > Mouse Mode >
Zoom Mode. The left mouse button then offers 3 zoom options by clicking and dragging in
different directions:
• The zoom amount is displayed at the mouse cursor. A zoom operation must be more
than 10 pixels to activate.
• You can enter zoom mode temporarily by holding the <Ctrl> key down while in select
mode.
• With the mouse in the Select Mode, the middle mouse button will perform the above
zoom operations.
To zoom with the scroll-wheel of your mouse, hold down the Ctrl key at the same time to scroll
in and out. The waveform pane will zoom in and out, centering on your mouse cursor.
Procedure
1. Zoom the Wave window as you see fit using one of the techniques discussed in Zooming
the Wave Window Display.
2. If the Wave window is docked, select Add > to Wave > Bookmark. If the Wave
window is undocked, select Add > Bookmark.
Editing Bookmarks
Once a bookmark exists, you can change its properties by selecting Wave > Bookmarks >
Bookmarks if the Wave window is docked; or by selecting Tools > Bookmarks if the Wave
window is undocked.
One option of note is Search for Expression. The expression can involve more than one signal
but is limited to signals currently in the window. Expressions can include constants, variables,
and DO files. Refer to Expression Syntax for more information.
Any search terms or settings you enter are saved from one search to the next in the current
simulation. To clear the search settings during debugging click the Reset To Initial Settings
button. The search terms and settings are cleared when you close Questa SIM.
Note
If your signal values are displayed in binary radix, refer to Searching for Binary Signal
Values in the GUI for details on how signal values are mapped between a binary radix and
std_logic.
4. You click the buttons in the Expression Builder dialog box to create a GUI expression.
Each button generates a corresponding element of Expression Syntax and is displayed in
the Expression field.
5. In addition, you can use the Selected Signal button to create an expression from signals
you select from the associated Wave window. For example, instead of typing in a signal
name, you can select signals in a Wave window and then click Selected Signal in the
Expression Builder. This displays the Select Signal for Expression dialog box shown in
Figure 14-15.
Figure 14-15. Selecting Signals for Expression Builder
6. Note that the buttons in this dialog box allow you to determine the display of signals you
want to put into an expression:
• List only Select Signals — list only those signals that are currently selected in the
parent window.
• List All Signals — list all signals currently available in the parent window.
7. Once you have selected the signals you want displayed in the Expression Builder, click
OK.
8. Other buttons will add operators of various kinds (see Expression Syntax), or you can
type them in.
Related Topics
GUI_expression_format.
• Put $foo in the Expression: entry box for the Search for Expression selection.
• Issue a searchlog command using foo:
searchlog -expr $foo 0
Procedure
1. Select the clock signal in the Wave window.
2. Choose Wave > Signal Search from the main menu to open the Wave Signal Search
dialog box.
3. Select Search for Expression radio button.
4. Click the Builder button to open the Expression Builder.
5. Click the Selected Signal button to open the Select Signal for Expression dialog box.
6. Click the List All Signals radio button.
7. Highlight the desired signal you want to search and click the OK button. This closes the
Select Signal for Expression dialog box and places the selected signal in the
Expression field of the Expression Builder.
8. Click 'rising. You can also select the falling edge or both edges. Or, click the &&
button to AND this condition with the rest of the expression.
9. Click the Search Forward or the Search Reverse button to perform the search.
Figure 14-16. Display Tab of the Wave Window Preferences Dialog Box
Zero specifies the full path, 1 specifies the leaf name, and any other positive number specifies
the number of path elements to be displayed (Figure 14-16).
Procedure
1. If the Wave window is docked, open the Wave Window Preferences dialog by
selecting Wave > Wave Preferences from the Main window menus.
If the Wave window is undocked, select Tools > Window Preferences from the Wave
window menus. This opens the Wave Window Preferences dialog box.
2. In the dialog, select the Grid & Timeline tab.
3. Enter the period of your clock in the Grid Period field and select “Display grid period
count (cycle count)” (Figure 14-17).
Figure 14-17. Grid and Timeline Tab of Wave Window Preferences Dialog Box
Results
The timeline will now show the number of clock cycles, as shown in Figure 14-18.
Or, you can right-click the selected object(s) and select Format from the popup menu.
If you right-click the and selected object(s) and select Properties from the popup menu, you
can use the Format tab of the Wave Properties dialog to format selected objects (Figure 14-20).
The default radix is hexadecimal, which means the value pane lists the hexadecimal values of
the object. For the other radices - binary, octal, decimal, unsigned, hexadecimal, or ASCII - the
object value is converted to an appropriate representation in that radix.
Note
When the symbolic radix is chosen for SystemVerilog reg and integer types, the values are
treated as binary. When the symbolic radix is chosen for SystemVerilog bit and int types,
the values are considered to be decimal.
Aside from the Wave Properties dialog, there are three other ways to change the radix:
• Change the default radix for all objects in the current simulation using Simulate >
Runtime Options (Main window menu).
• Change the default radix for the current simulation using the radix command.
• Change the default radix permanently by editing the DefaultRadix variable in the
modelsim.ini file.
Setting the Global Signal Radix for Selected Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Sfixed and Ufixed indicate “signed fixed” and “unsigned fixed,” respectively. To
display an object as Sfixed or Ufixed the object must be an array of std_ulogic elements
between 2 and 64 bits long with a descending range. The binary point for the value is
implicitly located between the 0th and -1st elements of the array. The index range for the
type need not include 0 or -1, for example (-4 downto -8) in which case the value will be
extended for conversion, as appropriate. If the type does not meet these criteria the value
will be displayed as decimal or unsigned, respectively.
Procedure
1. Select the signal above which you want to place the divider.
2. If the Wave pane is docked, select Add > To Wave > Divider from the Main window
menu bar. If the Wave window stands alone, undocked from the Main window, select
Add > Divider from the Wave window menu bar.
3. Specify the divider name in the Wave Divider Properties dialog. The default name is
New Divider. Unnamed dividers are permitted. Simply delete "New Divider" in the
Divider Name field to create an unnamed divider.
4. Specify the divider height (default height is 17 pixels) and then click OK.
5. You can also insert dividers with the -divider argument to the add wave command.
Related Topics
Recording Simulation Results With Datasets
Wave Groups
You can create a wave group to collect arbitrary groups of items in the Wave window. Wave
groups have the following characteristics:
• A wave group may contain 0, 1, or many items.
• You can add or remove items from groups either by using a command or by dragging
and dropping.
• You can drag a group around the Wave window or to another Wave window.
• You can nest multiple wave groups, either from the command line or by dragging and
dropping. Nested groups are saved or restored from a wave.do format file, restart and
checkpoint/restore.
• You can create a group that contains the input signals to the process that drives a
specified signal.
Creating a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Deleting or Ungrouping a Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Adding Items to an Existing Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Removing Items from an Existing Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Miscellaneous Wave Group Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Results
A group with the name Contributors:<signal_name> is placed below the selected signal in the
Wave window pathnames pane (Figure 14-26).
Results
The selected signals become a group with a name that references the dataset and common
region, for example: sim:/top/p.
If you use Ctrl-g to group any other signals, they will be placed into any existing group for their
region, rather than creating a new group of only those signals.
If a wave group is selected and the Wave > Ungroup menu item is selected the group will be
removed and all of its contents will remain in the Wave window in existing order.
2. Use menu or icon selections to cut or delete an item or items from the group.
3. Use the delete wave command to specify a signal to be removed from the group.
Note
The delete wave command removes all occurrences of a specified name from the
Wave window, not just an occurrence within a group.
4. To use the format file, start with a blank Wave window and run the DO file in one of two
ways:
• Invoke the do command from the command line:
VSIM> do <my_format_file>
Note
Window format files are design-specific. Use them only with the design you
were simulating when they were created.
5. In addition, you can use the write format restart command to create a single .do file that
will recreate all debug windows and breakpoints (see Saving and Restoring Breakpoints)
when invoked with the do command in subsequent simulation runs. The syntax is:
write format restart <filename>
6. If the ShutdownFile modelsim.ini variable is set to this .do filename, it will call the write
format restart command upon exit.
3. Move Cursor 2 to the other end of the portion of time you want to save. Cursor 2 is now
the active cursor, indicated by a bold yellow line and a highlighted name.
4. Right-click the time indicator of the inactive cursor (Cursor 1) to open a drop menu.
Figure 14-28. Waveform Save Between Cursors
5. Select Filter Waveform to open the Wave Filter dialog box. (Figure 14-29)
Figure 14-29. Wave Filter Dialog
6. Select Selected Signals in Wave Window to save the selected objects or signals. You
can also choose to save all waveforms displayed in the Wave window between the
specified start and end time or all of the logged signals.
7. Enter a name for the file using the .wlf extension. Do not use vsim.wlf since it is the
default name for the simulation dataset and will be overwritten when you end your
simulation.
(Open the Class Instances window by selecting View > Class Browser > Class
Instances from the menus or use the view class instances command.)
2. Place the class objects in the Wave window once they exist by doing one of the
following:
• Drag a class instance from the Class Instances window or the Objects window and
drop it into the Wave window.
• Select multiple objects in the Class Instances window, click and hold the Add
Selected to Window button in the Standard toolbar, then select the position of the
placement; the top of the Wave window, the end of the Wave window, or above the
anchor location The group of class instances are arranged with the most recently
created instance at the top. You can change the order of the class instances to show
the first instance at the top of the window by selecting View > Sort > Ascending.
Figure 14-31. Adding Class Objects in the Wave Window
3. You can hover the mouse over any class waveform to display information about the
class variable (Figure 14-32).
Related Topics
Working with Class Path Expressions
Logging Class Types and Class Instances
Viewing Class Instances in the Wave Window
• Add a virtual interface to the List window with the add list command.
• Add a virtual interface to the Wave window with the add wave command. For example:
add wave /test2/virt
• Select two or more signals in the Wave window and then choose Tools > Combine
Signals from the menu bar. A virtual signal that is the result of a comparison simulation
is not supported for combining with any other signal.
• Use the virtual signal command at the Main window command prompt.
In the illustration below, four signals have been combined to form a new bus called "Bus1."
Note that the component signals are listed in the order in which they were selected in the Wave
window. Also note that the value of the bus is made up of the values of its component signals,
arranged in a specific order.
Procedure
1. In the Wave window, locate the bus and select the range of signals that you want to
extract.
2. Select Wave > Extract/Pad Slice (Hotkey: Ctrl+e) to display the Wave Extract/Pad Bus
Dialog Box.
Figure 14-35. Wave Extract/Pad Bus Dialog Box
By default, the dialog box is prepopulated with information based on your selection and
will create a new bus based on this information.
This dialog box also provides you options to pad the selected slice into a larger bus.
3. Click OK to create a group of the extracted signals based on your changes, if any, to the
dialog box.
The new bus, by default, is added to the bottom of the Wave window. Alternatively, you
can follow the directions in Inserting Signals in a Specific Location.
• Source — The name of the bus from which you selected the signals.
• Result Name — A generated name based on the source name and the selected signals.
You can change this to a different value.
• Slice Range — The range of selected signals.
• Padding — These options allow you to create signal padding around your extraction.
o Left Pad / Value — An integer that represents the number of signals you want to
pad to the left of your extracted signals, followed by the value of those signals.
o Right Pad / Value — An integer that represents the number of signals you want to
pad to the right of your extracted signals, followed by the value of those signals.
• Transcript Commands — During creation of the bus, the virtual signal command to
create the extraction is written to the Transcript window.
• The Name field allows you to enter the name of the new virtual signal or select an
existing virtual signal from the drop down list. Use alpha, numeric, and underscore
characters only, unless you are using VHDL extended identifier notation.
• The Editor field is a regular text box. You can enter text directly, copy and paste, or drag
a signal from the Objects, Locals, Source , or Wave window and drop it in the Editor
field.
• The Operators field allows you to select from a list of operators. Double-click an
operator to add it to the Editor field.
• The Help button provides information about the Name, Clear, and Add Text buttons,
and the Operators field (Figure 14-37).
Tip
Select the Help button then place your cursor in the Operator field to view syntax
usage for some of the available operators. Refer to Figure 14-36
4. Enter a string in the Name field. Use alpha, numeric, and underscore characters only,
unless you are using VHDL extended identifier notation.
5. Select the Test button to verify the expression syntax is parsed correctly.
6. Select Add to place the new virtual signal in the Wave window at the default insertion
point. Refer to Inserting Signals in a Specific Location for more information.
Figure 14-38. Creating a Virtual Signal.
Results
The virtual signal is added to the Wave window and the Objects window. An orange diamond
marks the location of the virtual signal in the wave window. (Figure 14-39)
Related Topics
Virtual Objects
Virtual Signals
GUI_expression_format. Se also the virtual signal
virtual function
Miscellaneous Tasks
The Wave window allows you to perform a wide variety of tasks, from examining waveform
values, to displaying signal drivers and readers, to sorting objects.
Examining Waveform Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Displaying Drivers of the Selected Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Sorting a Group of Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
• Rest your mouse pointer on a waveform. After a short delay, a dialog will pop-up that
displays the value for the time at which your mouse pointer is positioned. If you’d prefer
that this popup not display, it can be toggled off in the display properties. See Setting
Wave Window Display Preferences.
• Right-click a waveform and select Examine. A dialog displays the value for the time at
which you clicked your mouse.
• Select a waveform and click the Show Drivers button on the toolbar.
• Right-click a waveform and select Show Drivers from the shortcut menu
• Double-click a waveform edge (you can enable/disable this option in the display
properties dialog; see Setting Wave Window Display Preferences)
2. This operation opens the Dataflow or Schematic window and displays the drivers of the
signal selected in the Wave window. A Wave pane also opens in the Dataflow or
Schematic window to show the selected signal with a cursor at the selected time. The
Dataflow or Schematic window shows the signal(s) values at the Wave pane cursor
position.
Related Topics
Double-Click Behavior in the Wave Window
Breakpoints within SystemC portions of the design can only be set using File-Line Breakpoints.
Signal Breakpoints
Signal breakpoints (“when” conditions) instruct Questa SIM to perform actions when the
specified conditions are met. For example, you can break on a signal value or at a specific
simulator time. When a breakpoint is hit, a message in the Main window transcript identifies the
signal that caused the breakpoint.
Setting Signal Breakpoints with the when Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Setting Signal Breakpoints with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Modifying Signal Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Examples
The command:
adds 2 ms to the simulation time at which the “when” statement is first evaluated, then stops.
The white space between the value and time unit is required for the time unit to be understood
by the simulator.
Related Topics
when
Results
A breakpoint is set on that signal and will be listed in the Modify Breakpoints dialog accessible
by selecting Tools > Breakpoints from the Main menu bar.
3. When you select a signal breakpoint from the list and click the Modify button, the Signal
Breakpoint dialog (Figure 14-41) opens, allowing you to modify the breakpoint.
File-Line Breakpoints
File-line breakpoints are set on executable lines in your source files. When the line is hit, the
simulator stops and the Source window opens to show the line with the breakpoint. You can
change this behavior by editing the PrefSource(OpenOnBreak) variable.
Since C Debug is invoked when you set a breakpoint within a SystemC module, your C Debug
settings must be in place prior to setting a breakpoint. See Setting Up C Debug for more
information. Once invoked, C Debug can be exited using the C Debug menu.
Examples
The command
bp top.vhd 147
Related Topics
Simulator GUI Preferences
2. The breakpoints are toggles. Click the left mouse button on the red breakpoint marker to
disable the breakpoint. A disabled breakpoint will appear as a black ball. Click the
marker again to enable it.
3. Right-click the breakpoint marker to open a context menu that allows you to Enable/
Disable, Remove, or Edit the breakpoint. create the colored diamond; click again to
disable or enable the breakpoint.
Related Topics
Source Window
2. If the ShutdownFile modelsim.ini variable is set to this .do filename, it will call the write
format restart command upon exit.
Results
The file created is primarily a list of add list, or add wave, and configure commands, though a
few other commands are included. This file may be invoked with the do command to recreate
the window format on a subsequent simulation run.
Waveform Compare
The Questa SIM Waveform Compare feature allows you to compare simulation runs.
Differences encountered in the comparison are summarized and listed in the Main window
transcript and are shown in the Wave and List windows.
In addition, you can write a list of the differences to a file using the compare info command.
1. Run one simulation and save the dataset. For more information on saving datasets, see
Saving a Simulation to a WLF File.
2. Run a second simulation.
3. Setup and run a comparison.
4. Analyze the differences in the Wave or List window.
Mixed-Language Waveform Compare Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Three Options for Setting up a Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Setting Up a Comparison with the GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Starting a Waveform Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Adding Signals, Regions, and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Specifying the Comparison Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Setting Compare Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Viewing Differences in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Viewing Differences in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Viewing Differences in Textual Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Saving and Reloading Comparison Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Comparing Hierarchical and Flattened Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
The graphic below shows the first dialog in the Wizard. As you can see from this
example, the dialogs include instructions on the left-hand side.
Figure 14-44. Waveform Comparison Wizard
Comparison Commands
There are numerous commands that give you complete control over a comparison. These
commands can be entered in the Transcript window or run via a DO file. The commands are
detailed in the Reference Manual, but the following example shows the basic sequence:
compare start gold vsim
compare add /*
compare run
This example command sequence assumes that the gold.wlf reference dataset is loaded with the
current simulation, the vsim.wlf dataset. The compare start command instructs Questa SIM to
compare the reference gold.wlf dataset against the current simulation. The compare add /*
command instructs Questa SIM to compare all signals in the gold.wlf reference dataset against
all signals in the vsim.wlf dataset. The compare run command runs the comparison.
Procedure
1. Initiate the comparison by specifying the reference and test datasets. See Starting a
Waveform Comparison for details.
2. Add objects to the comparison. See Adding Signals, Regions, and Clocks for details.
3. Specify the comparison method. See Specifying the Comparison Method for details.
4. Configure comparison options. See Setting Compare Options for details.
5. Run the comparison by selecting Tools > Waveform Compare > Run Comparison.
6. View the results.
Related Topics
Viewing Differences in the Wave Window
Viewing Differences in the List Window
Viewing Differences in Textual Format
Reference Dataset
The Reference Dataset is the .wlf file to which the test dataset will be compared. It can be a
saved dataset, the current simulation dataset, or any part of the current simulation dataset.
Test Dataset
The Test Dataset is the .wlf file that will be compared against the Reference Dataset. Like the
Reference Dataset, it can be a saved dataset, the current simulation dataset, or any part of the
current simulation dataset.
Once you click OK in the Start Comparison dialog box, Questa SIM adds a Compare tab to the
Main window.
After adding the signals, regions, and/or clocks you want to use in the comparison (see Adding
Signals, Regions, and Clocks), you will be able to drag compare objects from this tab into the
Wave and List windows.
Adding Signals
Add signals for a waveform comparison using the Structure Browser as follows.
Procedure
1. Select Tools > Waveform Compare > Add > Compare by Signal in the Wave window to
open the structure_browser window.
2. Highlight the signals to be used in the comparison.
3. Click the OK button.
Figure 14-47. Structure Browser
Adding Regions
Rather than comparing individual signals, you can also compare entire regions of your design.
Procedure
1. Select Tools > Waveform Compare > Add > Compare by Region to open the Add
Comparison by Region dialog.
2. Enter the desired region into the Reference Region field or click the Browse button to
search for and select the desired region.
3. Click the “Specify a different name for Test Region” if you want to give the Test Region
a different name.
4. Select from the “Compare Signals of Type” options.
5. Click the OK button.
Figure 14-48. Add Comparison by Region Dialog
Adding Clocks
You add clocks when you want to perform a clocked comparison.
Related Topics
Specifying the Comparison Method
Continuous Comparison
Continuous comparisons are the default. You have the option of specifying leading and trailing
tolerances and a when expression that must evaluate to true or 1 at the signal edge for the
comparison to become effective.
Clocked Comparison
To specify a clocked comparison you must define a clock in the Add Clock dialog. You can
access this dialog via the Clocks button in the Comparison Method tab or by selecting Tools >
Waveform Compare > Add > Clocks.
Figure 14-50. Adding a Clock for a Clocked Comparison
<path>/\refSignalName<>testSignalName\
If you compare two signals from different regions, the signal names include the uncommon part
of the path.
Timing differences are also indicated by red bars in the vertical and horizontal scroll bars of the
waveform display, and by red difference markers on the waveforms themselves. Rectangular
difference markers denote continuous differences. Diamond difference markers denote clocked
differences. Placing your mouse cursor over any difference marker will initiate a popup display
that provides timing details for that difference.
If the total number of differences between test and reference signals exceeds the maximum
difference limit, a yellow marker appears in the horizontal scroll bar, showing where waveform
comparison was terminated and no data was collected. You can set the difference limit in the
Waveform Comparison Options dialog box or with the compare options or compare start
commands.
The values column of the Wave window displays the words "match","diff", or “No Data” for
every test signal, depending on the location of the selected cursor. "Match" indicates that the
value of the test signal matches the value of the reference signal at the time of the selected
cursor. "Diff" indicates a difference between the test and reference signal values at the selected
cursor. “No Data” indicates that the cursor is placed in an area where comparison of test and
reference signals stopped.
In comparisons of signals with multiple bits, you can display them in "buswise" or "bitwise"
format. Buswise format lists the busses under the compare object whereas bitwise format lists
each individual bit under the compare object. To select one format or the other, click your right
mouse button on the plus sign (’+’) next to a compare object.
Annotating Differences
You can tag differences with textual notes that are included in the difference details popup and
comparison reports.
Procedure
Use either of the following methods to turn on annotations:
• Click a difference with the right mouse button, and select Annotate Diff.
• Use the compare annotate command.
Compare Icons
The Wave window includes six comparison icons that let you quickly jump between
differences. From left to right, the icons do the following: find first difference, find previous
annotated difference, find previous difference, find next difference, find next annotated
difference, find last difference.
These icons allow you to cycle through differences on all signals. To view differences for just
the selected signal, press <tab> and <shift - tab> on your keyboard.
Note
If you have differences on individual bits of a bus, the compare icons will stop on those
differences but <tab> and <shift - tab> will not.
The compare icons cycle through comparison objects in all open Wave windows. If you have
two Wave windows displayed, each containing different comparison objects, the compare icons
will cycle through the differences displayed in both windows.
Right-clicking on a yellow-highlighted difference gives you three options: Diff Info, Annotate
Diff, and Ignore/Noignore diff. With these options you can elect to display difference
information, you can ignore selected differences or turn off ignore, and you can annotate
individual differences.
Procedure
1. To view differences in the transcript, select Tools > Waveform Compare >
Differences > Show.
2. To save differences to a text file, select Tools > Waveform Compare > Differences >
Write Report.
• If the test design is flattened and test signal names are different from reference signal
names, the compare add command allows you to specify which signal in the test design
will be compared to which signal in the reference design.
• If, in addition, buses have been dismantled, or "bit-blasted", you can use the -rebuild
option of the compare add command to automatically rebuild the bus in the test design.
This will allow you to look at the differences as one bus versus another.
If signals in the RTL test design are different in type from the synthesized signals in the
reference design – registers versus nets, for example – the Waveform Compare feature will
automatically do the type conversion for you. If the type differences are too extreme (say
integer versus real), Waveform Compare will let you know.
The Schematic window provides an implementation view of your design, allowing you to see
design structure, connectivity, and hierarchy without consulting the RTL. It allows you to
explore the “physical” connectivity of your design; to trace events that propagate through the
design; and to identify the cause of unexpected outputs.
Figure 15-1. Schematic Window
The Schematic window displays both synthesizable and non-synthesizable parts of your design.
For the synthesizable parts, the Schematic window will:
• Show connectivity between components and separate data paths from control paths
• Identify clock and event triggers
• Separate combinational (Mux, Gates, Tristates) and sequential logic (Flops)
• Infer RAM/ROM blocks
In addition, integrated features like Causality Traceback and fan-in/fan-out trace help you
explore and debug the synthesizable parts of your design.
Non-synthesizable constructs are enclosed in black boxes in the Schematic window display, and
connectivity with surrounding context is maintained.
The +acc argument enables full visibility into the design for debugging purposes.
The -o argument is required for naming the optimized design object.
The -debugdb argument collects combinatorial and sequential logic data into the work
library.
Note
The +acc argument supports selective visibility into your design in order to reduce
the size of the debugging database. For example, if your testbench has an instance
called “instDut” of the design under test, you can use vopt -debugdb +acc+'/instDut' to
generate a debug database for only that instance.
The -debugdb argument creates a debug database, <dbname>, in the current working
directory. If you do not assign a database name with [=<dbname>], the default file name
vsim.dbg. This database contains annotated schematic connectivity information.
It is advisable to log the entire design. This will provide the historic values of the events
of interest plus its drivers. To reduce overhead, you may choose to log only the regions
of interest.
You may use the log command to simply save the simulation data to the .wlf file; or, use
the add wave command to log the simulation data to the .wlf file and display simulation
results as waveforms in the Wave window.
6. Run the simulation.
7. Debug your design using the Schematic window.
8. Exit the simulation.
Note
The Schematic window will not function without an extended dataflow license. If
you attempt to create the debug database (vsim -debugdb) without this license, the
following error message will appear:
Prerequisites
• Set up your simulation, similarly to the process defined in the section “Live Simulation
Schematic Debug Flow”.
Procedure
1. Start Questa SIM by doing either of the following:
• (Linux) Type vsim in a Linux shell, at the prompt.
• (Windows) Double-click a Questa SIM icon.
2. Select File > Change Directory and change to the directory where the post-simulation
debug database resides.
Questa SIM opens the .wlf dataset and its associated debug database (.dbg file with the
same basename), if it can be found. If Questa SIM cannot find db_pathname.dbg, it will
attempt to open vsim.dbg.
The logic of connectivity inside a process in the Full view is exactly same as in the Incremental
view. All processes that have any logic inside them are marked as blue boxes with a dotted
boundary, while un-synthesizable/black box processes (like initial blocks) are shown as boxes
with a solid boundary. If a process has less than 4 gates inside, the logic inside that box is shown
in the initial layout itself and the process boundary in such cases is removed.
You can only add instances to the Full view with the right- click popup menu in the Structure
(sim) window, with a command issued at the command line interface (such as: add schematic
-full <design unit>), or by simply dragging and dropping into the Schematic window.
In the Full view mode, you may select any net and add it to the Incremental view using the
right-click menu, and add the net to the current window or to a new window (Figure 15-3).
On module port signals, the direction of cursor arrow will be changed to either a left arrow, a
right arrow, or a double sided arrow to indicate the port direction as input, output, or inout.
Clicking on those ports sprouts the connected hierarchy.
• You may customize the Incremental view with the Schematic > Show menu selection,
or by right-clicking the Incremental view and selecting Show to open the display options
(Figure 15-5). By default, all displayed signal values are for the current active time, as
displayed in the Current Time label.
Figure 15-5. Show Incremental View Annotation
• Hovering the mouse cursor over a design object opens a tooltip (text popup box) that
displays design object information for the specific object type. For example, the tooltip
for a module displays the module name, design unit type, and design unit path as shown
in Figure 15-6.
Figure 15-6. Hover Mouse for Tooltip
The tooltip for a signal net displays the net name and its value at the current time.
• Double-click any object in the Incremental view to view its source code in a Code
Preview window. The code for the selected object is highlighted (Figure 15-7).
Figure 15-7. Code Preview Window
The Code Preview window includes a four-button toolbar that provides the options shown in
Table 15-1
• Drag and drop objects from other windows. Both nets and instances may be dragged
and dropped. Dragging an instance will result in the addition of all nets connected to
that instance.
• Use the Add > To Schematic menu options:
o Selected Signals— Display selected signals
o Signals in Region— Display all signals from the current region.
o Signals in Design— Clear the window and display all signals from the entire
design.
• Select the object(s) you want placed in the Schematic Window, then click-and-hold
the Add Selected to Window Button in the Standard toolbar and select Add to
Schematic.
When the Follow box is checked, any design unit you select in the Structure window is
displayed in the Full View.
2. If you then select a specific signal in the Objects windows, the selected signal is
highlighted in the Full View.
In other words, the Full View follows the selections you make in other windows that are
dynamically connected to the Schematic window. It allows you to quickly find specific
signals within the overall design schematic.
Procedure
1. Hover your mouse over a signal pin. The mouse cursor will change to a right-pointing or
left-pointing arrow.
2. If the arrow points to the right, you can double-click the pin to expand the net’s fanout to
its readers. If the arrow points left, you can double-click the pin to expand the net’s
fanout to its drivers (Figure 15-9).
Figure 15-9. Left-Pointing Mouse Arrow Indicates Drivers
You can change the default click-and-sprout expansion mode from a double-click of the
left mouse button to a single click by pressing the C shortcut key. (See How do I Use
Keyboard Shortcuts?)
A double-headed arrow that points in both directions indicates an inout signal pin, with
drivers and readers (Figure 15-10).
Figure 15-10. Double-Headed Arrow Indicates Inout with Drivers and Readers
3. To expand with the mouse, simply double-click a signal pin. Depending on the specific
pin you double-click, the view will expand to show the driving process and
interconnecting nets, the reading process and interconnecting nets, or both.
4. Alternatively, you can select a signal, register, or net, and use one of the toolbar buttons
in the first column of Table 15-2; or, right-click the selected item and make the menu
selection described in the second column of Table 15-2.
Table 15-2. Icon and Menu Selections for Exploring Design Connectivity
Expand net to all drivers Expand Net To > Drivers
display driver(s) of the selected signal, net, or
register
Expand net to all drivers and readers Expand Net To > Drivers &
display driver(s) and reader(s) of the selected signal, Readers
net, or register
Expand net to all readers Expand Net To > Readers
display reader(s) of the selected signal, net, or
register
As you expand the view, the layout of the design may adjust to show the connectivity
more clearly. For example, the location of an input signal may shift from the bottom to
the top of a process.
5. Use the Regenerate button in the Schematic Toolbar to automatically clear and redraw
either the Incremental or the Full view in order to better display schematic information.
For example, if you turn on signal values, some values for the pins of adjacent processes
may overlap. Click the Regenerate button to automatically redraw the schematic so
values do not overlap.
6. Set the limit for the number of readers to be drawn and click the OK button.
7. The schematic display tests for the number of readers to be drawn and compares that
number to a limit that you set in Schematic Preferences. The default value of this limit is
100 (if you set outputquerylimit to 0, the test is not done). If this limit is exceeded, a
dialog box asks whether you want all readers to be drawn. If you choose No, then no
readers are displayed.
Note
This limit does not affect the display of drivers.
Procedure
To change the display of redundant buffers and inverters in either the Incremental or Full views,
select Schematic > Preferences to open the Schematic Options dialog. The default setting is to
display both redundant buffers and redundant inverters (Figure 15-12).
You can then choose from one of five pre-defined colors, or Customize to choose from
the palette in the Preferences dialog box.
2. Clear highlighting using the Schematic > Highlight > Remove menu selection or by
clicking the Remove All Highlights icon in the toolbar. If you click and hold the
Remove All Highlights icon a dropdown menu appears, allowing you to remove the
selected highlights
Procedure
1. To unfold an instance and display its contents, do either of the following:
• Double-click the folded instance.
• Click the folded instance to select it, then right-click and select Fold/Unfold from
the popup menu.
2. To fold and instance, do either of the following:
• Ctrl + double-click the instance.
• Click the instance to select it, then right-click and select Fold/Unfold from the
popup menu.
Results
If you have not traced any signals into a folded instance (for example, if you simply dragged an
instance into the incremental view) and then you unfold it, this action will only make the
instance box transparent — you will not see the contents (Figure 15-15).
Figure 15-15. Unfolded Instance Not Showing Contents
However, you can double-click any input/output pin to trace the drivers/readers and cause the
connected gates and internal instances to appear (Figure 15-16).
Figure 15-16. Unfolded Instance with All Contents Displayed
Procedure
1. Abstract blocks can be unfolded to access detailed information and, if needed, refolded.
To unfold, simply double click an abstract block; or, right-click it and select Fold/
Unfold from the popup menu. To fold, press the Ctrl key and double-click the block; or,
right-click the block and select Fold/Unfold from the popup menu.
2. In the folded state, a keyword is written inside the abstract block — like FOR, GEN,
VW or MC — to indicate the type of abstract block it is. All the control signals are
routed through the bottom of abstract block, while input and output are routed through
left and right sides respectively.
3. To further prioritize Schematic comprehension, heuristics are used for identifying and
creating Abstract blocks — for example: iteration-count of for-loops, and count in
contiguous mux-chains.
4. Abstract blocks are displayed in both the Incremental and Full view mode. In the Full
view, some unfolded abstract blocks may contain other folded abstract blocks. These
abstract blocks can be unfolded as well to show further details of the design.
Examples
Abstract blocks are created under the following conditions:
Note
A single abstract-block is created for a for-generate statement (even if it contains
nested if-generate or for-generate statement) to keep abstract-block count to
appropriate level.
Procedure
1. To open the wave viewer, use the Schematic > Show Wave menu selection when the
Incremental view is active, or simply click the Show Wave toolbar button.
2. When wave viewer is first displayed, the visible zoom range is set to match that of the
last active Wave window, if one exists. Additionally, the wave viewer's moveable cursor
(Cursor 1) is automatically positioned to the location of the active cursor in the last
active Wave window.
3. When you select an instance or process in the schematic, all signals attached to that
instance or process are added to the wave viewer. In Figure 15-18, the #ALWAYS#35
process is selected and the wave viewer displays 3 inputs, 1 output, and an inout bus.
See Tracing Events in the Incremental View for another example of using the embedded
wave viewer.
4. With the embedded wave viewer open in the Incremental view you can run the design
for a period of time, then use time cursors to investigate value changes. As you place and
move cursors in the wave viewer (see Measuring Time with Cursors in the Wave
Window), the signal values update in the schematic view (Figure 15-18).
5. Notice that the title of the Schematic window changes to reflect which portion of the
window is active. When the schematic is active, the title of the window is “Schematic
(schematic).” When the embedded wave view is active, the title of the window is
“Schematic (wave).” Menu and toolbar selections will change depending on which
portion of the window is active.
Figure 15-18. Wave Viewer Displays Inputs and Outputs of Selected Process
• trace an event to the first sequential process that caused the event – Show Cause
• trace an event to its immediate driving process – Show Driver
• trace an event to its root cause – Show Root Cause
The event trace begins at the current “active time,” which is set a number of different ways:
The CurrentTime label includes a minimize/maximize button that allows you to hide or display
the label.
When a signal or net is selected, you can jump to the previous or next transition of that signal,
with respect to the current time, by clicking the Find Previous/Next Transition buttons.
To change the Current Time, simply click the label and type in the time you want to examine in
the Enter Value dialog box (Figure 15-21). The dialog box includes a check box that allows you
to switch to Now time (the time the simulation ended) or Current time (if “Now” is displayed in
the Current Time label.
The recommended work flow for initiating an event trace from the Incremental view is as
follows:
Procedure
1. Add a process or signal of interest into the Incremental view (if adding a signal, include
its driving process).
2. Open the embedded wave viewer by clicking the Show Wave toolbar button.
3. In the Incremental view, click the process of interest so that all signals attached to the
selected process will appear in the embedded wave viewer.
4. In the wave viewer, select a signal and place a cursor at an event of interest. In
Figure 15-22, signal q of the fifo module ff3 is selected and a cursor is placed on the
transition at 670 ns.
Figure 15-22. Signals for Selected Process in Embedded Wave Viewer
5. Right-click and select Event Traceback, then one of the three traceback options, from
the popup menu.
Results
A Source window opens with the cause of the event highlighted and driver information
displayed in the Show Driver Control Bar at the top of the Source window. There are four
buttons in the Show Drivers Control Bar: 1) the History button, 2) the List Menu button, 3) the
Previous button, and 4) the Next button (Figure 15-23).
In Figure 15-23, the Show Drivers Control Bar displays “1/12 Drivers” to indicate that the first
of twelve drivers is selected. When you click the List Menu button, a menu drops down showing
all drivers with a checkmark beside the selected driver, which is highlighted in the Source
window (Figure 15-24).
Figure 15-24. Multiple Drivers in the Show Drivers Control Bar
You can jump directly to the source code of any other driver in the list by simply clicking it. Or,
use the Previous and Next buttons to navigate through the list of drivers.
The History button allows you to review past Show Drivers operations (Figure 15-25). Click an
item in the list to return to a previous operation.
For more information about using the Show Drivers Control Bar see Multiple Drivers.
You can also display information about the sequential process(es) that caused the selected event
by opening the Active Driver Path Details window (Figure 15-26).
Figure 15-26. Active Driver Path Details for the q Signal
If you want to see the path details in the Schematic window, click the Schematic Window
button at the bottom of the Active Driver Path Details Window.
Figure 15-27. Click Schematic Window Button to View Path Details
This will open a Schematic window with the title Schematic (Path Details). In Figure 15-28,
the q signal event at 670 ns is traced to its root cause. All signals in the path to the root cause are
displayed in the wave viewer, and the path through the schematic is highlighted in red. The
wave viewer also displays two new cursors, labeled Trace Begin and Trace End to designate
where the event trace started and ended.
Figure 15-28. Path to Root Cause
For more details about event tracing see Using Causality Traceback.
Procedure
1. Optimize your design with +acc (for debugging visibility) and with -debugdb (to save
combinatorial and sequential logic events to the working library).
2. Load your design with vsim -debugdb to create a database (vsim.dbg) from the
combinatorial and sequential logic event data.
3. Log all signals in the design or any signals that may possibly contribute to the unknown
value (log -r /* will log all signals in the design).
4. Add signals to the Wave window or wave viewer pane, and run your design the desired
length of time.
5. Put a Wave window cursor on the time at which the signal value is unknown (StX). In
Figure 15-29, Cursor 1 at time 2305 shows an unknown state on signal t_out.
6. Add the signal of interest to the Schematic window. You can drag and drop it from the
Objects window, use the Add Selected to Window toolbar button, or the Add > to
Schematic > Selected Signals menu selection,
7. In the Schematic window, make sure the signal of interest is selected.
8. Click and hold the Event Traceback menu button to open the menu (Figure 15-30), then
select Show ‘X’ Cause (ChaseX).
Related Topics
Using Causality Traceback
Results
The Find toolbar opens at the bottom of the Schematic window (Figure 15-31).
Figure 15-31. Find Toolbar for Schematic Window
With the Find toolbar you can limit the search by type to instances or signal nets. You may do
hierarchical searching from the design root (when you check “Search from Top”) or from the
current context. The Zoom to selection zooms in to the item you enter in the Find field. The
Match case selection enforces case-sensitive matching of your entry. And you can select Exact
(whole word) to find an item that exactly matches the entry you type in the Find field.
The Find All Matches in Current Schematic button allows you to find and highlight all
occurrences of the item in the Find field. If the Zoom to box is checked, the view changes so all
selected items are viewable. If Zoom to is not checked, then no change is made to the zoom or
scroll state.
The Sticky Note option in the right-click menu provides four actions:
• Add — Create a note to annotate a component.
• Remove — Remove a sticky note from the selected component.
• Hide/Unhide — Hide or display an existing sticky note for the selected component.
• Hide/Unhide All — Hide or display all sticky notes.
Double-clicking on an existing sticky note will open an edit box, where you can edit and
update the note.
Sticky notes also get saved in the save/restore functionality. (See Saving and Restoring
the Schematic.)
Prerequisites
• This feature is available during a live simulation, not when performing post-simulation
debugging.
Procedure
1. Select Source — Click on the net to be your source
2. Select Destination — Shift-click on the net to be your destination
3. Run point-to-point tracing — Right-click in the Schematic window and select Point to
Point.
Results
After beginning the point-to-point tracing, the Schematic window highlights your design as
shown in Figure 15-33:
• All objects become gray
• The source net becomes yellow
• The destination net becomes red
• All intermediate processes and nets become orange.
Figure 15-33. Schematic: Point-to-Point Tracing
Examples
• Change the limit of highlighted processes — There is a limit of 400 processes that will
be highlighted.
The schematic.bsm file contains comments and name pairs, one comment or name per line. Use
the following Backus-Naur Format naming syntax:
For example:
org(only),p1 OR
andg(only),p1 AND
mylib,andg.p1 AND
norg,p2 NOR
Entities and modules representing cells are mapped the same way:
AND1 AND
# A 2-input and gate
AND2 AND
mylib,andg.p1 AND
xnor(test) XNOR
Note
Note that for primitive gate symbols, pin mapping is automatic. When you map a module/
entity, it must be defined as a cell via `celldefine in Verilog.
The default filename is schematic.bsm (.bsm stands for "Built-in Symbol Map"). The Schematic
window looks in the current working directory and inside each library referenced by the design
for the file schematic.bsm. It will read all files found. You can also manually load a .bsm file by
selecting Schematic > Symbol Library > Load Built in Symbol Map.
Note
The Schematic window will search for mapping files named dataflow.bsm first, then
schematic.bsm in order to maintain backwards compatibility with designs simulated with
older versions of Questa SIM.
User-Defined Symbols
You can also define your own symbols using an ASCII symbol library file format for defining
symbol shapes. This capability is delivered via Concept Engineering’s NlviewTM widget
Symlib format. The symbol definitions are saved in the schematic.sym file.
The formal BNF format for the schematic.sym file format is:
Note
The port names in the definition must match the port names in the entity or module
definition or mapping will not occur.
The Schematic window will search the current working directory, and inside each library
referenced by the design, for the file schematic.sym. Any and all files found will be given to the
Nlview widget to use for symbol lookups. Again, as with the built-in symbols, the DU name and
optional process name is used for the symbol lookup. Here's an example of a symbol for a full
adder:
Port mapping is done by name for these symbols, so the port names in the symbol definition
must match the port names of the Entity|Module|Process (in the case of the process, it’s the
signal names that the process reads/writes).
When you create or modify a symlib file, you must generate a file index. This index is how the
Nlview widget finds and extracts symbols from the file. To generate the index, select
Schematic > Schematic Preferences > Create Symlib Index (Schematic window) and specify
the symlib file. The file will be rewritten with a correct, up-to-date index. If you save the file as
schematic.sym the Schematic window will automatically load the file. You can also manually
load a .sym file by selecting Schematic > Schematic Preferences > Load Symlib Library.
Note
When you map a process to a gate symbol, it is best to name the process statement within
your HDL source code, and use that name in the .bsm or .sym file. If you reference a default
name that contains line numbers, you will need to edit the .bsm and/or .sym file every time you
add or subtract lines in your HDL source.
The Schematic window will search for mapping files named dataflow.sym first, then
schematic.sym in order to maintain backwards compatibility with designs simulated with older
versions of Questa SIM.
You cannot view SystemC objects in the Schematic window; however, you can view HDL
regions from mixed designs that include SystemC.
Table 15-3. Schematic Window Links to Other Windows and Panes (cont.)
Window Link
Wave Window trace through the design in the Schematic window, and the
associated signals are added to the Wave window along with
Trace Begin and Trace End cursors
move a cursor in the Wave window, and the values update in
the Schematic window
Source Window double-click an object in the Schematic window to open a
Code Preview; use Event Traceback in the Schematic window
to go directly to the source code for the cause of the event
Saving a .eps File and Printing the Schematic Display from UNIX
With the Schematic window active, select File > Print Postscript to setup and print the
Schematic display in UNIX, or save the waveform as an .eps file on any platform
(Figure 15-34).
You may also right-click in either the Incremental or Full view to select Show from the popup
menu, which gives you the display selections shown in Figure 15-37.
Net Names and Signal Values can be toggled on and off with the N and V keys on your
keyboard, respectively. (See How do I Use Keyboard Shortcuts?) By default, displayed signal
values are for the current active time.
Zoom In
zoom in by a factor of two from the current view
Zoom Out
zoom out by a factor of two from current view
Zoom Full
zoom out to view the entire schematic
To zoom with the mouse, you can either use the middle mouse button or enter Zoom Mode by
selecting Schematic > Zoom and then use the left mouse button.
• Enter Pan Mode by selecting Schematic > Mouse Mode > Pan and then drag with the
left mouse button to move the design
• Hold down the <Ctrl> key and drag with the middle mouse button to move the design.
Toggle the list closed by pressing the ‘?’ key again or simply click the list.
This chapter discusses how to use the Dataflow window for tracing signal values, browsing the
physical connectivity of your design, and performing post-simulation debugging operations.
Dataflow Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Dataflow Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Common Tasks for Dataflow Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Dataflow Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Dataflow Window Graphic Interface Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
The +acc argument provides visibility into the design while the -debugdb argument
collects combinatorial and sequential data.
3. Load the design with the following commands:
vsim -postsimdataflow -debugdb=<db_pathname> -wlf <db_pathname>
<optimized_design_name>
add log -r /*
By default, the Dataflow window is not available for post simulation debug operations.
You must use the -postsimdataflow argument with the vsim command to make the
Dataflow window available during post-sim debug.
Specify the post-simulation database file name with the -debugdb=<db_pathname>
argument to the vsim command. If a database pathname is not specified, Questa SIM
creates a database with the file name vsim.dbg in the current working directory. This
database contains dataflow connectivity information.
Specify the dataset that will contain the database with -wlf <db_pathname>. If a dataset
name is not specified, the default name will be vsim.wlf.
The debug database and the dataset that contains it should have the same base name
(db_pathname).
The add log -r /* command instructs Questa SIM to save all signal values generated
when the simulation is run.
4. Run the simulation.
5. Quit the simulation.
6. The -debugdb=<db_pathname> argument for the vsim command only needs to be used
once after any structural changes to a design. After that, you can reuse the vsim.dbg file
along with updated waveform files (vsim.wlf) to perform post simulation debug.
7. A structural change is any change that adds or removes nets or instances in the design, or
changes any port/net associations. This also includes processes and primitive instances.
Changes to behavioral code are not considered structural changes. Questa SIM does not
automatically detect structural changes. This must be done by the user.
Questa SIM opens the .wlf dataset and its associated debug database (.dbg file with the
same basename), if it can be found. If Questa SIM cannot find db_pathname.dbg, it will
attempt to open vsim.dbg.
• View region — clear the window and display all signals from the current region
• Add region — display all signals from the current region without first clearing the
window
• View all nets — clear the window and display all signals from the entire design
• Add ports — add port symbols to the port signals in the current region
When you view regions or entire nets, the window initially displays only the drivers of the
added objects. You can view readers as well by right-clicking a selected object, then selecting
Expand net to readers from the right-click popup menu.
The Dataflow window provides automatic indication of input signals that are included in the
process sensitivity list. In Figure 16-3, the dot next to the state of the input clk signal for the
#ALWAYS#155 process. This dot indicates that the clk signal is in the sensitivity list for the
process and will trigger process execution. Inputs without dots are read by the process but will
not trigger process execution, and are not in the sensitivity list (will not change the output by
themselves).
The Dataflow window displays values at the current “active time,” which is set a number of
different ways:
Alternatively, you can select a signal, register, or net, and use one of the toolbar buttons or drop
down menu commands described in Table 16-1.
Table 16-1. Icon and Menu Selections for Exploring Design Connectivity
Expand net to all drivers Right-click in the Dataflow
display driver(s) of the selected signal, net, or window > Expand Net to Drivers
register
Expand net to all drivers and readers Right-click in the Dataflow
display driver(s) and reader(s) of the selected window > Expand Net
signal, net, or register
Expand net to all readers Right-click in the Dataflow
display reader(s) of the selected signal, net, or window > Expand Net to Readers
register
As you expand the view, the layout of the design may adjust to show the connectivity more
clearly. For example, the location of an input signal may shift from the bottom to the top of a
process.
3. Right-click and select one of the Expand > Expand Bit ... options.
After internally analyzing your selection, the dataflow will then show the connected
net(s) for the scalar you selected without showing all the other parts of the bus. This
saves in processing time and produces a more compact image in the Dataflow window
as opposed to using the Expand > Expand Net ... options, which will show all readers
or drivers that are connected to any portion of the bus.
Note
This limit does not affect the display of drivers.
You can clear this highlighting using the Dataflow > Remove Highlight menu selection or by
clicking the Remove All Highlights icon in the toolbar. If you click and hold the Remove All
Highlights icon a drop down menu appears, allowing you to remove only selected
highlights.
You can also highlight the selected trace with any color of your choice by right-clicking
Dataflow window and selecting Highlight Selection from the popup menu (Figure 16-7).
You can then choose from one of five pre-defined colors, or Customize to choose from the
palette in the Preferences dialog box.
When wave viewer is first displayed, the visible zoom range is set to match that of the last
active Wave window, if one exists. Additionally, the wave viewer's movable cursor (Cursor 1)
is automatically positioned to the location of the active cursor in the last active Wave window.
The Current Time label in the upper right of the Dataflow window automatically displays the
time of the currently active cursor. Refer to Current Time Label for information about working
with the Current Time label.
One common scenario is to place signals in the wave viewer and the Dataflow panes, run the
design for some amount of time, and then use time cursors to investigate value changes. In other
words, as you place and move cursors in the wave viewer pane (see Measuring Time with
Cursors in the Wave Window for details), the signal values update in the Dataflow window.
Figure 16-8. Wave Viewer Displays Inputs and Outputs of Selected Process
Another scenario is to select a process in the Dataflow pane, which automatically adds to the
wave viewer pane all signals attached to the process.
Related Topics
Waveform Analysis
Tracing Events
Tracing Events
You can use the Dataflow window to trace an event to the cause of an unexpected output. This
feature uses the Dataflow window’s embedded wave viewer. First, you identify an output of
interest in the dataflow pane, then use time cursors in the wave viewer pane to identify events
that contribute to the output.
Procedure
1. Log all signals before starting the simulation (add log -r /*).
2. After running a simulation for some period of time, open the Dataflow window and the
wave viewer pane.
3. Add a process or signal of interest into the dataflow pane (if adding a signal, find its
driving process). Select the process and all signals attached to the selected process will
appear in the wave viewer pane.
4. Place a time cursor on an edge of interest; the edge should be on a signal that is an
output of the process.
5. Right-click and select Trace Next Event.
The Dataflow display “jumps” to the source of the selected input event(s). The operation
follows all signals selected in the wave viewer pane. You can change which signals are
followed by changing the selection.
8. To continue tracing, go back to step 5 and repeat.
9. If you want to start over at the originally selected output, right-click and select Trace
Event Reset.
Related Topics
Explore Designs with the Embedded Wave Viewer
Procedure
1. Load your design.
2. Log all signals in the design or any signals that may possibly contribute to the unknown
value (log -r /* will log all signals in the design).
3. Add signals to the Wave window or wave viewer pane, and run your design the desired
length of time.
4. Put a Wave window cursor on the time at which the signal value is unknown (StX). In
Figure 16-9, Cursor 1 at time 2305 shows an unknown state on signal t_out.
5. Add the signal of interest to the Dataflow window by doing one of the following:
• Select the signal in the Wave Window, select Add Selected to Window in the
Standard toolbar > Add to Dataflow.
• right-click the signal in the Objects window and select Add > To Dataflow >
Selected Signals from the popup menu,
• select the signal in the Objects window and select Add > To Dataflow > Selected
Items from the menu bar.
6. In the Dataflow window, make sure the signal of interest is selected.
With the search toolbar you can limit the search by type to instances or signals. You select
Exact to find an item that exactly matches the entry you’ve typed in the Find field. The Match
case selection will enforce case-sensitive matching of your entry. And the Zoom to selection
will zoom in to the item in the Find field.
The Find All button allows you to find and highlight all occurrences of the item in the Find
field. If Zoom to is checked, the view will change such that all selected items are viewable. If
Zoom to is not selected, then no change is made to zoom or scroll state.
Results
After beginning the point-to-point tracing, the Dataflow window highlights your design as
shown in Figure 16-10:
• All objects become gray
• The source net becomes yellow
• The destination net becomes red
Dataflow Concepts
This section provides an introduction to the following important Dataflow concepts:
Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
User-Defined Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Current vs. Post-Simulation Command Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Symbol Mapping
The Dataflow window has built-in mappings for all Verilog primitive gates (for example, AND,
OR, and so forth). You can also map VHDL entities and Verilog/SystemVerilog modules that
represent a cell definition, or processes, to built-in gate symbols.
Syntax
<bsm_line> ::= <comment> | <statement>
Arguments
• The following arguments are available:
o <comment> ::= "#" <text> <EOL>
o <statement> ::= <name_pattern> <gate>
o <name_pattern> ::= [<library_name> "."] <du_name> ["(" <specialization> ")"]
[","<process_name>]
o <gate> ::=
"BUF"|"BUFIF0"|"BUFIF1"|"INV"|"INVIF0"|"INVIF1"|"AND"|"NAND"|
"NOR"|"OR"|"XNOR"|"XOR"|"PULLDOWN"|"PULLUP"|"NMOS"|"PMOS"|"CM
OS"|"TRAN"| "TRANIF0"|"TRANIF1"
Description
The mappings are saved in a file where the default filename is dataflow.bsm (.bsm stands for
“Built-in Symbol Map”) The Dataflow window looks in the current working directory and
inside each library referenced by the design for the file. It will read all files found. You can also
manually load a .bsm file by selecting Dataflow > Dataflow Preferences > Load Built in
Symbol Map.
The dataflow.bsm file contains comments and name pairs, one comment or name per line. Use
the following Backus-Naur Format naming syntax:
Examples
• Example 1
org(only),p1 OR
andg(only),p1 AND
mylib,andg.p1 AND
norg,p2 NOR
• Entities and modules representing cells are mapped the same way:
AND1 AND
# A 2-input and gate
AND2 AND
mylib,andg.p1 AND
xnor(test) XNOR
Note
For primitive gate symbols, pin mapping is automatic.
User-Defined Symbols
The formal BNF format for the dataflow.sym file format is:
You can also define your own symbols using an ASCII symbol library file format for defining
symbol shapes. This capability is delivered via Concept Engineering’s NlviewTM® widget
Symlib format. The symbol definitions are saved in the dataflow.sym file.
Syntax
<sym_line> ::= <comment> | <statement>
Arguments
• The following arguments are available:
<comment> ::= "#" <text> <EOL>
<statement> ::= "symbol" <name_pattern> "*" "DEF" <definition>
<name_pattern> ::= [<library_name> "."] <du_name> ["(" <specialization> ")"]
[","<process_name>]
<gate> ::= "port" | "portBus" | "permute" | "attrdsp" | "pinattrdsp" | "arc" | "path" | "fpath"
| "text" | "place" | "boxcolor"
Note
The port names in the definition must match the port names in the entity or module
definition or mapping will not occur.
The Dataflow window will search the current working directory, and inside each library
referenced by the design, for the file dataflow.sym. Any and all files found will be given to
the Nlview widget to use for symbol lookups. Again, as with the built-in symbols, the DU
name and optional process name is used for the symbol lookup. Here's an example of a
symbol for a full adder:
symbol adder(structural) * DEF \
port a in -loc -12 -15 0 -15 \
pinattrdsp @name -cl 2 -15 8 \
port b in -loc -12 15 0 15 \
pinattrdsp @name -cl 2 15 8 \
port cin in -loc 20 -40 20 -28 \
pinattrdsp @name -uc 19 -26 8 \
port cout out -loc 20 40 20 28 \
pinattrdsp @name -lc 19 26 8 \
port sum out -loc 63 0 51 0 \
pinattrdsp @name -cr 49 0 8 \
path 10 0 0 7 \
path 0 7 0 35 \
path 0 35 51 17 \
path 51 17 51 -17 \
path 51 -17 0 -35 \
path 0 -35 0 -7 \
path 0 -7 10 0
Port mapping is done by name for these symbols, so the port names in the symbol definition
must match the port names of the Entity|Module|Process (in the case of the process, it’s the
signal names that the process reads/writes).
When you create or modify a symlib file, you must generate a file index. This index is how
the Nlview widget finds and extracts symbols from the file. To generate the index, select
Dataflow > Dataflow Preferences > Create Symlib Index (Dataflow window) and specify
the symlib file. The file will be rewritten with a correct, up-to-date index. If you save the file
as dataflow.sym the Dataflow window will automatically load the file. You can also
manually load a .sym file by selecting Dataflow > Dataflow Preferences > Load Symlib
Library.
Note
When you map a process to a gate symbol, it is best to name the process statement
within your HDL source code, and use that name in the .bsm or .sym file. If you
reference a default name that contains line numbers, you will need to edit the .bsm and/
or .sym file every time you add or subtract lines in your HDL source.
You cannot view SystemC objects in the Dataflow window; however, you can view HDL
regions from mixed designs that include SystemC.
Table 16-2. Dataflow Window Links to Other Windows and Panes (cont.)
Window Link
Source Window select an object in the Dataflow window, and the Source
window updates if that object is in a different source file
This chapter discusses the uses of the Source Window for editing, debugging, causality tracing,
and code coverage.
Opening Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Changing File Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Updates to Externally Edited Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Navigating Through Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Data and Objects in the Source Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Object Values and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Displaying Object Values with Source Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Setting Simulation Time in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
Search for Source Code Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Debugging and Textual Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Hyperlinked Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Highlighted Text in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Drag Objects Into Other Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Code Coverage Data in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Coverage Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Setting Individual Breakpoints in a Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Setting Breakpoints with the bp Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Setting SystemC Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Editing Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Saving and Restoring Source Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Setting Conditional Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Run Until Here . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
Source Window Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Setting and Removing Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Source Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Procedure
1. Right-click in the Source window
2. Select (un-check) Read Only.
3. Edit your file.
Note
The Open Instance option is essentially executing an environment command to
change your context. Therefore any time you use this command manually at the
command prompt, that information is also saved for use with the Back/Forward
options.
• Select an object, then right-click and select Examine or Describe from the context
menu.
• Pause over an object with your mouse pointer to see an examine window popup.
(Figure 17-2)
Figure 17-2. Examine Window Pop Up
You can also invoke the examine and/or describe commands on the command line or in a DO
file.
Note
Transitions are displayed only for those signals that you have logged. The Source window
displays the values for the simulation time shown in the time indicator in the top right corner
of the window. Refer to Setting Simulation Time in the Source Window for more information.
You can highlight a specific signal in the Wave window by double-clicking on an annotation
value in the source file.
Procedure
You have several options for setting the time display in the Source window,
Hyperlinked Text
The Source window supports hyperlinked navigation. When you double-click hyperlinked text
the selection jumps from the usage of an object to its declaration and highlights the declaration.
Hyperlinked text is indicated by a mouse cursor change from an arrow pointer icon to a pointing
finger icon:
• Jump from the usage of a signal, parameter, macro, or a variable to its declaration.
• Jump from a module declaration to its instantiation, and vice versa.
• Navigate back and forth between visited source files.
Hyperlinked text is off by default. To turn hyperlinked text on or off in the Source window:
In these cases, the relevant text in the source code is shown with a persistent highlighting. To
remove this highlighted display, right-click in the Source window and choose More > Clear
Highlights. You can also perform this action by selecting Source > More > Clear Highlights
from the Main menu.
Note
Clear Highlights does not affect text that you have selected with the mouse cursor.
To produce a compile error that displays highlighted text in the Source window, do the
following:
Procedure
1. Choose Compile > Compile Options
2. In the Compiler Options dialog box, click either the VHDL tab or the Verilog &
SystemVerilog tab.
3. Enable Show source lines with errors and click OK.
4. Open a design file and create a known compile error (such as changing the word “entity”
to “entry” or “module” to “nodule”).
5. Choose Compile > Compile and then complete the Compile Source Files dialog box to
finish compiling the file.
6. When the compile error appears in the Transcript window, double-click on it.
7. The source window is opened (if needed), and the text containing the error is
highlighted.
8. To remove the highlighting, choose Source > More > Clear Highlights.
Results
The textual dataflow functions of the Source window only work for pure HDL. They will not
work for SystemC or for complex data types like SystemVerilog classes.
The Source window contains textual connectivity information for the time specified in the time
indicator (refer to Setting Simulation Time in the Source Window). You can explore the
connectivity of your design through the source code. This feature is especially useful when used
with source annotation turned on.
When you double-click an instance name in the Structure (sim) window, a Source window will
open at the appropriate instance. You can then access textual connectivity information in the
Source window by right-clicking any signal. This opens a popup menu that gives you the
choices shown in Figure 17-7.
The Event Traceback > Show Driver selection causes the Source window to jump to the
source code defining the driver of the selected signal. If the Driver is in a different Source file,
that file will open in a new Source window and the driver code will be highlighted. You can also
jump to the driver of a signal by double-clicking the signal.
If there is more than one driver for the signal, the number of drivers will be shown in the Show
Drivers Control Bar at the top of the Source window.
There are four buttons in the Show Drivers Control Bar: 1) the History button, 2) the List Menu
button, 3) the Previous button, and 4) the Next button (Figure 17-8).
Figure 17-8. Show Drivers Control Bar Buttons
In Figure 17-8, the Show Drivers Control Bar displays “1/12 Drivers” to indicate that the first of
twelve drivers is selected. When you click the List Menu button, a menu drops down showing
all drivers with a checkmark beside the selected driver, which is highlighted in the Source
window (Figure 17-9).
Figure 17-9. Multiple Drivers in the Show Drivers Control Bar
You can jump directly to the source code of any other driver in the list by simply clicking it. Or,
use the Previous and Next buttons to navigate through the list of drivers.
The History button allows you to review past Show Drivers operations (Figure 17-10). Click an
item in the list to return to a previous operation.
Figure 17-10. History Button Displays Past Operations
By default, the drivers shown in the List Menu only include the instance path and the source
text. But the List Menu contains three viewing options that allow you to: Include Process
Names, Include Line Numbers, and Include File Name. Clicking the option toggles it on or off.
Figure 17-11 is an example of the List Menu with all three viewing options displayed.
The driver List Menu in Figure 17-12 shows two drivers. Driver #1 is displayed in black and
driver #2 is in blue. The blue color of driver #2 indicates that the instance path (in this case,
/test1/u1) is different from the starting point (which is /test1/ref_req). When the driver is
displayed in black, it means it has not left the instance it started in.
Figure 17-12. Click Any Driver to Display It
The Show Readers selection opens the Source Readers window. If there is more than one
reader for the signal, all will be displayed (Figure 17-13).
When the trace is complete, the Active Driver Path Details window displays all signals in the
causality path, the Objects window highlights all signals in the path, and the Source window
jumps to the assignment code that caused the event and highlights the code.
To see more information about any coverage item, click on the indicator icon, or in the Hits or
BC column for the line of interest. This brings up detailed coverage information for that line in
the Coverage Details window.
For example, when you select an expression in the Missed Expressions window, and you click
in the column of a line containing an expression, the associated truth tables appear in the
Coverage Details window. Each line in the truth table is one of the possible combinations for
the expression. The expression is considered to be covered (gets a green check mark) only if the
entire truth table is covered.
When you hover over statements, conditions or branches in the Source window, the Hits and BC
columns display the coverage numbers for that line of code. For example, in Figure 17-14, the
blue line shows that the expression (a && b) was hit 5 times and that the branch (if) was
evaluated as true once (1t) and false four times (4f). The value in the Hits column shows the
total coverage for all items in the UDP table (as shown in the Coverage Details window when
you click the specific line in the hits column).
Coverage data presented in the Source window is either calculated “by file” or “by instance”, as
indicated just after the source file name. If coverage numbers are mismatched between Missed
<coverage_type> window and the Source window, check to make sure that both are being
calculated the same — either “by file” or “by instance”.
To display only numbers in Hits and BC columns, select Tools > Code Coverage > Show
Coverage Numbers.
When the source window is active, you can skip to "missed lines" three ways:
• select Edit > Previous Coverage Miss and Edit > Next Coverage Miss from the menu bar
• click the Previous zero hits and Next zero hits icons on the toolbar
• press Shift-Tab (previous miss) or Tab (next miss)
Coverage Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
• Hide/Show coverage data — Toggles the Hits column off and on.
• Hide/Show branch coverage — Toggles the BC column off and on.
• Hide/Show coverage numbers — Displays the number of executions in the Hits and
BC columns rather than check marks and Xs. When multiple statements occur on a
single line an ellipsis ("...") replaces the Hits number. In such cases, hover the cursor
over each statement to highlight it and display the number of executions for that
statement.
• Show coverage By Instance — Displays only the number of executions for the
currently selected instance in the Main window workspace.
Related Topics
Source Window Code Coverage Indicator Icons.
Breakpoints
You can set a breakpoint on an executable file, file-line number, signal, signal value, or
condition in a source file. When the simulation hits a breakpoint, the simulator stops, the Source
window opens, and a blue arrow marks the line of code where the simulation stopped. You can
change this behavior by editing the PrefSource(OpenOnBreak) variable.
Note
When running in full optimization mode, breakpoints may not be set. Run the design in non-
optimized mode (or set +acc arguments) to enable you to set breakpoints in the design.
Refer to Preserving Object Visibility for Debugging Purposes and Design Object Visibility for
Designs with PLI.
Related Topics
Setting GUI Preferences.
Procedure
1. Enter a bp command at the command line. For example, entering
bp top.vhd 147
Editing Breakpoints
There are several ways to edit a breakpoint in a source file.
• Select Tools > Breakpoints from the Main menu.
• Right-click a breakpoint in your source file and select Edit All Breakpoints from the
popup menu.
• Click the Edit Breakpoints toolbar button from the Simulate Toolbar.
Using the Modify Breakpoints Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Deleting Individual Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Deleting Groups of Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
3. Fill out any of the following fields to edit the selected breakpoint:
• Breakpoint Label — Designates a label for the breakpoint.
• Instance Name — The full pathname to an instance that sets a SystemC breakpoint
so it applies only to that specified instance.
• Breakpoint Condition — One or more conditions that determine whether the
breakpoint is observed. If the condition is true, the simulation stops at the
breakpoint. If false, the simulation bypasses the breakpoint. A condition cannot refer
to a VHDL variable (only a signal). Refer to Setting Conditional Breakpoints for
more information.
Tip
: These fields in the File Breakpoint dialog box use the same syntax and format
as the -inst switch, the -cond switch, and the command string of the bp
command. For more information on these command options, refer to the bp
command in the Reference Manual.
The write format restart command creates a single .do file that saves all debug windows,
file/line breakpoints, and signal breakpoints created using the when command.The file
created is primarily a list of add list add wave, and configure commands, though a few
other commands are included. If the ShutdownFile modelsim.ini variable is set to this
.do filename, it will call the write format restart command upon exit.
To restore debugging windows and breakpoints enter:
do <filename>.do
Note
Editing your source file can cause changes in the numbering of the lines of code.
Breakpoints saved prior to editing your source file may need to be edited once they
are restored in order to place them on the appropriate code line.
Related Topics
do
The conditional breakpoint examples below refer to the following SystemVerilog source code
file source.sv:
1 class Simple;
2 integer cnt;
3 integer id;
4 Simple next;
5
6 function new(int x);
7 id=x;
8 cnt=0
9 next=null
10 endfunction
11
12 task up;
13 cnt=cnt+1;
14 if (next) begin
15 next.up;
16 end
17 endtask
18 endclass
19
20 module test;
21 reg clk;
22 Simple a;
23 Simple b;
24
25 initial
26 begin
27 a = new(7);
28 b = new(5);
29 end
30
31 always @(posedge clk)
32 begin
33 a.up;
34 b.up;
35 a.up
36 end;
37 endmodule
Note
You must use the +acc switch when optimizing with vopt to preserve visibility of
SystemVerilog class objects.
Results
The simulation breaks at line 13 of the simple.sv source file (Figure 17-17) the first time module
a hits the expression because the breakpoint is evaluating for an id of 7 (refer to line 27).
in the Breakpoint Condition field of the Modify Breakpoint dialog box. (Refer to
Figure 17-16) Note that the file name and line number are automatically entered.
Results
The simulation evaluates the expression at line 13 in the simple.sv source file (Figure 17-17),
continuing the simulation run if the breakpoint evaluates to false. When an instance evaluates to
true the simulation stops, the source is opened and highlights line 13 with a blue arrow. The first
time cnt=8 evaluates to true, the simulation breaks for an instance of module Simple b. When
you resume the simulation, the expression evaluates to cnt=8 again, but this time for an instance
of module Simple a.
Note
Run Until Here will not execute if you are running a fully optimized design. You
must run the simulation in non-optimized mode or set +acc arguments to enable you
to execute Run Until Here. Refer to Preserving Object Visibility for Debugging
Purposes and Design Object Visibility for Designs with PLI.
To specify Run Until Here, right-click on the line where you want the simulation to stop and
select Run Until Here from the pop up context menu. The simulation starts running the
moment the right mouse button releases.
The simulator run length is set in the Simulation Toolbar and specifies the amount of time the
simulator will run before stopping. By default, Run Until Here will ignore the time interval
entered in the Run Length field of the Simulation Toolbar unless the
PrefSouce(RunUntilHereUseRL) preference variable is set to 1 (enabled). When
PrefSource(RunUntilHereUseRL) is enabled, the simulator will invoke Run Until Here and
stop when the amount of time entered in the Run Time field has been reached, a breakpoint is
hit, or the specified line of code is reached, whichever happens first.
For more information about setting preference variables, refer to Setting GUI Preferences.
The Causality Traceback feature is designed to help you determine the cause of any signal event
or all possible drivers of a signal. It allows you to trace backward through simulation time to
find both event drivers and the logic behind the drivers. Causality Traceback uses the Questa
SIM optimization utility to detect combinatorial and sequential logic events, and saves data
about those events to your working library in a .dbg file. The .dbg file is a connectivity and
structure database that can be used for current simulation and post simulation analysis.
After a causality trace is complete, the design context is automatically changed and all signals
found in the trace are selected. You may view details of the trace in the Wave, Source, Objects,
Schematic, Structure, and Active Driver Path Details windows. These windows are
automatically updated with the latest trace results when the trace is complete.
During a trace analysis it is possible that multiple input values are changing at the same time.
When this occurs, “Multiple Drivers” will be indicated momentarily in the Show Drivers
control bar of the Source window and the number of drivers will be displayed.
Procedure
1. Create a library for your work.
vlib <library_name>
3. Optimize your design and collect combinatorial and sequential logic data.
vopt +acc <filename> -o <optimized_filename> -debugdb
The +acc switch maintains visibility into your design for debugging while the -debugdb
switch saves combinatorial and sequential logic events to the working library. All +acc
options are executed even when a -debugdb option is included.
4. Load your design (elaboration).
vsim -debugdb <optimized_filename>
The -debugdb switch instructs the simulator to look for combinatorial and sequential
logic event data in the working library, then creates the debug database (vsim.dbg) from
this information.
The default filename for the .dbg file is vsim.dbg. If you want to create a different name,
use the following command syntax:
vsim -debugdb=<custom_name>.dbg -wlf <custom_name>.wlf
<optimized_filename>
The <custom_name> must be the same for the .dbg file and the .wlf file.
5. Log simulation data.
log -r /* or add wave -r /*
It is advisable to log the entire design. This will provide the historic values of the events
of interest plus its drivers. However, to reduce overhead, you may log only the regions
of interest.
You may use the log command to simply save the simulation data to the .wlf file; or, use
the add wave command to log the simulation data to the .wlf file and display simulation
results as waveforms in the Wave window.
6. Run the simulation.
7. Initiate a causality trace from the command line or from the GUI.
8. Steps for Abbreviated Database Creation
You may abbreviate the database creation procedure with the steps that follow.
However, this abbreviated procedure does not give you the control over the optimization
process provided by the recommended procedure above.
The -voptargs=”+acc” switch for the vsim command maintains visibility into your
design for debugging, and the -debugdb switch performs a pre-simulation analysis of
the sequential and combinatorial elements in your design. The -debugdb switch
generates the required debug information for schematic analysis.
d. Log your design
log -r /* or add wave -r /*
Procedure
1. Use the find drivers command to initiate a causality trace.
2. You can interrupt the various “find drivers” operations by using the Escape key.
Related Topics
find drivers
Post-sim Debug
If you have logged the design, you can perform post-simulation Causality Traceback.
Simply open the library (directory) containing the saved .wlf file and enter the following
command:
If you have used a custom filename for the .dbg and .wlf files, use:
You may also use the dataset open command if you are entering the command from within
Questa SIM.
You can initiate a causality trace from any arbitrary time by selecting Show Cause from Time,
Show Driver from Time, or Show Root Cause from Time in the toolbar button menu above.
You may also use the time indicator in the Source window to set a starting time for the causality
trace.
Note
The Show Cause and Show Root Cause options will display a warning if you simulate with
the -novopt switch. You will only have access to the Show Driver option in the Source
window. Full causality traceback functionality requires optimization of your design with vopt or
vsim -voptargs. Refer to Creating a Database for Causality Traceback for more information.
Procedure
1. Select a signal of interest in the Wave window.
2. Perform either one of the following actions:
• Double-click (left mouse button) an event of interest in the waveform of the selected
signal.
Or,
• Click an event of interest in the waveform of the selected signal, then click the
Event Traceback toolbar button.
Either of these actions initiates a trace to find the sequential process(es) that caused the
selected event.
Results
When the causality trace ends, an annotated Source window opens with the causal process
highlighted (Figure 18-2). The Show Drivers Control Bar indicates how many drivers there are
for the event of interest. In this example, there is only one driver.
Click the Control Bar to display a drop-down menu that shows the driver (Figure 18-3), or a list
of drivers if there are multiple drivers (see Multiple Drivers).
Figure 18-3. Click to Show Drivers Control Bar to See Driver(s)
You can also display information about the sequential process(es) that caused the selected event
by opening the Active Driver Path Details window. To open this window, click and hold the
Event Traceback toolbar button and select View Path Details from the drop-down menu
(Figure 18-1). The Active Driver Path Details window (Figure 18-4) displays the selected
signal name, the time of each process in the causality path to the first sequential process, and
details about the location of the causal process in the code.
An active cursor named “Trace” is added to the Wave window at the time of the process that
caused the selected event. The time from the causal process to the selected event is displayed as
the relative time between the cursors (Figure 18-5).
Figure 18-5. Active Cursor Show Time of Causal Process
and the causal signal is highlighted in the Objects window (Figure 18-7).
Figure 18-7. Causal Signal Highlighted in the Objects Window
The Transcript window displays the command line equivalent of the GUI actions:
find drivers -source -time {<time>} -cause <signal>
Prerequisites
Run the simulation.
Procedure
1. Click the time indicator and select Set Current Time to open the Enter Value dialog
box (Figure 18-9).
2. Change the value to the starting time you want for the causality trace.
3. Click the OK button.
Figure 18-9. Enter an Event Time Value for Causality Tracing
4. To initiate a causality trace from the Source window simply double-click a signal of
interest, or do the following:
• Highlight a signal of interest in the Source window.
• Right-click anywhere in the Source window to open a popup menu.
5. Select Event Traceback > Show Cause in the popup menu to initiate a causality trace.
Figure 18-10 shows the selection in the Source window’s right-click popup menu.
Results
When the trace is complete, the Source window jumps to the assignment code that caused the
event and highlights the code, and the Objects window highlights all signals in the path. You
may open the Active Driver Path Details window to display all signals in the causality path.
Procedure
1. Select a signal.
2. Perform one of the following actions:
• Click the Event Traceback button in the Simulate Toolbar.
Or,
• Right-click anywhere in either window and select Event Traceback > Show Cause
from the popup menu.
Results
When the trace is complete, the Active Driver Path Details window displays all signals in the
causality path, the Objects window highlights all signals in the path, and the Source window
jumps to the assignment code that caused the event and highlights the code.
Procedure
1. Double-click the waveform trace of the signal of interest in Wave window.
This will open an annotated Source window with the driving process highlighted. The
Show Drivers Control Bar at the top of the Source window shows how many drivers
there are (Figure 18-11).
Figure 18-11. Source Window - Show Drivers Control Bar
You can also trace to the immediate driving process(es) using the Event Traceback
toolbar button or by right-clicking the Wave window and using the popup menu. The
immediate driving process may be a combinatorial or sequential assignment.
2. After the simulation, click a signal of interest in the Wave window. Click on the selected
signal’s waveform to place an active cursor at an event of interest.
• Right-click anywhere in the waveform pane and select Event Traceback > Show
Driver from the popup menu (Figure 18-13). The time shown in parenthesis is the
time at which the causality trace will start.
Figure 18-13. Right-click Menu – Show Driver
Causality Traceback examines the .dbg database for the immediate driving
process(es) of the selected signal event, then opens a Source window with the code
of the driving process(es) highlighted (Figure 18-2).
4. Open the Active Driver Path Details window by clicking and holding the Event
Traceback toolbar button, the selecting View Path Details from the drop-down menu.
The Active Driver Path Details window shows the selected signal name, the start time of
the causality trace (At time), the time of the driving process, and details about the
driving process (Figure 18-14).
The Transcript window displays the command line equivalent of the GUI actions.
find drivers -source -time {<time>} <signal>
Procedure
1. Select a signal of interest in the Wave window.
2. Click the selected signal’s waveform at any point to place a cursor there. The time of
this cursor is the start time of the causality trace.
3. Initiate a root cause trace using either of the following methods:
• Right-click anywhere in the waveform pane and select Event Traceback > Show
Root Cause from the popup menu.
• Click and hold the Event Traceback button until the drop-down menu appears, then
select Show Root Cause from the menu.
• If you have performed a trace to the first sequential process (Show Cause), or a trace
to the immediate process (Show Drivers), you can then initiate a trace to the root
cause from the Active Driver Path Details window. Simply click the Trace to Root
Cause button to find the root cause of the event of interest.
Results
The Active Driver Path Details window displays a list of all the signals linked from the root
cause to the event of interest, as shown in Figure 18-15.
Figure 18-15. Trace Event to Root Cause
The Source window jumps to the root cause source code and highlights the relevant line
(Figure 18-16).
Figure 18-16. Root Cause Highlighted in Source Window
The Transcript window displays the command line equivalent of the GUI actions:
find drivers -source -time {<time>} -root <signal>
The -root switch for the find drivers command initiates the trace to the root cause of the selected
event.
Procedure
1. Select a signal of interest that has an unknown ‘X’ value.
2. Click and hold the Event Traceback button until the drop-down menu appears.
3. Click “Show ‘X’ Cause (ChaseX)” as in Figure 18-17.
Figure 18-17. Show X Cause
Or, you may use the -chasex switch with the find drivers command.
Procedure
1. Select a signal of interest in the Wave window or Source window.
2. Click and hold the Event Traceback button until the drop-down menu appears.
3. Select Show All Possible Drivers from the drop-down menu (Figure 18-18).
This action will display all possible driving assignments of the selected signal
(Figure 18-19) in the Source window Show Drivers Control Bar without regard to the
time of any particular signal event. Refer to Multiple Drivers for more information.
Figure 18-19. Possible Drivers in the Source Window
4. The Transcript window displays the command line equivalent of the GUI actions:
find drivers -possible <signal>
5. The -possible switch for the find drivers command initiates the search for all possible
driving assignments of the selected signal.
Prerequisites
Run the simulation.
Procedure
1. Click and hold the Show Cause button until the drop-down menu appears
(Figure 18-20).
Figure 18-20. Selecting a Specific Time for a Trace
2. Enter a starting time for the causality trace and click the OK button.
Multiple Drivers
Depending on the complexity of the design, some signal events may be driven by multiple
processes. The number of drivers will be shown in the Show Drivers Control Bar at the top of
the Source window.
There are four buttons in the Show Drivers Control Bar: 1) the History button, 2) the List Menu
button, 3) the Previous button, and 4) the Next button (Figure 18-22).
In Figure 18-22, the Show Drivers Control Bar displays “1/12 Drivers” to indicate that the first
of twelve drivers is selected. When you click the List Menu button, a menu drops down showing
all drivers with a checkmark beside the selected driver, which is highlighted in the Source
window (Figure 18-23).
You can jump directly to the source code of any other driver in the list by simply clicking it. Or,
use the Previous and Next buttons to navigate through the list of drivers.
The History button allows you to review past Show Drivers operations (Figure 18-24). Click an
item in the list to return to a previous operation.
By default, the drivers shown in the List Menu only include the instance path and the source
text. But the List Menu contains three viewing options that allow you to: Include Process
Names, Include Line Numbers, and Include File Name. Clicking the option toggles it on or off.
Figure 18-25 is an example of the List Menu with all three viewing options displayed.
The driver List Menu in Figure 18-26 shows two drivers. Driver #1 is displayed in black and
driver #2 is in blue. The blue color of driver #2 indicates that the instance path (in this case, /
test1/u1) is different from the starting point (which is /test1/ref_req). When the driver is
displayed in black, it means it has not left the instance it started in.
You can double-click any variable in the Source window to produce a list of drivers in the Show
Drivers Control Bar.
When you click the Schematic Window button, a dedicated Schematic (Path Details) window
opens (Figure 18-28). It displays the causality path in the top half of the window (the schematic
in the Incremental view) and lists all causality path signals in the bottom half (the Wave viewer)
of the window. The causality path, from the beginning of the trace to the end, is highlighted in
red in the schematic.
When you perform another causality trace, all signals contained in the path found by the new
trace are added to the previous trace in the schematic.
In the Wave viewer (Figure 18-28), a cursor named “Trace Begin” marks the beginning of the
causality trace; a “Trace End” cursor marks the end of the trace. In the Schematic view, the path
of the trace is highlighted in red.
When you select a signal in the Wave viewer portion of the Schematic window, the signal is
highlighted in the schematic. You can click through the signals in the Wave view to explore the
connectivity of the causality path in the schematic view.
The times displayed in the Path Times bar, at the bottom left of the Schematic view, correspond
to the times found during the trace. The Path Times bar also includes a “Start” and an “ALL”
label. The times, Start, and ALL labels are clickable and will perform the following actions:
• Click a time to see the signals that were changing at the selected time highlighted in red.
Signals that changed at a prior traced time (if one exists) are highlighted in green.
• Click Start to see the signal used to run the trace highlighted in red.
• Click ALL to see all signals identified during the trace highlighted in red.
For example, Figure 18-29 shows what happens when time “810” is selected. Signals that were
changing at the selected time are red and those that changed a prior traced time are green.
Notice that the selected time in the Path Times bar is underlined in red to emphasize that it is the
selected time. In addition, the Current Time label in the upper right hand corner displays the
selected time.
You can close the Path Times bar by clicking the X button in the bar. To reopen the bar, click
the right mouse button to open a popup menu and select Event Traceback > View Path Times.
Note
The Path Times bar is only displayed in the dedicated Schematic (Path Details) window that
results from a causality trace.
Returning to the Active Driver Path Details window (Figure 18-4), when you click the Wave
Window button a dedicated Wave window opens that will include “(Path Details)” as part of its
title (Figure 18-30). This Wave window lists each signal in the path of the causality trace and
includes “Trace Begin” and “Trace End” cursors. When you perform another trace, this
dedicated window is updated with signals in the path of the new trace, with updated “Trace
Begin” and “Trace End” cursors.
This will open the Causality Trace Options dialog box (Figure 18-32).
Other Options
• You may elect to highlight the active drivers of a signal from all possible drivers.
• You may elect to have Causality Traceback ask before doing a causality path trace if the
current time differs from the time of the last completed trace.
• You can choose to have a warning issued if the design was simulated without the
-debugdb option and a debugging database is not available. Refer to Creating a
Database for Causality Traceback for more information about the vsim -debugdb
option.
• You can choose the default window to show the results of a trace:
a. Source Window — (default) Opens with the causal process highlighted.
b. Schematic Window — Opens with the causal path displayed and a Wave pane
showing the driving signal waveforms. Refer to Causality Path Details for more
information.
c. Wave Window — opens a new Wave window populated with the driving signal(s)
and waveforms.
Code coverage is the only verification metric generated automatically from design source in
RTL or gates. While a high level of code coverage is required by most verification plans, it does
not necessarily indicate correctness of your design. It only measures how often certain aspects
of the source are exercised while running a suite of tests.
Missing code coverage is usually an indication of one of two things: either unused code, or
holes in the tests. Because it is automatically generated, code coverage is a metric achieved with
relative ease, obtained early in the verification cycle. 100% code coverage can be achieved even
for designs containing impossible to achieve coverage (because of sections containing unused
code) by using a sophisticated exclusions mechanism (see “Coverage Exclusions”). Code
coverage statistics are collected and can be saved into the Unified Coverage DataBase for later
analysis.
For condition and expression coverage datatype support, see “Condition and Expression
Coverage”.
For FSM coverage datatype support, see “Finite State Machine Coverage”.
Code coverage is not collected on any code that is run at elaboration time (loading the design).
An example of such code might be a constant function that calculates the array range of a vector
signal.
Tip
Design units compiled with -nodebug are ignored by coverage: they are treated as if they
are excluded. However, toggle coverage of ports compiled with -nodebug is supported if
and only if -nodebug is used without any options. For example, options like
“-nodebug=ports” will disable toggle coverage.
The basic flow for collecting code coverage in a Questa SIM simulation is as follows:
The vlog (or vcom, if design is VHDL) command compiles the specified files. The vopt
command performs global analysis and optimizations on the design. The -o specifies the
output name for the optimized version of the design. The +cover argument to the vopt
command designates all coverage types for collection.
You may wish to apply coverage arguments differently, depending on whether you want
to collect coverage for a specific source file, or just a module/sub-module, or the entire
design. See “Specifying Coverage Types for Collection” for coverage application
options.
2. Enable coverage collection during simulation:
vsim -coverage opttop
Coverage is enabled for the entire design using the optimized design opttop. See
“Enabling Simulation for Code Coverage Collection” for further details.
3. Optionally, you can save the collected information for post-process viewing and
analysis:
coverage save -onexit top.ucdb
This command saves the coverage data at the end of simulation, in the current directory
in top.ucdb. See “Saving Code Coverage in the UCDB” for a list of all methods for
saving data to a UCDB.
4. Run simulation with coverage enabled:
run -all
• specific source files in the design — by supplying the +cover arguments to vcom or
vlog during compile:
vlog top.v proc.v cache.v +cover=bcesfx -coveropt 1
• specific modules or instance of design —by supplying the +cover arguments to vopt,
using the +<selection> modifier to designate the desired design units or instances:
vlog top.v proc.v cache.v
vopt -o top_opt +cover=bcesxf+moduleA +cover=st+/top/proc/cache
vsim -coverage top_opt
or by supplying the +cover arguments using vsim -voptargs (when not specifically using
vopt):
vlog top.v proc.v cache.v
vsim -coverage top -voptargs="+cover=bcesfx”
This union of arguments does not apply to the optimization number specified with -coveropt <1-
5> to vcom, vlog, or vopt (see “CoverOpt” for details on -coveropt levels). In this case, any
optimization level applied to a design unit or module takes precedence over the globally
specified -coveropt level.
Related Topics
Code Coverage in the UCDB
Related Topics
vcom
vlog
vopt
Procedure
1. CLI command: Use the -coverageargument to vsim. For example,
vsim -coverage work.top
2. GUI: Simulate > Start Simulation > Others > Enable Code Coverage check box.
Often, users simulate designs multiple times, with the intention of capturing different coverage
data from each test for post-process viewing and analysis. When this is the case, the naming of
the tests becomes important.
By default, for non-UVM/OVM tests, the name Questa SIM assigns to a test is the same as the
UCDB file base name. For UVM/OVM tests, the default name assigned to a test is the UVM or
OVM testname. In either case, if you fail to name the test you run explicitly, you can
unintentionally overwrite your data.
To explicitly name a test before saving the UCDB, use a command such as:
coverage save -testname <mytestname>
The name you enter (<mytestname>), can only be comprised of alphanumeric characters and
the underscore character (_).
While viewing results in Coverage View mode, you can make changes to the data (using
the coverage attribute command, for example). You can then save the changed data to a
new file using the following command:
coverage save myfile2.ucdb
To save coverage results only for a specific design unit or instance in the design, use a
command such as:
coverage save -instance <path> ... <dbname>
The resulting UCDB, <dbname>.ucdb, contains only coverage results for that instance,
and by default, all of its children.
• SystemVerilog System Tasks and Functions (captures code coverage only):
$coverage_save (not recommended)
$coverage_save_mti (not recommended)
If more than one method is used for a given simulation, the last command encountered takes
precedence. For example, if you issue the command coverage save -onexit vsim.ucdb, but your
SystemVerilog code also contains a $set_coverage_db_name() task, with no name specified,
coverage data is not saved for the simulation.
where b_test is the <filename> name that would otherwise used, by default, for the
output coverage UCDB.
3. The resulting coverage database is named c_test.ucdb.
All directory paths in the -coverstore argument should be the same for all the simulation
runs in a regression, as should the design hierarchy.
2. Merge all the coverage data accumulated in the coverstore using the path to the directory
as an input to the merge:
vcover merge -out <output_ucdb> <coverstore_directory_path>
The purpose of saving raw coverage merge output data from vcover merge is to take
advantage of fast merging in a hierarchical merge flow where an input to the current
merge operation is the output of a previous merge.
Such hierarchical flows are typically used to parallelize merging of coverage data
generated from a large number of tests in a regression. The parallel merge applications
take advantage of this mechanism when merging coverstores. The output coverstore
contains the same design shape as the input coverstore, with the individual tests replaced
by a merged data record index. For example:
vcover merge -outputstore merged1_out coverstore1
vcover merge -outputstore merged2_out coverstore2
...
vcover merge -out merged_final.ucdb merged1_out merged2_out ... mergedN_out
The last vcover merge command merges the coverage and design data that was output
from lower level merges. The performance gain is realized from the merging of that
data, rather than the self-contained UCDB files.
4. Optionally, you can choose to merge a user selected subset of tests in a coverstore into a
self-contained merged UCDB. Do this by specifying a comma separated list of test
names after the coverstore name, using the ':' as a separator. The command would be
similar to:
vcover merge -out <output_ucdb>
<coverstore_directory_path>[:<testname>[,<testname>]*]
The following are example commands valid for merging user selected tests from coverstore
area:
Note that using a coverstore approach, the merge performs a perfect merge for static coverage
items (code coverage). A design level signature is used to verify whether the static coverage bin
counts present in a coverstore are in sync or not. If so, then there is no mismatch at all between
coverage items, and the merge is considered “perfect”. If there is a mismatch between any
coverage items, the merge won't proceed, which lets you know that the coverstore flow cannot
be used.
For functional coverage items, a union merge algorithm is used, as the functional coverage
content may vary within a regression run. A coverstore is able to cope with these variations
within functional coverage shapes or models, but code coverage shapes or models must match
exactly.
However, you may be relying on the integer counts for other sorts of analysis. Particularly,
covergroup, toggle, and FSM transitions may require more than single-bit counts. In order to
enable full counting, the -multicount option can be used.
Example:
In this example, single bit counting is in effect for all coverage kinds except assertions, cover
directives, fsms and toggles. See the vsim command -multicount argument for syntax details.
Related Topics
vsim -coverstore and -viewcov arguments
vcover merge and other vcover commands
• Analyze coverage statistics in the GUI, either interactively with an active simulator, or
in a post-processing mode with vsim -viewcov (see “Usage Flow for Code Coverage
Collection”)
• Run and view reports on the collected code coverage data (see “Coverage Reports”)
• Exclude certain data from the coverage statistics (see “Methods for Excluding Objects”)
• View, merge, and rank sets of code coverage data without elaboration of the design or a
simulation license.
You can also merge test data with a verification plan.
Related Topics
Code Coverage Types
Coverage Exclusions
Coverage Reports
Coverage and Verification Management in the UCDB
Calculation of Total Coverage
Verification Management Users Manual
The coverage data in the Code Coverage Analysis window is displayed “by instance” or “by
file” depending on whether the “sim” tab (Structure window) or “Files” tab is active.
Additional Code Coverage Data is displayed in the Object, Source, and Structure windows. To
view coverage data in the Objects window, right click anywhere in the column title bar and
select Show All Columns from the popup menu. When you double-click and item in the Code
Coverage Analysis window or the Objects window, it will open a Source window with the
selected item highlighted. For details, see Table 19-1.
All subprograms - Verilog tasks and functions as well as VHDL subprograms - are displayed in
the Structure window. Since VHDL allows multiple subprograms of the same name but
different arguments, in the same hierarchical scope, the argument signature (list of arguments
and their types) is displayed along with the subprogram name in order to differentiate
overloaded subprogram names. The signature appears in the “design unit” column instead of the
design unit name.
The Instance Coverage window also displays subprograms, as well as instances, and their
respective code coverage data.
You can also write coverage statistics in different text and HTML reports (see “Coverage
Reports”). You can save raw coverage data to a UCDB (see “Code Coverage in the UCDB”)
and recall, or merge it with coverage data from previous simulations.
Statement Coverage
Statement coverage is the most basic form of coverage supported by Questa SIM. The metric
for statement coverage is the count of how many times a given statement is executed during
simulation.
Multiple statements may be present on a single line of HDL source code. Each such statement is
processed independently of other statements on the same line. Statement coverage counts are
prominently displayed in the Source window. They are present in most of the other coverage
windows as well.
Statement coverage statistics for“for” loops are presented using two separate entries relating to
one line of code: the first entry is the number of times the “for” statement was entered, while the
second is the number of times the loop was repeated. Consider the following statement
displayed in a coverage report:
The statement on line 31 displays counts in two entries: the count “1” refers to how many times
the loop was entered, the count “2” refers to how many times the loop was repeated.
Branch Coverage
Branch coverage is related to branching constructs such as “if” and “case” statements. True
branch and “AllFalse” branch execution are measured.
In order to achieve 100% branch coverage, each branching statement in the source code must
have taken its true path, and every AllFalse branch must have been taken.
module top;
integer i=10;
initial begin
#3 i = 18;
#3 i = 2;
#1 $finish();
end
always @ (i) begin
if (i == 16)
$display("sweet");
else if (i == 2)
$display("terrible");
else if (i == 10)
$display("double digits at last");
else if (i == 18)
$display("can vote");
else
$display("just another birthday"); end endmodule
When this example is run to completion and the branch coverage is collected and saved to
top.ucdb, the “vcover report top.ucdb -details” command produces the following report:
File: top.v
Branch Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Branches 5 3 2 60.0
==============================Branch Details=============================
------------------------------------IF Branch----------------------------
12 3 Count coming in to IF
12 1 ***0*** if (i == 16)
14 1 1 else if (i == 2)
16 1 1 else if (i == 10)
18 1 1 else if (i == 18)
20 1 ***0*** else
Branch totals: 3 hits of 5 branches = 60.0%
The 60% coverage number is derived, in that five bins under the initial 'if' have been inferred —
1 ‘if’ branch, 3 'else if' branches, and 1 'else' branch. Three of these branches were executed.
If the final 'else' had not been present in the example, the coverage score would remain the
same, but instead of listing an 'else' count, the report would list an 'All False Count' value of 0.
The second column indicates the item numbers of that coverage type on the line. There is only
one coverage item of that type on each line of the example report above, so the number is 1 in
each line.
Related Topics
Branch Coverage
Missing Branches in VHDL and Clock Optimizations
Case and Branches
AllFalse Branches
In order to gain more coverage detail on the HDL expressions used in branching statements, the
Condition and Expression Coverage features may be used
Related Topics
Branch Coverage
Condition and Expression Coverage
Missing Branches in VHDL and Clock Optimizations
Branch Coverage Examples
AllFalse Branches
AllFalse Branches
For “if” statements without a corresponding “else”, an implicit branch known as the “AllFalse”
branch is measured. If the “if” condition is executed and found to be false, the “all false” branch
is considered to be hit.
By default, Allfalse branches are designated in the coverage report with “ECOP” if the branch
was not hit, “E-hit” if hit, indicating that it was excluded because of the “clock optimization”.
This optimization can be turned off using the -noclkoptbuiltins argument to the vsim command.
the AllFalse branch is hit when “fsel” is not equal to “10” or “11”. In the following Verilog
example:
You can exclude an AllFalse branch from participation in branch coverage using the -allfalse
argument to a pragma exclusion or by using the coverage exclude command.
Code coverage includes an all false bin for Verilog case statements that do not contain a
“default” clause. Coverage reports and the GUI will show the case all false data similar to the
way if statement all false data is shown. Case statement all false branches can be excluded also
in a similar manner. Also, if the CoverExcludeDefault variable in the modelsim.ini file is used
to exclude case statement default clauses, it will also exclude case statement all false branches.
Related Topics
coverage exclude
Exclude Implicit (AllFalse) Branches
coverage on and coverage off Pragma Syntax
Exclude AllFalse Branches in Case Statements
You can turn off clock optimization in the VHDL code by compiling the design with the
CoverClkOptBuiltins modelsim.ini variable set to 0, or with the vcom/vlog -nocoverclkbuiltins
argument.
Related Topics
coverage exclude
Exclude Implicit (AllFalse) Branches
coverage on and coverage off Pragma Syntax
Exclude AllFalse Branches in Case Statements
The topics related to condition and expression coverage are numerous and detailed. See each of
the following sections for complete information on these coverage types.
Sum-of-Products checks that each set of inputs that satisfies the expression (results in a
“1”) must be exercised at least once, but not necessarily independently.
• Basic Sub-Condition — based on UDP data
Basic sub-condition checks that each subexpression has been both true and false.
Tip
Expressions whose result is greater than one bit wide are not counted for coverage;
they are silently ignored. In other words, multi-bit signals are not supported for
expression coverage.
Related Topics
Condition and Expression Coverage
FEC and Short-circuiting
FEC Concepts
Reporting Condition and Expression Coverage
UDP Coverage Details and Examples
• By default, when coverage is enabled with the “+cover=ec” argument (where “=ec”
enables expression and condition coverage) to vcom, vlog, or vopt only FEC coverage
statistics are collected and reported.
o You can turn on/off FEC collection using the -coverfec and -nocoverfec argument
to vcom/vlog, or vopt.
o You can turn on/off UDP collection (off by default) using the -coverudp and
-nocoverudp argument to vcom/vlog, or vopt.
• Print condition and expression coverage truth tables in coverage reports by:
o GUI: Select Coverage Reports > Condition Coverage or Expression Coverage
(see “Coverage Reports”)
o Command Line: with coverage report -details. Works when one or more of the rows
has a zero hit count. To force the table to be printed even when an expression is
100% covered, apply the -all switch to the coverage report command.
or
vcover report -details
• The expression appearing in the FEC report is a canonical representation of the lexical
expression that appears in the original source code. Effects of the optimizer are taken
into account, which means the canonical expression will match perfectly with the
subexpressions and terms used in the rest of the report.
• The default level of effort for FEC or UDP expressions/conditions determines the
number of expressions or conditions which are considered for coverage. You can
customize the effort level for FEC/UDP using the -fecudpeffort argument to
vlog|vcom|vopt, or the FecUdpEffort modelsim.ini file variable.
vcom/vlog -coverudp
then
or
Related Topics
Condition and Expression Coverage
FEC and Short-circuiting
FEC Report Examples
FEC Concepts
FEC Concepts
FEC measures coverage for each input of an expression. If all inputs are fully covered, the
expression has reached 100% coverage. In FEC, an input is considered covered only when other
inputs are in a state that allow it to control the output of the expression. Further, the output must
be seen in both 0 and 1 states while the target input is controlling it. If these conditions occur,
the input is said to be fully covered. The final FEC coverage number is the number of fully
covered inputs divided by the total number of inputs. FEC calculation is fully compliant with
the more widely known MC/DC coverage metric (Multiple Condition/Multiple Decision).
Every expression, regardless of how complex it may be, can eventually be broken down into N
smaller expressions consisting of only one operator each, where N is the number of operators in
the expression. We call these expressions 'basic expressions'. Consider the following
expression:
The && operator groups from left-to-right, therefore this expression can be represented as:
a && EXPR1
b && EXPR2
c && EXPR3
where EXPR1 = ‘b && (c && d)’, EXPR2 = ‘c && d’, and EXPR3 = ‘d’
Once the basic expression has been identified, the evaluation only operates on the basic
expression, thus we don't care about the actual complex expression. When working on any input
in an expression, it is important for avoid it masking the other input because of its value. For
example, if we want to measure coverage of 'a' in 'a && b', it is important that the value of 'b' is
'1'. If 'b' is 0, the result of the expression gets fixed to '0' and the value of 'a' is no longer of any
significance.
Also, since the expression is evaluated left-to-right in the presence of short-circuiting (see FEC
and Short-circuiting), it is correct to only look at the right side of the concerned input. The
assumption is that if we are evaluating the concerned input, it means that its left side is already
in a non-masking state. For example, if we're evaluating 'b' in 'a && b && c', it means that 'a'
was already evaluated to '1'. Table 19-2 lists operators with non-masking states of inputs. In this
table, the coverage of 'A' is being collected in the expression.
Note
Instead of the lexical expression that appears in the original source code, the FEC reports
show the canonical representation.
1. Inverting mode — When setting the value of an input terminal to '0' (or '1') with all other terminals in their
quiescent states in an FEC row, evaluates the expression to '1' (or '0'), the input terminal is said to be working
in an inverting mode.
2. Non-Inverting mode — When setting the value of an input terminal to '1' (or '0') with all other terminals in
their quiescent states in an FEC row, evaluates the expression to '1' (or '0'), the input terminal is said to be
working in a non-inverting mode.
Examine the following FEC report table for the expression (a & b & c), when it receives input
vectors {101, 011, 111}:
• The first table reports coverage on a per-input basis. For inputs that are not covered, the
report gives a brief reason for the lack of coverage. The “Hint” column provides
information on how to get the input covered. In the FEC report above, input 'c' was not
covered because the coverage bin '_0' associated with this input (i.e. c_0) did not receive
any hits. The hint says that to get 'c' FEC covered, an input vector satisfying non-
masking condition for c_0 (i.e. (a & b), while c == 0) must be applied to this expression
during simulation.
• The second table goes a step deeper and expands each input into its coverage bins. The
table lists the Rows, Hits, FEC Target and
• Non-masking condition(s).
In the FEC report above, consider the first row containing the FEC Target (or bin) of a_0, where
a is the input and _0 is the value of that input. The full tag of a_0 indicates that this row delivers
FEC testing when a's value is 0. This bin was incremented since an input vector (011) satisfying
its Non-masking condition (c && b) was seen. By definition a is 0 for every Non-masking
condition on the a_0 list. Similarly, the input vector (111) satisfying the Non-masking condition
for a_1 - row 2 in the table - was also observed. Again, by definition, the a_1 Non-masking
conditions are identical to the a_0 except with the 'a' bit equal to 1. This is always the case for
each pair of FEC rows (non-short circuit logic only).
In walking through the truth table, you can see how FEC ensures that each input a, b, and c has
been shown to independently affect the expression output. For example, for the conditions of
FEC to be satisfied, when an a_0 input vector flips to the corresponding a_1 vector - i.e., only
bit 'a' changes to 1, with the other bits unchanged - the output value of the expression MUST
also change.
If FEC coverage indicates any bins are missed (such as c_0 in Row 3 of Example 19-3) you
know that none of your tests ever produced a value of ‘1’ when other inputs are in a state that
allows it to control the output. You should then work on the design/stimulus to improve FEC
coverage. One method of raising FEC coverage numbers is to modify test stimulus such that
input vectors satisfying Non-masking conditions of zero-hit rows appear at the expression's
inputs.
Examine the FEC report table for the expression ((~a & c) | (a & b & ~c & d) | (a & ~b & c & d))
when it receives input vectors {0100, 1001, 1111}.
As in the simple, unimodal case illustrated in Example 19-3, the first table reports coverage on a
per-input basis. In the FEC report above, input ‘b’ was not covered because both rows
corresponding to this input were hit for the same output value (i.e. ‘b’ changed but the output
didn't change).
The second table expands each input into its coverage bins. In the FEC report above, consider
the first row containing the FEC Target (or bin) of a_0, where ‘a’ is the input and ‘_0’ is the
value of this input. The hits have been divided based on the output of the expression when
applying the input pattern satisfying its Non-masking condition. This is done to ensure that
while qualifying an input terminal as FEC covered, it has been shown to independently control
the output while operating in one mode, i.e. making sure that it receives '_0' and '_1' hits for
different output values.
The bin corresponding to 'a_0' was incremented for output value 1, as an input vector satisfying
the non-masking conditions was seen. Similarly, an input vector satisfying non-masking
condition for a_1 - row 2 in the table - was observed for output 0. Since input 'a' receives hits in
both the '_0' and '_1' rows for different output values, 'a' is considered 100% FEC covered.
Even though input 'b' receives hits in both '_0' and '_1' rows, it is not considered FEC covered.
This is because both the rows are hit for the same output value (i.e. 0). In cases where an input is
not FEC covered, use the reason and hint to improve the test stimulus, or potentially modify the
design if a design issue is found.
Tip
: After spending some time with FEC tables for bimodal expressions, you can see that inputs
which are FEC covered have at least one non-zero value in both the "->0" and "->1"
columns. Any input with two '0's in a given column will be uncovered. It can be efficient to scan
down the ->0 and ->1 columns looking for strings of '0's, then concentrate on those inputs and
their matching input patterns.
Related Topics
Condition and Expression Coverage
FEC and Short-circuiting
Reporting Condition and Expression Coverage
FEC Concepts
patterns for '_0' and '_1' rows. The following example shows a FEC report table for the
expression (a && b && c) when it receives input vectors {001, 100, 111}:
Note the non-masking condition for row 1 in the above example. Once input 'a' has been
evaluated to '0', the evaluation of the other inputs is not required. Note the asymmetry in non-
masking conditions for rows 'a_0' and 'a_1'. They no longer similar.
There is a further difference from non-short circuit coverage: Covering each expression input
may require a different level of effort. To be FEC covered, input 'c' requires considerably more
precise stimulus vectors than input 'a'.
For example, in the following expression, if A has a value of '0', the term B || C will never be
evaluated:
Short-circuit evaluation remains in effect per LRM rules when coverage is enabled.
You may want to analyze the coverage results when short-circuit evaluation is turned off, and
all terms in an expression are considered in an evaluation. To achieve this effect, use the
-nocovershort argument to vlog/vcom/vopt. Generally, expression and condition coverage
percentages are lower when short-circuit evaluation is active, since, on average, fewer inputs
are considered when evaluating expressions and conditions.
A brief short-circuit status is given in the Details window and the text coverage report for each
condition and expression.
Related Topics
Condition and Expression Coverage
Reporting Condition and Expression Coverage
FEC Report Examples
FEC Concepts
For this example, the input vectors applied to the expression were 0100, 1101 and 1000. Rows 2
and 7 of the FEC table could be excluded using a pragma exclusion such as:
#1 tempreg2 <= ((~a & c) | (a & b & ~c & d) | (a & ~b & c & d));
Note that instead of excluding these rows using a pragma, row 2 and 7 of this expression could
have been excluded using the coverage exclude command. Assuming that the expression was
defined on line 28 in a file called adder64.v, the coverage exclude command would be:
In this example, excluding the row corresponding to 'a_1' (row 2) breaks its pair with 'a_0'.
Input terminal 'a' is now considered covered irrespective of whether 'a_0' is hit for output '0' or
'1'. Similarly, input terminal 'd' is considered fully covered when 'd_1' is hit.
Example 19-5. Simple Expression - Pre-10.3 Style Report for FEC Coverage
During evaluation of a condition or expression, a truth table is constructed and counts are kept
for each row of the truth table that occurs. UDP truth tables are composed of columns that
correspond to each input of the targeted condition or expression. The right-most column
corresponds to the expression’s output value. The table rows correspond to combinations of
input and output values.
Values can be ‘0’, ‘1’, or ‘-‘ (don’t-care). ‘Z’ values are automatically excluded. Also
automatically excluded are rows corresponding to ternary expressions where the two data inputs
are the same and the select input is “don’t care”. The vlog, vopt or vsim -noexcludeternary
command argument can be used to override this automatic exclusion from coverage.
When the simulator evaluates an expression, each UDP row is examined. If the current values
match the given row, the row is said to be hit, and its hit count increments. If all rows have non-
0 hit counts, the expression or condition has reached 100% coverage.
Examples
An example of UDP coverage for conditions is shown in Example 19-6; with a condition with
vectors in Example 19-7; and Example 19-8 shows an example of UDP expression coverage.
Row 1 indicates that (a or b) is true if a is true, no matter what b is. The “counts” column
indicates that this combination has executed 5 times. The '-' character means “don't care.”
Likewise, row 2 indicates that the result is true if b is true no matter what a is, and this
combination has executed zero times. Finally, row 3 indicates that the result is always zero
when a is zero and b is zero, and that this combination has executed 8 times. The unknown row
indicates how many times the line was executed when one of the variables had an unknown
state.
If more than one row matches the input — as is the case in the example with an input vector
{1,1}) — each matching row (in this case, Row 1 and 2) is counted. If you would prefer no
counts to be incremented on multiple matches, set “CoverCountAll” to 0 in your modelsim.ini
file to reverse the default behavior. Alternatively, you can use the -covercountnone argument
to vsim to disable the count for a specific invocation.
Values that are vectors are treated as subexpressions external to the table until they resolve to a
boolean result. For example, take the IF statement:
A UDP truth table will be generated in which bus = “0111” is evaluated as a subexpression and
the result, which is boolean, becomes an input to the truth table. The truth table looks as
follows:
Index expressions also serve as inputs to the table. Conditions containing function calls cannot
be handled and will be ignored for condition coverage.
If a line contains a condition that is uncovered — that is, some part of its truth table was not
encountered — that line will appear in the Coverage Analysis window when you select
Condition Analysis from the Analysis Type pulldown menu (see Figure 19-2). When that line
is selected, the condition truth table will appear in the Details window. Double-click the line to
highlight it in the Source window.
In general, if branch and condition coverage are turned on but NOT expression coverage, the
ternary is treated as a (b && d) condition and a true and false branch. But if expression coverage
is on, the entire RHS is analyzed as a single expression, and you will not see a condition or
branch.
In short, condition coverage is considered for all logical operators, but not for “relational”
operators (==, <=, >=, !=). The entire relational subexpression is treated as a primary input.
If a line contains an expression that is uncovered (some part of its truth table was not
encountered) that line appears in the Coverage Analysis window when you select Expression
Analysis from the Type pulldown menu. When that line is selected, the expression truth table
appears in the Details window and the line will be highlighted in the Source window.
or:
where var, var1 and var2 may be of any type; <relop> is a relational operator (e.g.,==,<,>,>=);
and const is a constant of the appropriate type.
Expressions containing only one input variable are ignored, as are expressions containing
vectors. Logical operators (e.g.,and,or,xor) are supported for std_logic/std_ulogic, bit, and
boolean variable types.
When condition or expression coverage is enabled, all VHDL expression inputs are converted
to one of 4 states: 0, 1, X, or Z. In particular, a common scenario is for U to be converted to X,
which can sometimes visibly affect simulation results.
Related Topics
Condition and Expression Coverage
Toggle Coverage
Toggle coverage is the ability to count and collect changes of state on specified nodes,
including:
• Verilog and SystemVerilog signal types: wire, reg, bit, enum, real, shortreal, and integer
atoms (which includes shortint, int, longint, byte, real, integer, and time). SystemVerilog
integer atoms are treated as bit vectors of the appropriate number of bits, and counts are
kept for each bit. Aggregate types (arrays, structs, packed unions) are handled by
descending all the way to the leaf elements and collecting coverage on each leaf bit.
• VHDL signal types: boolean, bit, bit_vector, enum, integer, std_logic/std_ulogic, and
std_logic_vector/std_ulogic_vector. Aggregate types (arrays, records) are handled by
descending all the way to the leaf elements and collecting coverage on those bits.
There are two modes of toggle coverage operation - standard (or 2-state) and extended (or 3-
state). Extended coverage allows a more detailed view of test bench effectiveness and is
especially useful for examining the coverage of tri-state signals. It helps to ensure, for example,
that a bus has toggled from high 'Z' to a '1' or '0', and a '1' or '0' back to a high 'Z'. (See Standard
and Extended Toggle Coverage.)
When compiling or simulating, specify standard (2-state) toggle using the “t” code, and
extended (3-state) toggle using the “x” code. See “Specifying Toggle Coverage Statistics
Collection” for more information on this topic.
Toggle coverage can be excluded from statistics collection, though proper management of
exclusions is important. See “Toggle Exclusion Management” for information on this topic.
The “Toggle Ports Only” flow - viewing only the ports when collecting toggle coverage - helps
reduce this impact (see “Toggle Ports Only Flow”).
Other methodologies may help as well; for example, only collecting toggle coverage on a subset
of simulations, or on a subset of regions within a simulation.
In addition, the following vcom, vlog, and vsim options also can be used to control performance
and capacity when toggle coverage is in effect: -togglecountlimit, -togglewidthlimit,
-togglevlogint, -togglemaxintvalues, -togglevlogreal, -togglemaxrealvalues,
-togglefixedsizearray, and -togglemaxfixedsizearray.
In vopt, the following toggle related options are available: -togglecountlimit, -togglewidthlimit,
and -toggleportsonly.
Related Topics
Toggle Coverage
For VHDL enums, counts are recorded for each enumeration value and a signal is considered
“toggled” if all the enumerations have non-zero counts.
For VHDL integers, a record is kept of each value the integer assumes and an associated count.
The maximum number of values recorded is determined by a limit variable that can be changed
on a per-signal basis. The default is 100 values. The limit variable can be turned off completely
with the -notoggleints option for the vsim command or setting ToggleNoIntegers in the
modelsim.ini file. The limit variable can be increased by setting the vsim command line option
-togglemaxintvalues, setting ToggleFixedSizeArray in the modelsim.ini file, or setting the Tcl
variable ToggleMaxIntValues. A VHDL integer is considered 100% toggled if at least two
different values were seen during simulation. If only one value was ever seen, it is considered
0% toggled.
For VHDL arrays, toggles are counted when the array has less than ToggleWidthLimit elements
(see “Limiting Toggle Coverage”). Toggle coverage works for VHDL arrays by descending to
the bit elements at the leaves of the array, and then collecting counts for each leaf bit.
Related Topics
Toggle Coverage
SystemVerilog real types (real, shortreal) are not treated as toggle nodes by default. To treat
them as toggle nodes, use the vsim command’s -togglevlogreal argument or turn on the
ToggleVlogIntegers variable in modelsim.ini. When toggle collection is in effect for SV real
types, a record is kept of each value the real assumes and an associated count. The maximum
number of values recorded is determined by a limit variable. The default is 100 values. The limit
variable can be increased by setting the vsim command line option -togglemaxrealvalues, or
setting ToggleMaxRealValues in the modelsim.ini file. A SystemVerilog real is considered
100% toggled if at least two different values were seen during simulation. If only one value was
ever seen, it is considered 0% toggled.
SystemVerilog packed types include sophisticated data structures such as packed struct, packed
union, tagged packed union, multi-dimensional packed arrays, enumerated types, and
compositions of these types. By default, toggle coverage is reported for each dimension or
member of such types. However, you can control this by making use of the -togglepackedasvec
argument to the vsim command. This option causes coverage to be reported as if the object was
an equivalent one-dimensional packed array with the same overall number of bits. The
“TogglePackedAsVec” modelsim.ini variable provides a default value for -togglepackedasvec.
Objects of enumerated types are considered to be covered if all of the enumeration values occur
during simulation. However, the -togglevlogenumbits argument to the vsim command can be
used to cause the object to be treated as an equivalent packed array of bit or logic type. The
“ToggleVlogEnumBits” modelsim.ini variable provides a default value for
-togglevlogenumbits.
toggle coverage. The -togglepackedasvec option only applies to the packed dimensions of
multi-dimensioned SystemVerilog arrays.
SystemVerilog unpacked structs are supported as long as all struct elements consist of
supported data types. Unpacked structs are broken into their fields and toggle coverage for each
field is calculated individually.
Related Topics
Toggle Coverage
The coverage reports and GUI will only show numbers associated with togglenodes that are
ports in the design. Similarly, coverage aggregation calculations only involve ports. The Toggle
Ports Only flow correctly handles simulator port collapsing. Other approaches such as “toggle
add -ports …” and “coverage exclude …” don't work as smoothly or intuitively when port
collapsing is present.
Related Topics
Toggle Coverage
The sub-menu allows you to Add toggle coverage for the selected item(s) in the Objects
window; include Extended toggle coverage; Enable or Disable toggle coverage; or Reset.
Another sub-menu allows you to choose Selected Signals, Signals in Region, or Signals in
Design.
Toggle coverage data is displayed in the Objects window in multiple columns, as shown below.
Right-click the column title bar and select Show All Columns from the popup menu to make
sure all Toggle coverage columns are displayed. There is a column for each of the six transition
types. Click (left mouse button) any column name to sort data for that column. See Objects
Window for more details on each column.
Related Topics
Toggle Coverage
There are three different modes for extended toggle coverage. The modes range from optimistic
(mode 1) to pessimistic (mode 3). Select the mode that corresponds best to your coverage
methodology and goals.
Mode selection can be done on a per-design unit basis using vcom/vlog options, or on a more
global basis using vopt or vsim options.
The # total bins will affect the “Active” count in vcover stats and any reference to “toggle
nodes” in reports.
/top/clk
/top/dut/clk
/top/dut/deep/fsm/clk
may all be different names for the same signal. In Questa SIM, we use the term “alias name” to
refer to the set of duplicate names. We use the term “canonical name” to refer to a unique name
that can be used to describe the overall signal. In almost all cases, the “canonical name” is the
top-most name of the signal in the hierarchy. Note that a canonical name is just another alias in
the overall set of aliases. In other words. the canonical name can be considered an alias name,
too.
In the example above, /top/clk is the canonical name, and the other names are alias names.
When toggle coverage is enabled for such designs, one has to consider the issue of multiply
counting and reporting statistics on the signal's various alias names.
A couple of situations exist in which aliasing is not applicable. The following are some of the
more common cases, where a signal could be counted more than once:
1. Mixed language boundary — For example, in cases where a Verilog module instantiates
a VHDL entity (or vice-versa), separate counts are maintained for the Verilog signal and
the VHDL signal.
2. SystemVerilog variable ports (like a Verilog reg used as a port) — these are not treated
as connected nets, hence are not treated as aliases
3. VHDL conversion functions on port actuals
4. vsim -nocollapse option is used (only applies to VHDL designs)
Questa SIM uses the following rules when processing hierarchical togglenodes:
At times, the existence of alias names for high level toggle nodes can create confusion for users
when viewing toggle coverage numbers. For example, if you enable toggle reporting on one
specific instance using “toggle add -instance”, you might find that toggle coverage numbers
start appearing in other instances. Likewise, if you exclude a togglenode in one instance, you
might find that togglenodes (ports and internal signals) disappear in other instances. This
behavior occurs when nets span multiple instances and a set of alias names is present. The
behavior is normal and occurs by default: it does not compromise coverage numbers or
performance.
The best way to have full access to all alias names of hierarchical toggle nodes is to use the vopt
+acc=p switch and vsim -nocollapse. Without the use of these, many ports on hierarchical
signals are not visible to the coverage reporting system. The +acc=p switch can degrade
simulator performance significantly, so only use it when necessary for analysis. Use the
+acc=p+<selection> modifier whenever possible in order to prune down the affected area of the
design.
To see a complete list of all alias names on each hierarchical signal, you can use the -duplicates
switch with the toggle report command.
If you see that some toggle nodes (typically aliased ports) are missing in a coverage report, run
an exclusion report (coverage report with exclusions enabled) to see if those nodes might have
been excluded on a different alias, using a command such as:
If you are only interested in monitoring the coverage numbers of ports on selected blocks in
your design, you might also consider using the following command:
vlog +cover=x+/top
vlog +cover=t+/top/dut
In this scenario the compiler applies “extended toggle mode” to /top/clk, and regular toggle
mode to /top/dut/clk and lower aliases. In such cases, the mode that is applied to the canonical
name dominates the mode(s) applied to other aliases of the signal. So, /top/clk, /top/dut/clk, and
/top/dut/deep/fsm/clk would all be collected in extended toggle mode.
If there is more than one extended toggle mode applied to the same hierarchical signal at both
compile time and simulation time, the option with the highest priority overrides the setting.
Vsim time is lowest priority and vlog/vcom time is highest priority. For example, if a design is
compiled with -extendedtogglemode 1, but simulated with -extendedtogglemode 2, the
compiler option overrides the simulator option, so the -extendedtogglemode is applied to the
design as 1.
Related Topics
Toggle Coverage
• Compile (vcom/vlog) using the argument +cover= with either ‘t’ or ‘x’. See “Specifying
Coverage Types for Collection” for more information.
• Entering the toggle add command at the command line.
• Select Tools > Toggle Coverage > Add or Tools > Toggle Coverage > Extended in
the Main window menu.
Using the Toggle Add Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Note
If you do a toggle add command on a group of signals, then 'toggle add -full' on the same
signals will convert them to extended toggle coverage mode (all six transitions). (See
Standard and Extended Toggle Coverage.)Similarly, if you do a 'toggle add' command on
extended toggle coverage mode toggles (six transitions), then it will convert them into standard
coverage toggles (two transitions).
• When the toggle add command is given, the result '0' (number of toggles added) means
that any(all) existing extended toggle nodes were converted to standard toggles.
• When the 'toggle add -full' command is given, then result '0' (number of toggles added)
means that any(all) existing toggle nodes were converted to extended toggles.
• For SystemVerilog struct, conversion will apply to all fields of the structure and not to
any particular type of field.
Related Topics
Toggle Coverage
For example, if you are collecting toggle data on 0->1 and 1->0 transitions, both transition
counts must reach the limit. If you are collecting “full” data on 6 edge transitions, all 6 must
reach the limit. The default setting for this variable is 1. If the limit is set to zero, then it is
treated as unlimited.
If you want different toggle count limits on different design units, use the -togglecountlimit
argument for vcom or vlog. The -countlimit argument for the toggle add command will set a
count limit on a specific node.
If you want to override the ToggleCountLimit variable everywhere, like for a batch run, use the
-togglecountlimit argument for vsim.
The ToggleWidthLimit modelsim.ini variable limits the maximum width of signals that are
automatically added to toggle coverage with the +cover=t argument to vcom or vlog. The
default limit is 128. A value of 0 is taken as “unlimited.” This limit is designed to filter out
memories from toggle coverage. The limit applies to Verilog registers and VHDL arrays. If the
register or array is larger than the limit, it is not added to toggle coverage.
You can change the default toggle width limit on a design unit basis with the -togglewidthlimit
argument for vcom, vlog, or vsim.
The -widthlimit argument for the toggle add command will set the width limit for signals on a
specific node.
Related Topics
Toggle Coverage
Code coverage is reported separately for classes when you use the coverage report command,
and coverage data for classes appears in the Structure and Source windows.
Coverage Exclusions
When code coverage is enabled for an entire design, or for the purposes of debugging a
particular segment of the design, you may want to exclude coverage for individual design units,
files, lines of code, objects, etc. Coverage exclusions are used for this purpose.
Coverage objects can be excluded using the coverage exclude command, or with source code
pragmas. When exclusions are applied, they are saved into the UCDB along with all coverage
count data. This allows you to generate reports later in Coverage View mode which match the
most recent simulation state.
• Any number of lines or files containing various constructs such as states, branches,
expressions and conditions.
• Condition and expression truth table rows (see “Exclude Rows from UDP and FEC
Truth Tables”).
• Toggles (see “Toggle Exclusion Management”).
• FSM transitions and states (see “FSM Coverage Exclusions”).
• Functional coverage (see “Excluding Functional Coverage from the GUI and Reports”)
• Assertions (see “Excluding Assertions and Cover Directives”)
You can also exclude nodes from toggle statistics collection using “coverage exclude -code t”,
“coverage exclude -togglenode”, or“toggle disable”.
Related Topics
coverage exclude
toggle disable
Related Topics
Source Window Code Coverage Indicator Icons
Auto Exclusions
Exclusions are automatically applied to certain code constructs. One good example is assertion
code, which is normally not considered part of the “design”. It is not normally desired to have
assertions participate in code coverage.
Another case is FSM state exclusions. By default, when a state is excluded, all transitions to and
from that state are excluded. To explicitly control FSM auto exclusions set the vsim argument
-autoexclusionsdisable using a command such as:
To change the default behavior of the tool, set the variable AutoExclusionsDisable in the
modelsim.ini file.
See “Coverage Data in the Source Window” for a full list of icons (such as EA), and Table 19-6
for a list of codes (such as “EBCS”) appearing in the coverage report that are associated with
auto exclusions.
Related Topics
AllFalse Branches
Coverage Data in the Source Window
To exclude the true branch in this example, you enter the command:
Excluding line 30 excludes the true branch, while excluding line 32 excludes the false branch. A
special case applies when there is no “else”, or an “elsif” is used instead. In that case, an
“AllFalse” branch is created, whose exclusion must be set explicitly.
Related Topics
Exclude Implicit (AllFalse) Branches
In the event that either a or b remains at '1' throughout the simulation, you will end up with less
than 100% coverage, since the “AllFalse” branch of this construct was never exercised. (i.e. the
case of a = '0' and b = '0').
To explicitly exclude that implicit “AllFalse” branch, you must apply the -allfalse option to a
coverage exclude command on line 30:
If -code b is not used, all code coverage types on that line would be excluded, too.
In this example, if you do not use the -allfalse switch the “AllFalse” branch will not be
excluded. Only the True branch will be excluded.
If you specify the following command, where the -linerange switch covers all branches of the IF
statement:
You should note that if the line range that is mentioned in an exclusion command includes a
complete IF statement, then, the “AllFalse” branch of this IF statement will be excluded
automatically even if the “-allfalse” switch is not used. However, IF the linerange partially
covers an IF statement, then;
• Without using “-allfalse”, the AllFalse branch will not be excluded but other branches
will be excluded.
• With “-allfalse”, only the AllFalse branch will be excluded and nothing else even if the
linerange covers other True or False branches.
Suppose you are doing a simulation of a design and you want to exclude selected lines from
each file in the design and all mode INOUT toggle nodes. You can put all exclusions in a .do
file and name it, say, exclusions.do. The contents of the exclusions.do file might look like this:
This excludes lines 12, 55, and 67 to 90 (inclusive) of file xyz.vhd; lines 3 to 6, 9 to 14, and 77
of abc.vhd; all lines from pqr.vhd, and all INOUT toggle nodes in the design.
After compiling using +cover switch, you can load and run the simulation with the following
commands:
In order to view details about the exclusions applied, such as which exclusion commands failed,
enable the transcript mechanism prior to running vsim by entering the following line at the top
of the your .do file (exclusions.do).
Related Topics
Exclude Individual Metrics with CLI Commands
Supported Pragmas
The pragmas supported are as follows.
coverage on See "coverage on and coverage off Pragma Syntax"
coverage off
coverage never
coverage fixed_value
coverage fsm_off
coverage toggle_ignore
pragma synthesis_off
pragma synthesis_on
pragma translate_off
pragma translate_on
vcs coverage on
vcs coverage off
vnavigatoroff
vnavigatoron
• The “coverage on”, “coverage off”, and “coverage never” pragmas are currently
supported for use with branch, condition, expression, statement, toggle, and FSM
coverage exclusively. They have no effect on Functional coverage.
• For toggle coverage, signal is excluded from coverage if its declaration appears within
the confines of the “coverage off” section of code (see “Exclude Nodes from Toggle
Coverage”).
• For FSM coverage, FSM is excluded from coverage when the declaration of a ‘current
state’ variable appears within the confines of the “coverage off” region of code. The
individual transitions of the FSM are not affected by the exclusion (see “FSM Pragma
Exclusions” for FSM coverage pragma syntax and information).
Note
Multiple coverage items on a single line of code are numbered, from left to right in
ascending order. If a branch statement occurred on the same line as another type of
coverage object (such as an assignment) in the source code, the item number displayed
for the additional coverage object may change from one report to the next, depending on
whether branch coverage was enabled.
Related Topics
Verilog vs. VHDL Pragmas
coverage on and coverage off Pragma Syntax
Pragma Usage and Nesting
FSM Pragma Exclusions
• Each pragma is preceded in the code line by either a “//” (Verilog) or “--” (VHDL). For
example:
// coverage never (Verilog)
-- coverage never (VHDL)
• Bracket the line(s) you want to exclude with these pragmas. For example:
-- coverage off b
...
...
-- coverage on b
• The “pragma” keyword can also be replaced with either “synopsys”, “mentor”, or
“synthesis”.
• Pragmas can often nest in source code, often without the developer’s awareness. This
can result in coverage being turned on or off at unexpected intervals. For more
information, see “Pragma Usage and Nesting”.
Tip
Important: The 'coverage on' pragma, as well as other synonymous pragmas (such
as synthesis_on, etc.), do not support nested behavior. They turn on coverage,
irrespective of any number of 'coverage off' pragmas encountered earlier in the file.
• The “coverage off” and “coverage on” pragmas turn on and off coverage for specified
items. If no coverage items are specified, all items are affected.
• The “coverage on|off” pragma applies to branches, conditions, expressions, statements,
toggles and FSMs.
For information on toggle exclusions, see “Toggle Exclusion Management”.
The “fsm_off” pragma selectively turns coverage off and on for FSM state variables and
their associated transitions:
// coverage fsm_off <fsm_name> (Verilog)
-- coverage fsm_off <fsm_name> (VHDL)
where:
<input_terminal> is any condition or expression in the scope in which the pragma is
added, and in the same form as it appears in the coverage report.
<fixed_value> is ‘0’, ‘1’, or ‘Z’, which can be expressed as a boolean, integer, bit, or
std_logic literal expression, or as any constant signal or an expression, whose evaluated
value comes out as constant (0 or 1). The value must be enclosed in parentheses '( )'.
Examples:
//coverage fixed_value “a” (3’h0)
Arguments
• [bcesft]
Selectively turns on/off branch (“b”), condition (“c”), expression (“e”), statement (“s”),
FSM state variables and associated transitions (“f”), and/or toggle (“t”) coverage. If no
coverage type is specified, all are affected.
• -allfalse
Affects only the “all false” branch from the branch coverage of a specified “if” statement.
This argument is only valid for use with “coverage {on|off} -item b <item#>”.
The term “AllFalse” is being used as a name for an implicit branch at the end of an “if” or
“if-else” decision tree. The AllFalse branch is considered to be hit when none of the
conditions in the decision tree are true. An AllFalse branch doesn’t exist for any decision
tree which ends with a bare “else”. For further details on “all false” and how it applies to the
code, see “Branch Coverage”.
• -feccondrow
Affects only the specified rows from the FEC table of the specified condition.
• -fecexprrow
Affects only the specified rows from the FEC table of the specified expression.
Valid for use with coverage on | off “-item e <item#>”.
• -item
Selectively turns on/off branch (“b”), condition (“c”), expression (“e”), and/or statement
(“s”) coverage(s) for only the line of code immediately following the pragma. Requires both
a specification for type of coverage and an integer specifying the item numbers (<int>) for
the line immediately following pragma. Coverage items are numbered in ascending order,
from left to right, beginning with 1. Item numbers can be specified as an integer or a series
of integers (item 1 or items 2-4). Multiple items may be specified separated by whitespace.
• -udpcondrow
Affects only the specified rows from the UDP table of the specified condition.
Valid for use with coverage on | off “-item c <item#>” when UDP coverage is enabled with
vcom/vlog/vopt -coverudp.
Valid for use with coverage on | off “-item c <item#>”.
• -udpexprrow
Affects only the specified rows from the UDP table of the specified expression.
Valid for use with coverage on | off “-item e <item#>” when UDP coverage is enabled with
vcom/vlog/vopt -coverudp.
Description
• The effect of any “coverage on|off” fine-grained pragma exclusion is limited to the next
valid line of source code after excluding all blank lines and comments.
• The -item argument to “coverage on/off” selectively turns on/off coverage for
statements, branches, conditions and/or expressions for the next line of code.
• You do not need to add a matching "coverage off" directive when using fine-grained
exclusions (i.e. any pragma specified with a -item option).
• You can combine two or more coverage items in one coverage pragma if the item
numbers are the same. For example,
(// coverage off -item bs 2)
turns off coverage for statement #2 and branch #2 of the next line.
• To exclude/include different item numbers for different coverage items, use two
different pragmas.
// coverage on -item b 2
turns on coverage for branch #2 and condition #3,4,5 of the next line.
• You can use multiple item numbers and ranges in one pragma.
// coverage on -item s 1 3-5 7-9 11
• For Branches, enabling/disabling coverage for the (case) branch automatically enables/
disables coverage for all its branches even if they are not on the same line of the (case)
branch. You can override the coverage of a certain branch by an additional pragma that
changes coverage of this branch.
• For Conditions, you can selectively turn coverage on/off for certain FEC condition rows
using the -feccondrow (or -udpcondrow, if UDP collection is enabled). For example,
// coverage off -item c 1 -feccondrow 1 3-5
excludes UDP condition rows (1, 3, 4, 5) of the first condition item from coverage.
• For Expressions, the same functionality can be achieved using -fecexprrow options, or
-udpexprrow, if UDP collection is enabled).
// coverage off -item e 1 -fecexprrow 1-4 6
excludes FEC expression rows (1, 2, 3, 4, 6) of the first expression item from coverage.
Examples
• Exclude all the following conditions, and expressions, statement, branches, until a
“// coverage on” pragma is reached, or the end of the design unit is reached.
// coverage off
• Exclude 1st row from the FEC table of the first condition on the next line
-- coverage off -item c 1 -feccondrow 1
• Exclude the 2nd branch and 2nd statement from the next line
-- coverage off -item bs 2
• Include coverage for 2nd and 3rd branches, and condition #4 of the next line
// coverage on -item b 2-3
// coverage on -item c 4
• Exclude only the AllFalse branch from the 4th branch on the next line
-- coverage off -item b 4 -allfalse
o and the 3rd row in UDP table and 4th row in FEC table of 2nd condition:
-- coverage off –item ce 2 –udpcondrow 3 –feccondrow 4 -udpexprrow 1 -
fecexprrow 2
Related Topics
Verilog vs. VHDL Pragmas
Exclude Individual Metrics with Pragmas
Pragma Usage and Nesting
Consider how code coverage is enabled in the following examples of nested pragmas.
One might logically assume that coverage collection would be enabled by the fourth pragma.
However, it is the third pragma (on line 5) which enables the code coverage collection for the
remainder of the code. This is due to the fact that Questa SIM doesn’t support nested pragmas as
one might expect.
A note appears in the Transcript window stating the line responsible for enabling the coverage:
No warning or note appears for the fourth pragma, since the coverage has already been enabled.
If the code is compiled with all coverage enabled, the pragma on line 5 enables only branch,
condition and expression; coverage for all types is enabled at line 7. The following notes are
issued:
If, however, the code compiled enables only branch, condition and statement coverage, then line
5 (//coverage on bce) enables only branch and condition coverage until line 7, where all
coverage is enabled. The following notes are issued:
The rules governing how coverage is enabled/disabled with pragmas apply to any pragmas
which are synonymous with 'coverage on' and 'coverage off', including:
These pragmas, however, do not operate on individual coverage types (b,c,e,s,t, or f). They
enable/disable all types of code coverage as a whole.
Tip
Since pragma-excluded toggles are parsed in the source compilation, they are
only relevant to the compiler/simulator flow with +cover=t and -coverage. The
pragma exclusion has no effect on toggle add, disable, or enable.
o vsim -coverage — required in order to add all the toggles previously found by the
compiler.
o vcover report -excluded — prints an exclusions report detailing all toggles specific
toggles that were recognized in the design during compilation. The generated report
is actually an executable .do file that you can run at a later time.
o coverage exclude [disable|enable] -pragma — dynamically enables or disables
reporting on toggle nodes that were previously excluded by the compiler.
In this method, both “vcom/vlog +cover=t” and “vsim -coverage” are required in order
to add toggles for coverage.
These two flows of managing toggle coverage and exclusions are quite distinct. You can apply
toggle exclusions by executing an exclusions report as a .do file (TCL format), as mentioned
above. However, this .do file only consistently reproduces the same set of enabled toggles in the
compiler/simulator flow. This is because the exclude commands in the exclusions report depend
on having a given set of toggles currently enabled. In other words, if you introduce any toggle
add/enable/disable commands before applying a set of toggle exclusions from a saved .do file,
the resulting set of toggle exclusions will not be identical to your original set. The toggle
exclusions can only be applied with respect to currently enabled toggles, i.e., not to a pristine,
“toggle-free” environment.
This is important, because nothing in Questa SIM prevents you from mixing commands from
the manual and compiler/simulator flows, however you should only do so with a solid
understanding of how they interact.
For example:
coverage exclude -togglenode mybit myreg -trans 01 0z
excludes transitions 0->1 and 0->Z from toggle nodes mybit and myreg.
Transition names are not case sensitive and can be any of the following six transitions:
01 10 0Z 1Z Z0 Z1
You can re-enable toggle statistics collection on nodes whose toggle coverage has previously
been disabled via the toggle disable command using the toggle enable command.
the signal mysignal appears as “pragma excluded” in toggle coverage reports. See
“coverage on and coverage off Pragma Syntax” for further details.
2. “coverage toggle_ignore” — excludes toggles, including specific bus bits.
Verilog command syntax:
//coverage toggle_ignore <simple_signal_name> [<list>]
where <list> is a space-separated list of bit indices or ranges. A range is two integers
separated by ':' or '-'. If <list> is not specified, the entire signal is excluded.
The following additional rules apply to the use of these pragmas:
o The pragma must be placed within the declarative region of the module or
architecture in which <simple_signal_name> is declared.
o Glob-style wildcards are supported. For example, to exclude reg_123, reg_234,
reg_345 from toggle coverage, you can simply enter:
//coverage toggle_ignore “reg*”
Or, to exclude all toggles from coverage for a specific module, you can enter the
following within that module:
//coverage toggle_ignore “*”
o If using a range, the range must be in the same ascending or descending order as the
signal declaration.
3. “coverage never”
The behavior of the “// coverage toggle_ignore” matches that of the “// coverage on/off”
pragma — that is, toggle nodes will be pragma excluded and can only be included in
coverage by clearing the pragma exclusion at the vsim command line.
However, with the “// coverage never” pragma, toggle node data structures will not be
created and the nodes cannot be included later.
The precedence order of these three pragma exclusions will be:
“coverage never” > “coverage toggle_ignore” > “coverage on/off”
coverage toggle_ignore” pragma will override “// coverage on/off” pragma. For example, in the
following code:
module top;
reg temp;
// coverage off
reg temp1;
//coverage on
// coverage toggle_ignore temp
endmodule
module top;
// coverage toggle_ignore temp1
reg temp;
// coverage on
reg temp1;
endmodule
temp is ignored. This is consistent with the behavior of “// coverage toggle_ignore” because
default behavior is coverage ON.
The following are some examples of commands used to exclude data from the coverage report:
excludes FSM state S1 from coverage in the design unit fsm_top. <state> is the current state
variable. By default, when a state is excluded, all transitions to and from that state are excluded
(see “Auto Exclusions”).
excludes all transitions from the FSM whose FSM_ID is state in the design unit fsm_top.
coverage exclude -du fsm_top -ftrans state {idle -> wt_wd_1} {idle -> rd_wd_1}
excludes specified transitions (2 and 3) from the FSM whose FSM_ID is state, in the design unit
fsm_top. If whitespace is present in the transition, it should be surrounded by curly braces.
excludes all the transitions from the /fsm_top/a1 instance, in the FSM whose FSM_ID is state,
in instance /fsm_top/a1.
coverage exclude -scope /fsm_top/a1 -ftrans state {idle -> rd_wd_1} {idle -> rd_wd_1}
excludes specified transitions (numbers 3 and 4) from the FSM whose FSM_ID is state, in
instance /fsm_top/a1.
coverage exclude -clear -du fsm_test -ftrans <state_var> {idle -> rd_wd_1} {idle ->
rd_wd_1}
Related Topics
coverage exclude
1. “coverage off [f]” — excludes any FSM states and associated transitions that appear
after “coverage off” and before “coverage on” in the code. Current state variables
declared between “// coverage off” and “// coverage on” pragmas are excluded from the
FSM coverage; however, the FSM is recognized. This is consistent with the behavior of
the “// coverage fsm_off ” pragma. For example:
module mid(clock);
input clock;
// coverage off
reg [1:0] cst;
localparam s0 = 2'b00, s1 = 2'b01;
// coverage on
always @(posedge clock)
begin
case (cst)
s0: cst = s1;
s1: cst = s0;
endcase
end
endmodule
The FSM is recognized but is excluded from coverage. See “coverage on and coverage
off Pragma Syntax” for further details.
2. “coverage fsm_off” —
In Verilog, the pragma is:
// coverage fsm_off {<state_var_name>
| -fstate <state_var_name> [<state_list>]
| -ftrans <state_var_name> [<transition_list>]
| -fsamestate <state_var_name> [<state_list>]
b. To exclude the entire FSM that has state_variable cst and excludes those states and
transitions which constitute s1 and s2 of another FSM (cst2):
// coverage fsm_off cst -fstate cst2 s1 s2
d. To exclude state s1 and all related transitions of s1, and excludes s2->s0 and s3->s1
transitions of the other FSM (cst2):
//coverage fsm_off -fstate cst1 s1 -ftrans cst2 s2->s0 s3->s1
The state and transition name (strings) are the same as those recognized by the FSM and
as reported in the vsim FSM coverage report.
Warnings are printed only if code coverage is turned on with the +cover=f argument
during compile (with vcom or vlog). If an FSM coverage pragma is specified and
coverage is turned on, the Warning may look like the following:
** Warning: [13] fsm_safe1.vhd(18): Turning off FSM coverage for
"state".
If an FSM coverage pragma is specified before the object declaration, the Warning may
appear as follows:
** Warning: [13] fsm_safe1.vhd(17): Can't find decl "state" for
turning
off FSM coverage.
3. “coverage never” —
The behavior of "// coverage fsm_off" matches that of "// coverage on/off" pragma —
the FSM will be pragma excluded, and can only be included in coverage by clearing the
pragma exclusion at the vsim command line.
The order of precedence for these three pragma exclusions is:
module top(clock);
input clock;
// coverage on
reg [1:0] cst;
// coverage fsm_off cst
localparam s0 = 2'b00, s1 = 2'b01;
always @(posedge clock)
begin
case (cst)
s0: cst = s1;
s1: cst = s0;
endcase
end
endmodule
Even though coverage was ON while 'cst' was encountered, the 'fsm_off' pragma will override it
to turn off coverage for FSM (cst).
Related Topics
FSM Coverage Exclusions
You can load this .do file during a future analysis with the vsim command as follows:
For example, the contents of the exclusions.do file might look like the following:
This excludes lines 12, 55, and 67 to 90 (inclusive) of file xyz.vhd; lines 3 to 6, 9 to 14, and 77
of abc.vhd; and all lines from pqr.vhd.
To avoid running the “-do exclude.do” explicitly, you can set the default exclusion filter to run
the exclusion.do file automatically upon invocation.
Tip
: To view exclusion failures, edit the .do file and add “transcript on” at the beginning of the
file. You can then check the generated transcript after executing the .do file to see which
exclusions have failed.
See the “Exclude Rows from UDP and FEC Truth Tables” for details.
Note, you can have different exclude files <exclude_file_i> for each run i, numbered
from 1 to n.
4. Use vcover merge to merge the coverage data:
vcover merge <merged_results_file> <results_1> <results_2> ... <results_n>
All the various results files <results_i> contain the exclusion information inserted at step 3.
The exclusion information for the merged results file is derived by ORing the exclusion flags
from each vsim run. So, for example, if runs 1 and 2 exclude xyz.vhd line 12, but the other runs
don't exclude that line, the exclusion flag for xyz.vhd line 12 is set in the merged results since at
least one of the runs excluded that line. Then the final vcover report will not show coverage
results for file xyz.vhd line 12.
Let's suppose your <exclude_file_i> are all the same, and called exclude.do.
This will exclude lines 12, 55, and 67 to 90 (inclusive) of file xyz.vhd; lines 3 to 6, 9 to 14, and
77 of abc.vhd; and all lines from pqr.vhd.
Related Topics
Exclude Rows from UDP and FEC Truth Tables
Coverconstructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Covermodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Code Coverage Mode Interaction with Coverage Arguments. . . . . . . . . . . . . . . . . . . . . 1015
Coverconstructs
The covermode option provides user-controlled coverconstructs. The coverconstruct syntax is
provided along with examples and a description of the mnemonically named constructs.
A coverconstruct corresponds to a particular HDL code construct that may be instrumented for
coverage collection. Many coverconstructs are permanently enabled and cannot be controlled.
The user-controlled coverconstructs available with the covermode option have a trade-off: you
can collect coverage on these constructs or avoid them and benefit from higher performance and
less data to analyze.
Some examples of coverconstructs are “condition coverage inside a task or function” and
“expression on the right hand side of a variable declaration assignment.” Coverconstructs are
named by mnemonic abbreviations (see Table 19-7). These two example constructs are
abbreviated “citf” and “evda,” respectively.
Example:
The same can be done using the coverconstruct variable in the [vopt] sections of the
modelsim.ini file:
Covermodes
A covermode corresponds to a set of coverconstructs considered for coverage collection.
The default covermode set (the current behavior) is -covermode default. Other covermodes
differ from the default covermode and are essentially a synonym for sets of enabled
coverconstructs. You can think of -covermode as a shortcut for a specific list of -coverconstruct
mnemonics.
The same can be done using the Covermode variable in the [vopt] section of the modelsim.ini
file:
Covermode=set1
• +cover[=bcefst]
• +nocover
• -covermode [mode]
• -coverconstruct [list of constructs]
• -coveropt [1|2|3|4|5]
Note
If +cover is not active in a design region where -coverconstruct is active, the -coverconstruct
option has no effect. Coverage needs to be fundamentally enabled to control precise
constructs with -coverconstruct.
Coverage Arguments
The table provides descriptions of covermode arguments and corresponding coverconstructs.
Argument Description
-covermode full (Most exhaustive coverage collection) Has the richest set of HDL
constructs and contains all the constructs (except for negation items)
mentioned the mnemonic table.
-covermode default (Default) Has a rich set of cover constructs enabled. All the
covermodes have relative positioning with this default covermode.
Argument Description
-covermode set1 This covermode does not consider the following constructs for
coverage collection:
• Continuous/Concurrent Assignments
• Condition coverage inside Task/Function/Procedures/
• Task FSMs and two-state FSMs
• Condition coverage:
• In terminal connection lists in task-enabling statements
• In instance connection lists
• In “for” loops
• FSM coverage for unpacked dimension in current state variable
and next state variables
• Branch coverage for “if” and “case” statements and ternary
operator(?:) if they are in user-defined tasks or functions or in
code that executes as a result of a “for” loop.
• Coverage for partially/fully protected modules and their children
for any coverage metric. If a module has some part of the code
protected in it, then do not monitor the module or its self-instance
and the full hierarchy below it, for coverage.
• Toggle for integer atomic types (for example, int, integer, short).
• Coverage for SystemVerilog packages and classes.
• Branch and cond coverage inside assertions.
Hence -covermode set1 is equivalent to following -coverconstruct
option: -coverconstruct noca, nocitf, nofsmtf, nofsmds, noctes,
nocicl, nocprc, nocfl, nofsmup, nocifl, nocpm, notcint, nocpkg,
nocsva
-covermode set2 If an FSM definition spans through a task/procedure or the FSM has
less than three states, some users do not want to bother with
coverage. Covermode 3 removes such FSMs from coverage
collection. This covermode does not consider the following
constructs for coverage collection: Task FSMs and two-state FSMs.
Hence ‘-covermode set2’ is equivalent to the following
-coverconstruct option:
-coverconstruct nofsmtf, nofsmd
This example enables toggle coverage according to the default -covermode default; in addition
to all toggle nodes present in -covermode full, loop index toggle variables are also collected.
This example enables toggle coverage according to the default -covermode default. The
-coverconstruct option has no effect, because FSM coverage is not enabled and neither is
expression coverage. (Expression coverage handles continuous assignments.)
This example enables all code coverage metrics in -covermode set1 and, in addition, the
following are enabled: quad-state FSMs, togglenodes used as loop indexes, and condition
coverage inside tasks and functions.
This example enables all code coverage metrics in -covermode set1. Quad-state is not
recognized because the implicit nofsmqs inside -covermode set1 overrides the -coverconstruct
option that appeared earlier on the command line.
Coverage Reports
Create a coverage report from the command line or with the GUI.
Coverage reports can be created with:
Report Contents
By default, the coverage report contains a summary of coverage information for the indicated
design unit, file, or instance. A summary of code coverage numbers is given for each coverage
type.
When you specify -details with the coverage report command, the summary information is
followed by coverage details which correspond to each active coverage type:
• For statements — a code listing is given along with counts and exclusion details. This is
similar to the Source window when in coverage mode.
• For branches — a code listing is given and it appears, similar to that shown in the Source
window.
• For conditions and expressions — detailed row-by-row FEC and/or UDP tables are
printed, along with hit counts for each row. See “Reporting Condition and Expression
Coverage” for more information.
• For toggles — a listing of missed togglenodes is printed.
• For FSMs — a listing of missed states and transitions is printed.
• Auto-Exclusions — a list of exclusions along with a code defining the reason they are
excluded. These codes are listed in Table 19-6.
Related Topics
Reporting Condition and Expression Coverage
Auto Exclusions
The solution for resolving different profiles of coverage lies in reporting coverage by-instance.
When you report the data by-instance, you can see exactly which statements are there (no longer
optimized away) and what their coverage counts are. Whereas, if you report the data by-du or
by-file, Questa SIM attempts to merge these different profiles, which may result in apparently
contradictory counts. (Branch counts won't match the corresponding statement counts, and so
forth.) That is why it is recommended to perform reporting on a by-instance basis.
Here is a sample command sequence that outputs a textual code coverage report and saves the
coverage data:
vlog ../rtl/host/top.v
vlog ../rtl/host/a.v
vlog ../rtl/host/b.v
vlog ../rtl/host/c.v
vopt +cover=bcefsx top -o top_opt
vsim -c -coverage top_opt
run 1 ms
coverage report -file d:\\sample\\coverage_rep.txt
coverage save d:\\sample\\coverage.ucdb
The vlog command compiles Verilog and SystemVerilog design units. The +cover=bcefs[t|x]
argument applied to either vopt (for Three-Step Flow) or vlog (for Two-Step Flow) prepares the
design and specifies the types of coverage statistics to collect:
• b = branch coverage
• c = condition coverage
• e = expression coverage
• f = finite state machine coverage
• t = toggle coverage (two-state)
• s = statement coverage
• x = toggle coverage (four-state)
The -coverage option for the vsim command enables code coverage statistics collection during
simulation.
The -file option for the coverage report command specifies a filename for the coverage report:
coverage_rep.txt. And thecoverage save command saves the coverage data to
d:\sample\coverage.ucdb.
Related Topics
coverage report
4. You can produce this same information using the coverage report command.
Related Topics
toggle report
Port Collapsing and Toggle Coverage
coverage report
Also, you should selectively apply vopt +acc=p to avoid optimizing signals away from the
design and the toggle report. Also, make sure to selectively apply the vsim -nocollapse.
Related Topics
toggle report
Related Topics
toggle report
You may also specify a default coverage mode for the current invocation of Questa SIM by
using the -setdefault [byfile | byinstance | bydu] argument for either the coverage report or the
vcover report command.
Related Topics
Simulator GUI Preferences
coverage report
vcover report
XML Output
You can output coverage reports in XML format.
XML output is produced by checking Write XML Format in the Coverage Report dialog or by
using the -xml argument to the coverage report command.
The following example is an abbreviated “By Instance” report that includes line details:
“fn” stands for filename, “ln” stands for line number, and “st” stands for statement.
Related Topics
coverage report
HTML Output
You can output coverage reports in HTML format by checking Write HTML Format in the
Coverage Report dialog or by using the -html argument to the coverage report command.
For more information on HTML output reports, see “Generating HTML Coverage Reports”.
Related Topics
coverage report
Related Topics
Generating HTML Coverage Reports
When observing the Source window, you can tell which statements do not participate in
coverage activities by looking at the Statement and Branch Count columns on the left of the
window. If those columns are completely blank (no numbers or ‘X’ symbols at all), then the
associated statements have been optimized out of the simulation database, and they will not
participate in coverage activities.
By default, Questa SIM enables a reasonable level of optimizations while still maintaining the
logic necessary for the collection of coverage statistics (for details, see CoverOpt modelsim.ini
file variable). If you achieve 100% coverage with the default optimization level, the results are
as viable as achieving 100% coverage with no optimizations enabled at all.
You can customize the default optimization levels used when coverage is enabled for the
simulation as follows:
CoverOpt works as follows: After all other optimization-control options have been processed,
the specified level of CoverOpt optimizations is applied. All CoverOpt can do is turn OFF
certain optimizations known to be harmful or confusing to coverage. CoverOpt never turns on
an optimization that was not enabled already.
Some optimizations are always turned off when code coverage is in effect.
Some +acc flags are always turned on when code coverage is in effect (such as when line
numbering is correctly preserved).
The CoverOpt setting gives you a level of control over how much optimization is applied to
your design when specifying coverage types for collection.
Related Topics
CoverOpt
Using vopt and the -O Optimization Control Arguments
• Source files, design units, and classes whose names begin with the following prefixes:
ovm_
uvm_
avm_
mti_
urm_
tlm_ sqr_
A Finite State Machine (FSM) reflects the changes a state-based design has gone through from
the start of simulation to the present. Transitions indicate state changes and are described by the
conditions required to enable them. Because of the complexity of FSMs, designs containing
them can contain a high number of defects. It is important, therefore, to analyze the FSMs in
RTL before going to the next stages of synthesis in the design cycle.
FSM Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
FSM Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
FSM Multi-State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Collecting FSM Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Reporting Coverage Metrics for FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Viewing FSM Information in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
FSM Coverage Metrics Available in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Advanced Command Arguments for FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Recognized FSM Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
FSM Recognition Info Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
FSM Coverage Text Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
FSM Recognition
Questa SIM recognizes VHDL and Verilog FSMs.
The FSMs are recognized during compilation or optimization when you are Collecting FSM
Coverage Metrics or Viewing FSM Information in the GUI, and when they fit the following
criteria:
• There should be a finite number of states which the state variable can hold.
• The next state assignments to the state variable must be made under a clock.
• The next state value must depend on the current state value of the state variable.
State assignments that do not depend on the current state value are considered reset
assignments.
Questa SIM recognizes the following VHDL and Verilog FSM design styles:
• FSMs using complex “if” conditions where a current state variable is ANDed with
another current state variable.
• Using Verilog part-select expressions as a current-state variable.
• Using VHDL slice expressions as a current-state variable.
• Defining a single FSM in multiple modules.
FSM Design Style Examples
The following examples illustrate several supported FSM design styles.
module fsm_1proc (output reg out, input [7:0] inp, input clk, en, rst);
typedef enum {s0, s1, s2, s3, s4, s5, s6, s7} state_t;
state_t state;
endmodule
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fsm is port( in1 : in signed(1 downto 0);
in2 : in signed(1 downto 0);
en : in std_logic_vector(1 downto 0);
clk: in std_logic;
reset : in std_logic_vector( 3 downto 0);
out1 : out signed(1 downto 0));
end fsm;
begin
process(clk,reset)
begin
if(reset(1 downto 0) = "11") then
cst <= s0;
elsif(clk'event and clk = '1') then
case cst is
when s0 => cst <= s1;
when s1 => cst <= s2;
when s2 => cst <= s3;
when others => cst <= s0;
end case;
end if;
end process;
end arch;
module fsm_2proc (output reg out, input [7:0] inp, input clk, en, rst);
typedef enum {s0, s1, s2, s3, s4, s5, s6, s7} state_t;
state_t c_state, n_state;
always_comb
casex (c_state)
s0: begin out = inp[0]; n_state = s1; end
s1: begin out = inp[1]; n_state = s2; end
s2: begin out = inp[2]; n_state = s3; end
s3: begin out = inp[3]; n_state = s4; end
s4: begin out = inp[4]; n_state = s5; end
s5: begin out = inp[4]; n_state = s6; end
s6: begin out = inp[6]; n_state = s7; end
s7: begin out = inp[7]; n_state = s0; end
default: begin out = inp[5]; n_state = s1; end
endcase
endmodule
Example 20-4. VHDL Current-State Variable and Single Next-State Variable FSM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.pack.all;
entity fsm is port( in1 : in signed(1 downto 0);
in2 : in signed(1 downto 0);
en : in std_logic_vector(1 downto 0);
clk: in std_logic;
reset : in std_logic_vector( 3 downto 0);
out1 : out signed(1 downto 0));
end fsm;
begin
process(clk,reset)
begin
if(reset(1 downto 0) = "11") then
cst <= s0;
elsif(clk'event and clk = '1') then
cst <= nst;
end if;
end process;
process(cst)
begin
case cst is
when s0 => nst <= s1;
when s1 => nst <= s2;
when s2 => nst <= s3;
when others => nst <= s0;
end case;
end process;
end arch;
FSM Coverage
Questa SIM recognizes FSMs in your design during the compilation stages prior to simulation.
The simulation stage collects coverage metrics about which states and transitions were used
while simulating the test bench with the DUT.
The following metrics are collected for FSMs:
• State Coverage Metric — determines how many FSM states have been reached during
simulation.
• Transition Coverage Metric — determines how many transitions have been exercised
in the simulation of the state machine.
# S0 => S1 => S0
When you specify -fsmmultitrans you will be able to view this information in the:
• FSM Recognition Info Note in the transcript, specifically the multi-state transition table.
• FSM Coverage Text Report, specifically the covered transition and uncovered transition
tables.
• Details window
• Missed FSMs window
Procedure
1. Evaluate the commands and switches in Table 20-1 to determine which are required for
your flow.
• Several of the GUI windows will contain coverage metrics, refer to the section “FSM
Coverage Metrics Available in the GUI”.
Examples
• Enable FSM coverage on the complete design.
vcom a.vhdl b.vhdl
vcom top.vhdl
vopt +cover=f top -o opt_top
vsim -coverage opt_top
run -all
• Enable FSM coverage, including mutli-state transitions, on the complete design with
verbose reporting.
vcom top.vhdl
vcom a.vhdl b.vhdl
vopt +cover=f -fsmverbose -fsmmultitrans top -o opt_top
vsim -coverage opt_top
run -all
Related Topics
FSM Recognition
FSM Coverage
Code Coverage
Code Coverage in the Graphic Interface
FSM Coverage Exclusions
Prerequisites
• Run a simulation to collect coverage metrics for FSMs.
• (Optional) Exclude transitions or states from coverage collection. This will allow you to
reach 100% FSM coverage. Refer to the section “FSM Coverage Exclusions” for more
information.
Procedure
1. Select Tools > Coverage Report > Text.
Displays the Coverage Text Report dialog box.
2. From the “Report on” drop down menu, select one of the following:
• All files — reports data for FSMs for all design units defined in each file. (-byfile
switch with coverage report)
• All instances — reports data for all FSMs in each instance, merged together.
(-byinst with coverage report)
• All design unit — reports data for all FSMs in all instances of each design unit,
merged together. (-bydu with coverage report)
3. In the Coverage Type pane, ensure that Fsms is selected. (-code f with coverage report)
4. Alter any of the other options as needed.
5. Click OK
Results
• Writes the report (report.txt) to the current working directory.
• Opens a notepad window containing the report.txt file.
Related Topics
coverage report
FSM Coverage
FSM Coverage Metrics Available in the GUI
Code Coverage
The Generation of Coverage Reports
Coverage Reports
Prerequisites
• Invoke Questa SIM in GUI mode.
Procedure
1. Evaluate the commands and switches in Table 20-2 to determine which are required for
your flow.
The FSM Viewer and the Wave window are dynamically linked, allowing you to
analyze states and their transitions, based on your cursor position.
8. Run your simulation with the run command.
9. Rearrange the GUI so can see both the FSM Viewer and Wave windows simultaneously.
10. Link the FSM Viewer window to the cursor of the Wave window:
a. Select FSM View > Track Wave Cursor
b. View how states change by moving the cursor in the wave window, either by
dragging the cursor left and right or by using the Find Previous/Next Transition
buttons in the Wave Cursor toolbar.
Green indicates current state and yellow the previous state for the cursor location.
Related Topics
FSM Recognition
• Columned windows — provide FSM coverage metrics in the Structure, Files, Objects
and Instance Coverage windows, as indicated in Table 20-3.
Related Topics
FSM Coverage
Code Coverage
Code Coverage in the Graphic Interface
-fsm=[imrsx]
Any of the FSM arguments can be negated by prefixing its literal with “-”, for example:
-fsm=-r-xs
This example would disable recognition of implicit asynchronous reset transitions and FSMs
containing an X assignment, and enable recognition of FSMs having single-bit current-state
variable.
Related Topics
Collecting FSM Coverage Metrics
Viewing FSM Information in the GUI
Parameters
Table 20-5 defines the replaceable values from the Recognized FSM note.
Examples
# ** Note: (vlog-143) Recognized 1 FSM in module "decode_top".
# ** Note: (vlog-143) Recognized 1 FSM in module "psi_coder".
Parameters
The following table defines the information in the FSM Recognition Info note.
Examples
# ** Note: (vlog-1947) FSM RECOGNITION INFO
:# Fsm recognized in : decode_top
:# Current State Variable : present_state : ./rice_src/sysv/decode_top.sv(19)
:# Next State Variable : next_state : ./rice_src/sysv/decode_top.sv(19)
# Clock : pins.clk
# Reset States are: { S0 , XXX }
# State Set is : { S0 , S1 , XXX }
# Transition table is
# -------------------------------------------
# S0 => S1 Line : (32 => 34)
# S0 => S0 Line : (24 => 24)
# S0 => XXX Line : (30 => 30)
# S1 => S0 Line : (36 => 38) (24 => 24)
# S1 => XXX Line : (30 => 30)
# XXX => S0 Line : (24 => 24) (42 => 42)
# XXX => XXX Line : (30 => 30)
# -------------------------------------------
# Multi-state transition table is
# -------------------------------------------
# S0 => S1 => S0 (Loop)
# S0 => S1 => XXX
# S0 => S1 => XXX => S0 (Loop)
# S0 => XXX => S0 (Loop)
# S1 => S0 => S1 (Loop)
# S1 => S0 => XXX
# S1 => XXX => S0
# S1 => XXX => S0 => S1 (Loop)
# XXX => S0 => S1
# XXX => S0 => S1 => XXX (Loop)
# XXX => S0 => XXX (Loop)
# -------------------------------------------
Format
# Coverage Report by file with details
:#
:# File: <file.vhdl>
# FSM Coverage:
# Enabled Coverage Active Hits % Covered
# ---------------- ------ ---- ---------
# States 3 3 100.0
# Transitions 13 10 76.9
...
...
Parameters
• The FSM Coverage Report contains the following sections:
o Header — specifies whether the report was generated by file (-byfile), instance
(-byinstance), or design unit (-bydu).
o FSM Coverage — coverage metrics for States and Transitions
o FSM_ID — the name of the current state variable.
o State Value MapInfo — a mapping of the state names to internal values.
o Covered States — coverage metrics for each state
o Covered Transitions — coverage metrics for each transition, including multi-state
transitions if you use the -fsmmultitrans switch.
o Uncovered Transitions — a list of all transitions that have no coverage metrics.
o Summary — the same information as the FSM Coverage table at the top of the
report.
Examples
This examples shows an FSM coverage report, where the metrics are reported by file.
This chapter discusses methods for using VHDL, PSL, and SystemVerilog assertions and cover
directives for design verification with Questa SIM. It is organized into four sections.
• Overview of Assertions and Cover Directives
• Using PSL Assertions and Cover Directives
• Using SVA Assertions and Cover Directives
• Using -assertdebug to Debug with Assertions and Cover Directives
Questa SIM implements assertion verification capabilities via assert, cover, and assume
directives. In the discussions that follow, the term “assertion” is used to indicate both assertion
properties and verification directives unless otherwise noted.
Questa SIM supports the simple subset of PSL constructs and semantics as described in the
IEEE Std 1850-2005, IEEE Standard for Property Specific Language (PSL). Also, the
following formal types are supported: bit, bitvector, boolean, numeric, string, and hdltype.
Questa SIM supports the Questa Verification IP verification components. You can read more
about downloading and installing this package at:
http://supportnet.mentor.com/reference/technotes/public/technote.cfm?id=MG552145
We strongly encourage you to obtain and refer to a copy of the IEEE Std 1850-2005 for PSL as
well as the IEEE Std 1800-2009 for SystemVerilog.
The crucial difference between an assertion and a cover directive is that the assertion declares
that something must always hold. What is of interest is the assertion failure, which is a design
bug (or perhaps an assertion bug.) A cover directive declares that something should occur
sometimes. What is of interest is the cover success, which is a measure of coverage.
Furthermore, it is interesting to count how many times the cover success occurred. A cover
directive in PSL or a cover statement in SystemVerilog is a form of functional coverage: user-
defined coverage.
For more on functional coverage in general, see “Verification with Functional Coverage”.
For information on how assertion and cover directives and participate in the total coverage
aggregation, see “Coverage Aggregation in the Structure Window”.
1. Keep directives simple. Create named assertions that you then reference from the assert
directive (e.g., assert check1).
2. Keep properties and sequences simple too. Build complex assertions out of simple, short
assertions/sequences.
3. Whenever possible, reference a single clock. Properties referencing multiple clocks
require far more simulation time than properties referencing a single clock.
4. Do not use implication with never directives. You will rarely get what you want if you
use implication with a never.
5. Create named sequences so you can reuse them in multiple assertions.
6. Be aware of “unexpected matches.” For example, the following PSL assertion:
assert always a->next(b->next(c));
7. Avoid long or infinite time ranges. For example, if there is an effective timeout in a
sequence, make the time range for the timeout as short as possible given the overall
functional/timing requirements of the design. Using an infinite time range in an
assertion means that it is never able to fail.
Within a sequence, the use of large or unbounded time range can severely impact
simulation performance. The reason for this is that a separate thread is spawned for each
possibility in the legal range. For example, the sequence,
(a ##1 b[*1 to 8000] ##5 c ##1 d)
8. Use system functions like $rose and $fell to avoid inadvertently spawning a new thread
or several new threads each cycle. In the line below,
(!a[*0:$] ##1 a) |-> b;
a thread will be started at every clock edge to check if a is not true. A better way to write
this is:
$rose(a) |-> b;
9. Use a qualifying condition when repetitively checking ([->n]) for multiple occurrences
of a condition in the antecedent expression of an assertion. Often, writing assertions
involves the need to check for multiple occurrences of an expression to trigger when
additional expressions are evaluated. In the examples below, the intent is to check for 48
occurrences (non-consecutive) of signal a; and on the 48th time signal a is true, signal b
is also required to be true.
a[->48] |-> b;
When re-written in its equivalent form below, the above property is extremely expensive
in terms of spawning new threads. Since a brand new thread is started each and every
cycle signal a is not true, threads grow at an nearly an exponential rate. And previously
started threads, in turn, spawn new threads each subsequent cycle due the unbounded
time range when signal a is false.
10. In general, be very careful when using the non-consecutive ([=n]) operator, but
especially on the left-hand side of an implication. Consider the property:
property p3;
@(posedge clk) a ##1 d[=2] ##1 c |-> ##1 e;
endproperty
assert property (p3);
This sequence named easy appears to be straight-forward, and it is. It states that a is
followed by b which is followed by c (all with delay of a single cycle/clock). However,
if the correct behavior requires a and b signals to either remain asserted or to de-assert in
the next cycle, then this simple sequence will not check for the expected behavior. The
following modifications will:
a ##1 a & b ##1 a & b & c;
Another example: If a sequence is needed that says a happens at a clock edge followed
by b in 4 to 8 clock cycles followed by c, it can be written as:
sequence s1;
always @(posedge clk) a ##[4:8]b ##1 c;
endsequence
This accurately represents the above requirement. In most cases, however, the
requirement is: when a asserts, it is to be followed by b asserting in 4 to 8 clock cycles;
and the first time b asserts within the [4:8] cycle range it should be followed by c. This is
represented by:
sequence s2;
always @(posedge clk) a ##1 !b[*3:7] ##1 b ##1 c;
endsequence
The difference between sequences s1 and s2 is that in s2, c has to follow the first
occurrence of b in [*4:8] range whereas in seq1, c can follow any occurrence of b in
[*4:8]. In most cases the requirement is that of s2.
12. This is an example of a badly written cover sequence:
cover sequence (@(posedge clk)
dll_state == DL_INACTIVE [*1:$] ##1 dll_state == DL_INIT [*1:$]
##1 dll_state == DL_ACTIVE);
A thread will be started at every clock edge as long as the dll_state is DL_INACTIVE
which really makes no sense. A better way to write this is to use the cover property
statement:
cover property (@(posedge clk)
$changed(dll_state) |->
$past(dll_state == DL_INACTIVE) ##0 dll_state == DL_INIT
[*1:$] ##1 dll_state == DL_ACTIVE;
13. Be careful what you do in an assertion pass statement. SV assertions have an action
block which contains an assertion pass statement as well as an assertion failure
statement. If an assertion has a pass statement, then the pass statement gets executed on
both real and vacuous passes. Unless you care about vacuous passes you should use the
assert control task $assertvacuousoff to turn off executing of pass action blocks for
vacuous passes.
14. Take into account reset conditions. You don't want to see false failures due to an
assertion failing because either the design is not yet initialized or that a reset occurs
during operation.
15. For local var usage please refer to: www.mentor.com/resources/techpubs/upload/
mentorpaper_35466.pdf
Using Assert Directive Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
SystemVerilog Bind Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
In the absence of a label, Questa SIM generates assert directive names for reporting information
about assertions. For example:
The name generated for this assert directive will be assert__p0. Generically, the syntax of the
generated name is:
assert__<property name>.
there is no property name, so Questa SIM will generate a name like assert__0 (i.e., a number
appended to “assert__”).
Configuring Assertions
The various tasks required to configure assertions may be invoked via the command line or the
GUI.
The GUI interface for configuring assertions is the Configure Assertions dialog, accessed via
the Assertions > Configure menu selection when the Assertions window is active
(Figure 21-2).
Enabling Assertions
You can enable assertions with a command or with a GUI selection.
Procedure
Do any of the following:
• Selecting “On” in the Enable section of the Configure Assertions dialog box
(Figure 21-2) to enable all assertions.
• Use the assertion enable command. The assertion enable command allows you to
turn on or off assertions of a specific language (SystemVerilog, PSL, VHDL) or type
(concurrent or immediate).
The default value of the AssertionEnable variable in the modelsim.ini file is on (‘1’),
enabling all VHDL, PSL, and SystemVerilog assertions. You can override this
variable by specifying:
assertion enable -off
This is the equivalent of selecting Assertions > Enable from the menus when the
Assertions window is active.
2. Select View > Coverage > Assertions and View > Coverage > Cover Directives to
display memory and performance profile data in the Assertions and Cover Directives
windows.
Three columns in the Assertions and Cover Directives windows display this fine grained
profile information: Current Memory, Peak Memory, and Cumulative (number of
threads).
Assertions that create the most threads take the most time to simulate. Therefore, this
information is not only useful for memory profiling but also helps in performance
profiling as well. The cumulative number of threads can help in scenarios where an
assertion creates many short lived threads.
Examples
Threads
In the following assertion,
if 'a' is true throughout the simulation, the assertion will create a thread at every clock edge and
the thread will remain alive for exactly one clock cycle. This assertion may not be one of the
primary consumers of memory space but it will produce a high cumulative thread count.
Thresholds
The simulator will generate a message at every clock edge if the number of threads created by
an assertion or cover directive is more than the threshold. For example,
will write the following message to the Transcript window as the simulation runs when the
threshold of 100 threads is crossed:
Note that this message is printed at every clock edge when the thread threshold is crossed. So if
the threshold is too low, it will cause deluge of messages in the Transcript.
2. To edit the message logging for the current simulation run only, select Simulate >
Runtime Options and click the Message Severity tab in the Runtime Options dialog.
Check the appropriate box(es) under Verilog (Figure 21-5) and click OK.
Figure 21-5. Selecting Message Logging
• You can enable or disable failure and pass logging using the assertion fail or the
assertion pass commands, respectively.
• You can change the permanent defaults by setting the AssertionFailLog and
AssertionPassLog variables in the modelsim.ini file.
• To enable or disable an assertion’s failure or pass logging from the GUI, right-click
an assertion in the Assertions window and select Failure Log or Pass Log from the
popup menu (Figure 21-3). The selection acts as a toggle.
You can also select Assertions > Configure from the menu bar (or, right-click an
assertion and select Configure). This opens the Configure assertions dialog, where
you can enable/disable failure or pass logging.
Figure 21-7. Enabling/Disabling Failure or Pass Logging
Note
Assertion pass logging can be enabled only if the AssertionDebug variable in the
modelsim.ini file is on (set to 1), or if the -assertdebug argument is used with
the vsim command.
The assertion count is not verified until the end of the current time stamp. If multiple
threads are active for a given property and if all of them fail at the same time, then all
fail messages are reported. You may see more fail messages than the limit you set.
Questa SIM continues to respond to assertions if their limit has not been reached. The
limit applies to the entire simulation session and not to any single simulation run
command.
Examples
The following use of the assertion fail command
sets the failure response limit to 4 for all assertions in mydesign. Each assertion failure will be
responded to a maximum of 4 times during the current simulation. The “-r /” argument indicates
that the assertion command should start at the root of mydesign and find all assertions.
• Continue — (default) No action taken. This is the default value if you do not specify this
switch.
• Break — Halt simulation and return to the Questa SIM prompt.
• Exit — Halt simulation and exit Questa SIM.
• TCL — Execute a tcl subroutine call.
You can set the assertion action with the assertion action command or in the GUI.
Procedure
1. To set the action with the assertion action command, use the following syntax:
assertion action -exec [continue | break | exit | tcl_subroutine]
2. To set the action in the GUI, select Assertions > Configure from the menus when the
Assertions window is active, or right-click an assertion in the Assertions window and
select Configure. This will open the Configure Assertions dialog, where you can set the
assertion actions.
Figure 21-9. Set Assertion Actions
3. Select Cover Directives > Configure in the menu bar, or right-click the selected cover
directive and select Configure Directive from the popup menu. This opens the
“Configure selected cover directives” dialog box (Figure 21-10).
Figure 21-10. Configure Selected Cover Directives Dialog
This dialog box allows you to enable/disable directive counting and logging, include/
exclude cover directives from coverage statistics calculations, set a weight for
directives, and specify a minimum number of times a directive should fire. You can also
set the action for coverage directive passes, starts, and antecedent matches.
You can choose from four different actions for cover directive passes, starts, and
antecedent matches:
• Continue — No action is taken.
• Break — Halt simulation and return to the Questa prompt.
• Exit — Halt simulation and exit Questa.
• TCL — Execute designated tcl subroutine.
For example, the likelihood that each type of bus transaction could be interrupted in a general
test is very low as interrupted transactions are normally rare. But you might want to ensure the
design handles the interrupt of all types of transactions and recovers properly from them. To
accomplish this, you can construct a test bench so the stimulus is constrained to ensure that all
types of transactions are generated and that the probability of transactions being interrupted is
relatively high. For that test bench, the weighting of the interrupted transaction cover points
would probably be higher than the weightings of uninterrupted transactions (or other coverage
criteria).
Related Topics
Coverage Aggregation in the Structure Window
For example, say your test bench requires a certain level of PCI traffic during the simulation. 30
PCI STOP transactions might be a proxy measure of sufficient PCI traffic, so you would set an
AtLeast count of 30 on the “PCI STOP” cover directive. Another example might be that a FIFO
full should have been achieved at least once as that would indicate that enough activity occurred
during the simulation to reach a key threshold. So, your “FIFO full” directive would get an
AtLeast count of 1.
For example,
limits the evaluation of the refresh_during_rw cover directive to a count of 5 then disables it.
Once a cover directive is disabled, the assertion engine (which implements cover directives) no
longer makes a kernel call associated with that directive, thus improving simulation runtime
efficiency.
Simulating Assertions
If any assertions were compiled, the vsim command automatically invokes the assertion engine.
If you do not want to simulate compiled assertions, use the -nopsl argument to ignore PSL
assertions or the -nosva to ignore SystemVerilog assertions. You can perform the same action
in the GUI by selecting Disable PSL and Disable SVA in the Others tab of the Start Simulation
dialog box when you load the design with the Simulate > Start Simulation menu selections.
If you want to have access to the details of assertion failures in the Assertion Debug pane of the
Wave window, use the -assertdebug argument with vsim; or, select Enable assertion debug in
the Others tab of the Start Simulation dialog box when you load the design with the Simulate >
Start Simulation menu selections.
To invoke assertion thread viewing of specific assertions, use the -enable argument with the atv
log command after loading the design with vsim, and before the simulation is run.
assert property (@(posedge clk) disable iff (ignore) (b0 |=> b1 ##1 b2 ##1 b3));
In the following discussion we show what happens to the assertion counts for this assertion
when the simulation is run first without -assertcover or -assertdebug; then with -assertcover; and
then with -assertdebug.
The failure count for the assertion given above is 4, as shown in Figure 21-11.
If the design has been compiled with the +acc=a option, you can view the assertion waveform in
the Wave window, as shown in Figure 21-12. The assertion failures are indicated in the Wave
window by red triangles.
When the simulation is run with the -assertcover argument on the assertion property above, the
assertion in the Assertions Window contains a different column for each assertion count, as
shown in Figure 21-13.
• Attempt Count - 15 — The number of times the assertion was attempted, which
basically corresponds to the number of clock edges for the assertion.
• Failure Count - 4— The number of start attempts that resulted in failure.
• Vacuous Count - 3— The number of start attempts when the assertion passed vacuously.
• Pass Count - 1— The number of start attempts when the assertion passed.
• Disable Count - 4 — The number of start attempts that were disabled due to the disable
condition being TRUE.
• Active Count - 3— The number of start attempts that are currently active.
For these counts, note that:
1. Select Simulate > Start Simulation to open the Start Simulation dialog.
2. Open the Others tab.
3. In the Assertions section, select Enable assertion cover (Figure 21-14).
Figure 21-14. Enable Assertion Coverage
These assertion counts can also be enabled with the AssertionCover modelsim.ini variable.
In addition to the red triangles used to denote assertion failures, the Wave window includes the
following assertion indicators when -assertdebug is used:
The Assertions Window contains a different column for each assertion count, as shown in
(Figure 21-13).
• Attempt Count - 15 — The number of times the assertion was attempted, which
basically corresponds to the number of clock edges for the assertion.
• Failure Count - 4 — The number of start attempts that resulted in failure. In this case, the
attempts that started at 750, 850, 950 and 1050 ns resulted in failures
• Vacuous Count - 3 — The number of start attempts when the assertion passed
vacuously. In this case, the start attempts whenever 'b0' was FALSE - at 50, 550, 650 ns.
• Pass Count - 1 — The number of start attempts when the assertion passed. In this case,
for the attempt that started at 1150 ns.
• Disable Count - 4 — The number of start attempts that were disabled due to the disable
condition being TRUE. In this case the attempts that started at 150, 250, 350 and 450 ns.
• Active Count - 3 — The number of start attempts that are currently active. In this case,
the attempts that started at 1250, 1350 and 1450 ns have not yet completed.
• Peak Active Count - 4 — This represent the maximum number of start attempts active at
any time.
For these counts, note that:
Note
Assertion Success is a term used to describe coverage statistics for assertions. Assertion
Successes are those assertions that never failed and passed at least once. In the absence of “-
assertcover” Assertion Passes are not counted, and Assertion Successes are those assertions that
never failed.
3. The Assertions window lists all embedded and external assert directives that were
successfully compiled and simulated during the current session. The plus sign (’+’) to
the left of the Name field lets you expand the assertion hierarchy to show its elements
(properties, sequences, clocks, and HDL signals).
4. The Assertions window includes several columns for displaying information about
assertions. See Assertions Window for a description of each field.
5. When assertions fire with failure messages, the Assertions window displays the name
and failure count in red, both during simulation and in post-simulation mode
(Figure 21-18).
Figure 21-18. Assertion Failures Appear in Red
6. You can use the assertion count command to return the sum of the assertion failure
counts for a specified set of assertion directive instances. This command returns a “No
matches” warning if the given path does not contain any assertions.
Related Topics
Assertions Window Display Options
Filtering Data in the Assertions and Cover Directives Window
3. The Cover Directives window displays accumulated cover directive statistics at the
current simulation time, including percentages and a graph for each directive and
instance. The plus sign (’+’) to the left of the Name field lets you expand the directive
hierarchy to show its elements (properties, sequences, clocks, and HDL signals). Refer
to Cover Directives Window for a description of each column.
Related Topics
Display Options for Cover Directives
Filtering Data in the Assertions and Cover Directives Window
If ‘a’ is true throughout the simulation, then the above assertion will start a brand new attempt at
every clock. An attempt, once started, will only be alive until the next clock. So this assertion
will not appear abnormally high in the Memory and Peak Memory columns, but it will have a
high count in the Cumulative Threads column.
• Right-click any selected assertion and select Add Wave > Selected Objects from
the popup menu; or right-click any selected cover directive and select Add Wave >
Selected Functional Coverage from the popup menu.
2. Questa SIM represents assertions and cover directives as signals or waveforms in the
Wave window. The Wave window in Figure 21-20 shows several SystemVerilog
assertions and a single cover directive. SystemVerilog assertions are represented by
light blue triangles in the pathnames column. SystemVerilog cover directives are
represented by light blue chevrons.
Figure 21-20. SystemVerilog Assert and Cover Directives in the Wave Window
3. The Wave window in Figure 21-21 shows several PSL assertions and cover directives.
PSL assertions are represented by magenta triangles. PSL cover directives are
represented by magenta chevrons.
Figure 21-21. PSL Assert and Cover Directives in the Wave Window
4. The name of each assertion and cover directive comes from the assertion code. The plus
sign (’+’) to the left of the name indicates that an assertion or cover directive is a
composite trace and can be expanded to show its elements (properties, sequences,
clocks, and HDL signals). Note that signals are flattened out; hierarchy is not preserved.
5. The value in the value pane is determined by the active cursor in the waveform pane.
The value will be one of ACTIVE, INACTIVE, PASS, FAIL, or ANTCDENT.
6. The waveform for an assertion or cover directive represents both continuous and
instantaneous information.
• Continuous information is either active or inactive. The directive is active anytime it
matches the first element in the directive. When active, the trace is green; when
inactive it is blue.
• Instantaneous information is represented as a start, pass, or fail event. A start event is
shown as a blue square. A green triangle represents a pass. And a red triangle
indicates a fail.
7. A yellow triangle represents an antecedent match (Figure 21-22). The yellow triangle is
displayed only if the directive is browseable and assertion debug is on (vsim -
assertdebug). The yellow triangle is shown for each thread of the assertion under
ActiveCount in the assertion (see Using the Assertion Active Thread Monitor). The
signal values of the assertion also reflect the antecedent match (ANTCDENT).
8. Table 21-1 summarizes the graphic elements for assertions and cover directives used in
the Wave and ATV windows (see Viewing Assertion Threads in the ATV Window):
Related Topics
Displaying Cover Directives in Count Mode
The hierarchical display mode can be enabled or disabled by doing any one of the following:
• When the Assertions window is docked, select Assertions > Display Options >
Hierarchy Mode from the Main menus.
• Right-click in the Assertions window and select Display Options > Hierarchy Mode
from the popup menu.
The Display Options menu also includes the following options:
• The Recursive Mode option displays all assertions at and below the selected hierarchy
instance, the selection being taken from a Structure window. (i.e., the sim tab).
Otherwise only items actually in that particular scope are shown.
• The Show All Contexts option displays all instances in the design. It does not following
the current context selection in a structure pane. The Show All Context display mode
implies the recursive display mode as well, so the Recursive Mode selection is
automatically grayed out.
• The Show Concurrent Asserts option displays only concurrent assertions.
• The Show Immediate Asserts option displays only immediate assertions.
2. Count mode can be useful for evaluating the effectiveness of stimulus over time. If all
cover directive counts are static for a long period of time, it may be that the stimulus is
acting in a wasteful manner and can be improved.
Comparing Assertions
Questa SIM’s compare feature allows you to compare assertions (which includes any assertion-
like object such as accAssertion, accCover, accEndpoint, or accImmediateAssert.) There is no
cross-compare with assertion types outside the set listed, and assertion compare is further
limited to like types only. That is, both the reference and test items must be of the same type.
Comparing assertion signals differs from comparing normal HDL signals/ports because
assertion signals have two attributes:
All existing compare commands are supported for comparing assertion signals. Refer to the
Command Reference for syntax and command descriptions.
The Waveform Comparison Wizard will guide you through the selection of a reference dataset
and a test dataset. Assertions within those datasets are compared along with other signals. You
can start the Wizard is by selecting Tools > Waveform Compare > Comparison Wizard.
compare:/top/\my_assertion_sig<>my_assertion_sig\
The compare signal created is composed of the reference signal and the test signal. Differences
between the reference and text assertion signals are highlighted in red in the compare signal
when it is displayed in the Wave Window. Assertion differences cannot be viewed in the ATV
window.
Child Signals
An assertion object is composed of child signals. It is the evaluation of these child signals that
determine the assertion event (START/PASS/FAIL). If you choose to expand the assertion, the
difference marker is propagated to the child signals as well, but this may not necessarily mean a
change in value on the child signal at that specific time — the difference could have occurred
earlier.
If the reference signal has child signals but the test signal does not, or vice-versa, waveform
compare will still work because compare cares only about the absolute event on the assertion. If
there is a difference, it will be marked.
When coverage save is used without switches and arguments, all assertion and cover directive
metrics are saved to the UCDB. For details, see Saving Assertion and Cover Directive Metrics.
Related Topics
Assertion/Cover Directive Naming Conventions
The coverage exclude -assertpath and -dirpath options are only operational in the Coverage
View mode. During active simulation, these command options have no effect. See coverage
exclude for full syntax details.
Note
The output file defined by the -assertfile <filename> argument will also contain VHDL
assert messages.
Limitations
In some circumstances, processing cover directive will produce too many matches, causing the
cover count to be too high. The problem occurs with coverage of sequences like {{a;b} | {c;d}}
or {a[*1 to 2]; b[*1 to 2]}. In this instance, the same sequence for the same input at the same
start time may succeed simultaneously in multiple ways. The first sequence may succeed with a
and c followed on the next cycle by b and d; this satisfies both the simultaneous {a;b} and {c;d}
sequences. Logically, the evaluation should increment the count once and only once for a single
directive with a given set of inputs from a given start time, but the Questa SIM implementation
will increment the count twice.
The usage flow for PSL assertions and cover directives is shown in Figure 21-26.
When using optimization (vopt +acc), you may still specify assertions at compile time, but you
may also specify an external PSL file when you optimize your design with the vopt command.
Use the -pslfile_vl argument for PSL files that apply to Verilog modules and the -pslfile_vh
argument for PSL files that apply to VHDL modules.
There are several advantages to loading PSL files along with vopt:
• Rather than specifying a PSL file for every invocation of the compilers, you can put all
assertions in one file and specify that to vopt.
• Vunits can be bound to design unit instances only when provided to vopt using -
pslfile_vl/-pslfile_vh.
The vopt command maintains assertions that were compiled with vcom or vlog whether they
are embedded or external vunits.
PSL Syntax
PSL assertions are embedded using metacomments prefixed with 'psl'. For example:
-- psl sequence s0 is
-- {b0; b1; b2};
Note that the second line did not require a 'psl' prefix. Once in PSL context, the parser will
remain there until a PSL statement is terminated with a semicolon (';').
Note
The endpoint construct is not part of the IEEE Std 1850-2005. However, it was
present in the original Accellera PSL standard upon which Questa SIM’s PSL
support was based. Support of the endpoint construct will be maintained in Questa SIM.
Examples
Example 11-1 shows how embedded assertions should appear in your code.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.constants.all;
entity dram_control is
generic ( BUG : Boolean := TRUE );
port ( clk : IN std_logic;
reset_n : IN std_logic;
as_n : IN std_logic;
addr_in : IN std_logic_vector(AIN-1 downto 0);
addr_out: OUT std_logic_vector(AOUT-1 downto 0);
rw : IN std_logic; -- 1 to read; 0 to write
we_n : OUT std_logic;
ras_n : OUT std_logic;
cas_n : OUT std_logic;
ack : OUT std_logic );
end entity dram_control;
begin
.
For example, suppose you have a module called test with the following embedded PSL:
/* psl begin
default clock = (posedge clk);
A_E:assert always {b0} |=> b1;
always @(posedge clk)
$display($time, " TEST : posedge clk.");
end
*/
vunit v2(test)
{
default clock = (posedge clk);
A_V:assert always {b0} |=> b1;
always @(posedge clk)
$display($time, " VUNIT : posedge clk.");}
The compiler(vlog/vcom) -nopsl argument disables any embedded PSL parsing. This will
prevent parsing of any code within the PSL metacomment including any HDL code in the
metacomment. It has no effect on the vunit parsing in any way. If you provide a vunit file using
the -pslfile argument then the entire vunit will be parsed and code will be generated for it.
If you simulate with the vsim -nopsl switch, evaluation of all PSL assume/assert/cover
directives and endpoints will be disabled. It will not, however, affect any HDL code which was
present in a PSL metacomment or in a vunit.
Four possible simulation scenarios (using the Verilog example files located at <install_dir>/
examples/psl/verilog/nopsl_switch) are as follows:
This will display the TEST and VUNIT messages and evaluate assertions A_V and
A_E.
2. The -nopsl argument is only used during simulation.
vlog doctest.v -pslfile doctest.psl
vsim -c test -do "run -all" -nopsl
This will display only the VUNIT messages and evaluate assertion A_V.
Syntax
vunit name [(<HDL_design_unit>)]
{
default clock = <clock_decl>;
<assertions>;
...
}
name
<HDL_design_unit>
Can also be a design unit instance if you are running the simulation without optimization (see
Using PSL Assertions and Cover Directives).
Optional.
If the design unit is unspecified the vunit does not bind to anything.
Unbound vunits may be "inherited" from other vunits using the PSL keyword inherit. This
option is available only if you are running the simulation with optimization. (See Using PSL
Assertions and Cover Directives).
<clock_decl>
<assertions>
Restrictions
The following restrictions exist when providing PSL assertions in a separate file.
vunit check_dram_controller(dram_control)
{
default clock = rose(clk);
assert refresh_rate;
assert check_refresh;
assert check_write;
assert check_read;
}
Internally Questa SIM adds a `define VHDL_DEF or VLOG_DEF depending on how you read
in the .psl file — with vcom, vlog, or the -pslfile_vh/-pslfile_vl switches for vopt. For example,
if you read in the following file using vlog -pslfile or vopt -pslfile_vl, Questa SIM will ignore
the first vunit and parse the second:
`ifdef VHDL_DEF
vunit v1 ( top(a) )
{
default clock is rose(clk);
property vh_clk is always (a and b);
assert vh_clk;
}
`endif
`ifdef VLOG_DEF
vunit v1 ( top )
{
default clock = rose(clk);
property vl_clk = always (a && b);
assert vl_clk;
}
`endif
library modelsim_lib;
use modelsim_lib.util.all;
vunit top_vunit(test) {
signal vunit_local_sigA : bit := '0';
signal vunit_loc_sigB : bit := '0';
initial_proc: process
begin
--spy on a signal in a package
init_signal_driver("/pack/global_signal", "vunit_local_sigA");
--spy on a internal signal
init_signal_driver("/test/aa/internal_signal_AA",
"vunit_loc_sigB");
wait;
end process initial_proc;
Here are two points to keep in mind about library and use clauses in PSL files:
• If you already have the use clause applied to an entity, then you don’t need to specify it
for the vunit. The vunit gets the entity's complete visibility.
• If you have two vunits in a file and the use clause at the top, the use clause will apply
only to the top vunit. If you want the use clause to apply to both vunits, you have to
specify it twice. This follows the rules for use clauses as they apply to VHDL entities.
Default Clock
Any PSL assertion that is not individually clocked and appears below a default clock statement
will be clocked by the default clock.
For example:
The first assertion is sensitive to clk1. The second assertion is sensitive to clk (the default clock).
In this case, only the RHS of the implication(|->) expression is clocked. The outermost property
is unclocked, so default clock applies to this assertion.
Also, the complete assertion property, because it is not a simple expression, must be clocked.
For example, if you have the following assertion:
and no default clock preceding it, then since part of the property is unclocked, Questa SIM will
produce an error.
In this property, the @ operator has more precedence than the always operator, so the property
is interpreted like this:
Note that the always operator is unclocked but the property under always is clocked. This is
acceptable because Questa SIM detects that the property is to be checked at every rose(clk1).
Other Restrictions
Example 21-3 and Example 21-4 are two complete examples that demonstrate the use of
ended() in Verilog and VHDL code, respectively.
module test;
reg clk;
initial clk = 0;
always #50 clk <= ~clk;
initial
begin
b1 <= 0; b2 <= 0;
#100; b1 <= 0; b2 <= 0; //100
#100; b1 <= 0; b2 <= 0; //200
#100; b1 <= 0; b2 <= 0; //300
#100; b1 <= 1; b2 <= 0; //400
#100; b1 <= 1; b2 <= 1; //500
#100; b1 <= 1; b2 <= 1; //600
#100; b1 <= 0; b2 <= 0; //700
#100; b1 <= 0; b2 <= 1; //800
#100; b1 <= 0; b2 <= 0; //900
#100; b1 <= 0; b2 <= 0; //1000
#100;
$finish;
end
endmodule
use STD.textio.all;
entity test is
end test;
architecture a of test is
signal clk_0 : bit := '0';
signal clk_1 : bit := '0';
signal b1 : bit := '0';
signal b2 : bit := '0';
begin
-- psl begin
-- sequence s0(Boolean b_f) is {b1[*2]; [*0 to 2]; b_f};
-- sequence se0(Boolean clk_f) is {s0(b2)}@rose(clk_f);
-- end
endp_0 : process(clk_0)
variable test_val_0 : BOOLEAN;
variable vline : line;
begin
test_val_0 := ended(se0(clk_0));
write(vline, now);
write(vline, string'(": test_val_0 = "));
write(vline, test_val_0);
writeline(OUTPUT, vline);
end process;
endp_1 : process(clk_1)
variable test_val_1 : bit;
variable vline : line;
begin
if (ended(se0(clk_1)) = true) then
test_val_1 := '1';
else
test_val_1 := '0';
end if;
write(vline, now);
write(vline, string'(": test_val_1 = "));
write(vline, test_val_1);
writeline(OUTPUT, vline);
end process;
process
begin
wait for 400 ns; b1 <= '1'; b2 <= '0'; --400
wait for 100 ns; b1 <= '1'; b2 <= '1'; --500
wait for 200 ns; b1 <= '0'; b2 <= '0'; --700
wait for 100 ns; b1 <= '0'; b2 <= '1'; --800
wait for 100 ns; b1 <= '0'; b2 <= '0'; --900
wait for 300 ns; b1 <= '1'; b2 <= '1'; --1210
wait for 100 ns; b1 <= '1'; b2 <= '0'; --1300
end a;
Note
In VHDL, unused endpoints (defined but not used in the design) are optimized away during
compilation.
The design and its associated assertions file must be compiled in the same invocation.
See Using PSL Assertions and Cover Directives for more information.
PSL Limitations
Questa SIM supports the simple subset of PSL constructs and semantics as described in the
IEEE Std 1850-2005, except the following:
• next(), nondet, and nondet_vector() built-in functions
• Union expressions
• OBE properties
• assume_guarantee, restrict, restrict_guarantee, fairness and strong fairness directives
• Integer Range and Structure
The current release also has the following limitations.
• Vunits can be bound to design unit instances only when provided to vopt using -
pslfile_vl/-pslfile_vh.
• Level-sensitive clock expressions are not allowed.
• There is no support for integer, structures, and union in the modeling layer.
• There is no support for post-simulation run of assertions (i.e., users cannot run the
assertion engine in post-simulation mode).
property abc(a,b,c);
disable iff (a==2) @ (posedge clk) not (b ##1 c);
endproperty
env_prop: assert property (abc(rst,in1,in2)) pass_statement;
else fail_statement;
When no action is needed, a null statement is specified. If no statement is specified for else, then
$error is used as the statement when the assertion fails.
For SystemVerilog and VHDL immediate assertions, passes and failures cannot be enabled or
disabled independently. So if AssertionEnable or assertion enable are used, both passes and
failures are enabled for immediate assertions.
The "statement_or_null" syntax indicates an optional statement to be executed every time the
property succeeds or the sequence is matched.
The vopt command performs global optimizations on designs after they have been compiled
with vcom or vlog and produces an optimized version of your design in the working directory.
You must provide a name for this optimized version using the -o switch. You can then invoke
vsim directly on that new design unit name.
In the course of optimizing a design, the vopt utility will remove objects deemed unnecessary
for simulation — line numbers are removed, processes are merged, nets and registers may be
removed, etc. For debugging, you preserve object visibility into your assertions by using the
+acc=a argument with the vopt command. The +acc=a argument specifies which objects are to
remain accessible for the simulation. In this case the “a” stands for assertions. (See Preserving
Object Visibility for Debugging Purposes.)
When you invoke vsim on the design, the simulator automatically loads any assertions that are
present. The -assertdebug argument makes detailed assertion and cover directive information
available for viewing in the debugging windows of the GUI (see the next section, Viewing
Debugging Information).
When you invoke vsim on the optimized version of the design, the simulator automatically
loads any assertions that are present. The -assertdebug argument makes detailed assertion and
cover directive information available for viewing in the debugging windows of the GUI (see the
next section, Viewing Debugging Information).
If the -assertdebug argument is set with the vsim command, the coverage save command will
save the detailed assertion and cover directives information in the .ucdb file (see Saving
Assertion and Cover Directive Metrics). This information can be called up and viewed in the
debugging windows with the vsim-viewcov <filename>.ucdb command.
If the +acc=a argument is used with the vopt command and the -assertdebug argument is set
with the vsim command, the coverage save command will save the detailed assertion and cover
directives information in the .ucdb file (see Saving Assertion and Cover Directive Metrics).
This information can be called up and viewed in the debugging windows with the vsim-viewcov
<filename>.ucdb command.
Results
With assertion debugging enabled, assertion fail messages will be displayed in the transcript
and will include the expression that caused the assertion failure. Assertion failures are also
listed in the Message Viewer window (View > Message Viewer) under “Error.”
Local variable values corresponding to failed assertion threads are printed to the Transcript
along with assertion error messages when vsim is run with -assertdebug. This can be turned on/
off (default on) with AssertionFailLocalVarLog modelsim.ini variable or by using the CLI
assertion fail -lvlog command. For example:
# ** Error: Assertion error.
# Time: 450 ns Started: 250 ns Scope: test File: src/lvlog1.sv Line: 19 Expr: x==1
# Local vars : x = 0, s11 = '{x:'{10, 0, 0, 0, 0, 0, 0, 0, 0, 0}, y:1}
Note
There is a performance penalty when assertion debugging and assertion thread viewing are
enabled. You should use these features only when you need to debug failures.
Related Topics
Analyzing Assertions and Cover Directives
If you want access to the Assertion Thread Viewer (ATV), you must activate ATV recording
before the simulation is run with these two steps:
Procedure
1. The -assertdebug argument must be enabled with the vsim command, or “Enable
assertion debug” must be selected in the Others tab of the Start Simulation dialog.
2. ATV recording must be enabled with the atv log command.
An assertion path is specified with atv log -enable <path>... prior to running the
simulation so thread data can be collected over the course of the entire simulation. More
than one assertion path may be included in each atv log command.
3. You can also enable ATV recording with the GUI by doing one of the following when
the Assertions window is active and one or more assertions is highlighted:
• Select Assertions > Enable ATV from the menus.
• Right-click (RMB) any highlighted assertion or assertions and select Enable ATV
from the popup menu (Figure 21-29).
Figure 21-29. Enable ATV Menu Selection
4. When the GUI is used to enable ATV recording, the appropriate command will be
echoed to the transcript (for enabling ATV in .do files).
Examples
A correct procedure would be the following:
• The +acc=a argument is used with the vopt command to preserve assertion visibility for
debugging; and the -o argument is used to name the optimized version of the design
(dbgver).
• The -assertdebug argument is used with vsim to enable assertion debugging.
• The -assertdebug argument is used with vsim to enable assertion debugging on the
optimized version of the design.
• The atv log command line enables ATV recording for three assertions - assert_0,
assert_1, and assert_2 - in the top module.
Procedure
1. To enable ATV recording, enter the following command:
atv log -enable <path>...\
3. When you enable ATV recording during simulation, only threads that start after the
current time will be visible.
4. You can disable ATV Recording with the GUI by unchecking the Enable ATV selection
with Assertions > Enable ATV, or right-clicking an assertion and unchecking Enable
ATV (as in Figure 21-29).
Examples
To only monitor assertion thread /top/assert_1 between time T and time T+N, the code should
be something like this:
run Tns
atv log -enable /top/assert_1
run Nns
atv log -disable /top/assert_1
run 1000ns
To make all assertion and cover directive metrics available for saving into a .ucdb file you must
do all of the following steps.
Procedure
1. Compile your design,
2. Use +acc=a with the vopt command
3. Use -assertdebug with the vsim command
4. Use the coverage save command
5. If the coverage save command is used without arguments, all assertion and cover
directive metrics are saved to the UCDB. If other coverage types (branch, statement,
condition, etc.) are specified with the coverage save command, then the -assert
argument must be used to save assertions, like this:
coverage save -code bcest -assert
6. or the -directive argument must be used to save cover directives. like this:
coverage save -code bcest -directive
7. You can specify that only assertions and cover directives be saved with:
coverage save -assert -directive
8. If the -assertdebug argument is not used with vsim, the coverage save command will
only save the fail metrics for assertions and cover directives. When -assertdebug is
used, additional metrics saved for assertion directives include:
PassEnable
PassLog
PassCount
VacuousPassCount
DisabledCount
AttemptedCount
ActiveThreadCount
PeakActiveThreadCount
9. The -assertdebug argument determines how assertion coverage numbers are calculated
in the UCDB. When the -assertdebug argument is used, an assertion is considered
covered if the PassCount is > 0. If the -assertdebug argument is not used, an assertion is
considered covered if the FailCount = 0.
10. You can also use the GUI to save assertion and cover directive metrics.
• Select Tools > Coverage Save from the Main window
This opens the Coverage Save dialog, where you can select the type of coverage you
want to save, level of hierarchy to save, and output UCDB file name.
• Select Simulate > Start Simulation from the Main window
This opens the Start Simulation dialog. In the Others tab, check the “Enable code
coverage” box and the “Enable assertion debug” box.
11. Once the data is saved, assertion and cover directive coverage can be analyzed using:
• the Assertions window (see Viewing Assertions in the Assertions Window),
• the Cover Directives window (see Viewing Cover Directives in the Cover Directives
Window),
• the Wave window (see Viewing Assertions and Cover Directives in the Wave
Window),
• the Verification Management Tracker window when linked to from a Verification
Plan item (see Viewing Test Data in the Tracker Window),
• columns in the Structure Window (Cover and Assertion hits and misses) (see
Structure Window),
• the Instance Coverage window (see Instance Coverage Window),
• columns in the Verification Management Browser window (see Coverage and
Verification Management in the UCDB),
• and the coverage report and vcover report commands.
12. These methods are all available in live simulation mode as well as the Coverage View
(post-processing) mode.
Related Topics
Assertion/Cover Directive Naming Conventions
The Signals of Interest column displays the signals responsible for the assertion failure.
You can analyze these signals further in the Dataflow window by right-clicking a signal
and selecting Show Signal Drivers.
Questa SIM supports the PSL forall keyword, which replicates designated assertions
multiple times and reports PASS or FAIL on assert directives that contain replicators.
The Replicator Parameters column displays the value of the replicator parameter for
which the assertion failed.
The Assertion Active Thread Monitor is controlled by the BreakOnAssertion .ini variable,
whose default value is 1 (enabled). The number of rows the Assertion Active Thread Monitor
displays is limited, and is controlled by the AssertionActiveThreadMonitorLimit .ini variable.
Note
A large number of active thread rows will result in large .wlf files and increased memory
usage. The default for AssertionActiveThreadMonitorLimit is 5.
As with the main assertion Wave display, assertion start (blue square), pass (green triangle), fail
(red triangle), and antecedent match (yellow triangle) symbols appear in the active thread
monitor display. Right-clicking on one of these symbols reveals a View ATV menu selection
which will show assertion evaluation attempt start times. Selecting a start time will open an
assertion thread view. See Viewing Assertion Threads in the ATV Window.
• From the command line — The add atv command opens an ATV window for the
specified assert or cover directive (designated by its pathname), at the specified
evaluation attempt start time. For example:
• add atv /top/assert_1 450 ns
• From the Assertion Active Thread Monitor in the Wave window — Right-click any
assertion start (blue square), pass (green triangle), and fail (red triangle) symbol to
open a popup menu. Select View ATV, then an assertion evaluation attempt start
time. See Using the Assertion Active Thread Monitor.
• From the menu bar — Select (highlight) an assertion in the Assertions window then
select Assertions > Add ATV from the menus. This will bring up the View Thread
dialog, which allows you to select an assertion evaluation attempt start time. Note
that a given assertion instance typically has many evaluation attempt start times.
Any one of these times may be selected from the dialog box (Figure 21-32).
Selecting (or typing) an entry will bring up the ATV view for that particular instance
and starting time.
Figure 21-32. Selecting Assertion Thread Start Time
Note
If the Start Time and Logged Start Times fields are empty, either ATV recording
has not been enabled or no evaluation attempts have occurred.
• From the Assertions window — Right-click (RMB) any assertion and select View
ATV from the popup menu. Making this selection brings up the View Thread dialog
box (Figure 21-32), where you can select an evaluation attempt start time.
The View Thread dialogue allows you to filter the displayed list of logged thread
starting times by failed, passed, and still-active attempts.
• From the Wave window — If the assertion is logged, there will be symbols on the
assertion signal consisting of start objects (blue squares), pass objects (green
triangles) and fail objects (red triangles). Right-clicking near one of these objects
will open a pop-up menu with a View ATV selection and a sub-menu of evaluation
attempt start times (Figure 21-33). Select a start time to bring up the ATV view for
the selected assertion or cover directive.
Note
If the sub-menu of evaluation attempt start times is empty, ATV recording has
not been enabled.
Note
If the sub-menu of evaluation attempt start times is empty, ATV recording has
not been enabled.
Expression Pane
The Expression pane is a hierarchical representation of the assertion. From bottom to top, each
term in the assertion statement is represented following the left to right order of the original
expression. From left to right, the hierarchy of expression statements is represented with the
highest order terms on the left and the child terms on the right. Each term that has children can
be expanded or collapsed in the viewer by clicking on the ‘+’ and ‘–’ symbols. To expand or
collapse all terms, right-click anywhere in the Expression Pane and select Expand All Terms
or Collapse All Terms.
Failed boolean expressions are highlighted in red(Figure 21-36).
By default, assertion expressions are displayed in the Expressions Pane in descending order.
You can change to ascending order by right-clicking in the Expressions Pane and selecting
Ascending Order from the popup menu.
Assertion statement progress is shown on the Y axis. The Y axis coordinates map directly to the
expression terms shown in the thread expression pane. So, as a thread is seen jumping to a
particular Y level, this shows that a particular term is being evaluated.
• When the ATV window is docked in the Main window, select ATV > Show Local
Vars.
• When the ATV window is undocked, select View > Show Local Vars.
A solid blue square indicates a local variable.
Local variable assignments are stripped out of the assertion statement at the top of the Thread
Viewer Pane for readability, but they do appear in the Expression Pane as “(LV assign).” You
can hover the cursor over any local variable icon (blue square) in the Thread Viewer pane to see
the actual assignment; or turn on local variables annotation (see Annotating Local Variables).
When a thread is highlighted (see Highlighting a Thread) and it contains local variables, the
values for the local variables on that highlighted thread will appear in the Local Variables Pane
(Figure 21-37).
Like other windows in the GUI, the display radix for the values in the Local Variables Pane are
controlled by the radix command.
The values shown in the Design Objects pane are the values used when the assertion expression
is evaluated. For PSL assertions, the values are at the time that the clock transitions. For
SystemVerilog assertions, the values at the beginning of the simulation time step before any
signals have transitioned In either case, these values may be different than the values for these
objects at the end of that simulation time step.
assert property (@(posedge clk) (b0 |=> ((b1 && b2) || b3)));
Even though ((b1 && b2) || b3)) is a boolean expression, the ATV window will show which
sub-expression – b1/b2/b3 – failed. In the Assertions window we right-click the assertion and
select View ATV from the popup menu. This opens the View Thread dialog, where we’ll elect
to Start at 150 ns (Figure 21-38).
This opens the ATV window for the assertion, as shown in Figure 21-39.
Highlighting a Thread
You can highlight any thread in the Thread Viewer Pane to differentiate it from the other
threads by simply clicking on it with the left mouse button. Highlighting appears as a bold
purple line. Depending on where the thread is clicked, any sub-threads that are forked and occur
to the right of the click-point will also be highlighted. Going left, parent thread events which
lead up to the current thread and selection point will also be highlighted. Any parent thread
forks, other than the one which leads to the selected thread, will not be highlighted.
In Figure 21-42, a Thread Failed icon (hollow red triangle) is clicked, showing the path from the
start thread to the failure. In this case, the thread failure is redundant because other threads of
the assert directive are still running.
Hovering over a SystemVerilog local variable assignment symbol (a large blue square) reveals
the values assigned to the particular local variables at that point (Figure 21-43).
• When the ATV window is docked in the Main window, select ATV > Annotate Local
Vars from the Main menu bar.
• When the ATV window is undocked, select View > Annotate Local Vars from the
menu bar.
• Right-click anywhere in the Thread Viewer Pane and select Annotate Local Vars from
the popup menu.
When Annotate Local Vars is selected, annotation appears in the Thread Viewer Pane only on
the highlighted thread, as shown in Figure 21-45.
SystemVerilog implements functional coverage with covergroups and cover directives (for
more information on cover directives, see chapter entitled “Verification with Assertions and
Cover Directives”). Because cover directives are usually temporal and can inspect multiple
signals and states in the same evaluation, they are usually inserted by designers in the design
source as "white box" testing – i.e., they specify and validate the expected behavior of a design.
This allows the verification tool to observe (and log) when particular events occur or
assumptions are violated.
Because covergroups operate upon integral values and have limited temporal features, they are
most often inserted in the test bench itself as "black box" testing. That is, the values monitored
by covergroups are most often high-level test bench or design features, like transaction types,
modes, addresses, opcodes, and so on.
Questa SIM compiles SystemVerilog functional coverage constructs along with other
SystemVerilog code when either the source file ends in .sv or you specify the -sv argument to
vlog command.
When you invoke vsim on the top-level of the design, the simulator automatically handles any
functional coverage constructs that are present. Next, you run the simulation. You may
optionally view coverage interactively in the GUI with commands such as ‘coverage report’,
and/or save off coverage to the Unified Coverage DataBase (UCDB) with the ‘coverage save’
command. The UCDB can then be used for reporting, merging, ranking, or other types of
verification analysis.
change covervar.type_option.weight 20
If set at the covergroup syntactic level, this command specifies the weight of this covergroup for
computing the overall cumulative (or type) coverage of the saved database. If set at the
coverpoint (or cross) syntactic level, it specifies the weight of a coverpoint (or cross) for
computing the cumulative (or type) coverage of the enclosing covergroup.
Note that a type_option is not accessible with the type name and "::" in the command line
interface. Instead, refer to the type_option through an instantiated covergroup variable, as
shown in the example above.
• set to 0 in the SV code — aggregated bins do not exist for this algorithm choice
• set to 1 in the SV code — aggregated bins do exist
• not set — in this case, the Questa default is determined according to the dictates
outlined in the section “SystemVerilog 2009 type_option.merge_instances”. If the tool
chooses to set it to 0, you won't have any aggregated bins, or you can use vsim -
cvgmergeinstances at runtime to override the default tool setting.
The equivalent modelsim.ini variable is SVCovergroupMergeInstancesDefault (0|1). For more
information and some examples of SV code containing these options, see IEEE Std 1800-2009
Option Behavior.
There are certain cases in which the optimization can not be performed. For example, if a
coverpoint participates in a cross, such coverpoint can not be disabled since the sampling of the
cross may require the sampling of the coverpoint. When such optimization can not be done on a
particular coverpoint/cross/covergroup instance, the instance will be handled in the same way as
in a normal simulation.
Related Topics
change
vsim
Loading a Functional Coverage Database into Simulation
For details on this function, you can refer to IEEE Std 1800-2009 LRM, Section 19.9.
The changes as they relate to covergroup calculation and reporting — and instructions for
reverting the settings — are summarized in Table 22-1:
The default in the 2009 standard, if you were to explicitly set it in the code, would be:
The report generated for default option settings would look like this:
# COVERGROUP COVERAGE:
# -----------------------------------------------------------------------
# Covergroup Metric Goal/ Status
# At Least
# -----------------------------------------------------------------------
# TYPE /top/cgtype 50.0% 100 Uncovered
# Coverpoint cgtype::vbl 50.0% 100 Uncovered
# Covergroup instance \/top/ci 50.0% 100 Uncovered
# Coverpoint vbl 50.0% 100 Uncovered
# covered/total bins: 1 2
# missing/total bins: 1 2
# bin b['b000000] 1 1 Covered
# bin b['b000011] 0 1 ZERO
#
# TOTAL COVERGROUP COVERAGE: 50.0% COVERGROUP TYPES: 1 #
In this case, the coverage of the covergroup type is the average of the two covergroup instances.
Since each of the two instances has 50% coverage, the type-based coverage is also 50%. The
type-based coverage is computed as a weighted average based on the option.weight of each
covergroup instance.
By default, the following coverage report is produced with instances visible. For example:
It results in a detailed display of data in the GUI and reports, including the instances. If you
want to hide the instances, use the -hidecvginstspi0 argument to the coverage/vcover report
command.
Note
When type_option.merge_instances is set to 0, since the type-based coverage is calculated
from covergroup instances rather than child coverpoints and crosses, the
type_option.weight specified in coverpoints and crosses has no effect on the type-based
coverage of the covergroup.
In this table, the default settings for the options are indicated with bold values.
In this example, using both 'merge_instances' and 'get_inst_coverage' you can get different
results for the two methods: get_inst_coverage and get_coverage.
module get_inst_example;
typedef enum {red, white, blue} color;
color c1;
covergroup color_cg;
type_option.merge_instances = 1;
option.get_inst_coverage = 1;
coverpoint c1;
endgroup : color_cg
color_cg cg_inst_1 = new();
color_cg cg_inst_2 = new();
initial
begin
c1 = red;
cg_inst_1.sample();
$display("Sampled 'red' in cg_inst_1 and results are...");
$display("cg_inst_1.get_inst_coverage() == %f",
cg_inst_1.get_inst_coverage());
$display("cg_inst_1.get_coverage() == %f", cg_inst_1.get_coverage());
$display("");
$display("cg_inst_2.get_inst_coverage() == %f",
cg_inst_2.get_inst_coverage());
$display("cg_inst_2.get_coverage() == %f", cg_inst_2.get_coverage());
end
endmodule : get_inst_example
• 6.6 — Default settings for options were changed to be IEEE 1800-2009 compliant
• 6.4 — type_option.merge_instances and option.get_inst_coverage were added
It is possible that tests or scripts you have developed may depend on some legacy behavior. To
ease the transition, use the information contained in Table 22-1 on Questa SIM and
SystemVerilog IEEE 1800-2009 Options.
Related Topics
change
vsim
module top;
int vbl;
covergroup cgtype (int lhs, rhs);
option.per_instance = 1;
type_option.merge_instances = 1;
coverpoint vbl {
bins b[] = { lhs, rhs };
}
endgroup
cgtype cgvar1_2 = new(1,2);
cgtype cgvar1_3 = new(1,3);
initial
begin
vbl = 1;
cgvar1_2.sample();
vbl = 3;
cgvar1_3.sample();
$display("cgvar1_2.get_inst_coverage() == %f",
cgvar1_2.get_inst_coverage());
$display("cgvar1_3.get_inst_coverage() == %f",
cgvar1_3.get_inst_coverage());
$display("cgvar1_2.get_coverage() == %f", cgvar1_2.get_coverage());
$display("cgvar1_3.get_coverage() == %f", cgvar1_3.get_coverage());
end
endmodule
# COVERGROUP COVERAGE:
# -----------------------------------------------------------------------
# Covergroup Metric Goal/ Status
# At Least
# -----------------------------------------------------------------------
# TYPE /top/cgtype 66.7% 100 Uncovered
# Coverpoint cgtype::vbl 66.7% 100 Uncovered
# bin b[1] 1 1 Covered
# bin b[3] 1 1 Covered
# bin b[2] 0 1 ZERO
# Covergroup instance \/top/cgvar1_2 50.0% 100 Uncovered
# Coverpoint vbl 50.0% 100 Uncovered
# bin b[1] 1 1 Covered
# bin b[2] 0 1 ZERO
# Covergroup instance \/top/cgvar1_3 50.0% 100 Uncovered
# Coverpoint vbl 50.0% 100 Uncovered
# bin b[1] 0 1 ZERO
# bin b[3] 1 1 Covered
#
# TOTAL COVERGROUP COVERAGE: 66.7% COVERGROUP TYPES: 1
The instance coverage is clear – each covergroup instance has 50% coverage because each has
two bins and only one of those is covered.
The type-based coverage is a little more complicated. The type-based coverage is 66.7%, or two
out of three bins covered. The reason is that the type has three bins. Since
type_option.merge_instances is in effect, the total number of bins is the union of bins of all
instances. The cgvar1_2 instance has the set of bins { b[1], b[2] }. The cgvar1_3 instance has
the set of bins { b[1], b[3] }. The union of these two sets of bins is { b[1], b[2], b[3] }. Of this
set of bins, the set { b[1], b[3] } is actually covered. So type-based coverage is 2 / 3 =
66.666666%.
Questa SIM’s approach is to consider bins to be the same if they have the same name. This
relies on a naming convention that is not completely specified by the IEEE Std 1800-2009
LRM. For more details on the naming convention used, see “Canonical String Representation
for Coverpoint Bin Value”.
1 bins a = { 1, 2, 3 }; // bin a
2 bins b[] = { 1, 2, 3 }; // bins b[1], b[2], b[3]
3 bins c[2] = { 1, 2, 3 }; // bins c[0] <- 1; c[1] <- 2,3
The first two examples clearly declare bins a, b[1], b[2], and b[3]. But what of the bins
specified with identifier “c?” Questa SIM specifies bins c[0] and c[1]. This is consistent with
the constructs in the LRM where bins with an explicit size constant (as is the case for identifier
"c") are taken very literally in order. For example, "bins c[2] = { 1, 1 };" is perfectly legal. In
this case, c[0] is incremented when the value 1 is sampled, and so is c[1].
Now, reconsider Example 22-2 with an explicit size constant in the bin declaration, as shown in
Example 22-3:
module top;
int vbl;
covergroup cgtype (int lhs, rhs);
option.per_instance = 1;
type_option.merge_instances = 1;
coverpoint vbl {
bins b[2] = { lhs, rhs }; // now with explicit size constant!
}
endgroup
cgtype cgvar1_2 = new(1,2);
cgtype cgvar1_3 = new(1,3);
initial
begin
vbl = 1;
cgvar1_2.sample();
vbl = 3;
cgvar1_3.sample();
$display("cgvar1_2.get_inst_coverage() == %f",
cgvar1_2.get_inst_coverage());
$display("cgvar1_3.get_inst_coverage() == %f",
cgvar1_3.get_inst_coverage());
$display("cgvar1_2.get_coverage() == %f", cgvar1_2.get_coverage());
$display("cgvar1_3.get_coverage() == %f", cgvar1_3.get_coverage());
end
endmodule
# COVERGROUP COVERAGE:
# -----------------------------------------------------------------------
# Covergroup Metric Goal/ Status
# At Least
# -----------------------------------------------------------------------
# TYPE /top/cgtype 100.0% 100 Covered
# Coverpoint cgtype::vbl 100.0% 100 Covered
# bin b[0] 1 1 Covered
# bin b[1] 1 1 Covered
# Covergroup instance \/top/cgvar1_2 50.0% 100 Uncovered
# Coverpoint vbl 50.0% 100 Uncovered
# bin b[0] 1 1 Covered
# bin b[1] 0 1 ZERO
# Covergroup instance \/top/cgvar1_3 50.0% 100 Uncovered
# Coverpoint vbl 50.0% 100 Uncovered
# bin b[0] 0 1 ZERO
# bin b[1] 1 1 Covered
#
# TOTAL COVERGROUP COVERAGE: 100.0% COVERGROUP TYPES: 1
In this case, the union of the bins in the type is { b[0], b[1] }. While it is true that in cgvar1_2,
b[1] maps from value 2, and in cgvar1_3, b[1] maps from value 3, that does not matter for the
type coverage. These are the same bin as far as the type-based coverage is concerned.
So in this case, cgvar1_2 covers bin b[0] (mapped from vbl==1) and cgvar1_3 covers bin b[1]
(mapped from vbl==3). So the instance-based coverage is 50% for each instance, and the type-
based coverage is 100% because both bins are covered for the union of bins in the type.
Projected Covergroups
Users write covergroups in template classes, and each parameterized class instance of a
template class creates separate covergroup type scopes. That causes low coverage of those
covergroup type scopes due to the fact that parameterized class instances are specifically
optimized though their covergroups are still general. As such, it is not possible to cover all the
parts of a general covergroup residing under a specifically parameterized class.
To improve the coverage of those covergroup type scopes, you can use a new covergroup option
— parameter_projection_name — to project covergroup instances from their actual covergroup
type scopes into a virtually created covergroup type scope. This allows covergroup instances
covering similar regions in different parameterized classes to associate together to form a new
covergroup type scope, thereby yielding a higher coverage number for that new covergroup.
Specifically, his projection functions by collecting some of the covergroup instances of those
different covergroup type scopes based on a key to construct a virtual covergroup type scope,
and then use the coverage of that virtual covergroup type scope instead of the original
covergroup type scopes.
The option parameter_projection_name is the key for doing the projection of covergroup
instances. The projection essentially collects together the covergroup instances from different
covergroup types in different parameterized class objects of a same template class to form a new
covergroup type scope under the template class. The name of this new covergroup type scope is
the value specified for option.parameter_projection_name. The value of this parameter setting
must be specified within the covergroup declaration, and cannot be changed later. If the
option.parameter_projection_name is not specified for a covergroup instance, then that
covergroup instance is not projected.
The following code shows an example of how to specify the parameter_projection_name for a
covergroup instance.
function new;
cvg = new ("valid");
endfunction
endclass
3. The Covergroups window displays the Coverage of each covergroup, coverpoint, cross,
and bin. Covergroup coverage is a weighted average of the coverage of the constituent
coverpoints and crosses.
4. See “Functional Coverage Computation” for additional details.
5. For a description of the columns that can be displayed, see “Covergroups Window”.
You can create an ASCII file with the functional coverage statistics by selecting Tools >
Coverage Report > Text. This brings up the Coverage Text Report dialog (Figure 22-4).
Use the Coverage Text Report dialog to create functional coverage reports on specific instances
or on all coverage items. Options allow you to report only on covergroup coverage or on
directive coverage. If covergroup coverage is selected, a functional coverage report will be
created using covergroup type objects.
• Filtering does not affect the calculation of aggregated statistics. It merely affects the data
displayed in the report.
• A report response of "No match" indicates that the report was empty.
• The report will be sorted such that all bins with 0 counts show up as the first rows. Then,
within that first section of 0-count rows, the covergroups would be the secondary sort.
Thus, all 0's in covergroup A would appear next to each other, and so on for covergroup
B, and others.
• Timestamp values are saved in the ucdb file along with coverage information when you
save coverage. Timestamp values and test names are saved with each covergroup bin.
• For reports from a simulation run (i.e. not from a ucdb file), the test name column
contains the string "Current Test" instead of a test name.
• Merging UCDB files —
If you merge two ucdb files that contain timestamp values, the output (merged) ucdb file
maintains the earliest timestamp value of the ucdb files, even if the merged cover items
have different at_least values. The merged ucdb file also maintains the test name for the
test that has the smallest timestamp value.
As a result of this fact, if you merge two different UCDB files where a timestamp value
for a covergroup bin is the same in both files, that timestamp value is only assigned to
one of the tests. You will lose the information that the second test also covered the bin at
that timestamp.
Related Topics
vsim
coverage edit
Reporting on Functional Coverage
Viewing Functional Coverage Statistics in the Covergroups Window
2. To create a new filter, click the Create button to open the Create Filter dialog
(Figure 22-6).
Figure 22-6. Create Filter Dialog
The Edit Filter dialog – which you open by clicking the Edit button in the Filter Setup
dialog - contains all of the same functions as the Create Filter dialog.
3. Click the Add button to add criteria, attributes, operators, and values to the filter in the
Add/Modify Select Criteria dialog (Figure 22-7).
Figure 22-7. Add-Modify Select Criteria Dialog
The Criterion field includes a dropdown list that corresponds to the columns in the
Assertions/Cover Directives/Covergroups window, allowing you to filter the display
according to values in a specific column or columns.
4. You can copy the criteria from an existing filter into another by clicking the Copy button
in the Filter Setup dialog, which opens the Copy Filter dialog. Or, can rename a filter by
clicking the Rename button and opening the Rename Filter dialog.
Figure 22-8. Copy and Rename Filter Dialogs
The filter you just created appears in the Filters list within the Filter Setup dialog box
(Figure 22-5).
5. Either select Apply to filter the displayed data immediately, or select Done to exit the
dialog box.
The following is sample report output from saved data using the vcover report command.
# -----------------------------------------------------------------------
# Covergroup Metric Goal/ Status
# At Least
# -----------------------------------------------------------------------
# TYPE sm_cvg 72.5% 90 Uncovered
# Coverpoint sm_cvg::int_state 50.0% 90 Uncovered
# bin idle_bin 38 500 Uncovered
# bin load_bins 5112 500 Covered
# bin send_bins 20800 500 Covered
# bin others 0 500 ZERO
# Coverpoint sm_cvg::in_hs 100.0% 90 Covered
# bin auto[0] 21448 1 Covered
# bin auto[1] 4502 1 Covered
# Coverpoint sm_cvg::out_hs 100.0% 90 Covered
# bin auto[0] 21449 1 Covered
# bin auto[1] 4501 1 Covered
# Cross sm_cvg::in_hsXint_state 62.5% 90 Uncovered
# bin <auto[0],idle_bin> 15 1 Covered
# bin <auto[1],idle_bin> 23 1 Covered
# bin <auto[0],load_bins> 633 1 Covered
# bin <auto[1],load_bins> 4479 1 Covered
# bin <auto[0],send_bins> 20800 1 Covered
# bin <auto[1],send_bins> 0 1 ZERO
# bin <auto[0],others> 0 1 ZERO
# bin <auto[1],others> 0 1 ZERO
# -----------------------------------------------------------------------
# Name Design Design Lang File(Line) Count Status
# Unit UnitType
# -----------------------------------------------------------------------
#cover_intl_sm interleaver Verilog SVA interleaver.v(140) 375 Covered
By default, the report includes coverage statistics for both covergroups and cover directives.
You may specify the -covergroup or -directive options for either the coverage report or vcover
report command to report only covergroup coverage or only cover directive coverage,
respectively.
or
Note the braces {}, which prevent Tcl from evaluating [st2].
• To exclude a covergroup instance:
coverage exclude -cvgpath {/top/mach/machcover/\/top/mach/cov }
Related Topics
coverage exclude
The transitive exclusion applies to all associated bins in the crosses where the coverpoint or
cross participates, and propagates that hierarchically into crosses where those crosses
participate. This propagation goes recursively all the way for crosses of crosses.
If a whole coverpoint or cross is excluded, then each cross where the excluding coverpoint or
cross participates will also be excluded transitively. That means the transitive exclusion will
also work in the same way for coverpoint and cross exclusions. For example:
With the coverage exclude command, bin /top/cvg/i1/y is excluded transitively. The coverage
report of exclusions then shows the exclusion of all bins associated with /top/cvg/i1/y.
Transitive exclusion works for cross userbins and autobins as well. If you exclude a cross
userbin or autobin then the associated cross bins in the cross which is associated to the first
cross (cross of crosses) will also be excluded.
A cross userbin may include a range of cross products, where some are associated with an
excluding coverpoint or cross bin and others are not. In that case the userbin will not be
excluded transitively as that contains some cross products which are not related to the excluding
coverpoint or cross bin. For simplicity, if all the cross products of an userbin are associated with
an excluding coverpoint or cross bin then the userbin could be excluded transitively. Otherwise,
you need to exclude that userbin explicitly if required.
For example, say a cross 'cx' has three coverpoints cvp1, cvp2, cvp3; each of which has two
coverpoint bins: (a1, a2), (b1, b2), and (c1, c2) respectively. A user cross bin 'x1' has selected
two cross products " <a1,b1,c1>, <a2,b2,c2>". When you exclude bin a1, that logically excludes
the first cross product.transitively. But the bin 'x1' will not be excluded as the cross product
<a2,b2,c2> is still active; and doing so may cover up a hole for that active cross product. Now,
if the bin a2 is also excluded then logically both the cross products are excluded transitively.
Hence, the userbin x1 is logically excluded but is not done as a limitation as the tool does not
keep track of exclusions for each cross product due to performance and capacity reasons. So
you need to exclude the userbin x1 explicitly in this case.
Cross autobins do not have this limitation as each autobin is for a single cross product. So all the
cross autobins related to an excluding coverpoint or cross bin will be excluded.
The assertion name my_assert and cover directive name my_cover allow you to easily identify
those particular properties throughout all windows and cover reports.
Related Topics
Loading a Functional Coverage Database into Simulation
module top;
covergroup ct; option.per_instance = 1; ... endgroup
ct cv = new;
In this case, the instance name will be "\/top/cv". Note the extra space at the end to terminate the
extended identifier. The report will identify the instance as "\/top/cv". The covergroup type
name will be "/top/ct" and in UCDB hierarchy the covergroup instance will appear as "/top/ct/\/
top/cv ".
If a duplicate covergroup instance name is specified in the source code, the simulator by default
issues a warning and then automatically generates a unique name to resolve the conflict. When
the vsim option -pedanticerrors is used, the duplicate name triggers a fatal error.
Covergroup in a Class
There are a couple of unexpected cases in covergroup naming conventions that occur with the
embedded covergroup (the covergroup in a class):
• SystemVerilog 2009 requires that the embedded covergroup create an anonymous type,
while the declaration name is considered a covergroup variable. The UCDB does not use
the anonymous type name; it uses the variable name or declaration name. This has the
consequence that the simulator's context tree (seen in the Structure window) is different
from the context tree created in Coverage View mode. The coverage reports and user
interface will be consistent between interactive simulation and Coverage View mode,
but the hierarchy will not be.
Example:
module top;
class c;
int i;
covergroup ct;
coverpoint i { bins b[] = { [0:9] }; }
endgroup
In this case, the simulator hierarchy browser will show “/top/c/#ct#” as the covergroup
type. The coverage view mode hierarchy browser will show /top/c/ct.
• Parameterized classes — There is no prescribed naming scheme for specializations of
parameterized classes. Questa SIM names these as the class name suffixed by "__" and a
unique integer. These names appear in the path naming the covergroup type. For
example:
module top;
class child #(type T = bit, int size = 1 );
T [size-1:0] l1;
covergroup cg;
...
endclass
child #(logic, 3) child_inst1 = new;
child #(bit, 4) child_inst2 = new;
In this case, the hierarchy browser will show “/top/child/child__1” as the scope for the
first class specialization, and /top/child/child__2 as the scope for the second. In complex
cases, it may not be obvious which index-suffixed name corresponds to which
specialization.
Related Topics
Loading a Functional Coverage Database into Simulation
Covergroup Naming Conventions
Canonical String Representation for Coverpoint Bin Value
To ensure unique identification, Questa SIM uses the following three forms of a naming
algorithm to produce canonical string representations of coverpoint bin values:
• Decimal radix form — Uses regular decimal notation. Negative bin values have a
leading minus sign '-'. No leading zeros and no radix prefix is added.
For example, consider the bin value 3'b110. If the coverpoint type is unsigned, the
canonical string of this form is 6. If signed, the canonical string is -2.
• 4-state binary radix form — Uses regular binary notation. The binary form uses a two
character 'b prefix to distinguish itself from the decimal form, followed by a string of 4-
state binary digits. There is exactly one binary digit per bit. Leading zeros are always
maintained. The only valid characters after the 'b prefix are "01xz".
For example, consider the bin value 7'b00x11z0. The canonical string of this form is
'b00x11z0.
• Enumerated constant form — Uses enumerated constants as declared in HDL source
code. 4-state values with 'x' and 'z' are legal enum values.
For example, consider the following HDL enumerated type declaration:
enum logic[7:0] { red = 1, green = 8'h02, blue = 8'b0001x0x } ;
The canonical string of this form is one of the enumeration constants (red, green, blue).
Which of the above forms of canonical naming is applied to the coverpoint bin is determined by
the coverpoint expression type and the bin value itself, using the rules listed in Table 22-3:
Related Topics
Covergroup Naming Conventions
Covergroup in a Class
You can also change the default name of the database by editing that variable.
• Command Line — enter the coverage save -onexit command at the command line
as follows:
coverage save -onexit [UCDBFilename <name>]
• GUI — select Tools > Coverage Save from the Main window
This opens the Coverage save dialog, where you can select the type of coverage you
want to save, level of hierarchy to save, and output UCDB file name.
Once set using one of the above methods, the coverage data is saved at the end-of-
simulation, which can occur as a result of:
• an assertion failure
• Existing data values (bin counts, option, and type_option values) are replaced by the
corresponding values from the database file when a data object is identified.
• A covergroup TYPE is identified first by its hierarchical path in the design. Then, a
covergroup instance -- only those covergroups with option.per_instance set to 1 -- is
identified by its option.name in the list of instances of a covergroup TYPE. All
coverpoints, crosses, and bins will be identified subsequently by exactly matching their
names. A bin count is then loaded, but only if a bin is identified properly.
• If a covergroup, coverpoint, cross, or bin is present in the loaded design but absent from
the database file, then it is ignored (remains unchanged), and a non-fatal error message
is issued.
• Similarly, if a covergroup, coverpoint, cross, or bin is not identified in the design (in
other words, it exists in the database file, but is absent from the loaded design), it is
ignored and a non-fatal error message is issued.
Tip
You can suppress non-fatal error messages issued during object identification
failures using the -suppress <msgid> argument to vsim, or the "suppress = <msgid>"
directive in the modelsim.ini file.
• Bin identification tries to match bin RHS values, regardless of whether the
option.per_instance is set. Any mismatch results in a failure to load that bin and a non-
fatal error message to that effect. The bin RHS values are ignored for automatically
created cross bins, which are not identified by names; rather, they are identified by a pair
of index values stored in UCDB files. If the index values are out of bound, a non-fatal
error message is issued stating that the bin is not found: Otherwise, the bin is loaded.
Tip
Avoid loading incorrect automatically created cross bins:
If the index pair points to a different automatically generated cross bin in the
simulation, you can inadvertently load the incorrect cross bins without any notification.
Related Topics
SVCovergroupPerInstanceDefault
SystemVerilog 2009 option.per_instance
Merging Databases
When merging coverage databases offline using vcover merge, the following parameters must
be the same for a given scope:
• coverage weighting
• covergroup type name
• covergroup variable name
• coverpoint name
• bin name
If coverage data exists in the source database file but does not match the data in the target
database, then it will be created in the target database.
Related Topics
vcover merge command
Merging Coverage Data
SystemVerilog supports automated test bench development with random constraints, giving you
the ability to automatically generate test benches for functional verification. SystemVerilog
provides an object-oriented method for specifying constraints on random test bench values.
Questa SIM then processes these constraints using a constraint solver, which generates random
values that meet those constraints.
Note
The functionality described in this chapter requires an additional license feature for
ModelSim SE. Refer to the section “License Feature Names” in the Installation and
Licensing Guide for more information or contact your Mentor Graphics sales representative.
Verification Concepts
In many modern electronic designs, exhaustive testing is impossible because the space of all
possible inputs is too large. A simulator could not possibly reproduce all possible input vectors
in any reasonable simulation time. Moreover, exhaustive testing may not be desirable because
the set of interesting design states is much smaller than the set of possible inputs.
Ideally, it would be best to create targeted input vectors to test particular design states.
However, this is often difficult because of the knowledge or time required to create all
necessary inputs. Using constrained random stimulus allows a verification engineer to avoid the
repetitive work that the simulator can perform automatically. In addition, it is possible that you
obtain data on obscure corner cases that occur as consequences of the “random” input.
Functional coverage is required to evaluate which design states occurred (see Verification with
Functional Coverage). Without functional coverage, there is no way of knowing what of interest
actually occurred during a random test bench. It is also desirable to record the random seed with
the coverage results, which the Questa UCDB takes into account.
Finally, note that fully random verification is a rarity. While some verification teams have used
it exclusively, in most cases, random verification and targeted test vectors coexist because there
is usually some design behavior that is, after all, easy to verify with targeted test benches.
Questa SIM provides the following constraint solvers (commonly referred to as “engines”),
which you can choose to apply to a given verification run:
Random tests are built onto the SystemVerilog class system by assigning special modifiers to
class variables. The rand and randc modifiers can be used to designate a class variable as a
random variable. Class variables designated with rand modifiers are standard random variables
with values uniformly distributed over their range. Class variables designated with the randc
modifiers are random-cyclic variables that cycle through all the values randomly in their
declared range.
Values generated for random variables are controlled using constraints, as shown in
Example 23-1.
class Bus;
rand bit [15:0] addr;
rand bit [31:0] data;
constraint word_align {addr[1:0] == 2’b0;}
endclass
This shows a simplified bus with the addr and data random variables, which represent the
address and data values on the bus. The word_align constraint shows that only the addr random
variable is constrained, the data variable is not constrained. The data variable will be assigned
any value in its declared range.
Questa SIM support of randc includes the following SystemVerilog types: integral, multi-
dimension arrays, dynamic arrays, queues, and parameterized types. randc is not supported for
associative arrays.
Calling randomize() selects new values for all random variables in an object such that all
constraints are satisfied. In Example 23-2, the busA object is created and then randomized 50
times. The result of each randomization is checked for success. If randomization is successful,
the new random values for addr and data are displayed. If randomization fails, the
“Randomization FAILED” error message is displayed and the simulation halts.
Note
If Questa SIM cannot acquire the proper license to execute the call to randomize(), it will
display a fatal error message.
Attributes Of Randomization
The modelsim.ini file contains numerous variables whose settings control solver behavior for
randomization. You can also use attributes that correspond to these variables when calling
randomize() to apply their control only to that call. Using an attribute allows you to override the
variable setting on a per-randomize basis.
Table 23-1 lists the attributes available for use with randomize(), along with the corresponding
modelsim.ini variable.
Examples:
• Use the solveengine attribute of randomize() to perform the same function as the
vsim -solveengine command.
• Use the SolveEngine variable (defined in modelsim.ini), but on a per-randomize
basis.
Examples
The following example shows how to use the solveengine attribute to choose the Arithmetic
Constraint Technology (ACT) solver for a randomize call:
module top;
class TFoo;
rand bit[7:0] a, b, c;
endclass
TFoo f = new;
int status;
initial
begin
status = randomize (* solveengine="act" *) (f);
$display(status);
status = f.randomize (* solveengine="act" *) ();
$display(status);
end
endmodule
module top;
class TFoo;
rand bit[7:0] a, b, c;
endclass
TFoo f = new;
int status;
initial
begin
status = randomize (* solveactretrycount=1 *) (f);
$display(status);
status = f.randomize (* solveactretrycount=2 *) ();
$display(status);
end
endmodule
Inheriting Constraints
SystemVerilog constraints restrict the range of random variables and allow you to specify
relationships between those variables.
Constraints follow the same rules of inheritance as class variables so they can be inherited from
the parent class to any subclass. In this example,
the MyBus class inherits all random values and constraints of the Bus class. A random variable
called type has been added to control the address range with the addr_rang constraint. The
value of type is used by the addr_rang constraint to select one of the three range constraints.
As you can see here, inheritance can be used to build layered constraints, giving you the ability
to develop generalized models that can be constrained to perform application-specific tasks.
In the same way, rand_mode() is used to enable or disable random variables. When random
variables are disabled they behave just like nonrandom variables.
• The set of constraints cannot be solved. This is most often due to an error in specifying
constraint variables. For example:
a > b; b > c; a < c;
o If you have not specified vsim -solvefaildebug, the solver returns a status of 0 and
does not modify any random variables.
o If you have specified vsim -solvefaildebug, the solver does the following:
i. Prints the message
** Note: tb.sv(19): randomize() failed;
which indicates the file line number of the failing call to randomize().
ii. Generates a Verilog testcase that includes the constraints that cannot be solved,
which you can use to further investigate the constrain conflict.
iii. The solver then attempts to find the minimum set of constraints that produce the
conflict. In this example, all three of the constraints are required to cause the
conflict.
Note that this is a conflict in the Verilog code—the set of constraints is not solvable and
the problem is independent of solver setting. Changing the solver engine or using other
vopt switches will not correct the problem. You must fix the conflict in constraint
specification in the Verilog source code (in this example, delete: a < c;).
• The solver encounters an internal limitation.
The solver will report a message similar to the following:
file.sv(line#): randomize() failed; solution graph size exceeds
limit (SolveGraphMaxSize=value)
This type of error message indicates that the solver could not solve the constraints due to
some kind of limitation.
o If the failure is due to the values for the GraphMaxSize or GraphMaxEval variables,
increasing those values in the modelsim.ini file may help. Another correction that is
more likely to help is to change to an ACT solver engine.
o If the error is due to the value of the SolveACTMaxTests variable, increasing this
value in the modelsim.ini file may help. Another correction that is more likely to
help is to change to a BDD solver engine.
Following the error report, if you have specified vsim -solvefaildebug, the solver also
dumps a testcase containing the constraints that were run.
Procedure
1. Use either of the following methods:
• Set the SolveRev variable in the modelsim.ini file to a previous release.
• Use the -solverev argument with the vsim command to set a previous release.
2. The release number you designate must consist of release number and letter, such as
6.6a, but only prior letter releases within same number release are allowed. For example,
if you are using version 6.6c, you can specify 6.6b, 6.6a, or 6.6, but cannot specify 6.5f.
Note
These instructions do not apply to the SystemC/SCV solver.
Tip
: If you want to change the randomization seed after elaboration, you can do so by
using vsim -load_elab and vsim -elab. You can elaborate the design once using the -
elab argument and then use the -load_elab argument with different seed values specified
with -sv_seed for subsequent simulation runs.
If you do not use vsim -sv_seed, the value of the Sv_Seed variable in the modelsim.ini
file is used as the value for the initial seed. If Sv_Seed does not have a value, the initial
seed value defaults to 0.
2. You can obtain the initial value of the random seed with either of the following methods:
• Use the $get_initial_random_seed system function.
• Enter the following command in a Tcl shell window:
echo $Sv_Seed
• Seed the root RNG with a random number selected by Questa SIM:
vsim -sv_seed random
Note
For class::randomize, the value will be sampled after pre_randomize().
int a, b, c;
int status;
a = 123;
status = randomize(a, b, c) with {
b == const'(a);
c == a;
a == 999;
};
$display("a=%0d, b=%0d, c=%0d", a, b, c);
After running the above randomize() call, the following values are displayed:
The expression “const'(a)” is interpreted as a constant value — that is, the current value (before
randomization) of variable “a”. As a result, the constraint “b == const'(a);” is equivalent to “b
== 123;” (where 123 is the value of “a” before randomize). Without the use of const cast, the
constraint “c == a;” forces the values of random variables “c” and “a” to be equal (since “a” is
constrained to 999, the value of “c” is as well).
This chapter contains the following, basic information regarding coverage and the management
of your verification environment within Questa SIM.
The features available for managing verification are:
Every project starts with a design specification. The specification contains elaborate details on
the design construction and its intent.
A verification team uses the design specification to create a verification plan. The verification
plan contains a list of all questions that need to be answered by the verification process (the
golden reference). The verification plan also serves as a functional spec for the test bench.
Once the test bench is built and the designers succeed in implementing the design, you simulate
the design to answer the question: “Does it work?”. If the answer is no, the verification engineer
gives the design back to designers to debug the design. If yes, it is time to ask the next question:
“Are we done yet?”. Answering this question involves investigating how much of the design
has been exercised by looking at the coverage data and comparing it against the verification
plan.
When created from Questa SIM, the UCDB is a single “snapshot” of data in the kernel. Thus, it
represents all coverage and assertion objects in the design and test bench, along with enough
hierarchical environment to indicate where these objects reside. This data is sufficient to
generate complete coverage reports and can also be combined with data acquired outside Questa
SIM – for example, Questa Formal created functional coverage and other user-defined data.
For more information about the coverage data contained in the UCDB, see “Understanding
Stored Test Data in the UCDB”.
Weighted Coverage
Weighting is a decision the verification engineer makes as to which coverage types are more
important than others within the context of the design and the objectives of the test bench.
Weightings might change based on the simulation run as specific runs could be setup with
different test bench objectives. The weightings would then be a good way of filtering how close
the test bench came to achieving its objectives.
For example, the likelihood that each type of bus transaction could be interrupted in a general
test is very low as interrupted transactions are normally rare. You would probably want to
ensure that the design handles the interrupt of all types of transactions and recovers properly
from them. Therefore, you might construct a test bench such that the stimulus is constrained to
ensure that all types of transactions are generated and that the probability of transactions being
interrupted is relatively high. For that test bench, the weighting of the interrupted transaction
cover points would probably be higher than the weightings of uninterrupted transactions (or
other coverage criteria).
• Design Units — aggregated coverage for a specific design unit is the weighted average
of all kinds of coverage found within it. For coverage summary statistics viewable in the
above listed locations, the coverage number is pre-aggregated into the design unit. This
pre-aggregation behaves like a merge operation, where the coverage of the design unit is
the union of coverage in all the instances of that design unit. This pre-aggregation occurs
for all code coverage types, functional coverage (both covergroups and cover
directives), and assertions which have succeeded or have been formally proven to
succeed. The coverage weight command allows these to be weighted independently —
but globally — in the aggregation computation. This is equivalent to averaging together
the numbers reported with “coverage report -bydu” for that particular design unit --
weighted by the coverage weights shown with “coverage weight -bydu”.
• all code coverage types — statements, branches, conditions, expressions, FSM, and
toggles
• covergroups, coverpoints, and cover directives — The crux of SystemVerilog
functional coverage reporting is that coverage for a bin is binary – a bin is either covered
or not covered – while coverage statistics are aggregated within a coverpoint and within
covergroups as a percentage of desired coverage. Coverage statistics may be aggregated
among all instances of a covergroup or per instance, as desired by the user.
• assertions which have succeeded or have been formally proven to succeed. A successful
assertion is one that passed — if pass counts are available (use
vsim -assertdebug to enable pass counts) — and never failed.
The Ranking summary from the vcover ranktest command includes contributing and
noncontributing tests. For example:
Ranking summary:
Total coverage = 90.34%
Total CPU time = 52.06
Total SIM time = 66021930.00 ns
# contributing tests = 9
Test order: <ordered list of contributing ucdb files>
# non-contributing tests = 1
Non-contributing tests: <list of non-contributing ucdb files>
where:
The coverage types (t) are as shown in Table 24-1. Each type of coverage has its own definition
of how bins are created and how many bins exist.
Aggregation is performed across different scopes depending on the UI command issued (i.e.
you can aggregate across a single design unit, or you can aggregate across the entire design, or
various ranges between those extremes). The region in which coverage is calculated is known as
the “scope of aggregation”. For each coverage type, cov(t) is calculated across the complete set
of bins visible in the scope of aggregation.
Individual weights can be assigned for all coverage types in table below, using the coverage
weight command. Additional methods for assigning weights are detailed for each type.
Note
Weights in the coverage weight command for assertion counts (other than non-vacuous
passes) are not used for any purpose.
The weights, listed by the different kinds of coverage, would be shown by entering:
You can find out exactly what the coverage was for each coverage type using either of the
following commands:
The information from these commands, along with Table 24-1, can help you understand the
Total Coverage number. See coverage analyze for further details.
The Structure window includes the Total Coverage column, which by default shows a weighted
average of all coverage types in the sub-tree recursively, including covergroup type-based
coverage, and cover directive coverage, code coverage, assertion coverage, method and
type_option.weight weighting. Cover directives are weighted using the weights you set (see
“Weighting Cover Directives”). By default, a cover directive is weighted equally with a
covergroup type.
When you disable the default selection of Structure -> Code Coverage -> Enable Recursive
Coverage Sums, only constructs local to the current design instance contribute to the Total
Coverage number. In this mode, the Total Coverage column displays coverage information for
each design instance in isolation, and no contributions from child instances are taken into
account.
Browser's calculation is always done recursively, which means that all hierarchy underneath all
design roots is taken into account.
Each of these modes of analysis act upon a single, universal database that stores your coverage
data, the Unified Coverage Database.
To save coverage:
• Automatically save coverage data into a coverstore using the vsim -coverstore
argument. See “Coverage Auto-save Coverstore” for more information.
• Elect the type of code coverage to be collected (vopt/vlog +cover). See “Specifying
Coverage Types for Collection”.
• Enable the coverage collection mechanism for the simulation run. See “Enabling
Simulation for Code Coverage Collection”.
• Optionally, you can name the test UCDB files. If not explicitly named, the name will be
taken according from the UCDB file. See “Name Selection for Test UCDB Files”.
Tip
If you are saving test data for later test-associated merging and ranking, it is
important that the name for each test be unique. Otherwise, you will not be able to
distinguish between tests when they are reported in per-test analysis.
1. The implicit, default test name is based on the UCDB filename specified in the coverage
save command.
2. Explicitly setting the name always takes priority, such as:
coverage attribute -test mytestname
or
coverage save -testname <name> <name>.ucdb
3. If running a UVM (or OVM) test, you can specify that the OVM/UVM testname be used
for the coverage UCDB using commands similar to the following:
a. Define the testname within UVM using a plusarg to the vsim command, such as:
vsim +UVM_TESTNAME=mytest
b. Use the coverage save -uvmtestname switch to define the test name defined in the
UVM (mytest), such as:
coverage save -uvmtestname <other args> <file_name>
For more detailed information on this recommended method for setting OVM/UVM test
names, as well as other methods, see the Verification Academy website
(www.verificationacademy.com) or the OVM and UVM Cookbooks, available on the
same website.
4. To name tests according to a seed using “coverage save -seed [value]”: the default
UCDB name is used with the specified “_<seed value>” appended to it. If no value is
specified, 0 is used.
Options for saving coverage data dynamically (during simulation) or in coverage view mode
are:
During simulation, the following command saves data from the current simulation into a
UCDB file called myfile1.ucdb:
coverage save myfile1.ucdb
While viewing results in coverage view mode, you can make changes to the data (using
the coverage attribute command, for example). You can then save the changed data to a
new file using the following command:
coverage save myfile2.ucdb
• GUI: Tools > Coverage Save. Enable the “Save on exit” radio button.
This brings up the Coverage Save dialog box, where you can also specify coverage types
to save, select the hierarchy, and the output UCDB filename.
• UCDBFilename=“<filename>”, set in modelsim.ini
By default, <filename> is an empty string ("").
• coverage save -onexit command, specified at Vsim> prompt
The coverage save command preserves instance-specific information. For example:
coverage save -onexit myoutput.ucdb
Related Topics
Running Tests and Collecting Data
Merging Coverage Data
Ranking Coverage Test Data
• you are running multiple simulations using the same UCDB filename and you have used
the same UCDB name in different directories (fred/cov.ucdb, george/cov.ucdb, and so
forth), or
• you are loading multiple UCDBs from the same basic test (that is, fred.ucdb is the basic
test and you want to create multiple runs of that test).
If either of these cases is true, your initial simulation run (the one you intend to re-run) must
include a command to set the TESTNAME attribute. Failure to set the TESTNAME attribute in
these cases may result in otherwise unique tests being identified as duplicates (and therefore not
executed) by the re-run algorithm and in the merge/rank output files. See the Tip below for
further information.
To explicitly set the TESTNAME attribute in simulation, include a command such as:
Tip
When you rerun a test, the simulator uses an attribute called TESTNAME, saved in each test
record, to build a list of unique files selected for re-run of that test. By default, the
TESTNAME is the pathless basename of the UCDB file. See “Multiple Test Data Records with
Same Name” for further details on ensuring unique test data records for subsequent runs.
Procedure
1. To rerun a test or execute a command from the Browser:
2. Enter the re-run setup:
a. Select one or more UCDB files.
b. Right-click and select Command Execution > Setup.
This displays the Command Setup dialog box, shown in Figure 24-3.
The Command Execution Setup dialog box allows you to select and view user-
defined command setups, save new setups, and remove run setups previously saved.
You can either select an existing test to re-run, or enter the following commands to
run individually:
o Pre-command — a script you may need to run once at startup, prior to the run
A merged file contains one test data record for each of the different tests that were merged into
the file. For example, if you merged three UCDBs saved from simulation (vsim), you get three
test attribute records. If you merge that file with another one saved from vsim, you get 3 + 1 = 4
test data records, and so on.
Several methods are available which allow you to interface with the test record and its
attributes. These include:
• the UCDB API (Application Programming Interface). See the UCDB API User’s
Manual for further details.
• the UCIS database API (Application Programming Interface). See the “Accellera
Systems Initiative Unified Coverage Interoperability Standard (UCIS)”, a user’s
reference document, for further details.
• the CLI (Command Line Interface) See the Questa SIM Reference Manual for command
syntax.
• directly within SystemVerilog using the DPI (Direct Programming Interface). See the
appendix entitled “Verilog Interfaces to C”.
Using one of these methods it is possible to set values to the default fields or add any number of
user defined fields to carry other interesting information about the verification run.
• In simulation mode, override the values using the “coverage attribute” command
• Before saving the UCDB file, use the “coverage save” command.
Table 24-3 lists fields in the test attribute record (in the UCDB) that are predefined for users.
Caution
On Overloading Predefined Attributes: Some risk is inherent in overloading a predefined
attribute (such as TESTSTATUS). If you change the setting of a predefined attribute to
outside the set of expected values, unintended behavior may result.
Related Topics
Merging Verification Plan with Test Data
Importing an XML Verification Plan
coverage analyze
xml2ucdb.ini Configuration File
Storing User Attributes in the UCDB
Another example scenario would be if you’ve run 100 test runs, all using different stimulus.
Next, you would want to analyze the data in those UCDBs to determine the coverage
redundancy, and eliminate extraneous tests. You can merge and rank the data for just this
purpose.
You can also merge a verification plan (or “testplan”) with the actual coverage test data
contained in the UCDB(s). If you are merging a verification plan with UCDB test data, you
must have an imported testplan in UCDB format.
You can also edit a UCDB, modifying its contents, using the coverage edit command. See
“Modifying UCDBs”.
• instance-specific toggles
A file locking feature of the merge allows for cumulative merging on a farm — “vcover merge
out out in” — such that the “out” file is not corrupted with multiple concurrent merges. It
recovers from crashing merges, crashing hosts, and allows time-out of merges, as well as
backups of the previous output.
4. Fill in fields in the Merge Files dialog box, as required. A few of the more important,
less intuitive fields are highlighted here. For full details related to these fields, see
“vcover merge”.
• Set the Hierarchy Prefix: Strip Level / Add Prefix to add or remove levels of
hierarchy from the specified instance or design unit.
• For Exclusion Flags, select AND when you want to exclude statements in the output
file only if they are excluded in all input files. When OR is selected (default) a
statement is excluded in the output merge file if the statement is excluded in any of
the input files.
• Totals merge is the default Merge Level. A test-associated merge is required for any
test analysis features such as “coverage analysis”, the Tracker window’s Test
Analysis, and such. To understand the difference between the two merges, refer to
“Test-Associated Merge versus Totals Merge Algorithm”.
For a description of what is not supported with the Totals merge, see “Limitations of
Merge for Coverage Analysis”.
5. Click OK
This creates the merged file and loads the merged file into the Verification Browser
window.
Results
If the merge was successful, a transcript message such as the following appears:
# Merge in Process......
#
# Merging file C:/QuestaSim_<ver>/examples/ucdb/testplan/DataTest.ucdb
# Merging file C:/QuestaSim_<ver>/examples/ucdb/testplan/FifoTest.ucdb
# Merging file C:/QuestaSim_<ver>/examples/ucdb/testplan/IntialTest.ucdb
# Merging file C:/QuestaSim_<ver>/examples/ucdb/testplan/ModeTwoTest.ucdb
# Writing merged result to merge.ucdb
Related Topics
Merging with the vcover merge Command
Ranking Coverage Test Data
Warnings During Merge
• Invoke vsim with -coverstore option to specify a directory path where the simulator will
dump coverage data at the end of the simulation. The user doesn't need to save the
coverage data explicitly. All the simulation runs in a regression should use the same
coverstore directory path and their design hierarchy needs to be the same for this new
use model.
• Invoke vsim with -testname option along with the -coverstore option to specify the name
of the running test.
• After the coverage data is accumulated in the coverstore area from all the simulation
runs, merge the coverage data and create a self-contained UCDB file for further
analysis. You simply need to specify the coverstore directory path as an input to the
vcover merge. No other option is required.
• You can also dump the output of a merge to a coverstore directory instead of creating the
output UCDB file by using the -outputstore option to specify the output directory path.
This is useful when the user merges the outputs of lower level merges in a hierarchical
merge.
• The coverage data by default is stored using single-bit counters for code coverage items
(statements, branches, conditions, expressions, fsms, toggles), and multi-bit counters for
functional coverage items (covergroups, cover directives, assertions). That means we
store 1 for a code coverage bin whose count is greater than 0. The user can specify
which coverage types to be stored using single-bit counters and which coverage types to
be stored using multi-bit counters. The -multicount[=-a|b|c|-d|e|f|-g|s|t] option is added
for that. The '-' is preceded to functional coverage types whose defaults are multi-bit, so
the user can turn those coverage types to single-bit by using it. For example, -
multicount=f-gt will turn the fsm and toggle coverage types to multi-bit and covergroup
coverage type to single bit, keeping the other coverage types as unchanged.
merges coverage statistics in UCDB files inputA.ucdb and inputB.ucdb and writes them to a
new UCDB file called output.
Procedure
1. Load the UCDB into vsim in “viewcov” mode, using a command such as:
vsim -viewcov <UCDB file>
2. Use the “coverage edit” command line tool to change the design path(s):
coverage edit -movedesign <source path> <dest path>
Related Topics
vcover merge
Merging Using a Master UCDB
Warnings During Merge
Example:
• Merges the content of the master UCDB, which means bin counts from the master
UCDB are added up in the final merged file (output.ucdb).
• Merges any scope of a coveritem from the other input files, if and only if the
corresponding scope or coveritem is found in the master database.
• Merges any attribute, tag, and comment from the other input files if and only if the
corresponding item is found in the master database. However, this restriction does not
apply to test data records and other data which are generated at run time. The following
is a list of items which are merged from non-master UCDB files even when those items
are not present in the master UCDB file:
o Test data records
o Memory statistics
o Covergroup bin first hit timestamp data
o Any count, such as a branch scope's count coming in
o Information on whether a covergroup is sampled or not
Related Topics
vcover merge
Modifying UCDBs
Ranking Coverage Test Data
Warnings During Merge
Merging and Source Code Mismatches
Parallel Merge
The vcover parallelmerge command performs a merge on a UCDB or CoverStore database
using parallel processes, automatically merging intermediate merge results, and producing the
final merged results.
Requirements for Parallel Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
The Parallel Merge Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Options Used for Building the Merge List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Distribution of Files into Parallel Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Modes of Operation
The parallel merge process can be run in three main modes of operation.
These modes are as shown in Table 24-4.
A full list of arguments used for parallel merge is found in vcover parallelmerge.
• Stage 1: The file list, which contains a list of UCDB files to be merged, is either supplied
or built.
o If the file list is supplied, the UCDB files and their full absolute paths need to appear,
one per line, in the text file.
o If the file list is built, then relevant options must be provided for search name, search
directory, and the teststatus filtering. See options Used for Building the Merge List
for specific details.
• Stage 2: The original file list is split into a certain number of parallel merges.
o Depending on options provided (according to the run mode of the operation),
parallel jobs will run either locally on a multi-core machine, via remote shell to
specified machines or on a compute farm managed by grid software. See Options
Used for Splitting First Level Merges for specific details.
o Once the file list has been split into the number of jobs required, then the first level
Merge processes are launched, using the method set by the -runmode option.
• Stage 3: When the first level merges are complete, an intermediate UCDB file is
generated.
o These intermediate files are managed internally by auto-merge algorithm in vcover
for second level merge.
o Vcover automatically merges intermediate UCDB files as the first level merges are
completed.
o Final merged file is then generated based on the prefix name provided by -outname
option.
** Warning: (vcover-6854) Multiple test data records with the same name
encountered during the merge of file 'xyz.ucdb'
These test data records contain conflicting data....
On the other hand, if you are NOT using the following features, you can safely ignore the
warning:
• coverage analyze -coverage option (reports which test had most, least, etc. coverage)
• vcover ranktest with -plan or -path (test ranking on testplan or design hierarchy)
• Tracker GUI's Test Analysis sub-menus which correspond to the coverage analyze or
vcover ranktest arguments listed above
• coverage analyze -testextract: reporting coverage based on test subsets
• Tracker GUI's “Specify Tests” tab on the Edit Filter dialogue (accessed from menu
Filter > Setup > Edit selection, which corresponds to “coverage analyze -testextract”.
• vcover ranktest in test-associated merging mode, or the corresponding option selected
from the Rank menu of the Test Browser GUI
• Adding a unique test name for each run prior to saving the UCDB. You would do this by
entering the following command for each test:
coverage attribute -name TESTNAME -value test_1
• Alternatively, you could open the already created UCDBs in Viewcov mode and assign
different TESTNAME attributes for each, by entering the following commands at the
command prompt:
coverage attribute -ucdb -name TESTNAME -value run_1
coverage save run_1.ucdb
coverage attribute -ucdb -name TESTNAME -value run_2
coverage save run_2.ucdb;
Note
While a particular instance or du is skipped, note that all other coverage metrics are merged
from that particular test UCDB.
Causes of legitimate differences between the design source in two different UCDBs:
• File location — this is an insignificant difference and any resulting mismatch can be
safely ignored.
• A difference in the UCDB release version for certain specific VHDL designs —
However legitimate the cause, these difference may not be substantive. In cases where
they are not, you might decide to bypass or work around this check.
Potential solutions for the above causes are evident, depending on the cause identified.
Determine if the differences are legitimate: If so, work to bring the code in the individual files
into alignment. If not legitimate, you can choose to ignore or work around the mismatches.
To bypass this check, use the -ignoredusig argument to the vcover merge command, such as:
Caution
DO NOT use -ignoredusig lightly, without validating that the differences in source code are
OK. See “Causes of Source Code Differences” for more information.
Related Topics
Merging Using a Master UCDB
vcover merge
About the Merge Algorithm
Merge Usage Scenarios
Modifying UCDBs
Merging Verification Plan with Test Data
Modifying UCDBs
It is possible, and can sometimes be useful to edit the contents of a UCDB.
Specifically, you can use the coverage edit command to:
You can enable timestamping using the vsim -cvgbintstamp argument. Timestamps are not
recorded for each count increment for the coveritem.
As a consequence of the timestamping, it is not possible to make a later change to the coveritem
goal recorded in the database (i.e. after it’s been saved) — for example by modifying the UCDB
using the coverage edit command — and automatically infer a different timestamp. You would
have to rerun simulation for the new timestamp to appear.
A similar confusion can arise with timestamps during merges. When coveritems with multiple
timestamps are merged, the earliest timestamp is retained, even if the merged coveritems have
different at_least (goal) values.
Related Topics
vsim -cvgbintstamp
Covergroup Bin Reporting and Timestamps
coverage goal
Parameter for Mapping by Column Sequence
Overriding at_least Values in Test Plan
• When you perform a merge on multiple UCDBs, all test data records with unique
testnames are concatenated into the merged UCDB file. If you merge two tests that have
identical names but different data contents, a warning is issued.
• A merged file contains one test data record for each of the different tests that were
merged into the file. For example, if you merged three UCDBs saved from simulation
(vsim), you get three test attribute records. If you merge that file with another one saved
from vsim, you get 3 + 1 = 4 test data records, and so on. See “Understanding Stored
Test Data in the UCDB” for more information on the content of test data records.
• The merge algorithm that Questa SIM uses is a union merge. Line numbers from the
files are merged together, so that if different UCDBs have different sets of coverage
source lines, the resulting merged database contains a union of the set of source lines in
the inputs.
• Toggles and FSMs, which have no source information, are merged as follows:
o Toggles are merged with a union operation: objects with the same name are always
merged together, regardless of how many are present in each UCDB input file.
o FSMs are merged together by the order in which they appear in a given module
instance or design unit.
Assertion and functional coverage objects in the UCDB are always merged as a union
algorithm: objects of the same name are merged together, but the result contains the union set of
differently named objects from all inputs. Covergroup instances — those for which
option.per_instance = 1 — are merged together based on the “option.name” string for each
instance. Instances with the same name are considered the same, and bins are merged together
as a union, regardless of parameterization. There are some exceptions for other kinds of data
(besides coverage counts):
(This has implications if class specializations are used; see “Covergroup Naming Conventions”
for more information.)
• Assertion and cover directive limits are taken as the maximum of all inputs.
• User-defined flag values are ORed together.
Only the -testassociated merge provides the tool with the level of data required for coverage
analyze, which you can use to analyze your results on a per-test basis and coverage ranktest (the
non-iterative default ranking method) to analyze contributing tests.
• -totals merge — This is the default merge, which merges (sums) the coverage of the
coverage scopes, design scopes, and testplan scopes. The counts are totaled (ORed
together, in the case of vector bin counts) and by default the final merge is a union of
objects from the input files.
Information about which test contributed what coverage into the merge is lost.
Information about tests themselves are not lost — multiple test data records are retained
from all merge inputs. While this level of merge lists the tests run, it loses the
information as to which tests incremented specific bins.
• -testassociated merge — Includes all data in totals merge, but additionally stores
information on which tests hit which bins. While this level of merge allows you to tell if
a test hit a bin, it can not tell you how many times the test hit the bin. The criteria which
must be met for a test to be considered as having covered a bin is as follows:
o For functional coverage, the bin hit count must be greater than or equal to the value
set for the at_least parameter of that object.
o For code coverage and assertion data, any non-zero count for a test causes the bin to
be marked as hit by the test.
In some cases, you may wish to preserve the information as to which bins were incremented by
which specific tests and by how much. If this is the case, instead of (or in addition to) merging,
consider retaining the individual UCDBs for later use.
These circumstances are detected during the merge, and a warning is issued as follows:
Information has not been perfectly preserved during the merge of file
'test.ucdb'.
If you use 'coverage analyze -test', test filtering in the Tracker GUI, or
test ranking, results may be inaccurate based on this merge.
For more information issue the command 'verror 6846'.
For more details, rerun merge with the '-verbose' option set.
You only need to be concerned about this warning if you are using any of the following
verification management features:
• For functional coverage: Coverage thresholds (at_least values) are different in separate
merge input files. See Example 24-2.
In these cases, it would be possible for a bin to be covered after the merge but in none of
the inputs. In this case, test-associated analysis will be correct with respect to the
individual tests but incorrect regarding merged coverage; ranking in particular will be
inaccurate because of the discrepancy in merged coverage.
• Weights (for example, covergroup weights) are different in separate merge input files.
In these cases, because coverage (for example, covergroup coverage) can depend on
weighting, it will be impossible to recreate the original coverage of some of the input
files. During the merge, the maximum weight is chosen; conflicting weights are not
preserved.
• Differing sets of coverage objects in merge input files.
This most commonly occurs due to parameterization. See Example 24-3.
For these cases, your best option may be to preserve the original UCDBs and analyze or rank
them individually
Tip
: In the case of different sets of coverage objects in different merge input files — test
ranking is actually more accurate with the test-associated merge, because ranking should
reasonably be done with respect to the union of all coverage.
For example, suppose at_least == 3 and you have 2 testcases each with counts of 2 in a cover
directive.
The result for “-test test1 test2” (generating test-associated merge data) is not the same as
without -test (a totals merged data), because the test-associated database is missing the
covercount information that is contained in the totals database.
Here's a typical example of code which, when merged with the “vcover merge -testassociated”
merge, provokes verror 6846. It contains a parameterized array:
module top;
parameter int size = 2;
bottom #(size) inst();
endmodule
module bottom;
parameter int size = 2;
reg[size-1:0] tog;
if (size==2) begin
initial begin
#1 tog[0] = 0;
#1 tog[0] = 1;
#1 tog[0] = 0;
end
end else begin
initial begin
#1 tog[1] = 0;
#1 tog[1] = 1;
end
end
endmodule
Imagine you compile this for toggle coverage, creating two different UCDB files with two
different array sizes, then merge them together, like so:
This provokes warning 6846. What is the potential problem? Look at the results of these two
different summary reports, the first issued during simulation on the active database, and the
second during post-processing on a saved UCDB:
> vsim -viewcov test.ucdb -c -do "coverage analyze -test test2 -summary;
quit"
The difference between these two summary reports is that the “test-associated” merge loses
some data: in particular, it loses knowledge of what coverage objects were in what file. The
knowledge of what was covered is accurate (in this case), namely “tog[0]”, but as the merged
result has 3 toggles, that is used as the denominator of the coverage fraction.
Related Topics
Ranking Coverage Test Data
Merge Usage Scenarios
Merging Verification Plan with Test Data
You have data from two or more UCDB files, at different levels of hierarchy. For
example: /top/des instance in filea.ucdb, and top/i/des instance in fileb.ucdb.
o Option 1: Strip top levels of hierarchy from both and then merge the stripped files.
Example commands:
vcover merge -strip 1 filea_stripped.ucdb filea.ucdb
vcover merge -strip 2 fileb_stripped.ucdb fileb.ucdb
vcover merge output.ucdb filea_stripped.ucdb fileb_stripped.ucdb
o Option 2: Strip levels off instance in one UCDB file, and install to match the
hierarchy in the other. In this example, strip /top/ off the /top/des and then add the /
top/i hierarchy to it. Example commands:
vcover merge -strip 1 filea_stripped.ucdb filea.ucdb
vcover merge -install /top/i filea_installed.ucdb filea_stripped.ucdb
vcover merge output.ucdb filea_installed.ucdb fileb.ucdb
o for VHDL with an entity name of design and an architecture name of arch1 would
be
vcover merge -du design(arch1) -recursive output.ucdb file3.ucdb
Note
If this is the very first merge, the input file “out.ucdb” will not exist yet, so the
simulator issues a warning. In this case, specify the appropriate <input>.ucdb file.
This command takes the output UCDB and merges it with a second input UCDB.
vcover merge out.ucdb out.ucdb in2.ucdb -timeout 10 -backup
Then, another machine can take the output of the first merge command and third input
UCDB, and so on.
Related Topics
Merging Coverage Data
About the Merge Algorithm
Merging Verification Plan with Test Data
This command adds the “Responsible” attribute to the list of attributes and values displayed
when you create a coverage report on testname.UCDB. This shows up as a column when the
UCDB is viewed in the Tracker pane.
This opens the Colorization Threshold dialog box, which allows you to control the colorization
of coverage results displayed in the “Coverage” column, as well as set the low and high
threshold coverage values for highlighting coverage values:
Procedure
1. Open the Verification Management window:
View > Verification Management > Browser
2. Add files to the Browser using one of the following three methods:
• Right-click in the window and select Add File. Select desired .ucdb files from the
list that appears in the Add File(s) dialog box.
• When the window is active, select Verification Browser > Add File from the menu
bar of the Main window. Select desired .ucdb files from the list that appears in the
Add File(s) dialog box.
• At the vsim command prompt, execute the add testbrowser command, which
accepts UCDB and rank result files as arguments. For example,
add testbrowser test.ucdb
Results
The Verification Browser window appears, similar to Figure 24-6.
The coverage numbers in the Browser window are based on the Total Coverage calculations
described in “Calculation of Total Coverage”, however all design roots are taken into account
and include all hierarchy underneath all design roots. See “Coverage Calculation in the Browser
Window”.
2. Command Line:
Entervsim with the -viewcov <ucdb_filename> argument. Multiple -viewcov arguments
are allowed. For example, the Coverage View mode is invoked with:
vsim -viewcov myresult.ucdb
where myresult.ucdb is the coverage data saved in the UCDB format. The design
hierarchy and coverage data is imported from a UCDB.
Related Topics
Coverage View Mode and the UCDB
Viewing Test Data in the Tracker Window
Procedure
1. Select one or more .ucdb files.
2. Right-click and select Rank.
This displays the Rank Files Dialog Box. The various options within the dialog box
correspond to arguments available with the -du and -path arguments to vcover ranktest
command.
3. Fill in What to Rank, Rank By, and Stop Ranking When and Messages, as desired. (The
selection of Rank By > Fewest means to rank the files by the fewest number of tests.)
4. Select Advanced Options to open the dialog box to set your coverage metrics,
arguments file, and ranked results file names.
5. Click OK
This creates the .rank file and loads it into the Test Browser; it also outputs ranking data
to the transcript window.
Results
If the rank was successful, a transcript message such as the following appears:
#
# Metric Bins Covered% Inc%
#
# Cover Groups/Points 5/18 0.0000 0.0000 |
# CoverDirectives 10 0.0000 0.0000 |
# Statements 2605 47.0633 47.0633 ********* |
# Branches 1978 29.6764 29.6764 ***** |
# Expressions 711 18.2841 18.2841 *** |
# Conditions 1315 15.9696 15.9696 *** |
# ToggleNodes 2214 1.1743 1.1743 |
# States 17 17.6471 17.6471 *** |
# Transitions 45 6.6667 6.6667 * |
# AssertPasses 12 0.0000 0.0000
• -groupby <attribute> — Specifies the attribute within a UCDB test record that will be
used to group tests by.
o -groupfilter <regex> — Specifies a regular expression match to apply to the attribute
being grouped.
o -norun — Displays groups without ranking so you can see grouping before running
the ranking process.
o -r[ecursive] — Enables recursive ranking of items within a group selected by the use
of -groupby and -groupfilter so they will, in turn, be ranked against one another.
Grouping by Attribute
You can specify any attribute that exists within an input set of UCDBs, such that when ranking,
all tests sharing the same attribute value will be treated as one input. For example, assume the
following attributes in 10 different UCDB files (where TESTNAME is <testname>_<seed>):
You can merge the tests then group and rank them with the following commands:
The parenthesis of the filter expression are used to define the group (and subsequently the group
name). The result is a ranked output containing testA and testB.
The coverage numbers listed in a merged UCDB are raw coverage numbers for that particular
test. Whereas, in the ranked report, the numbers within each column for a particular test are a
cumulative total of all the data in the columns from tests listed above it.
You can see that in Figure 24-7, the 80.89 number in the FifoTest.ucdb within the directed.rank
section represents the cumulative total Statement coverage for FifoTest as well as the three tests
listed above it; whereas the 73.76 number in the directed.ucdb represents only that single test’s
total contribution toward Statement coverage.
2. Assertions are not included in the ranked coverage because the numbers are not monotonically increasing.
In fact, they start at 100% and may decrease as tests are added.
iteration of merges on the file system. Therefore, if you have a merged test included in your
ranking, make sure that the merged file was produced using a test-associated merge (vcover
merge run with the -testassociated switch).
Tip
Important: Test-associated ranking, which is the default ranking method, depends on the
existence of a test-associated merged result from a previous run of vcover merge
-testassociated. If you attempt a test-associated ranking when no test-associated merge result
exists, an error results and a message is output regarding the error.
The test-associated ranking method (default) is superior to the iterative method in two important
ways:
This is the same limitation as explained in “Limitations of Merge for Coverage Analysis”.
The iterative ranking option is available to work around cases of covergroups and cover
directives where at_least > 1, however it is considerably less efficient (slower). Iterative ranking
ranks each individual test by performing an iteration of merges on the file system.
Related Topics
About the Merge Algorithm
Test-Associated Merge versus Totals Merge Algorithm
Merge Usage Scenarios
Merging Verification Plan with Test Data
Coverage Reporting
You can generate ASCII text or HTML reports of coverage using the GUI or with command
line commands.
The Generation of Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Generating ASCII Text Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Generating HTML Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
• Run a simulation with the various coverage types enabled to collect coverage metrics.
• If opening from the Browser window, the UCDB must be opened in Coverage View
mode by right-clicking on the UCDB and selecting Invoking CoverageView Mode.
To access any of the Coverage Report dialogs, you can:
• Right-click on any object in the Files or Structure (sim) windows and select Code
Coverage > Code Coverage Reports
• Select Tools > Coverage Report > Text or HTML or Exclusions.
• Select a UCDB in the Browser window and Select Tools > Coverage Report > Text or
HTML or Exclusions.
These actions display the Coverage Text Report, Coverage HTML Report, or Coverage
Exclusions Report dialog boxes.
Procedure
1. From the Report on dropdown, select one of the following:
All files — reports data for all design units defined in each file. (-byfile switch with
coverage report).
All instances — reports data in each instance, merged together. (-byinst with coverage
report).
All design unit — reports data in all instances of each design unit, merged together. (-
bydu with coverage report).
2. In the Coverage Type pane, ensure that the desired coverage types are selected.
3. Alter any of the other options as needed. All options in this dialog correspond to
coverage report and vcover report options.
4. Click OK to create coverage report.
Results
• Writes the report (report.txt) to the current working directory.
• Opens a notepad window containing the report.txt file.
Related Topics
FSM Coverage
Code Coverage
Verification with Functional Coverage
The Generation of Coverage Reports
Once the server has been started with the -servermode -port <port_num> argument, you
can stop the server using -stopserver -port <port_num>. See vcover report -html for
more information.
Procedure
1. Command Line:
• To generate a static HTML report from the command line, use the -html argument
with the coverage report or vcover report commands.
• To create a dynamic HTML report from the command line, use the -html and the
-dynamic arguments with the “vcover report” command.
2. GUI: To generate a static HTML report,
a. Select a single UCDB file from the Verification Management Browser.
b. From the main menu, select Verification Browser > HTML Report
or in the Browser, select Right-click > HTML Report.
This brings up the Coverage HTML Report from File dialog box that allows you to
control the generation and subsequent viewing of the report.
c. Set the color for both the high and low threshold to define the number above which
the coverage number displays in green, and below which it is displayed in red.
d. Select No Frames to save on report generation time and disk space for larger designs
(see HTML Generation for Large Designs).
e. Select the coverage details you want to see in your report.
Results
• Writes the static report (index.html) to the specified directory (default is /covhtmlreport).
The HTML file is viewable with any reasonably modern web browser, an example of
which is shown in Figure 24-10.
The web browser allows you to explore the hierarchy of the design, much like you might
browse a file system. Colorized copies of the design source code are generated and linked into
the report at the appropriate places.
The coverage numbers displayed in the sections of the HTML are calculated according to the
following algorithms:
• Coverage Summary by Structure — calculated in accordance with the algorithms
shown in “Calculation of Total Coverage”.
• Coverage Summary by Type — calculated using the algorithms and weightings as
described in Table 24-1.
Exclusion comments you add with the coverage exclude -comment command will appear as
tooltips when you mouse over hit count cells denoted with a plus ‘+’ sign. The plus sign is
added to the cell to indicate that it contains an exclusion comment. For example, Figure 24-12
displays the exclusion comment, “This assertion is excluded” when we mouse over the cell that
shows the failure count of the assert_location_full_on_write assertion.
Figure 24-12. Exclusion Comment Displays as Tooltip
Compared to other types of coverage reports, HTML report generation can cause machines to
be particularly sensitive to issues of disk space, memory usage and slowness. Many of the
HTML reporting options, both through the radio buttons in the Coverage HTML Report dialog
box and the coverage report -html options, are geared toward improving the speed and
performance of report generation. Additionally, you may want to target the reports by excluding
specific coverage types and/or reducing the scope of items in the report.
See coverage report -html for full details on these options.
Procedure
1. Generate the HTML Report on a merged UCDB, including the -testhitsdata argument.
The UCDB must have been merged with the test-associated switch set (vcover merge
-testassociated). See Generating HTML Coverage Reports for details.
2. Click on the Design scope or Testplan section whose bins-hit information you want to
see and click into the scope or instance, descending down the hierarchy until a hypertext
link is visible for the item you are interested in viewing. Your report will be similar to
that shown in Figure 24-13.
3. Click on the hypertexted Bin number in the Hits column of the report to bring up a table
which lists the tests which hit that bin. You can sort the list in three ways —
alphabetically a - z, z - a, or order of tests as listed in merged UCDB — by toggling the
left pointing triangle in the column name.
Figure 24-14. Test-Bins-Hit Table
report comes up as a single frame containing the top-level summary page and an HTML-only
design scope index page is available as a link from the top-level page.
Additionally, the No Details option omits coverage detail pages. This can save report generation
time and disk space for HTML generation for very large designs.
Related Topics
Code Coverage
The Generation of Coverage Reports
Coverage Reports
Procedure
1. Select Pragma and/or User Defined Exclusions to report.
2. Save the pathname.
3. Click OK.
Related Topics
Code Coverage
Coverage Exclusions
The Generation of Coverage Reports
Coverage Reports
Filtering Data
The following information is related to the filtering of data from the UCDB.
Filtered Data in the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Setting up or Modifying a Filter for UCDB Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Applying a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
Filtering Results by User Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
4. Select Criterion and choose the type of coverage you wish to use as a filter.
a. Select Operator.
b. Enter Value of item to match.
c. Click OK.
The criterion you just entered appears in the Select Criteria list.
5. Enter a Filter Name and select OK to save that filter.
6. Either select Apply to filter the UCDB data, or select Done to exit the dialog box.
Related Topics
coverage analyze
Applying a Filter
The filter can be applied using the same Filter Setup dialog.
Procedure
1. From the Filter Setup dialog, select the desired Filter from the list and select Apply.
2. From the Verification Management Browser:
a. Right-click on UCDB(s) to filter.
b. Click on Filter > Apply, and then select a filter from the list.
UCDBs with matching criteria are included in the data now displayed in the Browser.
Prerequisites
In order to successfully filter by user attributes:
• The user attribute used to filter the data must already exist in the original plan, or you
must add the user attribute to the original plan before importing it (see “Storing User
Attributes in the UCDB”).
• Plan must be imported.
• Plan must be merged with test results.
Procedure
1. To filter items for display on a specific column in the UCDB verification plan:
2. Select all tests to which you wish to apply selection criteria.
3. Right-click in the Tracker or Browser window and select Filter > Setup.
This opens the Filter Setup dialog box.
4. Select Create.
This opens the Create Filter dialog box to the Selection Criteria tab.
5. Select Add.
This opens the Add/Modify/Select Criteria dialog box.
6. For Criterion, select Attributes from the pulldown list. Without selecting Attributes,
the Attribute Name field is grayed out.
a. For Attribute Name, select desired attribute name(s) from pull-down list. The list
contains all pre-defined attributes and any user attributes you added.
b. For Operator, select one of the options. Seecoverage analyze -select for definitions.
c. Enter Value of item to match.
d. Click OK.
The criterion you just entered appears in the Selection Criteria list.
7. Select the Specify Tests tab to select specific tests. By default, all tests are subject to the
filter.
8. Enter a Filter Name and select OK to save the filter with the specified selection criteria.
The filter you just created appears in the Filters list within the Filter Setup dialog box.
9. Either select Apply to filter the UCDB data, or select Done to exit the dialog box.
10. The filter can be applied using the same Filter Setup dialog.
• From the Filter Setup dialog, select the desired Filter from the list and select Apply.
• From the Verification Management Browser:
a. Right-click on UCDB(s) to filter.
b. Click on Filter > Apply, and then select a filter from the list.
UCDBs with matching criteria are included in the data now displayed in the Browser.
Related Topics
Understanding Stored Test Data in the UCDB
coverage analyze
Importing an XML Verification Plan
Merging Verification Plan with Test Data
xml2ucdb.ini Configuration File
Storing User Attributes in the UCDB
• a UCDB file loaded with -viewcov, use coverage attribute. For example:
coverage attribute -test <testname>
2. The Verification Browser and Tracker windows display columns which correspond to
the individual test data record contents, including name/value pairs created by the user.
The pre-defined attributes that appear as columns are listed in Table 24-3.
Related Topics
Customizing the Column Views in Verification Windows
coverage attribute
vcover attribute
Verification Management tools to analyze which tests most effectively cover those few areas
and re-run those specific tests to demonstrate satisfactory coverage numbers.
• Rank tests (see “Ranking Coverage Test Data”).
• Re-run tests (see “Rerunning Tests and Executing Commands”).
Before you use C Debug, please note the following qualifications and requirements:
You should install the g++ compiler at the same directory level as your product install
Setting Up C Debug
Before viewing your SystemC/C/C++ source code, you must set up the C Debug path and
options.
Procedure
1. Compile and link your C code with the -g switch (to create debug symbols) and without
-O (or any other optimization switches you normally use). See SystemC Simulation for
information on compiling and linking SystemC code. Refer to the chapter Verilog
Interfaces to C for information on compiling and linking C code.
2. Specify the path to the gdb debugger by selecting Tools > C Debug > C Debug Setup
Figure 25-1. Specifying Path in C Debug setup Dialog
Select “default” to point at the supplied version of gdb or “custom” to point at a separate
installation.
3. Start the debugger by selecting Tools > C Debug > Start C Debug. Questa SIM will
start the debugger automatically if you set a breakpoint in a SystemC file.
4. If you are not using gcc, or otherwise have not specified a source directory, specify a
source directory for your C code with the following command:
Questa
SIM> gdb dir <srcdirpath1>[:<srcdirpath2>[...]]
In your DO file, add the command cdbg_wait_for_starting to alleviate this problem. For
example:
cdbg enable_auto_step on
cdbg set_debugger /modelsim/5.8c_32/common/linux
cdbg debug_on
cdbg_wait_for_starting
run 10us
Setting Breakpoints
Breakpoints in C Debug work much like normal HDL breakpoints. You can create and edit
them with Questa SIM commands (bp, bd, enablebp, and disablebp) or within a Source window
in the GUI.
Some differences do exist:
• The Modify Breakpoints dialog, accessed by selecting Tools > Breakpoints, in the
Questa SIM GUI does not list C breakpoints.
• C breakpoint id numbers require a “c.” prefix when referenced in a command.
• When using the bp command to set a breakpoint in a C file, you must use the -c
argument.
• You can set a SystemC breakpoint so it applies only to the specified instance using the
-inst argument to the bp command.
• If you set a breakpoint inside an export function call that was initiated from an
SC_METHOD, you must use the -scdpidebug argument to the vsim command. This
will enable you to single-step through the code across the SystemC/SystemVerilog
boundary.
Here are some example commands:
bp -c *0x400188d4
Sets a C breakpoint at the hex address 400188d4. Note the ’*’ prefix for the hex address.
bp -c or_checktf
bp -c or.c 91
Sets a C breakpoint at line 10 of source file foo.c for the condition expression “x < 5”.
enablebp c.1
The graphic below shows a C file with one enabled breakpoint (indicated by a red ball on line
151) and one disabled breakpoint (indicated by a gray ball on line 154).
Clicking the red ball with your right (third) mouse button pops up a menu with commands for
removing or enabling/disabling the breakpoints.
Note
The gdb debugger has a known bug that makes it impossible to set breakpoints reliably in
constructors or destructors. Do not set breakpoints in constructors of SystemC objects; it
may crash the debugger.
Stepping in C Debug
Stepping in C Debug works much like you would expect. You use the same buttons and
commands that you use when working with an HDL-only design.
• With some platform and compiler versions, step may actually behave like run
-continue when in a C file. This is a gdb limitation that results from not having any
debugging information when in an internal function to VSIM (that is, any FLI or VPI
function). In these situations, use step -over to move line-by-line.
Quitting C Debug
You can end SystemC debugging session from the GUI or from the command line.
• From the GUI:
Select Tools > C Debug > Quit C Debug.
• From the command line, enter the following in the Transcript window:
cgdb quit
Note
Recommended usage is that you invoke C Debug once for a given simulation and
then quit both C Debug and Questa SIM. Starting and stopping C Debug more than
once during a single simulation session may cause problems for gdb.
The Auto find bp command sets breakpoints in an enabled state and does not toggle that state to
account for step -over or run -continue commands. This may result in unexpected behavior.
For example, say you have invoked the Auto find bp command and you are currently stopped
on a line of code that calls a C function. If you execute a step -over or run -continue command,
Questa SIM will stop on the breakpoint set in the called C file.
When you first enable Auto step mode, Questa SIM scans your design and sets enabled
breakpoints at all currently known function entry points. As you step through the simulation,
Auto step continues looking for newly registered callbacks and sets enabled breakpoints at any
new entry points it identifies. Once you execute a step -over or run -continue command, Auto
step disables the breakpoints it set, and the simulation continues running. The next time you
execute a step command, the automatic breakpoints are re-enabled and Auto step sets
breakpoints on any new entry points it identifies.
Because Auto step mode is enabled, Questa SIM automatically sets a breakpoint in the
underlying xor_gate.c file. If you click the step button at this point, Questa SIM will step into
that file.
• Auto find bp provides a “snapshot” of currently known function entry points at the time
you invoke the command. Auto step mode continues to locate and set automatic
breakpoints in newly registered function calls as the simulation continues. In other
words, Auto find bp is static while Auto step mode is dynamic.
• Auto find bp sets automatic breakpoints in an enabled state and does not change that
state to account for step-over or run-continue commands. Auto step mode enables and
disables automatic breakpoints depending on how you step through the design. In cases
where you invoke both features, Auto step mode takes precedence over Auto find bp. In
other words, even if Auto find bp has set enabled breakpoints, if you then invoke Auto
step mode, it will toggle those breakpoints to account for step-over and run-continue
commands.
Initialization Mode
Key tasks and concepts for the initialization mode.
Debugging Functions During Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
FLI Functions in Initialization Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
PLI Functions in Initialization Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
VPI Functions in Initialization Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
Completing Design Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
6. or
bp -c and_gate_init
7. Questa SIM in turn reports that it has set a breakpoint at line 37 of the and_gate.c file.
As you continue through the design load using run -continue, Questa SIM hits that
breakpoint and displays the file and associated line in a Source window.
Figure 25-7. Highlighted Line in Associated File
You can set a breakpoint on the function using either the function name (for example, bp -c
in_params) or the function pointer (for example, bp -c *0x4001a950). Note, however, that
foreign functions aren’t called during initialization. You would hit the breakpoint only during
runtime and then only if you enabled the breakpoint after initialization was complete or had
specified Keep user init bps in the C debug setup dialog.
You can set breakpoints on non-null callbacks using the function pointer
(for example, bp -c *0x40019570). You cannot set breakpoints on null functions. The sizetf and
misctf entries in the example above are null (the function pointer is '0x0').
Questa SIM reports the entries in multiples of four with at least one entry each for calltf,
checktf, sizetf, and misctf. Checktf and sizetf functions are called during initialization but calltf
and misctf are not called until runtime.
The second registration method uses init_usertfs functions for each usertfs entry. Questa SIM
produces a Transcript message like the following when it encounters an init_usertfs function
during initialization:
You can set a breakpoint on the function using either the function name
(for example, bp -c init_usertfs) or the function pointer (for example, bp -c *0x40019bec).
Questa SIM will hit this breakpoint as you continue through initialization.
You can set a breakpoint on the function using the function pointer
(for example, bp -c *0x4001d310). Questa SIM will hit this breakpoint as you continue through
initialization.
5. With this mode enabled, if you have set a breakpoint in a quit callback function, C
Debug will stop at the breakpoint after you issue the quit command in Questa SIM. This
allows you to step and examine the code in the quit callback function.
6. Invoke run -continue when you are done looking at the C code. When simulation
completes, Questa SIM automatically quits C-debugger and the GUI (whether or not a C
breakpoint was hit and you return to the VSIM> prompt).
The Questa SIM profiler combines a statistical sampling profiler with a memory allocation
profiler to provide instance specific execution and memory allocation data. It allows you to
quickly determine how your memory is being allocated and easily identify areas in your
simulation where performance can be improved. The profiler can be used at all levels of design
simulation—Functional, RTL, and Gate-Level—and has the potential to save hours of
regression test time. In addition, ASIC and FPGA design flows benefit from the use of this tool.
Note
The functionality described in this chapter requires an additional license. Refer to the
section "License Feature Names" in the Installation and Licensing Guide for more
information or contact your Mentor Graphics sales representative.
• non-accelerated VITAL library cells that are impacting simulation run time
• objects in the sensitivity list that are not required, resulting in a process that consumes
more simulation time than necessary
• a test bench process that is active even though it is not needed
• an inefficient C module
• random number processes that are consuming simulation resources in a test bench
running in non-random mode
With this information, you can make changes to the VHDL or Verilog source code that will
speed up the simulation.
The memory allocation profiler provides insight into how much memory different parts of the
design are consuming. The two major areas of concern are typically: 1) memory usage during
elaboration, and 2) during simulation. If memory is exhausted during elaboration, for example,
memory profiling may provide insights into what part(s) of the design are memory intensive.
Or, if your HDL or PLI/FLI code is allocating memory and not freeing it when appropriate, the
memory profiler will indicate excessive memory use in particular portions of the design.
The statistical profiler reports only on the samples that it can attribute to user code. For
example, if you use the -nodebug argument to vcom or vlog commands, it cannot report sample
results.
Profile Database
The profile save and profile open commands allow writing and reading of profile data to/from
a profile database file (.pdb extension suggested).
This allows you to capture profile data during a simulation session and store it for later review
or passing to others for analysis. When you read a profile database using the profile open
command, you can then use any of the profile windows or profile report commands to analyze
data. You can also use profile save -onexit <filename> to automatically save profile results, for
all runs in a session, to the named file at the end of the session.
2. Note that profile-data collection for the call tree is off by default. See Calltree Window
for additional information on collecting call-stack data.
3. You can use the following graphic user interface procedure to perform the same task.
4. Choose Simulate > Start Simulation or the Simulate icon, to open the Start Simulation
dialog box.
5. Select the Others tab.
6. Click the Enable memory profiling checkbox to select it.
7. Click OK to load the design with memory allocation profiling enabled.
8. If memory allocation during elaboration is not a concern, the memory allocation profiler
can be enabled at any time after the design is loaded by doing any one of the following:
• choose Tools > Profile > Memory
• use the -m argument with the profile on command
profile on -m
The -memprof+file=<filename> option will collect memory profile data during both elaboration
and simulation and save it to the named external file and makes the data available for viewing
and reporting during the current simulation.
The -memprof+fileonly=<filename> option will collect memory profile data during both
elaboration and simulation and save it to only the named external file. No data is saved for
viewing and reporting during the current simulation, which reduces the overall amount of
memory required by memory allocation profiling.
Alternatively, you can save memory profile data from the simulation only by using either the
-m -file <filename> or the -m -fileonly <filename> argument with the “profile on” command.
The -m -file <filename> option saves memory profile data from simulation to the designated
external file and makes the data available for viewing and reporting during the current
simulation.
The -m -fileonly <filename> option saves memory profile data from simulation to only the
designated external file. No data is saved for viewing and reporting during the current
simulation, which reduces the overall amount of memory required by memory allocation
profiling.
After elaboration and/or simulation is complete, a separate session can be invoked and the
profile data can be read in with the profile reload command for analysis. It should be noted,
however, that this command will clear all performance and memory profiling data collected to
that point (implicit profile clear). Any currently loaded design will be unloaded (implicit
quit -sim), and run-time profiling will be turned off (implicit profile off -m -p). If a new design
is loaded after you have read the raw profile data, then all internal profile data is cleared
(implicit profile clear), but run-time profiling is not turned back on.
If the statistical sampling profiler and the memory allocation profiler are on, the status bar will
display the number of Profile Samples collected and the amount of memory allocated, as shown
below. Each profile sample will become a data point in the simulation’s performance profile.
• Deselect the Performance and/or Memory options in the Tools > Profile menu.
• Deselect the Performance Profiling and Memory Profiling icons in the toolbar.
• Use the “profile off” command with the -p or -m arguments.
Results
Any Questa SIM run commands that follow will not be profiled.
2. These switches add symbols to the .dll file that the profiler can use in its report.
There are times, however, when the statistical sampling and memory allocation profilers tell
you nothing more than that simulation time or memory allocation is fairly equally distributed
throughout your design. In such situations, the profiler provides little helpful information and
improvement must come from a higher level examination of how the design can be changed or
optimized.
Ranked Window
The Ranked window displays the results of the statistical performance profiler and the memory
allocation profiler for each function or instance. By default, ranked profiler results are sorted by
values in the In% column, which shows the percentage of the total samples collected for each
function or instance.
Click the down-arrow to the left of the Name column to open a list of available columns and
allows you to select which columns are to be hidden or displayed (Figure 26-2).
You can sort ranked results by any other column by clicking the column heading.
The use of colors in the display provides an immediate visual indication of where your design is
spending most of its simulation time. By default, red colored text indicates functions or
instances that are consuming 5% or more of simulation time.
Calltree Window
Data collection for the calltrees is off by default for memory profiling and on for performance
profiling. Collection can be turned on from the VSIM command prompt with profile option
collect_calltrees on and off with profile option collect_calltrees off. Call stack data collection
can also be turned on with the -memprof+call argument to the vsim command.
By default, profiler results in the Calltree window are sorted according to the Under(%) column,
which shows the percentage of the total samples collected for each function or instance and all
supporting routines or instances. Sort results by any other column by clicking the column
heading. As in the Ranked window, red object names indicate functions or instances that, by
default, are consuming 5% or more of simulation time.
The Calltree window differs from the Ranked window in two important respects.
• Entries in the Name column of the Calltree window are indented in hierarchical order to
indicate which functions or routines call which others.
• A %Parent column in the Calltree window allows you to see what percentage of a parent
routine’s simulation time is used in which subroutines.
The Calltree window presents data in a call-stack format that provides more context than does
the Ranked window about where simulation time is spent. For example, your models may
contain several instances of a utility function that computes the maximum of 3-delay values. A
Ranked window might reveal that the simulation spent 60% of its time in this utility function,
but would not tell you which routine or routines were making the most use of it. The Calltree
window will reveal which line is calling the function most frequently. Using this information,
you might decide that instead of calling the function every time to compute the maximum of the
3-delays, this spot in your VHDL code can be used to compute it just once. You can then store
the maximum delay value in a local variable.
The %Parent column in the Calltree window shows the percent of simulation time or allocated
memory a given function or instance is using of its parent’s total simulation time or available
memory. From this column, you can calculate the percentage of total simulation time or
memory taken up by any function. For example, if a particular parent entry used 10% of the
total simulation time or allocated memory, and it called a routine that used 80% of its simulation
time or memory, then the percentage of total simulation time spent in, or memory allocated to,
that routine would be 80% of 10%, or 8%.
In addition to these differences, the Ranked window displays any particular function only once,
regardless of where it was used. In the Calltree window, the function can appear multiple
times—each time in the context of where it was used.
Structural Window
The Structural profile window displays instance-specific performance and memory profile
information in a hierarchical structure format identical to the Structure window. It contains the
same information found in the Calltree window but adds an additional dimension with which to
categorize performance samples and memory allocation. It shows how call stacks are associated
with different instances in the design.
Figure 26-5. Structural Window
In the Calltree and Structural profile windows, you can expand and collapse the various levels
to hide data that is not useful to the current analysis and/or is cluttering the display. Click on the
'+' box next to an object name to expand the hierarchy and show supporting functions and/or
instances beneath it. Click the '-' box to collapse all levels beneath the entry.
You can right-click any function or instance in the Calltree and Structural windows to obtain
popup menu selections for rooting the display to the currently selected item, to ascend the
displayed root by one level, or to expand and collapse the hierarchy (Figure 26-6).
• Instance Usage — opens the Profile Details window and displays all instances with the
same definition as the selected instance.
Figure 26-8. Profile Details Window: Instance Usage
• View Instantiation — opens the Source window to the point in the source code where
the selected instance is instantiated.
• Callers and Callees — opens the Profile Details window and displays the callers and
callees for the selected function. Items above the selected function are callers; items
below are callees.
The selected function is distinguished with an arrow on the left and in 'hotForeground'
color as shown below.
Figure 26-9. Profile Details Window: Callers and Callees
• Display in Call Tree — expands the Calltree window and displays all occurrences of
the selected function and puts the selected function into a search buffer so you can easily
cycle across all occurrences of that function.
Note that profile-data collection for the calltree is off by default for memory profiling
and on for performance profiling. See Calltree Window for additional information on
collecting call-stack data.
• Display in Structural — expands the Structural window and displays all occurrences of
the selected function and puts the selected function into a search buffer so you can easily
cycle across all occurrences of that function.
You can perform the same task by right-clicking any function or instance in any one of the four
Profile views and choosing View Source from the popup menu that opens.
When you right-click an instance in the Structural window, the View Instantiation selection
will become active in the popup menu. Choosing this option opens the instantiation in a Source
window and highlights it.
The right-click popup menu also allows you to change the root instance of the display, ascend to
the next highest root instance, or reset the root instance to the top level instance.
The selection of a context in the structure window will cause the root display to be set in the
Structural window.
performance. Compiling your C code with debug symbols enables the profiler to report
functions accurately.
Factors that can affect simulator performance when a design includes C code are as follows:
Procedure
Do either of the following to create a profile report:
Examples
The command:
will produce a Call Tree profile report in a text file called calltree.rpt, as shown in Figure 26-12.
Capacity Analysis
Questa SIM collects memory usage (capacity) data as the simulation is run. This data can be
displayed in the Capacity window of the graphical user interface.
The following types of SystemVerilog constructs are supported for capacity analysis:
• Classes
• Queues, dynamic arrays, and associative arrays and strings (QDAS)
• Assertions and cover directives
• Covergroups
• Solver (calls to randomize() )
• Verilog memories
• Some static design objects
Questa SIM updates memory usage data at the end of every time step of the simulation and
collects:
Note
Coarse-level and fine-level analyses are described in Levels of Capacity Analysis.
In addition, you can use various other commands to enable collection of memory capacity data,
along with viewing and reporting that data. Table 26-1 summarizes the different ways to enable,
view, and report memory capacity data.
Refer to the ModelSim Reference Manual for more information on using the commands listed
in Table 26-1.
Table 26-1. Commands for Enabling and Viewing Capacity Analysis (cont.)
Command Result Description
vcover report -memory Reports coarse-grain data Use with -cvg and -details
from a previously saved switches to obtain fine-
code or functional coverage grain data for covergroups.
run in either the Transcript
window or to a file.
vcover stats -memory Reports coarse-grain data No fine-grain analysis
from a previously saved available.
code or functional coverage
run in either the Transcript
window or to a file.
Choose View > Capacity Displays the Capacity Same as entering the view
from main menu window containing capacity command.
capacity data.
Coarse-grain Analysis
The coarse-grain analysis data is enabled by default when you run the vsim command. The
purpose of this analysis is to provide a simple summary of the number of objects, the memory
allocated for each class of design objects, the peak memory allocated, and the time at which
peak memory occurred.
You can display the results of a coarse-grain analysis as either a graphical display in the user
interface (see Opening the Capacity Window) or as a text report (see Writing a Text-Based
Report).
Fine-grain Analysis
When you enable a fine-grain analysis, Questa SIM collects detailed capacity data that you can
use to dig deeper into the area where memory consumption is problematic. The details about
each type of object are further quantified.
The display of the Capacity window expands the coarse-grain categories and shows the count
and current memory allocation per object declaration.
The solver data is expanded to show peak memory allocation per randomize call.
Classes — displays aggregate information about number of objects and memory usage for each
class type, including the name, file name and line number where the class is declared.
QDAS — displays aggregate information about number of objects and memory usage for each
object (queues, dynamic, associative and strings), including the name, file name and line
number where it is declared.
Assertions — displays aggregate information about the number of threads and memory usage
for each active assertion, including the name, file name and the line number where it is declared.
Covergroups — displays the aggregate information about the number of objects and memory
usage for each covergroup including name, file name and the line number where it is declared.
Solver — displays the aggregate information about the number of calls and peak memory usage
for each randomize() call, including the file name and line number.
Verilog Memories — displays aggregate information about number of objects and memory
usage for each object (sparse or non-sparse memories), including the name, file name and line
number where it is declared.
vsim -capacity
This generates capacity data based on the point of declaration. To show the point of
allocation as well as the point of declaration, use the “=line” option with -capacity as
follows:
vsim -capacity=line
You can then generate a fine-grained point of allocation (line) based report with the
write report command as follows:
write report -capacity -l -line
view capacity
Results
This creates the Capacity window that displays memory data for the current design
(Figure 26-13).
Related Topics
Capacity Window
The “totals” argument creates a pool for memory data so you can see its growth. It allows you to
produce an analog waveform of the memory usage, which is especially useful for revealing
where you are leaking memory. Enter the command as follows:
add wave -format Analog-Step -height 300 -max 1300000000.0 -radix decimal /
#vsim_capacity#/totals
The default format of the "totals" field in the #vsim_capacity# region is Analog, with a height of
500 and a maximum value that corresponds to the available physical memory.
2. When you specify -s or no other switch, the tool reports coarse-grain analysis. When you
specify -l, it reports the fine-grain analysis.
3. When you specify -capacity -l -line together, the tool reports fine-grained point of
allocation (line) based capacity data. (You must use vsim -capacity=line prior to this
step to create a line-based capacity data.)
Examples
This command,
To generate a point of allocation (line) based capacity report, use the following syntax:
2. Currently the fine-grain analysis data is not available from this report except as details
related to covergroup memory usage.
3. To report the covergroup memory usage details, you can use the vcover report command
with the following arguments:
vcover report -cvg -details -memory
Examples
The command,
COVERGROUP MEMORY USAGE: Total 13.3 KBytes, Peak 13.3 KBytes at time 0 ns
for total 4 coverpoints/crosses.
ASSERT/COVER MEMORY USAGE: Total Memory 0 Bytes.
CONSTRAINT SOLVER MEMORY USAGE: Total 1.1 MBytes, Peak 1.1 MBytes at time
0 ns for total 100 randomize() calls.
CLASS OBJECTS MEMORY USAGE: Total Memory 68 Bytes and Peak Memory 68 Bytes
used at time 0 ns for total 1 class objects.
DYNAMIC OBJECTS MEMORY USAGE: Total Memory 35 Bytes and Peak Memory 35
Bytes used at time 0 ns for total 2 dynamic objects.
The Verilog language allows access to any signal from any other hierarchical block without
having to route it through the interface. This means you can use hierarchical notation to either
write or read the value of a signal in the design hierarchy from a test bench. Verilog can also
reference a signal in a VHDL block or reference a signal in a Verilog block through a level of
VHDL hierarchy.
With the VHDL-2008 standard, VHDL supports hierarchical referencing as well. However, you
cannot reference from VHDL to Verilog. The Signal Spy procedures and system tasks provide
hierarchical referencing across any mix of Verilog, VHDL and/or SystemC, allowing you to
monitor (spy), drive, force, or release hierarchical objects in mixed designs. While not strictly
required for references beginning in Verilog, it does allow references to be consistent across all
languages.
library modelsim_lib;
use modelsim_lib.util.all;
The Verilog tasks and SystemC functions are available as built-in SystemVerilog System Tasks
and Functions.
Note that using Signal Spy procedures limits the portability of your code—HDL code with
Signal Spy procedures or tasks works only in Questa and Modelsim. Consequently, you should
use Signal Spy only in test benches, where portability is less of a concern and the need for such
procedures and tasks is more applicable.
• If the name does not include a dataset name, then the current dataset is used.
• If the name does not start with a path separator, then the current context is used.
• If the name is a path separator followed by a name that is not the name of a top-level
design unit, then the first top-level design unit in the design is used.
• For a relative name containing a hierarchical path, if the first object name cannot be
found in the current context, then an upward search is done up to the top of the design
hierarchy to look for a matching object name.
• If no objects of the specified name can be found in the specified context, then an upward
search is done to look for a matching object in any visible enclosing scope up to an
instance boundary. If at least one match is found within a given context, no (more)
upward searching is done; therefore, some objects that may be visible from a given
context will not be found when wildcards are used if they are within a higher enclosing
scope.
• The wildcards '*' and '?' can be used at any level of a name except in the dataset name
and inside of a slice specification.
• A wildcard character will never match a path separator. For example, /dut/* will match /
dut/siga and /dut/clk. However, /dut* will not match either of those.
Related Topics
VHDL Utilities Package (util)
• SystemC-SystemVerilog
• SystemC-SystemC
• SystemC-VHDL
• VHDL-SystemVerilog
• SystemVerilog-SystemVerilog
In addition to referring to the complete signal, you can also address the bit-selects, field-selects
and part-selects of the supported types. For example:
/top/myInst/my_record[2].my_field1[4].my_vector[8]
disable_signal_spy
This reference section describes the following:
• VHDL Procedure — disable_signal_spy()
• Verilog Task — $disable_signal_spy()
• SystemC Function — disable_signal_spy()
The disable_signal_spy call disables the associated init_signal_spy. The association between
the disable_signal_spy call and the init_signal_spy call is based on specifying the same
src_object and dest_object arguments to both. The disable_signal_spy call can only affect
init_signal_spy calls that had their control_state argument set to “0” or “1”.
Syntax
VHDL Syntax
disable_signal_spy(<src_object>, <dest_object>, <verbose>)
Verilog Syntax
$disable_signal_spy(<src_object>, <dest_object>, <verbose>)
SystemC Syntax
disable_signal_spy(<src_object>, <dest_object>, <verbose>)
Arguments
• src_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal, SystemVerilog or Verilog register/net, or SystemC signal.
This path should match the path that was specified in the init_signal_spy call that you want
to disable.
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal, SystemVerilog or Verilog register/net, or SystemC signal.
This path should match the path that was specified in the init_signal_spy call that you want
to disable.
• verbose
Optional integer. Specifies whether you want a message reported in the transcript stating
that a disable occurred and the simulation time that it occurred.
0 — Does not report a message. Default.
1 — Reports a message.
Return Values
Nothing
Description
By default this command uses a forward slash (/) as a path separator. You can change this
behavior with the SignalSpyPathSeparator variable in the modelsim.ini file.
Examples
See init_signal_spy.
Related Topics
init_signal_spy
enable_signal_spy
enable_signal_spy
This reference section describes the following:
• VHDL Procedure — enable_signal_spy()
• Verilog Task — $enable_signal_spy()
• SystemC Function — enable_signal_spy()
The enable_signal_spy() call enables the associated init_signal_spy call. The association
between the enable_signal_spy call and the init_signal_spy call is based on specifying the same
src_object and dest_object arguments to both. The enable_signal_spy call can only affect
init_signal_spy calls that had their control_state argument set to “0” or “1”.
Syntax
VHDL Syntax
enable_signal_spy(<src_object>, <dest_object>, <verbose>)
Verilog Syntax
$enable_signal_spy(<src_object>, <dest_object>, <verbose>)
SystemC Syntax
enable_signal_spy(<src_object>, <dest_object>, <verbose>)
Arguments
• src_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal, SystemVerilog or Verilog register/net, or SystemC signal.
This path should match the path that was specified in the init_signal_spy call that you want
to enable.
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal, SystemVerilog or Verilog register/net, or SystemC signal.
This path should match the path that was specified in the init_signal_spy call that you want
to enable.
• verbose
Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported
in the transcript stating that an enable occurred and the simulation time that it occurred.
0 — Does not report a message. Default.
1 — Reports a message.
Return Values
Nothing
Description
By default this command uses a forward slash (/) as a path separator. You can change this
behavior with the SignalSpyPathSeparator variable in the modelsim.ini file.
Related Topics
init_signal_spy
disable_signal_spy
init_signal_driver
This reference section describes the following:
• VHDL Procedure — init_signal_driver()
• Verilog Task — $init_signal_driver()
• SystemC Function— init_signal_driver()
The init_signal_driver() call drives the value of a VHDL signal, Verilog net, or SystemC (called
the src_object) onto an existing VHDL signal or Verilog net (called the dest_object). This
allows you to drive signals or nets at any level of the design hierarchy from within a VHDL
architecture or Verilog or SystemC module (for example, a test bench).
Note
Destination SystemC signals are not supported.
Syntax
VHDL Syntax
init_signal_driver(<src_object>, <dest_object>, <delay>, <delay_type>, <verbose>)
Verilog Syntax
$init_signal_driver(<src_object>, <dest_object>, <delay>, <delay_type>, <verbose>)
SystemC Syntax
init_signal_driver(<src_object>, <dest_object>, <delay>, <delay_type>, <verbose>)
Arguments
• src_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal, Verilog net, or SystemC signal. Use the path separator to
which your simulation is set (for example, “/” or “.”). A full hierarchical path must begin
with a “/” or “.”. The path must be contained within double quotes.
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to an existing VHDL signal or Verilog net. Use the path separator to which
your simulation is set (for example, “/” or “.”). A full hierarchical path must begin with a “/
” or “.”. The path must be contained within double quotes.
• delay
Optional time value. Specifies a delay relative to the time at which the src_object changes.
The delay can be an inertial or transport delay. If no delay is specified, then a delay of zero
is assumed.
• delay_type
Optional del_mode or integer. Specifies the type of delay that will be applied.
Description
The init_signal_driver procedure drives the value onto the destination signal just as if the
signals were directly connected in the HDL code. Any existing or subsequent drive or force of
the destination signal, by some other means, will be considered with the init_signal_driver value
in the resolution of the signal.By default this command uses a forward slash (/) as a path
separator. You can change this behavior with the SignalSpyPathSeparator variable in the
modelsim.ini file.
For VHDL, you should place all init_signal_driver calls in a VHDL process and code this
VHDL process correctly so that it is executed only once. The VHDL process should not be
sensitive to any signals and should contain only init_signal_driver calls and a simple wait
statement. The process will execute once and then wait forever. See the example below.
For Verilog, you should place all $init_signal_driver calls in a Verilog initial block. See the
example below.
Limitations
• For the VHDL init_signal_driver procedure, when driving a Verilog net, the only
delay_type allowed is inertial. If you set the delay type to mti_transport, the setting will
be ignored and the delay type will be mti_inertial.
• For the Verilog $init_signal_driver task, when driving a Verilog net, the only delay_type
allowed is inertial. If you set the delay type to 1 (transport), the setting will be ignored,
and the delay type will be inertial.
• For the SystemC init_signal_driver function, when driving a Verilog net, the only
delay_type allowed is inertial. If you set the delay type to 1 (transport), the setting will
be ignored, and the delay type will be inertial.
• Any delays that are set to a value less than the simulator resolution will be rounded to
the nearest resolution unit; no special warning will be issued.
• Verilog memories (arrays of registers) are not supported.
Examples
This example creates a local clock (clk0) and connects it to two clocks within the design
hierarchy. The .../blk1/clk will match local clk0 and a message will be displayed. The .../blk2/clk
will match the local clk0 but be delayed by 100 ps. For the second call to work, the .../blk2/clk
must be a VHDL based signal, because if it were a Verilog net a 100 ps inertial delay would
consume the 40 ps clock period. Verilog nets are limited to only inertial delays and thus the
setting of 1 (transport delay) would be ignored.
`timescale 1 ps / 1 ps
module testbench;
reg clk0;
initial begin
clk0 = 1;
forever begin
#20 clk0 = ~clk0;
end
end
initial begin
$init_signal_driver("clk0", "/testbench/uut/blk1/clk", , , 1);
$init_signal_driver("clk0", "/testbench/uut/blk2/clk", 100, 1);
end
...
endmodule
This example creates a local clock (clk0) and connects it to two clocks within the design
hierarchy. The .../blk1/clk will match local clk0 and a message will be displayed. The open
entries allow the default delay and delay_type while setting the verbose parameter to a 1. The .../
blk2/clk will match the local clk0 but be delayed by 100 ps.
drive_sig_process : process
begin
init_signal_driver("clk0", "/testbench/uut/blk1/clk", open, open, 1);
init_signal_driver("clk0", "/testbench/uut/blk2/clk", 100 ps,
mti_transport);
wait;
end process drive_sig_process;
...
end;
Related Topics
init_signal_spy
signal_force
signal_release
init_signal_spy
This reference section describes the following:
• VHDL Procedure — init_signal_spy()
• Verilog Task — $init_signal_spy()
• SystemC Function — init_signal_spy()
The init_signal_spy() call mirrors the value of a VHDL signal, SystemVerilog or Verilog
register/net, or SystemC signal (called the src_object) onto an existing VHDL signal, Verilog
register, or SystemC signal (called the dest_object). This allows you to reference signals,
registers, or nets at any level of hierarchy from within a VHDL architecture or Verilog or
SystemC module (for example, a test bench).
Syntax
VHDL Syntax
init_signal_spy(<src_object>, <dest_object>, <verbose>, <control_state>)
Verilog Syntax
$init_signal_spy(<src_object>, <dest_object>, <verbose>, <control_state>)
SystemC Syntax
init_signal_spy(<src_object>, <dest_object>, <verbose>, <control_state>)
Arguments
• src_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to a VHDL signal or SystemVerilog or Verilog register/net. Use the path
separator to which your simulation is set (for example, “/” or “.”). A full hierarchical path
must begin with a “/” or “.”. The path must be contained within double quotes.
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to an existing VHDL signal or Verilog register. Use the path separator to
which your simulation is set (for example, “/” or “.”). A full hierarchical path must begin
with a “/” or “.”. The path must be contained within double quotes.
• verbose
Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported
in the Transcript stating that the src_object value is mirrored onto the dest_object.
0 — Does not report a message. Default.
1 — Reports a message.
• control_state
Optional integer. Possible values are -1, 0, or 1. Specifies whether or not you want the
ability to enable/disable mirroring of values and, if so, specifies the initial state.
-1 — no ability to enable/disable and mirroring is enabled. (default)
0 — turns on the ability to enable/disable and initially disables mirroring.
1— turns on the ability to enable/disable and initially enables mirroring.
Return Values
Nothing
Description
The init_signal_spy call only sets the value onto the destination signal and does not drive or
force the value. Any existing or subsequent drive or force of the destination signal, by some
other means, will override the value that was set by init_signal_spy.
By default this command uses a forward slash (/) as a path separator. You can change this
behavior with the SignalSpyPathSeparator variable in the modelsim.ini file.
However, you can place simultaneous read/write calls on the same signal using multiple
init_signal_spy calls, for example:
The control_state determines whether the mirroring of values can be enabled/disabled and what
the initial state is. Subsequent control of whether the mirroring of values is enabled/disabled is
handled by the enable_signal_spy and disable_signal_spy calls.
For VHDL procedures, you should place all init_signal_spy calls in a VHDL process and code
this VHDL process correctly so that it is executed only once. The VHDL process should not be
sensitive to any signals and should contain only init_signal_spy calls and a simple wait
statement. The process will execute once and then wait forever, which is the desired behavior.
See the example below.
For Verilog tasks, you should place all $init_signal_spy tasks in a Verilog initial block. See the
example below.
Limitations
• When mirroring the value of a SystemVerilog or Verilog register/net onto a VHDL
signal, the VHDL signal must be of type bit, bit_vector, std_logic, or std_logic_vector.
• Verilog memories (arrays of registers) are not supported.
Examples
In this example, the value of /top/uut/inst1/sig1 is mirrored onto /top/top_sig1. A message is
issued to the transcript. The ability to control the mirroring of values is turned on and the
init_signal_spy is initially enabled.
The mirroring of values will be disabled when enable_sig transitions to a ‘0’ and enable when
enable_sig transitions to a ‘1’.
library ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
entity top is
end;
begin
...
spy_process : process
begin
init_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",1,1);
wait;
end process spy_process;
...
spy_enable_disable : process(enable_sig)
begin
if (enable_sig = '1') then
enable_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",0);
elseif (enable_sig = '0')
disable_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",0);
end if;
end process spy_enable_disable;
...
end;
The mirroring of values will be disabled when enable_reg transitions to a ‘0’ and enabled when
enable_reg transitions to a ‘1’.
module top;
...
reg top_sig1;
reg enable_reg;
...
initial
begin
$init_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",1,1);
end
always @ (posedge enable_reg)
begin
$enable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0);
end
always @ (negedge enable_reg)
begin
$disable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0);
end
...
endmodule
Related Topics
init_signal_driver
signal_force
signal_release
enable_signal_spy
disable_signal_spy
signal_force
This reference section describes the following:
• VHDL Procedure — signal_force()
• Verilog Task — $signal_force()
• SystemC Function — signal_force()
The signal_force() call forces the value specified onto an existing VHDL signal, Verilog
register/register bit/net, or SystemC signal (called the dest_object). This allows you to force
signals, registers, bits of registers, or nets at any level of the design hierarchy from within a
VHDL architecture or Verilog or SystemC module (for example, a test bench).
Syntax
VHDL Syntax
signal_force(<dest_object>, <value>, <rel_time>, <force_type>, <cancel_period>, <verbose>)
Verilog Syntax
$signal_force(<dest_object>, <value>, <rel_time>, <force_type>, <cancel_period>,
<verbose>)
SystemC Syntax
signal_force(<dest_object>, <value>, <rel_time>, <force_type>, <cancel_period>, <verbose>)
Arguments
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to an existing VHDL signal, SystemVerilog or Verilog register/bit of a
register/net or SystemC signal. Use the path separator to which your simulation is set (for
example, “/” or “.”). A full hierarchical path must begin with a “/” or “.”. The path must be
contained within double quotes.
• value
Required string. Specifies the value to which the dest_object is to be forced. The specified
value must be appropriate for the type.
Where value can be:
o a sequence of character literals or as a based number with a radix of 2, 8, 10 or 16.
For example, the following values are equivalent for a signal of type bit_vector (0 to
3):
• 1111 — character literal sequence
• 2#1111 —binary radix
• 10#15— decimal radix
• 16#F — hexadecimal radix
• verbose
Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported
in the Transcript stating that the value is being forced on the dest_object at the specified
time.
0 — Does not report a message. Default.
1 — Reports a message.
Return Values
Nothing
Description
A signal_force works the same as the force command with the exceptions that you cannot issue
a repeating force. The force will remain on the signal until a signal_release, a force or noforce
command, or a subsequent signal_force is issued. Signal_force can be called concurrently or
sequentially in a process.
This command displays any signals using your radix setting (either the default, or as you
specify) unless you specify the radix in the value you set.
By default this command uses a forward slash (/) as a path separator. You can change this
behavior with the SignalSpyPathSeparator variable in the modelsim.ini file.
Limitations
• Verilog memories (arrays of registers) are not supported.
Examples
This example forces reset to a “1” from time 0 ns to 40 ns. At 40 ns, reset is forced to a “0”,
200000 ns after the second $signal_force call was executed.
`timescale 1 ns / 1 ns
module testbench;
initial
begin
$signal_force("/testbench/uut/blk1/reset", "1", 0, 3, , 1);
$signal_force("/testbench/uut/blk1/reset", "0", 40, 3, 200000, 1);
end
...
endmodule
This example forces reset to a “1” from time 0 ns to 40 ns. At 40 ns, reset is forced to a “0”, 2
ms after the second signal_force call was executed.
If you want to skip parameters so that you can specify subsequent parameters, you need to use
the keyword “open” as a placeholder for the skipped parameter(s). The first signal_force
procedure illustrates this, where an “open” for the cancel_period parameter means that the
default value of -1 ms is used.
entity testbench is
end;
force_process : process
begin
signal_force("/testbench/uut/blk1/reset", "1", 0 ns, freeze, open, 1);
signal_force("/testbench/uut/blk1/reset", "0", 40 ns, freeze, 2 ms,
1);
wait;
end process force_process;
...
end;
Related Topics
init_signal_driver
init_signal_spy
signal_release
signal_release
This reference section describes the following:
• VHDL Procedure — signal_release()
• Verilog Task — $signal_release()
• SystemC Function — signal_release()
A signal_release works the same as the noforce command. Signal_release can be called
concurrently or sequentially in a process.
By default this command uses a forward slash (/) as a path separator. You can change this
behavior with the SignalSpyPathSeparator variable in the modelsim.ini file.
The signal_release() call releases any force that was applied to an existing VHDL signal,
SystemVerilog or Verilog register/register bit/net, or SystemC signal (called the dest_object).
This allows you to release signals, registers, bits of registers, or nets at any level of the design
hierarchy from within a VHDL architecture or Verilog or SystemC module (for example, a test
bench).
Syntax
VHDL Syntax
signal_release(<dest_object>, <verbose>)
Verilog Syntax
$signal_release(<dest_object>, <verbose>)
SystemC Syntax
signal_release(<dest_object>, <verbose>)
Arguments
• dest_object
Required string. A full hierarchical path (or relative downward path with reference to the
calling block) to an existing VHDL signal, SystemVerilog or Verilog register/net, or
SystemC signal. Use the path separator to which your simulation is set (for example, “/” or
“.”). A full hierarchical path must begin with a “/” or “.”. The path must be contained within
double quotes.
• verbose
Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported
in the Transcript stating that the signal is being released and the time of the release.
0 — Does not report a message. Default.
1 — Reports a message.
Return Values
Nothing
Examples
This example releases any forces on the signals data and clk when the signal release_flag is a
“1”. Both calls will send a message to the transcript stating which signal was released and when.
entity testbench is
end;
begin
stim_design : process
begin
...
wait until release_flag = '1';
signal_release("/testbench/dut/blk1/data", 1);
signal_release("/testbench/dut/blk1/clk", 1);
...
end process stim_design;
...
end;
This example releases any forces on the signals data and clk when the register release_flag
transitions to a “1”. Both calls will send a message to the transcript stating which signal was
released and when.
module testbench;
reg release_flag;
...
endmodule
Related Topics
init_signal_driver
init_signal_spy
signal_force
This chapter describes JobSpy™®, a tool for monitoring and controlling batch simulations and
simulation farms.
Designers frequently run multiple simulation jobs in batch mode once verification reaches the
regression testing stage. They face the problem that simulation farms and batch-mode runs offer
little visibility into and control over simulation jobs. JobSpy helps alleviate this problem by
allowing you to interact with batch jobs. By creating a process external to the running simulator,
JobSpy can send and receive information about the running jobs.
• port@host— Refer to the section ““Start the JobSpy Daemon” on page 1326”
• directory — Refer to the section ““Set the JOBSPY_DAEMON Variable as a
Directory” on page 1327”
• port number
• host name that the job was started on
• working directory
With a connection to the job established, you can invoke various commands via the command
line or GUI to monitor or control the job. There are two steps to starting the daemon:
Procedure
1. Set the JOBSPY_DAEMON environment variable.
The environment variable is set with the following syntax:
JOBSPY_DAEMON=<port_NUMBER>@<host>
For example,
JOBSPY_DAEMON=1301@mymachine
Every user who runs JobSpy must set this environment variable, typically in a start-up
script such as the .cshrc file. This gives every new shell access to the daemon.
2. Invoke the daemon using the jobspy -startd command or by selecting
Tools > JobSpy > Daemon > Start Daemon from within Questa SIM.
You do not need to specify -startd if you set the JOBSPY_DAEMON to a directory.
3. If you correctly set port@host in the JOBSPY_DAEMON variable, you can control jobs
submitted to that host. The intended use is that you set your JOBSPY_DAEMON
variable, start the daemon, and then control only your jobs (unless you tell others what
port@host to use). Each user can use his/her own port id to monitor only their jobs.
JOBSPY_DAEMON=/server/directory/subdirectory
This instructs any simulation job invoked with the same $JOBSPY_DAEMON to create files
containing communication and run information in the specified directory, which enables
communication between JobSpy and the simulation jobs.
The jobspy command behaves similarly regardless of your using a TCP/IP port or a directory
name for your JobSpy Daemon.
See the jobspy command for complete syntax. The most common invocations are:
Table 28-1. Simulation Commands You can Issue from JobSpy (cont.)
Command Description
profile on enable profiling of remote job
profile off disable profiling of remote job
profile save [<filename>] save a profile of remote job. Default <filename> is
job<jobid>.prof
pwd prints the job's current working directory
quit exits a simulation (terminates job)
savecov [<filename>] writes out a coverage data UCDB file, equivalent to the
coverage save command. Default <filename> is
Job_<gridtype>_<jobid>.ucdb where <gridtype> is mti,
sge, lsf or vov.
set sets a TCL variable in the remote job's interpreter
simstatus shows current status of the simulation
suspend suspends job (releases license)
unsuspend un-suspends job (reacquires license)
Example Session
The following example illustrates a session of JobSpy:
Note
If you check Advanced Mode, you can enter any Questa SIM command at the prompt.
However, you need to be careful as many Questa SIM commands will not function properly
with JobSpy.
Here are two important points to remember about viewing waveforms from the GUI:
• You must first log signals before you can view them as waveforms. If you haven’t
logged any signals, the View Waveform command in the GUI will be disabled.
• View Waveform uses the pathname from the remote machine to access a WLF file. The
command may not work on some networks. See View Commands and Pathnames for
details.
Viewing Waveforms from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
2. Save a dataset
$ jobspy 1204 savewlf snap.wlf
Dataset "sim" exported as WLF file: snap.wlf. @ 84,785,547 ns
Checkpointing Jobs
Checkpointing allows you to save the state of a simulation and restore it at a later time.
There are three primary reasons for checkpointing jobs:
If you need to checkpoint a job for migration or backup, keep in mind the following restrictions:
• The job must be restored on the same platform and exact OS on which the job was
checkpointed.
• If your job includes any foreign C code (such as PLI or FLI), the foreign application
must be written to support checkpointing. See The PLI Callback reason Argument for
more information on checkpointing with PLI applications. See the Foreign Language
Interface Reference Manual for information on checkpointing with FLI applications.
• Checkpoint is not supported once a SystemC design has been loaded.
JobSpy supports Sun Grid Engine’s task arrays, where the simulation jobs use the JOB_ID and
the SGE_TASK_ID environment variables. The jobspy command can reference these jobs as
“<taskId>.<jobId>”.
The Questa SIM Waveform Editor offers a simple method for creating design stimulus. You can
generate and edit waveforms in a graphical manner and then drive the simulation with those
waveforms.
Common tasks you can perform with the Waveform Editor:
• Create waveforms using four predefined patterns: clock, random, repeater, and counter.
Refer to Accessing the Create Pattern Wizard.
• Edit waveforms with numerous functions including inserting, deleting, and stretching
edges; mirroring, inverting, and copying waveform sections; and changing waveform
values on-the-fly. Refer to Editing Waveforms.
• Drive the simulation directly from the created waveforms
• Save created waveforms to four stimulus file formats: Tcl force format, extended VCD
format, Verilog module, or VHDL architecture. The HDL formats include code that
matches the created waveforms and can be used in test benches to drive a simulation.
Refer to Exporting Waveforms to a Stimulus File
The current version does not support the following:
2. Edit the waveforms in the Wave window. See Editing Waveforms for more details.
3. Run the simulation (see Simulating Directly from Waveform Editor) or save the created
waveforms to a stimulus file (see Exporting Waveforms to a Stimulus File).
Results
After the first step, a Wave window opens and displays signal names with the orange Waveform
Editor icon (Figure 29-2).
2. Use the Create Pattern wizard to create the waveforms (see Accessing the Create Pattern
Wizard).
3. Edit the waveforms as required (see Editing Waveforms).
4. Run the simulation (see Simulating Directly from Waveform Editor) or save the created
waveforms to a stimulus file (see Exporting Waveforms to a Stimulus File).
In this dialog you specify the signal that the waveform will be based upon, the Drive Type (if
applicable), the start and end time for the waveform, and the pattern for the waveform.
The second dialog in the wizard lets you specify the appropriate attributes based on the pattern
you select. The table below shows the five available patterns and their attributes:
Editing Waveforms
You can edit waveforms interactively with menu commands, mouse actions, or by using the
wave edit command.
Procedure
1. Create an editable pattern as described under Accessing the Create Pattern Wizard.
2. Enter editing mode by right-clicking a blank area of the toolbar and selecting
Wave_edit from the toolbar popup menu.
This will open the Wave Edit toolbar.
Figure 29-5. Wave Edit Toolbar
3. Select an edge or a section of the waveform with your mouse. See Selecting Parts of the
Waveform for more details.
4. Select a command from the Wave > Wave Editor menu when the Wave window is
docked, from the Edit > Wave menu when the Wave window is undocked, or right-
click on the waveform and select a command from the Wave context menu.
5. The table below summarizes the editing commands that are available.
Figure 29-6. Manipulating Waveforms with the Wave Edit Toolbar and Cursors
Here are some points to keep in mind about stretching and moving edges:
• If you stretch an edge forward, more waveform is inserted at the beginning of simulation
time.
• If you stretch an edge backward, waveform is deleted at the beginning of simulation
time.
• If you move an edge past another edge, either forward or backward, the edge you moved
past is deleted.
Related Topics
vsim
Related Topics
wave export
Note
This command works only with extended VCD files created with Questa SIM.
Related Topics
Waveform Compare
This chapter covers the Questa SIM implementation of SDF (Standard Delay Format) timing
annotation. Included are sections on VITAL SDF and Verilog SDF, plus troubleshooting.
Verilog and VHDL VITAL timing data can be annotated from SDF files by using the
simulator’s built-in SDF annotator.
ASIC and FPGA vendors usually provide tools that create SDF files for use with their cell
libraries. Refer to your vendor’s documentation for details on creating SDF files for your
library. Many vendors also provide instructions on using their SDF files and libraries with
Questa SIM.
The SDF specification was originally created for Verilog designs, but it has also been adopted
for VHDL VITAL designs. In general, the designer does not need to be familiar with the details
of the SDF specification because the cell library provider has already supplied tools that create
SDF files that match their libraries.
Note
Questa SIM can read SDF files that were compressed using gzip. Other compression
formats (for example, Unix zip) are not supported.
-sdfmin [<instance>=]<filename>
-sdftyp [<instance>=]<filename>
-sdfmax [<instance>=]<filename>
Any number of SDF files can be applied to any instance in the design by specifying one of the
above options for each file. Use -sdfmin to select minimum, -sdftyp to select typical, and
-sdfmax to select maximum timing values from the SDF file.
Instance Specification
The instance paths in the SDF file are relative to the instance to which the SDF is applied.
Usually, this instance is an ASIC or FPGA model instantiated under a test bench.
For example, to annotate maximum timing values from the SDF file myasic.sdf to an instance
u1 under a top-level named testbench, invoke the simulator as follows:
If the instance name is omitted then the SDF file is applied to the top-level. This is usually
incorrect because in most cases the model is instantiated under a test bench or within a larger
system level simulation. In fact, the design can have several models, each having its own SDF
file. In this case, specify an SDF file for each instance. For example,
You can access this dialog by invoking the simulator without any arguments or by selecting
Simulate > Start Simulation.
For Verilog designs, you can also specify SDF files by using the $sdf_annotate system task. See
$sdf_annotate for more details.
See Troubleshooting for more information on errors and warnings and how to avoid them.
Note
When compiled SDF files are used, the annotator behaves as if the -v2k_int_delays switch
for the vsim command has been specified.
• If the annotation order of multiple $sdf_annotate() calls is important, you must have all
of them in a single initial block.
The SDF statement CONDELSE, when targeted for Vital cells, is annotated to a tpd generic of
the form tpd_<inputPort>_<outputPort>.
Resolving Errors
If the simulator finds the cell instance but not the generic, an error message is issued.
For example,
In this case, make sure that the design is using the appropriate VITAL library cells. If it is, then
there is probably a mismatch between the SDF and the VITAL cells. You need to find the cell
instance and compare its generic names to those expected by the annotator. Look in the VHDL
source files provided by the cell library vendor.
If none of the generic names look like VITAL timing generic names, then perhaps the VITAL
library cells are not being used. If the generic names do look like VITAL timing generic names
but don’t match the names expected by the annotator, then there are several possibilities:
Related Topics
VITAL Usage and Compliance
Troubleshooting
Verilog SDF
Verilog designs can be annotated using either the simulator command line options or the
$sdf_annotate system task (also commonly used in other Verilog simulators). The command
line options annotate the design immediately after it is loaded, but before any simulation events
take place. The $sdf_annotate task annotates the design at the time it is called in the Verilog
source code. This provides more flexibility than the command line options.
$sdf_annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
SDF to Verilog Construct Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
$sdf_annotate
The $sdf_annotate task annotates the design when it is called in the Verilog source code.
Syntax
$sdf_annotate
([“<sdffile>”], [<instance>], [“<config_file>”], [“<log_file>”], [“<mtm_spec>”],
[“<scale_factor>”], [“<scale_type>”]);
Arguments
• “<sdffile>”
String that specifies the SDF file. Required.
• <instance>
Hierarchical name of the instance to be annotated. Optional. Defaults to the instance where
the $sdf_annotate call is made.
• “<config_file>”
String that specifies the configuration file. Optional. Currently not supported, this argument
is ignored.
• “<log_file>”
String that specifies the logfile. Optional. Currently not supported, this argument is ignored.
• “<mtm_spec>”
String that specifies the delay selection. Optional. The allowed strings are “minimum”,
“typical”, “maximum”, and “tool_control”. Case is ignored and the default is
“tool_control”. The “tool_control” argument means to use the delay specified on the
command line by +mindelays, +typdelays, or +maxdelays (defaults to +typdelays).
• “<scale_factor>”
String that specifies delay scaling factors. Optional. The format is
“<min_mult>:<typ_mult>:<max_mult>”. Each multiplier is a real number that is used to
scale the corresponding delay in the SDF file.
• “<scale_type>”
String that overrides the <mtm_spec> delay selection. Optional. The <mtm_spec> delay
selection is always used to select the delay scaling factor, but if a <scale_type> is specified,
then it will determine the min/typ/max selection from the SDF file. The allowed strings are
“from_min”, “from_minimum”, “from_typ”, “from_typical”, “from_max”,
“from_maximum”, and “from_mtm”. Case is ignored, and the default is “from_mtm”,
which means to use the <mtm_spec> value.
Examples
Optional arguments can be omitted by using commas or by leaving them out if they are at the
end of the argument list. For example, to specify only the SDF file and the instance to which it
applies:
$sdf_annotate("myasic.sdf", testbench.u1);
The IOPATH construct usually annotates path delays. If Questa SIM can’t locate a
corresponding specify path delay, it returns an error unless you use the +sdf_iopath_to_prim_ok
argument to vsim. If you specify that argument and the module contains no path delays, then all
primitives that drive the specified output port are annotated.
Both of these constructs identify a module input or inout port and create an internal net that is a
delayed version of the port. This is called a Module Input Port Delay (MIPD). All primitives,
specify path delays, and specify timing checks connected to the original port are reconnected to
the new MIPD net.
If the SDF cell instance is a primitive instance, then that primitive’s delay is annotated. If it is a
module instance, then all specify path delays are annotated that drive the output port specified in
the DEVICE construct (all path delays are annotated if the output port is omitted). If the module
contains no path delays, then all primitives that drive the specified output port are annotated (or
all primitives that drive any output port if the output port is omitted).
To see complete mappings of SDF and Verilog constructs, please consult IEEE Std 1364-2005,
Chapter 16 - Back Annotation Using the Standard Delay Format (SDF).
Because rval2 and rval 3 on the RETAIN line are optional, the simulator makes the following
assumptions:
• Only rval1 is specified — rval1 is used as the value of rval2 and rval3.
• rval1 and rval2 are specified — the smaller of rval1 and rval2 is used as the value of
rval3.
During simulation, if any rval that would apply is larger than or equal to the applicable path
delay, then RETAIN delay is not applied.
You can specify that RETAIN delays should not be processed by using +vlog_retain_off on the
vsim command line.
Retain delays apply to an IOPATH for any transition on the input of the PATH unless the
IOPATH specifies a particular edge for the input of the IOPATH. This means that for an
IOPATH such as RCLK -> DOUT, RETAIN delay should apply for a negedge on RCLK even
though a Verilog model is coded only to change DOUT in response to a posedge of RCLK. If
(posedge RCLK) -> DOUT is specified in the SDF then an associated RETAIN delay applies
only for posedge RCLK. If a path is conditioned, then RETAIN delays do not apply if a delay
path is not enabled.
data with respect to clock, while the SDF file may contain only a single setup check for both
edges:
In this case, the cell accommodates more accurate data than can be supplied by the tool that
created the SDF file, and both timing checks correctly receive the same value.
Likewise, the SDF file may contain more accurate data than the model can accommodate.
In this case, both SDF constructs are matched and the timing check receives the value from the
last one encountered.
Timing check edge specifiers can also use explicit edge transitions instead of posedge and
negedge. However, the SDF file is limited to posedge and negedge. For example,
The explicit edge specifiers are 01, 0x, 10, 1x, x0, and x1. The set of [01, 0x, x1] is equivalent to
posedge, while the set of [10, 1x, x0] is equivalent to negedge. A match occurs if any of the
explicit edges in the specify port match any of the explicit edges implied by the SDF port.
Optional Conditions
Timing check ports and path delays can have optional conditions.
The annotator uses the following rules to match conditions:
• A match occurs for a timing check if the SDF port condition is semantically equivalent
to the specify port condition.
• A match occurs for a path delay if the SDF condition is lexically identical to the specify
condition.
Timing check conditions are limited to very simple conditions, therefore the annotator can
match the expressions based on semantics. For example,
The conditions are semantically equivalent and a match occurs. In contrast, path delay
conditions may be complicated and semantically equivalent conditions may not match. For
example,
The annotator does not match the second condition above because the order of r1 and r2 are
reversed.
using the simulator’s SDF command line options. The Verilog $sdf_annotate system task can
annotate Verilog cells only.
Related Topics
vsim
Interconnect Delays
An interconnect delay represents the delay from the output of one device to the input of another.
Questa SIM can model single interconnect delays or multisource interconnect delays for
Verilog, VHDL/VITAL, or mixed designs.
Timing checks are performed on the interconnect delayed versions of input ports. This may
result in misleading timing constraint violations, because the ports may satisfy the constraint
while the delayed versions may not. If the simulator seems to report incorrect violations, be sure
to account for the effect of interconnect delays.
Related Topics
vsim
Troubleshooting
Questa SIM provides a number of tools for troubleshooting designs that use SDF files.
Specifying the Wrong Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Matching a Single Timing Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Mistaking a Component or Module Name for an Instance Label. . . . . . . . . . . . . . . . . . 1374
Forgetting to Specify the Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Reporting Unannotated Specify Path Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
The name of the model is myasic and the instance label is dut. For either test bench, an
appropriate simulator invocation might be:
The important thing is to select the instance for which the SDF is intended. If the model is deep
within the design hierarchy, an easy way to find the instance name is to first invoke the
simulator without SDF options, view the structure pane, navigate to the model instance, select
it, and enter the environment command. This command displays the instance name that should
be used in the SDF command line option.
Related Topics
Instance Specification
Results in:
After annotation is done, the simulator issues a summary of how many instances were not found
and possibly a suggestion for a qualifying instance:
The simulator recommends an instance only if the file was applied to the top-level and a
qualifying instance is found one level down.
Also see Resolving Errors for specific VHDL VITAL SDF troubleshooting.
The partial annotation of specify objects occurs when the SDF statements contain some null
values.
Procedure
1. (optional) Add the +acc argument to the vopt command to view line numbers in the
report.
2. Add the -sdfreport=<filename> argument to your vsim command line.
Results
The Unannotated Specify Objects Report contains a list of objects that fit into any of the
following three categories:
• Unannotated specify paths (UASP).
• Unannotated timing checks (UATC). This indicates either a single-value timing check
that was not annotated or part of a $setuphold or $recrem that was not annotated.
• Incompletely-annotated specify path transition edges (IATE). This indicates that certain
edges of a specify path, such as 0->1, 1->Z, and so on, were incompletely annotated.
The header of the report contains a full description of the syntax.
Examples
This example report shows the format if you have full design visibility (vopt with the +acc
argument):
This example report shows the format if you fully optimized the design (lines are abbreviated
for readability):
The Value Change Dump (VCD) file format is supported for use by Questa SIM and is specified
in the IEEE 1364-2005 standard. A VCD file is an ASCII file that contains information about
value changes on selected variables in the design stored by VCD system tasks. This includes
header information, variable definitions, and variable value changes.
VCD is in common use for Verilog designs and is controlled by VCD system task calls in the
Verilog source code. Questa SIM provides equivalent commands for these system tasks and
extends VCD support to SystemC and VHDL designs. You can use these Questa SIM VCD
commands on Verilog, VHDL, SystemC, or mixed designs.
Extended VCD supports Verilog and VHDL ports in a mixed-language design containing
SystemC. However, extended VCD does not support SystemC ports in a mixed-language
design.
If you need vendor-specific ASIC design-flow documentation that incorporates VCD, contact
your ASIC vendor.
2. With the design loaded, specify the VCD file name with the vcd file command and add
objects to the file with the vcd add command as follows:
vcd file myvcdfile.vcd
vcd add /test_counter/dut/*
VSIM 3> runVSIM 4> quit -f
Results
Upon quitting the simulation, there will be a VCD file in the working directory.
Procedure
1. Compile and load the design. For example:
cd <installDir>/examples/tutorials/verilog/basicSimulation
vlib work
vlog counter.v tcounter.v
vopt test_counter +acc -o test_counter_opt
vsim test_counter_opt
2. With the design loaded, specify the VCD file name and objects to add with the
vcd dumpports command:
vcd dumpports -file myvcdfile.vcd /test_counter/dut/*
run
VSIM 4> quit -f
Results
Upon quitting the simulation, there will be an extended VCD file called myvcdfile.vcd in the
working directory.
Note
There is an internal limit to the number of ports that can be listed with the vcd dumpports
command. If that limit is reached, use the vcd add command with the -dumpports option to
name additional ports.
1. Simulate the top level of a design unit with the input values from an extended VCD file.
2. Specify one or more instances in a design to be replaced with the output values from the
associated VCD file.
Simulating with Input Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Replacing Instances with Output Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . 1384
Port Order Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
cd <installDir>/examples/tutorials/verilog/basicSimulation
vlib work
vlog counter.v tcounter.v
vopt test_counter +acc -o test_counter_opt
vsim test_counter_opt +dumpports+nocollapse
vcd dumpports -file counter.vcd /test_counter/dut/*
run
quit -f
Next, rerun the counter without the test bench, using the -vcdstim argument:
cd <installDir>/examples/vcd
vlib work
vcom gates.vhd adder.vhd stimulus.vhd
vopt testbench2 +acc -o testbench2_opt
vsim testbench2_opt +dumpports+nocollapse
vcd dumpports -file addern.vcd /testbench2/uut/*
run 1000
quit -f
Next, rerun the adder without the test bench, using the -vcdstim argument:
vsim -vcdstim addern.vcd addern -gn=8 -do "add wave /*; run 1000"
Mixed-HDL Design
First, create three VCD files, one for each module:
cd <installDir>/examples/tutorials/mixed/projects
vlib work
vlog cache.v memory.v proc.v
vcom util.vhd set.vhd top.vhd
vopt top +acc -o top_opt
vsim top_opt +dumpports+nocollapse
vcd dumpports -file proc.vcd /top/p/*
vcd dumpports -file cache.vcd /top/c/*
vcd dumpports -file memory.vcd /top/m/*
run 1000
quit -f
Next, rerun each module separately, using the captured VCD stimulus:
vsim -vcdstim proc.vcd proc -do "add wave /*; run 1000"
quit -f
vsim -vcdstim cache.vcd cache -do "add wave /*; run 1000"
quit -f
vsim -vcdstim memory.vcd memory -do "add wave /*; run 1000"
quit -f
Note
When using VCD files as stimulus, the VCD file format does not support recording of delta
delay changes – delta delays are not captured and any delta delay ordering of signal changes
is lost. Designs relying on this ordering may produce unexpected results.
First, create VCD files for all instances you want to replace:
Next, simulate your design and map the instances to the VCD files you created:
Note
When using VCD files as stimulus, the VCD file format does not support recording of delta
delay changes – delta delays are not captured and any delta delay ordering of signal changes
is lost. Designs relying on this ordering may produce unexpected results.
The order of the ports in the module line (clk, addr, data, ...) does not match the order of those
ports in the input, output, and inout lines (clk, rdy, addr, ...). In this case the -vcdstim argument
to the vcd dumpports command needs to be used.
In cases where the order is the same, you do not need to use the -vcdstim argument to vcd
dumpports. Also, module declarations of the form:
Questa SIM also supports extended VCD (dumpports system tasks). The table below maps the
VCD dumpports commands to their associated tasks.
Questa SIM supports multiple VCD files. This functionality is an extension of the IEEE Std
1364-2005 specification. The tasks behave the same as the IEEE equivalent tasks such as
$dumpfile, $dumpvar, and so forth. The difference is that $fdumpfile can be called multiple
times to create more than one VCD file, and the remaining tasks require a filename argument to
associate their actions with a specific file. Table 31-3 maps the VCD commands to their
associated tasks. For additional details, please see the Verilog IEEE Std 1364-2005
specification.
Table 31-3. VCD Commands and System Tasks for Multiple VCD Files
VCD commands VCD system tasks
vcd add -file <filename> $fdumpvars( levels, {, module_or_variable }1, filename)
vcd checkpoint <filename> $fdumpall( filename )
vcd files <filename> $fdumpfile( filename )
vcd flush <filename> $fdumpflush( filename )
vcd limit <filename> $fdumplimit( filename )
vcd off <filename> $fdumpoff( filename )
vcd on <filename> $fdumpon( filename )
1. denotes an optional, comma-separated list of 0 or more modules or variables
sc_in<T>, sc_out<T>, sc_inout<T>, where <T> can be any of types shown in the following
table.
entity SHIFTER_MOD is
port (CLK, RESET, data_in : IN STD_LOGIC;
Q : INOUT STD_LOGIC_VECTOR(8 downto 0));
END SHIFTER_MOD ;
VCD Output
The VCD file created as a result of the preceding scenario would be called output.vcd. The
following pages show how it would look.
VCD to WLF
The Questa SIM vcd2wlf command is a utility that translates a .vcd file into a .wlf file that can
be displayed in Questa SIM using the vsim -view argument. This command only works on VCD
files containing positive time values.
Driver States
Table 31-5 shows the driver states recorded as TSSI states if the direction is known.
If the direction is unknown, the state will be recorded as one of the following:
Identifier Code
The <identifier_code> is an integer preceded by < that starts at zero and is incremented for each
port in the order the ports are specified. Also, the variable type recorded in the VCD header is
“port”.
Resolving Values
The resolved values written to the VCD file depend on which options you specify when creating
the file.
Default Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
When force Command is Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Extended Data Type for VHDL (vl_logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
Ignoring Strength Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
Default Behavior
By default, Questa SIM generates VCD output according to the IEEE Std 1364™-2005, IEEE
Standard for Verilog® Hardware Description Language. This standard states that the values 0
(both input and output are active with value 0) and 1 (both input and output are active with value
1) are conflict states. The standard then defines two strength ranges:
• Strong: strengths 7, 6, and 5
• Weak: strengths 4, 3, 2, 1
The rules for resolving values are as follows:
• If the input and output are driving the same value with the same range of strength, the
resolved value is 0 or 1, and the strength is the stronger of the two.
• If the input is driving a strong strength and the output is driving a weak strength, the
resolved value is D, d, U or u, and the strength is the strength of the input.
• If the input is driving a weak strength and the output is driving a strong strength, the
resolved value is L, l, H or h, and the strength is the strength of the output.
This specification also defines three charge storage strengths for signals originating in the trireg
net type:
Each of these strengths can assume a strength level ranging from 0 to 7 (expressed as a binary
value from 000 to 111), combined with the standard four-state values of 0, 1, X, and Z. This
results in a set of 256 strength values, which preserves Verilog strength values going through
the VHDL portion of the design and allows a VCD in extended format for any downstream
application.
The vl_logic type is defined in the following file installed with Questa SIM, where you can
view the 256 strength values:
<install_dir>/vhdl_src/verilog/vltypes.vhd
This location is a pre-compiled verilog library provided in your installation directory, along
with the other pre-compiled libraries (std and ieee).
Note
The Wave window display and WLF do not support the full range of vl_logic values for
VHDL signals.
The nc_sim_index argument is required yet ignored by Questa SIM. It is required only to be
compatible with NCSim’s argument list.
The file_format argument accepts the following values or an ORed combination thereof (see
examples below):
This example demonstrates how vcd dumpports resolves values based on certain combinations
of driver values and strengths and whether or not you use strength ranges. Table 31-10 is sample
driver data.
Given the driver data above and use of 1364 strength ranges, here is what the VCD file output
would look like:
#0
p0 7 0 <0
#100
p0 7 0 <0
#200
p0 7 0 <0
#300
pL 7 0 <0
#900
pB 7 6 <0
#27400
pU 0 5 <0
#27500
p1 0 4 <0
#27600
p1 0 4 <0
Tcl is a scripting language for controlling and extending Questa SIM. Within Questa SIM you
can develop implementations from Tcl scripts without the use of C code. Because Tcl is
interpreted, development is rapid; you can generate and execute Tcl scripts “on the fly” without
stopping to recompile or restart Questa SIM. In addition, if Questa SIM does not provide a
command you need, you can use Tcl to create your own commands.
Tcl Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Tcl Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
Simulator State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
List Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Simulator Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
The Tcl Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
TclPro Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
Tcl Features
Using Tcl with Questa SIM gives you these features:
• command history (like that in C shells)
• full expression evaluation and support for all C-language operators
• a full range of math and trig functions
• support of lists and arrays
• regular expression pattern matching
• procedures
• the ability to define your own commands
• command substitution (that is, commands may be nested)
• robust scripting language for DO files
Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Tcl References
For quick reference information on Tcl, choose the following from the Questa SIM main menu:
Help > Tcl Man Pages
In addition, the following books provide more comprehensive usage information on Tcl:
Name is the name of a scalar variable; the name is terminated by any character that
isn't a letter, digit, or underscore.
o $name(index)
Name gives the name of an array variable and index gives the name of an element
within that array. Name must contain only letters, digits, and underscores. Command
substitutions, variable substitutions, and backslash substitutions are performed on
the characters of index.
o ${name}
Name is the name of a scalar variable. It may contain any characters whatsoever
except for close braces.
There may be any number of variable substitutions in a single word. Variable
substitution is not performed on words enclosed in braces.
• If a backslash (\) appears within a word then backslash substitution occurs. In all cases
but those described below the backslash is dropped and the following character is treated
as an ordinary character and included in the word. This allows characters such as double
quotes, close brackets, and dollar signs to be included in words without triggering
special processing. Table 32-1 lists the backslash sequences that are handled specially,
along with the value that replaces each sequence.
1. If a pound sign (#) appears at a point where Tcl is expecting the first character of the first
word of a command, then the pound sign and the characters that follow it, up through the
next newline, are treated as a comment and ignored. The # character denotes a comment
only when it appears at the beginning of a command.
2. Each character is processed exactly once by the Tcl interpreter as part of creating the
words of a command. For example, if variable substitution occurs then no further
substitutions are performed on the value of the variable; the value is inserted into the
word verbatim. If command substitution occurs then the nested command is processed
entirely by the recursive call to the Tcl interpreter; no substitutions are performed before
making the recursive call and no additional substitutions are performed on the result of
the nested script.
3. Substitutions do not affect the word boundaries of a command. For example, during
variable substitution the entire value of the variable becomes part of a single word, even
if the variable's value contains spaces.
If Command Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
set Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Command Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Command Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Multiple-Line Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Evaluation Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Tcl Relational Expression Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Variable Substitution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
System Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Questa SIM Replacements for Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
If Command Syntax
The Tcl if command executes scripts conditionally. Note that in the syntax below the question
mark (?) indicates an optional argument.
Syntax
if expr1 ?then? body1 elseif expr2 ?then? body2 elseif ... ?else? ?bodyN?
Arguments
None
Description
The if command evaluates expr1 as an expression. The value of the expression must be a
boolean (a numeric value, where 0 is false and anything else is true, or a string value such as
true or yes for true and false or no for false); if it is true then body1 is executed by passing it to
the Tcl interpreter. Otherwise expr2 is evaluated as an expression and if it is true then body2 is
executed, and so on. If none of the expressions evaluates to true then bodyN is executed. The
then and else arguments are optional “noise words” to make the command easier to read. There
may be any number of elseif clauses, including zero. BodyN may also be omitted as long as else
is omitted too. The return value from the command is the result of the body script that was
executed, or an empty string if none of the expressions was non-zero and there was no bodyN.
Arguments
• The following arguments are available:
o <varName> — (required) The name of a Tcl variable. The variable name relates to
the following:
• GUI preference variables. You can view a complete list of these variables within
the GUI from the Tools > Edit Preferences menu selection.
• Simulator control variables.
If you do not specify a <value> this command will return the value of the <varName> you
specify.
o <value> — (optional) The value to be assigned to the variable.
When you specify <value> you will change the current state of the <varName> you
specify.
Description
Returns the value of variable varName. If you specify value, the command sets the value of
varName to value, creating a new variable if one does not already exist, and returns its value. If
varName contains an open parenthesis and ends with a close parenthesis, then it refers to an
array element: the characters before the first open parenthesis are the name of the array, and the
characters between the parentheses are the index within the array. Otherwise varName refers to
a scalar variable. Normally, varName is unqualified (does not include the names of any
containing namespaces), and the variable of that name in the current namespace is read or
written. If varName includes namespace qualifiers (in the array name if it refers to an array
element), the variable in the specified namespace is read or written.
If no procedure is active, then varName refers to a namespace variable (global variable if the
current namespace is the global namespace). If a procedure is active, then varName refers to a
parameter or local variable of the procedure unless the global command was invoked to declare
varName to be global, or unless a Tcl variable command was invoked to declare varName to be
a namespace variable.
Command Substitution
Placing a command in square brackets ([ ]) will cause that command to be evaluated first and its
results returned in place of the command. For example:
set a 25
set b 11
set c 3
echo "the result is [expr ($a + $b)/$c]"
Substitution allows you to obtain VHDL variables and signals, and Verilog nets and registers
using the following construct:
The %name substitution is no longer supported. Everywhere %name could be used, you now
can use [examine -value -<radix> name] which allows the flexibility of specifying command
options. The radix specification is optional.
Command Separator
A semicolon character (;) works as a separator for multiple commands on the same line. It is not
required at the end of a line in a command sequence.
Multiple-Line Commands
With Tcl, multiple-line commands can be used within scripts and on the command line. The
command line prompt will change (as in a C shell) until the multiple-line command is complete.
In the example below, note the way the opening brace “{” is at the end of the if and else lines.
This is important because otherwise the Tcl scanner won't know that there is more coming in the
command and will try to execute what it has up to that point, which won't be what you intend.
Evaluation Order
An important thing to remember when using Tcl is that anything put in braces ({}) is not
evaluated immediately. This is important for if-then-else statements, procedures, loops, and so
forth.
• However, if a literal cannot be represented as a number, you must quote it, or Tcl will
give you an error. For instance:
if {[exa var_2] == 001Z}...
will work.
• For the equal operator, you must use the C operator (==). For not-equal, you must use
the C operator (!=).
Variable Substitution
When a $<var_name> is encountered, the Tcl parser will look for variables that have been
defined either by Questa SIM or by you, and substitute the value of the variable.
Note
Tcl is case sensitive for variable names.
$env(<var_name>)
echo My user name is $env(USER)
See modelsim.ini Variables for more information about Questa SIM-defined variables.
System Commands
To pass commands to the UNIX shell or DOS window, use the Tcl exec command:
echo The date is [exec date]
Related Topics
Simulator GUI Preferences
Depending on the current simulator state, this command could result in:
If you do not want the dollar sign to denote a simulator variable, precede it with a “\”. For
example, \$now will not be interpreted as the current simulator time.
See Simulator Tcl Time Commands for details on 64-bit time operators.
Related Topics
when
Reads the string value for the specified variable in the specified section. Optionally provides a
default value if no value is present.
Setting Tcl variables with values from the modelsim.ini file is one use of these Tcl functions.
For example,
This example reports the value of the variable named SolveGraphMaxSize from the vsim
section in the modelsim.ini file.
List Processing
In Tcl, a “list” is a set of strings in braces separated by spaces. Several Tcl commands are
available for creating lists, indexing into lists, appending to lists, getting the length of lists and
shifting lists, as shown in the following table.
Two other commands, lsearch and lsort, are also available for list manipulation. See the Tcl man
pages (Help > Tcl Man Pages) for more information on these commands.
Related Topics
when
Tcl Examples
This section provides examples of Tcl command usage.
• Tcl while Loop
This example uses the Tcl while loop to copy a list from variable a to variable b,
reversing the order of the elements along the way:
set b [list]
set i [expr {[llength $a] - 1}]
while {$i >= 0} {
lappend b [lindex $a $i]
incr i -1
}
This example uses the Tcl for command to copy a list from variable a to variable b,
reversing the order of the elements along the way:
set b [list]
for {set i [expr {[llength $a] - 1}]} {$i >= 0} {incr i -1} {
lappend b [lindex $a $i]
}
DO Files
Questa SIM DO files are simply scripts that contain Questa SIM and, optionally, Tcl
commands. You invoke these scripts with the Tools > TCL > Execute Macro menu selection
or the do command.
Creating DO Files
You can create DO file scripts, like any other Tcl script, by doing one of the following.
Procedure
1. Type the required commands in any editor and save the file with the extension .do.
2. Save the transcript as a DO file (refer to Saving a Transcript File as a DO file.
3. Use the write format restart command to create a .do file that will recreate all debug
windows, all file/line breakpoints, and all signal breakpoints created with the when
command.
4. All “event watching” commands (for example, onbreak, onerror, and so forth) must be
placed before run commands within the script in order to take effect.
5. The following is a simple DO file script that was saved from the transcript. It is used in
the dataset exercise in the Questa SIM Tutorial. This script adds several signals to the
Wave window, provides stimulus to those signals, and then advances the simulation.
add wave ld
add wave rst
add wave clk
add wave d
add wave q
force -freeze clk 0 0, 1 {50 ns} -r 100
force rst 1
force rst 0 10
force ld 0
force d 1010
onerror {cont}
run 1700
force ld 1
run 100
force ld 0
run 400
force rst 1
run 200
force rst 0 10
run 1500
There is no limit to the number of parameters that can be passed to DO file scripts, but only nine
values are visible at one time. You can use the shift command to see the other parameters.
4. The first line will close the current log file. The second will open a new log file. If it has
the same name as an existing file, it will replace the previous one.
This script specifies the compiler arguments and lets you compile any number of files.
variable Files ""
set nbrArgs $argc
for {set x 1} {$x <= $nbrArgs} {incr x} {
set Files [concat $Files $1]
shift
}
eval vcom -93 -explicit -noaccel std_logic_arith $Files
Related Topics
Simulator State Variables
You can also set the OnErrorDefaultAction Tcl variable to determine what action Questa SIM
takes when an error occurs.
To set the variable on a permanent basis, you must define the variable in a modelsim.tcl file (see
The modelsim.tcl File for details).
When a do command is interrupted by an error or breakpoint, it does not update any windows,
and keeps the DO file “locked”. This keeps the Source window from flashing, scrolling, and
moving the arrow when a complex DO file is executed. Typically an onbreak resume command
is used to keep the script running as it hits breakpoints. Add an onbreak abort command to the
DO file if you want to exit the script and update the Source window.
Note
Mentor Graphics would like to acknowledge the contribution from Gregor Schmid for
making TDebug available for use in the public domain.
The TDebug program is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of FITNESS FOR A PARTICULAR
PURPOSE.
The Debugger
Select Tools > TCL > Tcl Debugger to run the debugger. Make sure you use the Questa SIM
and TDebug menu selections to invoke and close the debugger.
Select the Popup button in the Chooser to open the debugger window (Figure 32-2).
The debugger window is divided into the main region with the name of the current procedure
(Proc), a listing in which the expression just executed is highlighted, the Result of this
execution and the currently available Variables and their values, an entry to Eval expressions
in the context of the current procedure, and some button controls for the state of the debugger.
A procedure listing displayed in the main region will have a darker background on all lines that
have been prepared. You can prepare or restore additional lines by selecting a region
(<Button-1>, standard selection) and choosing Selection > Prepare Proc or Selection >
Restore Proc from the debugger menu (or by pressing Ctrl-P or Ctrl-R).
When using `Prepare' and `Restore', try to be smart about what you intend to do. If you select
just a single word (plus some optional white space) it will be interpreted as the name of a
procedure to prepare or restore. Otherwise, if the selection is owned by the listing, the
corresponding lines will be used.
Be careful with partial prepare or restore! If you prepare random lines inside a `switch' or `bind'
expression, you may get surprising results on execution, because the parser doesn't know about
the surrounding expression and can't try to prevent problems.
There are seven possible debugger states, one for each button and an `idle' or `waiting' state
when no button is active. The button-activated states are shown in Table 32-10.
Closing the debugger doesn't quit it, it only does `wm withdraw'. The debugger window will
pop up the next time a prepared procedure is called. Make sure you close the debugger with
Debugger > Close.
The Chooser
Select Tools > TCL > Tcl Debugger to open the TDebug chooser.
The TDebug chooser has three parts. At the top the current interpreter, vsim.op_, is shown. In
the main section there are two list boxes. All currently defined procedures are shown in the left
list box. By clicking the left mouse button on a procedure name, the procedure gets prepared for
debugging and its name is moved to the right list box. Clicking a name in the right list box
returns a procedure to its normal state.
Press the right mouse button on a procedure in either list box to get its program code displayed
in the main debugger window.
The three buttons at the bottom let you force a Rescan of the available procedures, Popup the
debugger window or Exit TDebug. Exiting from TDebug doesn't terminate Questa SIM, it
merely detaches from vsim.op_, restoring all prepared procedures to their unmodified state.
The Eval entry supports a simple history mechanism available via the <Up_arrow> and
<Down_arrow> keys. If you evaluate a command while stepping through a procedure, the
command will be evaluated in the context of the procedure; otherwise it will be evaluated at the
global level. The result will be displayed in the result field. This entry is useful for a lot of
things, but especially to get access to variables outside the current scope.
Try entering the line `global td_priv' and watch the Variables box (with global and array
variables enabled of course).
Configuration
You can customize TDebug by setting up a file named .tdebugrc in your home directory.
TclPro Debugger
The Tools menu in the Main window contains a selection for the TclPro Debugger from
Scriptics Corporation. This debugger and any available documentation can be acquired from
Scriptics. Once acquired, do the following steps to use the TclPro Debugger:
1. Make sure the TclPro bin directory is in your PATH.
2. In TclPro Debugger, create a new project with Remote Debugging enabled.
3. Start Questa SIM and select Tools > TclPro Debugger.
4. Press the Stop button in the debugger in order to set breakpoints, and so forth.
Note
TclPro Debugger version 1.4 does not work with Questa SIM.
The modelsim.ini file is the default initialization file and contains control variables that specify
reference library paths, optimization, compiler and simulator settings, and various other
functions. This chapter covers the contents and modification of the modelsim.ini file.
Organization of the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
Making Changes to the modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
Editing modelsim.ini Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
Overriding the Default Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
The Runtime Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
AcceptLowerCasePragmaOnly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
AccessObjDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
AddPragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
AmsStandard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
AppendClose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
AssertFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
AssertionActiveThreadMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
AssertionActiveThreadMonitorLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
AssertionCover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
AssertionDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
AssertionEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
AssertionEnableVacuousPassActionBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
AssertionFailAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
AssertionFailLocalVarLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
AssertionFailLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
AssertionLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
AssertionPassLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
AssertionThreadLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
AssertionThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
ATVStartTimeKeepCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
AutoExclusionsDisable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
AutoLibMapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
BatchMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
BatchTranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
BindAtCompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
BreakOnAssertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
CheckPlusargs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
CheckpointCompressMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
CheckSynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
ClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
CodeCoverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
CodeLinkAutoLoad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
CommandHistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
CompilerTempDir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
ConcurrentFileLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
CoverAtLeast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
CoverCells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
CoverClkOptBuiltins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
CoverConstruct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
CoverCountAll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
CoverDeglitchOn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
CoverDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
CoverEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
CoverExcludeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
CoverFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
CoverLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
CoverLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
CoverMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
CoverOpt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
CoverREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
CoverRespectHandL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
CoverReportCancelled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
CoverShortCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
CoverSub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
CoverThreadLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
CoverThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
CoverUDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
CoverWeight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
CppInstall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
CppOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
CppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
CreateDirForFileAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
CreateLib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
CvgZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
DatasetSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
DefaultForceKind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
DefaultLibType. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
DefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
DefaultRadixFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
DefaultRestartOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
DelayFileOpen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527
displaymsgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
DpiCppPath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
DpiOutOfTheBlue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
DumpportsCollapse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
EmbeddedPsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
EnableDpiSosCb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
EnableSVCoverpointExprVariable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
EnableTypeOf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
EnumBaseInit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
ErrorFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
Explicit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
ExtendedToggleMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
fatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
FecCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
FecUdpEffort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
FlatLibPageSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
FlatLibPageDeletePercentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
FlatLibPageDeleteThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
floatfixlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
ForceSigNextIter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
ForceUnsignedIntegerToVHDLInteger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
FsmImplicitTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
FsmResetTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
FsmSingle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
FsmXAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
GCThreshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
GCThresholdClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
GenerateFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
GenerateLoopIterationMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
GenerateRecursionDepthMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
GenerousIdentifierParsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
GlobalSharedObjectList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
GlobalSharedObjectsList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Hazard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
ieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
IgnoreError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
IgnoreFailure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
IgnoreNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
IgnorePragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
ignoreStandardRealVector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568
IgnoreSVAError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
IgnoreSVAFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
IgnoreSVAInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
IgnoreSVAWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
IgnoreVitalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573
IgnoreWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
ImmediateContinuousAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
IncludeRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
InitOutCompositeParam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
IterationLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
LargeObjectSilent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
LargeObjectSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
LibrarySearchPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
MaxReportRhsCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583
MaxReportRhsSVCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
MaxSVCoverpointBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
MaxSVCoverpointBinsInst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
MaxSVCrossBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
MaxSVCrossBinsInst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
MessageFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
MessageFormatBreak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
MessageFormatBreakLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
MessageFormatError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
MessageFormatFail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
MessageFormatFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
MessageFormatNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
MessageFormatWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
MixedAnsiPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
modelsim_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
MsgLimitCount. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
msgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
mtiAvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
mtiOvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
mtiPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
mtiUPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
mtiUvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
MultiFileCompilationUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
MvcHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
NoCaseStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
NoDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
NoDeferSubpgmCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
NoIndexCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
NoOthersStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
NoRangeCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
NoVital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
NoVitalCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
NumericStdNoWarnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
OldVHDLConfigurationVisibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
OldVhdlForGenNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
OnFinish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
OnFinishPendingAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Optimize_1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
osvvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
ParallelJobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
PathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
PedanticErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
PliCompatDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
PreserveCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
PrintSimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
PrintSVPackageLoadingAttribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
PslOneAttempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
PslInfinityThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
RequireConfigForAllDefaultBinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
RunLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Sc22Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
ScalarOpts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
SccomLogfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
SccomVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
ScEnableScSignalWriteCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
ScMainFinishOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
ScMainStackSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
ScStackSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
ScShowIeeeDeprecationWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
ScTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
ScvPhaseRelationName . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
SeparateConfigLibrary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Show_BadOptionWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Show_Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Show_PslChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Show_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Show_VitalChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Show_Warning1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Show_Warning2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Show_Warning3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
Show_Warning4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Show_Warning5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
ShowConstantImmediateAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
ShowFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
ShowUnassociatedScNameWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
ShowUndebuggableScTypeWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
ShutdownFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
SignalForceFunctionUseDefaultRadix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
SignalSpyPathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
SimulateAssumeDirectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
SimulateImmedAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
SimulatePSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
SimulateSVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
SmartDbgSym. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
SolveACTMaxOps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
SolveACTMaxTests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
SolveACTRetryCount. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
SolveArrayResizeMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
SolveBeforeErrorSeverity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
SolveEngine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
SolveFailDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
SolveFailDebugMaxSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
SolveFailSeverity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
SolveGraphMaxEval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
SolveGraphMaxSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
SolveIgnoreOverflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683
SolveRev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
SolveTimeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
SparseMemThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
StackTraceDepth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
Stats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689
std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
std_developerskit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
StdArithNoWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
suppress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694
SuppressFileTypeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
Sv_Seed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
sv_std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
SVAPrintOnlyUserMessage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
SVCovergroupGetInstCoverageDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
SVCovergroupGoal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
SVCovergroupGoalDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
SVCovergroupMergeInstancesDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
SVCovergroupPerInstanceDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
SVCovergroupSampleInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
SVCovergroupStrobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
SVCovergroupStrobeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
SVCovergroupTypeGoal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
SVCovergroupTypeGoalDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
SVCovergroupZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
SVCoverpointAutoBinMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
SVCoverpointExprVariablePrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
SVCoverpointWildCardBinValueSizeWarn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
SVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
SVCrossNumPrintMissingDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
SvExtensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
SVFileSuffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Svlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
SVPrettyPrintFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
SvRandExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
SyncCompilerFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
ToggleCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
ToggleDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
ToggleFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
ToggleMaxFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
ToggleMaxIntValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
ToggleMaxRealValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
ToggleNoIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
TogglePackedAsVec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
TogglePortsOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
ToggleVHDLRecords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
ToggleVlogEnumBits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
ToggleVlogIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
ToggleVlogReal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
ToggleWidthLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
TranscriptFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
UCDBFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
UCDBTestStatusMessageFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
UdpCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
UnattemptedImmediateAssertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
UnbufferedOutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
UndefSyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
UpCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
UserTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
UseScv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
UseSVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
UseUvmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
UVMControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
Veriuser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
VHDL93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
VhdlSeparatePduPackage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
VhdlVariableLogging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
vital2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
vlog95compat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
VoptFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
WarnConstantChange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
WaveSignalNameWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
WildcardFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
WildcardSizeThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
WildcardSizeThresholdVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
WLFCacheSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
WLFCollapseMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
WLFCompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
WLFDeleteOnQuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
WLFFileLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
WLFFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
WLFOptimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
WLFSaveAllRegions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773
WLFSimCacheSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
WLFSizeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775
WLFTimeLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
WLFUpdateInterval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
WLFUseThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
WrapColumn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
WrapMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
WrapWSColumn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
XpropAssertionLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
Commonly Used modelsim.ini Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Common Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Hierarchical Library Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
Creating a Transcript File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
Using a Startup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Turn Off Assertion Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Turn Off Warnings from Arithmetic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
Force Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
Restart Command Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
VHDL Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
Delay Opening VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
2. Right-click on the modelsim.ini file and choose Properties from the popup menu. This
displays the modelsim.ini Properties dialog box.
3. Uncheck the Attribute: Read-only.
4. Click OK.
5. To protect the modelsim.ini file after making changes, repeat the preceding steps, but at
Step 3, check the Read-only attribute.
<variable> = <value>
Procedure
1. Open the modelsim.ini file with a text editor.
2. Find the variable you want to edit in the appropriate section of the file.
3. Type the new value for the variable after the equal ( = ) sign.
4. If the variable is commented out with a semicolon ( ; ) remove the semicolon.
5. Save.
Note
Reading and setting Tcl variable values is detailed in “Reading Variable Values
From the INI File”.
Procedure
1. Open the modelsim.ini file with a text editor.
2. Make changes to the modelsim.ini variables.
3. Save the file with an alternate name to any directory.
4. After start up of the tool, specify the -modelsimini <ini_filepath> switch with one of the
following commands:
Variables
The modelsim.ini variables are listed in order alphabetically. The following information is given
for each variable.
• A short description of how the variable functions.
• The location of the variable, by section, in the modelsim.ini file.
• The syntax for the variable.
• A listing of all values and the default value where applicable.
• Related arguments that are entered on the command line to override variable settings.
Commands entered at the command line always take precedence over modelsim.ini
settings. Not all variables have related command arguments.
• Related topics and links to further information about the variable.
AcceptLowerCasePragmaOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
AccessObjDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
AddPragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
AmsStandard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
AppendClose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
AssertFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
AssertionActiveThreadMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
AssertionActiveThreadMonitorLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
AssertionCover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
AssertionDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
AssertionEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
AssertionEnableVacuousPassActionBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
AssertionFailAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
AssertionFailLocalVarLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
AssertionFailLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
AssertionLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
AssertionPassLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
AssertionThreadLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
AssertionThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
ATVStartTimeKeepCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
AutoExclusionsDisable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
AutoLibMapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
BatchMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
BatchTranscriptFile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
BindAtCompile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
BreakOnAssertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
CheckPlusargs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
CheckpointCompressMode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
CheckSynthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
ClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
CodeCoverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
CodeLinkAutoLoad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
CommandHistory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
CompilerTempDir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
ConcurrentFileLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
CoverAtLeast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
CoverCells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
CoverClkOptBuiltins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
CoverConstruct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
CoverCountAll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
CoverDeglitchOn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
CoverDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
CoverEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
CoverExcludeDefault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
CoverFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
CoverLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
CoverLog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
CoverMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
CoverOpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
CoverREC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
CoverRespectHandL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
CoverReportCancelled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
CoverShortCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
CoverSub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
CoverThreadLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
CoverThreadLimitAction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
CoverUDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
CoverWeight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
CppInstall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
CppOptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
CppPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
CreateDirForFileAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
CreateLib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
CvgZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
DatasetSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
DefaultForceKind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
DefaultLibType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
DefaultRadix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
DefaultRadixFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
DefaultRestartOptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
DelayFileOpen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527
displaymsgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
DpiCppPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
DpiOutOfTheBlue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
DumpportsCollapse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
EmbeddedPsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
EnableDpiSosCb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
EnableSVCoverpointExprVariable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
EnableTypeOf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
EnumBaseInit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
ErrorFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
Explicit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
ExtendedToggleMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
fatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
FecCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
FecUdpEffort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
FlatLibPageSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
FlatLibPageDeletePercentage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
FlatLibPageDeleteThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
floatfixlib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
ForceSigNextIter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
ForceUnsignedIntegerToVHDLInteger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
FsmImplicitTrans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
FsmResetTrans. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
FsmSingle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
FsmXAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
GCThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
GCThresholdClassDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
GenerateFormat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
GenerateLoopIterationMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
GenerateRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
GenerousIdentifierParsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
GlobalSharedObjectList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
GlobalSharedObjectsList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Hazard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
ieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
IgnoreError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
IgnoreFailure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
IgnoreNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
IgnorePragmaPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
ignoreStandardRealVector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568
IgnoreSVAError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569
IgnoreSVAFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
IgnoreSVAInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
IgnoreSVAWarning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
IgnoreVitalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573
IgnoreWarning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
ImmediateContinuousAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
IncludeRecursionDepthMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
InitOutCompositeParam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
IterationLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
LargeObjectSilent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
LargeObjectSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
LibrarySearchPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
License. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
MaxReportRhsCrossProducts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583
MaxReportRhsSVCrossProducts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
MaxSVCoverpointBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
MaxSVCoverpointBinsInst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
MaxSVCrossBinsDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
MaxSVCrossBinsInst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
MessageFormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
MessageFormatBreak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
MessageFormatBreakLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
MessageFormatError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
MessageFormatFail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
MessageFormatFatal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
MessageFormatNote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
MessageFormatWarning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
MixedAnsiPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
modelsim_lib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
MsgLimitCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
msgmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
mtiAvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
mtiOvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
mtiPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
mtiUPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
mtiUvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
MultiFileCompilationUnit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
MvcHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
NoCaseStaticError. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
NoDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
NoDeferSubpgmCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
NoIndexCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
NoOthersStaticError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
NoRangeCheck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
NoVital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
NoVitalCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
NumericStdNoWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
OldVHDLConfigurationVisibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
OldVhdlForGenNames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
OnFinish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
OnFinishPendingAssert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Optimize_1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
osvvm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
ParallelJobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
PathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
PedanticErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
PliCompatDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
PreserveCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
PrintSimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
PrintSVPackageLoadingAttribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
PslOneAttempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
PslInfinityThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
RequireConfigForAllDefaultBinding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
RunLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Sc22Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
ScalarOpts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
SccomLogfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
SccomVerbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
ScEnableScSignalWriteCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
ScMainFinishOnQuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
ScMainStackSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
ScStackSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
ScShowIeeeDeprecationWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
ScTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
ScvPhaseRelationName . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
SeparateConfigLibrary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Show_BadOptionWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
Show_Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Show_PslChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Show_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Show_VitalChecksWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Show_Warning1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Show_Warning2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Show_Warning3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
Show_Warning4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Show_Warning5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
ShowConstantImmediateAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
ShowFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
ShowUnassociatedScNameWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
ShowUndebuggableScTypeWarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
ShutdownFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
SignalForceFunctionUseDefaultRadix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
SignalSpyPathSeparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
SimulateAssumeDirectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
SimulateImmedAsserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
SimulatePSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
SimulateSVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
SmartDbgSym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
SolveACTMaxOps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
SolveACTMaxTests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
SolveACTRetryCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
SolveArrayResizeMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
SolveBeforeErrorSeverity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
SolveEngine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
SolveFailDebug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
SolveFailDebugMaxSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
SolveFailSeverity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
SolveGraphMaxEval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
SolveGraphMaxSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
SolveIgnoreOverflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683
SolveRev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
SolveTimeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
SparseMemThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
StackTraceDepth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
Stats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689
std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
std_developerskit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
StdArithNoWarnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
suppress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694
SuppressFileTypeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
Sv_Seed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
sv_std. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
SVAPrintOnlyUserMessage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
SVCovergroupGetInstCoverageDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
SVCovergroupGoal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
SVCovergroupGoalDefault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
SVCovergroupMergeInstancesDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
SVCovergroupPerInstanceDefault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
SVCovergroupSampleInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
SVCovergroupStrobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
SVCovergroupStrobeDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
SVCovergroupTypeGoal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
SVCovergroupTypeGoalDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
SVCovergroupZWNoCollect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
SVCoverpointAutoBinMax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
SVCoverpointExprVariablePrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
SVCoverpointWildCardBinValueSizeWarn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
SVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
SVCrossNumPrintMissingDefault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
SvExtensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
SVFileSuffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Svlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
SVPrettyPrintFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
SvRandExtensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
SyncCompilerFiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
ToggleCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
ToggleDeglitchPeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
ToggleFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
ToggleMaxFixedSizeArray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
ToggleMaxIntValues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
ToggleMaxRealValues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
ToggleNoIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
TogglePackedAsVec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
TogglePortsOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
ToggleVHDLRecords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
ToggleVlogEnumBits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
ToggleVlogIntegers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
ToggleVlogReal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
ToggleWidthLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
TranscriptFile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
UCDBFilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
UCDBTestStatusMessageFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
UdpCountLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
UnattemptedImmediateAssertions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
UnbufferedOutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
UndefSyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
UpCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
UserTimeUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
UseScv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
UseSVCrossNumPrintMissing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
UseUvmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
UVMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
Veriuser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
VHDL93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
VhdlSeparatePduPackage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
VhdlVariableLogging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
vital2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
vlog95compat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
VoptFlow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
WarnConstantChange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
WaveSignalNameWidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
WildcardFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
WildcardSizeThreshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
WildcardSizeThresholdVerbose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
WLFCacheSize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
WLFCollapseMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
WLFCompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
WLFDeleteOnQuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
WLFFileLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
WLFFilename. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
WLFOptimize. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
WLFSaveAllRegions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773
WLFSimCacheSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
WLFSizeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775
WLFTimeLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
WLFUpdateInterval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
WLFUseThreads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
WrapColumn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
WrapMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
WrapWSColumn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
XpropAssertionLimit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
AcceptLowerCasePragmaOnly
Section [vlog]
This variable instructs the Verilog compiler to accept only lower case pragmas in Verilog
source files.
Syntax
AcceptLowerCasePragmaOnly = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vlog -lowercasepragma.
AccessObjDebug
Section [vsim]
This variable enables logging a VHDL access variable—both the variable value and any access
object that the variable points to during the simulation.
Syntax
AccessObjDebug = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim-accessobjdebug or
-noaccessobjdebug.
Description
Display-only names such as [10001] take on a different form, as follows:
By default, this variable is turned off. This means that while access variables themselves can be
logged and displayed in the various display windows, any access objects that they point to will
not be logged. The value of an access variable, which is the “name” of the access object it points
to, is suitable only for displaying, and cannot be used as a way for a command to reference it.
For example, for an access variable “v1” that designates some access object, the value of “v1”
will show as [10001]. This name cannot be used as input to any command that expects an object
name, it is for display only; but it is a unique identifier for any access object that the design may
produce. This value replaces any hexadecimal address-based 'value' that may have been
displayed in prior versions of Questa SIM.
AddPragmaPrefix
Section [vcom], [vlog]
This variable enables recognition of synthesis and coverage pragmas with a user specified
prefix. If this argument is not specified, pragmas are treated as comments and the previously
excluded statements included in the synthesized design. All regular synthesis and coverage
pragmas are honored.
Syntax
AddPragmaPrefix = <prefix>
Arguments
• The arguments are described as follows:
o <prefix> — Specifies a user defined string where the default is no string, indicated
by quotation marks ("").
AmsStandard
Section [vcom]
This variable specifies whether vcom adds the declaration of REAL_VECTOR to the
STANDARD package. This is useful for designers using VHDL-AMS to test digital parts of
their model.
Syntax
AmsStandard = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom {-amsstd | -noamsstd}.
Related Topics
MGC_AMS_HOME and the vcom command.
Setting Environment Variables
AppendClose
Section [vsim]
This variable immediately closes files previously opened in the APPEND mode as soon as there
is either an explicit call to file_close, or when the file variable's scope is closed. You can
override this variable by specifying vsim -noappendclose at the command line.
Syntax
AppendClose = {0 | 1}
Arguments
• The arguments are described as follows:
o 0
Off
o 1
(default) On
When set to zero, the simulator will not immediately close files opened in the
APPEND mode. Subsequent calls to file_open in APPEND mode will therefore not
require operating system interaction, resulting in faster performance. If your designs
rely on files to be closed and completely written to disk following calls to file_close,
because they perform operations on the files outside the simulation, this
enhancement could adversely impact those operations. In those situations, turning
this variable on is not recommended.
AssertFile
This variable specifies an alternative file for storing VHDL/PSL/SVA assertion messages.
Syntax
AssertFile = <filename>
Arguments
• The arguments are described as follows:
o <filename> — Any valid file name containing assertion messages, where the default
name is assert.log.
You can override this variable by specifying vsim-assertfile.
Description
By default, assertion messages are output to the file specified by the TranscriptFile variable in
the modelsim.ini file. If the AssertFile variable is specified, all assertion messages will be stored
in the specified file, not in the transcript.
Related Topics
TranscriptFile
Creating a Transcript File
AssertionActiveThreadMonitor
Section [vsim]
This variable enables tracking of currently active assertion threads for a given instance.
Syntax
AssertionActiveThreadMonitor = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Tracking is disabled.
o 1 — (default) Tracking is enabled.
Related Topics
Using the Assertion Active Thread Monitor
AssertionActiveThreadMonitorLimit
Section [vsim]
This variable limits the number of active assertion threads displayed for a given instance.
Syntax
AssertionActiveThreadMonitorLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer, where 5 is the default.
Related Topics
Using the Assertion Active Thread Monitor
AssertionCover
Section [vsim]
This variable enables extended count information for assertions.
Syntax
AssertionCover = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -assertcover or -noassertcover at
the command line.
AssertionDebug
Section [vsim]
This variable specifies that assertion passes are reported and enables debug options such as
assertion thread viewing (ATV), HDL failed expression analysis, extended count information,
and causality traceback.
Syntax
AssertionDebug = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -assertdebug or -noassertdebug at
the command line.
Related Topics
Analyzing Assertion Failures in the Assertion Debug Pane of the Wave Window
AssertionEnable
Section [vsim]
This variable enables VHDL/PSL/SVA assertions.
Syntax
AssertionEnable = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying assertion enable -off.
Passes and failures cannot be enabled or disabled independently. So if
AssertionEnable is used, both passes and failures are enabled or disabled.
AssertionEnableVacuousPassActionBlock
Section [vsim]
This variable enables execution of assertion pass actions for vacuous passes in action blocks.
Syntax
AssertionEnableVacuousPassActionBlock = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You may override this variable, when it is turned on (1), by specifying assertion
action
-actionblock vacuousoff.
AssertionFailAction
Section [vsim]
This variable sets an action for a PSL/SVA failure event.
Syntax
AssertionFailAction = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — (default) Continue
o 1 — Break
o 2 — Exit
You can override this variable by specifying assertion fail -action.
AssertionFailLocalVarLog
Section [vsim]
This variable prints SVA concurrent assertion local variable values corresponding to failed
assertion threads when you run vsim -assertdebug.
Syntax
AssertionFailLocalVarLog = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying assertion fail -lvlog.
AssertionFailLog
Section [vsim]
This variable enables transcript logging for PSL assertion failure events.
Syntax
AssertionFailLog = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying assertion fail -log.
AssertionLimit
Section [vsim]
This variable sets a limit for the number of times Questa SIM responds to a VHDL/PSL/SVA
assertion failure event. Questa SIM disables an assertion after reaching the limit.
Syntax
AssertionLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is -1 (unlimited).
You can override this variable by specifying assertion fail -limit.
AssertionPassLog
Section [vsim]
This variable enables logging of SystemVerilog and PSL assertion pass events.
Syntax
AssertionPassLog = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying assertion pass -log.
AssertionThreadLimit
Section [vsim]
This variable sets a limit on the number of threads logged for each assertion. If the number of
threads logged for an assert directive exceeds the limit, the assertion is either killed or switched
off as specified by the AssertionThreadLimitAction variable.
Syntax
AssertionThreadLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is -1 (unlimited hits)
Related Topics
AssertionThreadLimitAction
AssertionThreadLimitAction
Section [vsim]
This variable controls the action taken once the assert limit set by the AssertionThreadLimit
variable has been reached.
Syntax
AssertionThreadLimitAction = {kill | off}
Arguments
• The arguments are described as follows:
o kill — (default) All existing threads for an assertion are terminated and no new
instances of the assertion are started.
o off — All current assertions and threads are kept but no new instances of the
assertion are started. Existing instances of the assertion continue to be evaluated and
generate threads.
Related Topics
AssertionThreadLimit
assertion enable
ATVStartTimeKeepCount
Section [vsim]
This variable controls how many thread start times will be preserved for ATV viewing for a
given assertion instance.
Syntax
ATVStartTimeKeepCount = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative number where the default is -1 (all).
AutoExclusionsDisable
Section [vsim]
This variable is used to control automatic code coverage exclusions. By default, assertions and
FSMs are excluded from the code coverage. For FSMs, all transitions to and from excluded
states are also automatically excluded. When “all” is selected, code coverage is enabled for both
assertions and FSMs.
Syntax
AutoExclusionsDisable = {assertions | fsm | all}
Arguments
• The arguments are described as follows:
o assertions — Enable code coverage for assertions.
o fsm — Enable code coverage for FSMs.
o all — Enable code coverage for all automatic exclusions.
To enable multiple values, use a comma or space separated list.
You can override this variable by specifying vsim -autoexclusionsdisable.
AutoLibMapping
Section [Library]
Automatically perform logical-to-physical mapping for physical libraries that appear in -L/-Lf
options with file system path delimiters (e.g. '.' or '/'). The tail of the file system path name will
be the logical library name.
Syntax
AutoLibMapping = {0 | 1}
Arguments
• The arguments are:
0 — (default) Off
1 — On
Examples
In the command:
This implicit mapping will occur as long as there is no other logical library present with a
matching name (lib1 in this case). Any implicit mapping which does not occur for any reason is
flagged with a suppressible “Note.”
BatchMode
Section [vsim]
This variable runs batch (non-GUI) simulations. The simulations are executed via scripted files
from a Windows command prompt or UNIX terminal and do not provide for interaction with
the design during simulation. The BatchMode variable will be ignored if you use the -batch, -c,
-gui, or -i options to vsim. Refer to BatchMode for more information about running batch
simulations.
Syntax
BatchMode = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Runs the simulator in interactive mode. Refer to vsim -i for more
information.
o 1 — Enables batch simulation mode.
You can also enable batch mode by specifying vsim -batch.
Related Topics
Batch Mode
BatchTranscriptFile
TranscriptFile
vsim
BatchTranscriptFile
Section [vsim]
This variable enables automatic creation of a transcript file when the simulator runs in batch
mode. All transcript data is sent to stdout when this variable is disabled and the simulator is run
in batch mode (BatchMode = 1, or vsim -batch).
Syntax
BatchTranscriptFile = <filename>
Arguments
• The arguments are described as follows:
o <filename> — Any string representing a valid filename where the default is
transcript.
You can override this variable by specifying vsim -logfile <filename>, vsim -nolog.
Related Topics
Batch Mode
BatchMode
TranscriptFile
transcript file
vsim
BindAtCompile
Section [vcom]
This variable instructs Questa SIM to perform VHDL default binding at compile time rather
than load time.
Syntax
BindAtCompile = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom {-bindAtCompile |
-bindAtLoad}.
Related Topics
Default Binding
RequireConfigForAllDefaultBinding
BreakOnAssertion
Section [vsim]
This variable stops the simulator when the severity of a VHDL assertion message or a
SystemVerilog severity system task is equal to or higher than the value set for the variable.
Syntax
BreakOnAssertion = {0 | 1 | 2 | 3 | 4}
Arguments
• The arguments are described as follows:
o 0 — Note
o 1 — Warning
o 2 — Error
o 3 — (default) Failure
o 4 — Fatal
Related Topics
The Runtime Options Dialog
Tcl Command Syntax
CheckPlusargs
Section [vsim]
This variable defines the simulator’s behavior when encountering unrecognized plusargs. The
simulator checks the syntax of all system-defined plusargs to ensure they conform to the syntax
defined in the Reference Manual. By default, the simulator does not check syntax or issue
warnings for unrecognized plusargs (including accidentally misspelled, system-defined
plusargs), because there is no way to distinguish them from a user-defined plusarg.
Syntax
CheckPlusargs = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — (default) Ignore
o 1 — Issues a warning and simulates while ignoring.
o 2 — Issues an error and exits.
CheckpointCompressMode
Section [vsim]
This variable specifies that checkpoint files are written in compressed format.
Syntax
CheckpointCompressMode = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Related Topics
set Command Syntax
CheckSynthesis
Section [vcom]
This variable turns on limited synthesis rule compliance checking, which includes checking
only signals used (read) by a process and understanding only combinational logic, not clocked
logic.
Syntax
CheckSynthesis = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -check_synthesis.
ClassDebug
Section [vsim]
This variable enables visibility into and tracking of class instances.
Syntax
ClassDebug = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -classdebug.
CodeCoverage
Section [vsim]
This variable enables code coverage.
Syntax
CodeCoverage = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
CodeLinkAutoLoad
Section [vsim]
This variable adds the contents of the $CODELINK_HOME/sim/ms.cmd file to the vsim
command line. This file contains information required by Questa Codelink during the loading of
a simulation. If you do not have $CODELINK_HOME set, a warning will be issued and the
simulation will continue.
Syntax
CodeLinkAutoLoad = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
CommandHistory
Section [vsim]
This variable specifies the name of a file in which to store the Main window command history.
Syntax
CommandHistory = <filename>
Arguments
• The arguments are described as follows:
o <filename> — Any string representing a valid filename where the default is
cmdhist.log.
The default setting for this variable is to comment it out with a semicolon ( ; ).
CompilerTempDir
Section [vcom]
This variable specifies a directory for compiler temporary files instead of “work/_temp.”
Syntax
CompilerTempDir = <directory>
Arguments
• The arguments are described as follows:
o <directory> — Any user defined directory where the default is work/_temp.
ConcurrentFileLimit
Section [vsim]
This variable controls the number of VHDL files open concurrently. This number should be less
than the current limit setting for maximum file descriptors.
Syntax
ConcurrentFileLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where 0 is unlimited and 40 is the default.
Related Topics
Syntax for File Declaration
Coverage
Section [vcom], [vlog]
This variable enables coverage statistic collection.
Syntax
Coverage = {0 | s | b | c| e | f | t}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o s — statement
o b— branch
o c — condition
o e — expression
o f — fsm
o t — toggle
CoverAtLeast
Section [vsim]
This variable specifies the minimum number of times a functional coverage directive must
evaluate to true.
Syntax
CoverAtLeast = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 1.
CoverCells
Section [vlog]
This variable enables code coverage of Verilog modules defined by `celldefine and
`endcelldefine compiler directives.
Syntax
CoverCells = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vlog or vopt {-covercells
|-nocovercells}.
Related Topics
Verilog-XL Compatible Compiler Arguments
CoverClkOptBuiltins
Section [vcom]
This variable enables clock optimization builtins for code coverage. When these clock
optimizations are enabled, some branches of VHDL code may be excluded from code coverage,
and given a code of ECOP (when not hit).
Syntax
CoverClkOptBuiltins = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Description
Refer to“Missing Branches in VHDL and Clock Optimizations” for more details.
CoverConstruct
Section [vopt]
This variable controls the set of HDL cover constructs that will be considered for coverage
collection.
Syntax
CoverConstruct = <argument>
Arguments
• bind, cafif, cafcase, cdcase, cicl, cifl, citf, cpkg, cpm, cprc, csva, ctes, fsmqs, fsmqs, fsmup,
tce, tcint, tcpmda, tcua, tcuu, tcpu
The arguments listed here are mnemonics for particular HDL code constructs. The list is not
comprehensive and can include other options. The default for each mnemonic is “on.” To
turn the construct off, place “no” before the mnemonic: as in nofsmup.
Description
Cover constructs are a comma-separated list of mnemonics that designate particular HDL code
constructs that may be instrumented for coverage collection. The CoverConstruct modelsim.ini
variable may be overridden with the vopt -coverconstruct command.
Examples
Cover constructs are named by mnemonic abbreviations. For example, the CoverConstruct
“condition coverage inside a task or function” is abbreviated with the mnemonic “citf”, and the
coverage of packages is "cpkg". Both mnemonics are designated with the CoverConstruct
variable as follows:
CoverConstruct nocpkg
Related Topics
CoverMode
Code Coverage Modes
Coverconstructs
CoverCountAll
Section [vsim]
This variable applies to condition and expression coverage UDP tables. Thus, it has no effect
unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. If this variable is turned
off (0) and a match occurs in more than one row, none of the counts for all matching rows is
incremented. By default, counts are incremented for all matching rows.
Syntax
CoverCountAll = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -covercountnone.
Related Topics
Verilog-XL Compatible Compiler Arguments
CoverDeglitchOn
Section [vcom], [vlog]
This variable enables deglitching of statement, branch, condition, and expression code coverage
in combinatorial, non-clocked processes.
Syntax
CoverDeglitchOn = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
CoverDeglitchPeriod
Section [vcom], [vlog]
This variable controls the period of statement, branch, condition, and expression code coverage
deglitching in combinatorial, non-clocked processes. If a process is entered more than once
during any period of length <period>, only the last execution during that period will be added
into the coverage data for that process. For a new pass to be counted, it must occur at a time
greater than the previous pass plus the deglitch period.
Syntax
CoverDeglitchPeriod = {“<n> <time_unit>”}
Arguments
• The arguments are described as follows:
o <n> — A string specifying the number of time units. A value of zero ( 0 ) eliminates
delta cycle glitches: only the last delta cycle pass will be counted toward the
coverage data.
o <time_unit> — (required if “n” is anything other than “0”) fs, ps, ns, us, ms, or sec.
You must surround n <time_unit> with quotation marks (“ “) when you put a space
between “n” and <time_unit>.
CoverEnable
Section [vsim]
This variable specifies that all PSL/SVA coverage directives in the current simulation are
enabled.
Syntax
CoverEnable = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
CoverExcludeDefault
Sections [vcom], [vlog]
This variable excludes VHDL code coverage data collection from the OTHERS branch in both
Case statements and Selected Signal Assignment statements.
Syntax
CoverExcludeDefault = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
CoverFEC
Sections [vcom], [vlog]
This variable controls the collection of code coverage for focused expression and condition
coverage statistics.
Syntax
CoverFEC = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom, vlog, or vopt -coverfec.
CoverLimit
Section [vsim]
This variable specifies the number of cover directive hits before the directive is auto disabled.
Syntax
CoverLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is -1 (unlimited hits).
CoverLog
Section [vsim]
This variable enables transcript logging for functional coverage directive messages.
Syntax
CoverLog = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off (default)
o 1 — On
CoverMode
Section [vopt]
This variable controls the set of cover constructs that are being considered for coverage
collection.
Syntax
CoverMode = <argument>
Arguments
• full, default, set1, set2, fast
The default CoverMode set (the current behavior) is default. Other CoverModes – full, set1,
set2, and fast – differ from the default CoverMode and are essentially synonyms for sets of
enabled CoverConstructs. You can think of CoverMode as a shortcut for a specific list of
CoverConstruct mnemonics.
Description
The CoverMode modelsim.ini variable may be overridden with the vopt -covermode command.
Related Topics
CoverConstruct
Code Coverage Modes
Covermodes
CoverOpt
Section [vcom], [vlog]
This variable controls the default level of optimizations for compilations with code coverage.
Syntax
CoverOpt = {0 | 1 | 2 | 3 | 4 | 5}
Arguments
• The arguments are described as follows:
o 0 — Turns off Verilog module inlining and VHDL arch lining.
o 1 — Turns off continuous assignment optimizations and clock suppression.
o 2 — Turn off expression optimization, converint primitives to continuous
assignment, VHDL subprogram inlining and VHDL clkOpt (converting FF’s to
builtins).
o 3 — (default) Turns off process, always block and if statement merging.
o 4 — Turns off removal of unreferenced code.
o 5 — Turns on all allowable optimizations, 0 - 4.
You can override this variable by specifying the vcom, vlog, or vopt command with
the -coveropt argument.
Note
If fsm coverage is turned on, optimizations are forced to level 3 and conversion
of primitives to continuous assigns is turned off.
Related Topics
vlog
CoverREC
Sections [vcom], [vlog]
This variable controls the collection of code coverage for rapid expression and condition
coverage statistics. Disabling (0) REC collection converts non-masking conditions in FEC
tables to matching input patterns.
Syntax
CoverREC = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vcom, vlog, or vopt -nocoverrec.
Description
Refer to Legacy FEC Reporting for more information on the new REC-style reports vs. old style
FEC reports.
CoverRespectHandL
Section: [vcom]
This variable specifies whether you want the VHDL 'H' and 'L' input values on conditions and
expressions to be automatically converted to ‘1’ and ‘0’, respectively.
Syntax
CoverRespectHandL = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — On.
o 1 — (default) Off. H and L values are not automatically converted.
If you are not using 'H' and 'L' values and do not want the additional UDP rows that
are difficult to cover—you can:
• Change your VHDL expressions of the form (a = '1') to (to_x01(a) = '1') or to
std_match(a,'1'). These functions are recognized and used to simplify the UDP
tables.
• Override this variable by specifying vcom -nocoverrespecthandl.
CoverReportCancelled
Section [vcom], [vlog], [vopt]
This variable Enables code coverage reporting of branch conditions that have been optimized
away due to a static or null condition. The line of code is labeled EA in the Source Window and
EBCS in the hits column in a Coverage Report.
Syntax
CoverReportCancelled = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Do not report code that has been optimized away.
o 1 — Enable code coverage reporting of code that has been optimized away.
CoverShortCircuit
Sections [vcom], [vlog]
This variable enables short-circuiting of expressions when coverage is enabled.
Syntax
CoverShortCircuit = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying either the vcom or vlog command with
the -nocovershort argument.
CoverSub
Section [vcom]
This variable controls the collection of code coverage statistics in VHDL subprograms.
Syntax
CoverSub = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
CoverThreadLimit
Section [vsim]
This variable sets a limit on the number of threads logged for each cover directive. If the
number of threads logged for a cover directive exceeds the limit, the assertion is either killed or
switched off as specified by the CoverThreadLimitAction variable.
Syntax
CoverThreadLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is -1 (unlimited hits)
Related Topics
CoverThreadLimitAction
CoverThreadLimitAction
Section [vsim]
This variable controls the action taken once the cover directive limit set by the
CoverThreadLimit variable has been reached.
Syntax
AssertionThreadLimitAction = {kill | off}
Arguments
• The arguments are described as follows:
o kill — (default) All existing threads for an assertion are terminated and no new
instances of the assertion are started.
o off — All current assertions and threads are kept but no new instances of the
assertion are started. Existing instances of the assertion continue to be evaluated and
generate threads.
Related Topics
CoverThreadLimit
assertion enable
CoverUDP
Sections [vcom], [vlog]
This variable controls the collection of code coverage for UDP expression and condition
coverage statistics. By default, UDP coverage is not collected when expression and/or condition
coverage is active, and can be enabled on a select basis using the vcom/vlog/vopt -coverudp
argument.
Syntax
CoverUDP = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
CoverWeight
Section [vsim]
This variable specifies the relative weighting for functional coverage directives.
Syntax
CoverWeight = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer, where the default is 1.
CppInstall
Section [sccom] [vopt] [vsim]
This variable specifies the version of the desired GNU compiler supported and distributed by
Questa SIM, such as with the entry:
Syntax
CppInstall = <(gcc|g++) version>
Arguments
• The arguments are described as follows:
o <version> — Any version of a GNU compiler that is supported and distributed with
Questa SIM. See Supported Platforms and Compiler Versions for details.
Description
CppInstall = 4.5.0
Use this variable to set an alternate GNU compiler, other than the default one.
CppOptions
Section [sccom]
This variable adds any specified C++ compiler options to the sccom command line at the time
of invocation.
Syntax
CppOptions = <options>
Arguments
• The arguments are described as follows:
o <options> — Any normal C++ compiler options where the default is -g (enable
source debugging).
You turn this variable off by commenting the variable line in the modelsim.ini file.
Related Topics
sccom
CppPath
Section [sccom] [vopt] [vsim]
This variable should point directly to the location of the g++ executable, such as:
Syntax
CppPath = <path>
Arguments
• The arguments are described as follows:
o <path> — The path to the g++ executable.
Description
CppPath = /usr/bin/g+
This variable is not required when running SystemC designs. By default, you should install and
use the built-in g++ compiler that comes with Questa SIM.
CreateDirForFileAccess
Section [vsim]
This variable controls whether the Verilog system task $fopen or vpi_mcd_open() will create a
non-existent directory when opening a file in append (a), or write (w) modes.
Syntax
CreateDirForFileAccess = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
New Directory Path With $fopen
CreateLib
Section [vcom], [vlog], [vopt]
This variable enables automatic creation of missing work libraries.
Syntax
CreateLib = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Description
You can use the -nocreatelib option for the vcom, vlog, or vopt commands to override this
variable and stop automatic creation of missing work libraries (which reverts back to the 10.3x
and earlier version behavior).
CvgZWNoCollect
Section [vsim]
This variable controls coverage collection for any coverage item (coverpoint, cross, or the entire
covergroup) when 0 is assigned as its option.weight.
Syntax
CvgZWNoCollect = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Collect coverage data for zero-weight coverage items as normal.
o 1 — On. Disables collection of coverage data for the zero-weight coverage item.
Zero-weight coverage items will not be displayed in any coverage report or
contribute to any coverage score computation.
You can override this variable with the -cvgzwnocollect argument to vsim
DatasetSeparator
Section [vsim]
This variable specifies the dataset separator for fully-rooted contexts, for example:
Syntax
DatasetSeparator = <character>
Arguments
• The arguments are described as follows:
o <character> — Any character except special characters, such as backslash (\),
brackets ({}), and so forth, where the default is a colon ( : ).
Description
sim:/top
The variable for DatasetSeparator must not be the same character as the PathSeparator variable,
or the SignalSpyPathSeparator variable.
DefaultForceKind
Section [vsim]
This variable defines the kind of force used when not otherwise specified.
Syntax
DefaultForceKind = {default | deposit | drive | freeze}
Arguments
• The arguments are described as follows:
o default — Uses the signal kind to determine the force kind.
o deposit — Sets the object to the specified value.
o drive — Default for resolved signals.
o freeze — Default for unresolved signals.
You can override this variable by specifying force {-default | -deposit | -drive |
-freeze}.
Related Topics
The Runtime Options Dialog
set Command Syntax
DefaultLibType
Section [utils]
This variable determines the default type for a library created with the vlib command.
Syntax
DefaultLibType = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 - legacy library using subdirectories for design units
o 1 - archive library (deprecated)
o 2 - (default) flat library
Related Topics
vlib
DefaultRadix
Section [vsim]
This variable allows a numeric radix to be specified as a name or number. For example, you can
specify binary as “binary” or “2” or octal as “octal” or “8”.
Usage
DefaultRadix = {ascii | binary | decimal | hexadecimal | octal | symbolic | unsigned}
Arguments
• The arguments are described as follows:
o ascii — Display values in 8-bit character encoding.
o binary— Display values in binary format. You can also specify 2.
o decimal or 10 — Display values in decimal format. You can also specify 10.
o hexadecimal— (default) Display values in hexadecimal format. You can also
specify 16.
o octal — Display values in octal format. You can also specify 8.
o symbolic — Display values in a form closest to their natural format.
o unsigned — Display values in unsigned decimal format.
You can override this variable by specifying radix {ascii | binary | decimal |
hexadecimal | octal | symbolic | unsigned}, or by using the -default_radix switch
with the vsim command.
Related Topics
Changing Radix (base) for the Wave Window
The Runtime Options Dialog
set Command Syntax
DefaultRadixFlags
Section [vsim]
This variable controls the display of enumeric radices.
Syntax
DefaultRadixFlags = {" " | enumnumeric | enumsymbolic | showbase | showverbose}
Arguments
• The arguments are described as follows:
o No options. — Formats enums symbolically.
o enumnumeric — Display enums is in numeric format.
o enumsybmolic — Display enums is in symbolic format.
o showbase — (default) Display enums showing the number of bits of the vector and
the radix that was used where:
binary = b
decimal = d
hexadecimal = h
ASCII = a
time = t
For example, instead of simply displaying a vector value of “31”, a value of
“16’h31” may be displayed to show that the vector is 16 bits wide, with a
hexadecimal radix.
o showverbose — Display enums with verbose information enabled.
You can override this variable with the radix command.
DefaultRestartOptions
Section [vsim]
This variable sets the default behavior for the restart command.
Syntax
DefaultRestartOptions = {-force | -noassertions | -nobreakpoint | -nofcovers | -nolist | -nolog |
-nowave}
Arguments
• The arguments are described as follows:
o -force — Restart simulation without requiring confirmation in a popup window.
o -noassertions — Restart simulation without maintaining the current assert directive
configurations.
o -nobreakpoint — Restart simulation with all breakpoints removed.
o -nofcovers — Restart without maintaining the current cover directive
configurations.
o -nolist — Restart without maintaining the current List window environment.
o -nolog — Restart without maintaining the current logging environment.
o -nowave — Restart without maintaining the current Wave window environment.
o semicolon ( ; ) — Default is to prevent initiation of the variable by commenting the
variable line.
You can specify one or more value in a space separated list.
You can override this variable by specifying restart {-force | -noassertions |
-nobreakpoint | -nofcovers | -nolist | -nolog | -nowave}.
Related Topics
vsim
Checkpointing and Restoring Simulations
DelayFileOpen
Section [vsim]
This variable instructs Questa SIM to open VHDL87 files on first read or write, else open files
when elaborated.
Syntax
DelayFileOpen = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) On
o 1 — Off
Related Topics
set Command Syntax
displaymsgmode
Section [msg_system]
This variable controls where the simulator outputs system task messages. The display system
tasks displayed with this functionality include: $display, $strobe, $monitor, $write as well as the
analogous file I/O tasks that write to STDOUT, such as $fwrite or $fdisplay.
Syntax
displaymsgmode = {both | tran | wlf}
Arguments
• The arguments are described as follows:
o both — Outputs messages to both the transcript and the WLF file.
o tran — (default) Outputs messages only to the transcript, therefore they are
unavailable in the Message Viewer.
o wlf — Outputs messages only to the WLF file/Message Viewer, therefore they are
unavailable in the transcript.
You can override this variable by specifying vsim -displaymsgmode.
Related Topics
Message Viewer Window
DpiCppPath
Section [vsim], [vlog]
This variable specifies an explicit location to a gcc compiler for use with automatically
generated DPI export wrappers.
Syntax
DpiCppPath = <gcc_installation_directory>/bin/gcc
Arguments
• The arguments are described as follows:
o <gcc_installation_directory> — Specifies the path to the gcc compiler. Ensure that
the argument points directly to the compiler executable.
DpiOutOfTheBlue
Section [vsim]
This variable enables DPI out-of-the-blue Verilog function calls. It is also used to enable
debugging support for a SystemC thread. The C functions must not be declared as import tasks
or functions.
Syntax
DpiOutOfTheBlue = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — (default) Support for DPI out-of-the-blue calls is disabled.
o 1 — Support for DPI out-of-the-blue calls is enabled, but debugging support is not
available.
o 2 — Support for DPI out-of-the-blue calls is enabled with debugging support for a
SystemC thread.
To turn on debugging support in a SystemC method, set DpiOutOfTheBlue = 2 and
specify vsim -scdpidebug.
You can override this variable using vsim -dpioutoftheblue.
Related Topics
Making Verilog Function Calls from non-DPI C Models
DumpportsCollapse
Section [vsim]
This variable collapses vectors (VCD id entries) in dumpports output.
Syntax
DumpportsCollapse = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim {+dumpports+collapse |
+dumpports+nocollapse}.
EmbeddedPsl
Sections [vcom], [vlog]
This variable enables the parsing of embedded PSL statements in VHDL files.
Syntax
EmbeddedPsl = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
EnableDpiSosCb
Section [vsim]
Enables DPI export calls from the SystemC start_of_simualtion() callback.
Syntax
EnableDpiSosCb = {0 | 1}
Arguments
• The arguments are as follows:
0 — (default) Off
1 — On
You can override this variable by specifying vsim -enabledpisoscb.
Description
The side effect of this option is that any SystemC signal writes done in start_of_simulation()
callback will not reflect the updated value at time 0. Insert a delta cycle using a wait statement
in the processes to get the correct value updated for these signals. Also, with mixed language
simulation, process execution order may change at time 0 with this option.
EnableSVCoverpointExprVariable
Section [vlog]
This variable, used in conjunction with the SVCoverpointExprVariablePrefix variable, creates
variables containing the effective values of Coverpoint expressions. The current settings for
both expression variables are displayed in the Object view.
Note
You must re-compile your design after any change in the setting of either this variable, or
the SVCoverpointExprVariablePrefix variable.
Syntax
EnableSVCoverpointExprVariable = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
SVCoverpointExprVariablePrefix
EnableTypeOf
Section [vlog]
This variable enables support of SystemVerilog 3.1a $typeof() function. This variable has no
impact on SystemVerilog 1364-2005 designs.
Syntax
EnableTypeOf = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
EnumBaseInit
Section [vsim]
This variable initializes enum variables in SystemVerilog using either the default value of the
base type or the leftmost value.
Syntax
EnumBaseInit= {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Initialize to leftmost value
o 1 — (default) Initialize to default value of base type
error
Section [msg_system]
This variable changes the severity of the listed message numbers to “error.”
Syntax
error = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable by specifying the sccom, vcom, vlog, vopt, or vsim
command with the -error argument.
Related Topics
verror
Message Severity Level
fatal
note
suppress
warning
ErrorFile
Section [vsim]
This variable specifies an alternative file for storing error messages. By default, error messages
are output to the file specified by the TranscriptFile variable in the modelsim.ini file. If the
ErrorFile variable is specified, all error messages will be stored in the specified file, not in the
transcript.
Syntax
ErrorFile = <filename>
Arguments
• The arguments are described as follows:
o <filename> — Any valid filename where the default is error.log.
You can override this variable by specifying vsim -errorfile.
Related Topics
Creating a Transcript File
TranscriptFile
Explicit
Section [vcom]
This variable enables the resolving of ambiguous function overloading in favor of the “explicit”
function declaration (not the one automatically created by the compiler for each type
declaration). Using this variable makes Questa Sim compatible with common industry practice.
Syntax
Explicit = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -explicit.
ExtendedToggleMode
Section [vsim]
This variable specifies one of three modes for extended toggle coverage.
Syntax
ExtendedToggleMode = {1 | 2 | 3}
Arguments
• The arguments are described as follows:
o 1 — 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z')
o 2 — 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'
o 3 — (default) 0L->1H & 1H->0L & all 'Z' transitions
You can override this variable by specifying -extendedtogglemode {1|2|3} to the
vcom, vlog, vopt, or toggle add commands.
Related Topics
Understanding Toggle Counts
fatal
Section [msg_system]
This variable changes the severity of the listed message numbers to “fatal”.
Syntax
fatal = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable by specifying the sccom, vcom, vlog, vopt, or vsim
command with the -fatal argument.
Related Topics
verror
Message Severity Level
error
note
suppress
warning
FecCountLimit
Section [vsim]
This variable limits the number of counts that are tracked for Focused Expression Coverage.
Specifically, when a bin has reached the specified count, coverage will ignore further tracking
of the inputs linked to the bin.
Note
If you change this value from the default you may affect simulation performance.
Syntax
FecCountLimit = {<n> | 0 }
Arguments
• The arguments are described as follows:
o <n> — Specifies the count limit for FEC. The default is 1.
o 0 — Specifies an unlimited count
Related Topics
UdpCountLimit
FecUdpEffort
Section [vcom], [vlog], [vopt]
This variable increases or decreases the limit on the size of FEC/UDP expressions and
conditions considered for coverage. A higher FecUdpEffort value allows more expressions/
conditions to be considered for coverage, though as a result, the compile, optimization and
simulation times may increase.
Syntax
FecUdpEffort = {1 | 2 | 3}
Arguments
• The arguments are described as follows:
o 1 — (low) (Default) Only small expressions or conditions considered for coverage.
o 2 — (medium) Bigger expressions/conditions considered.
o 3 — (high) Very large expressions/conditions considered.
FlatLibPageSize
Section [utils]
This variable sets the size in bytes for flat library file pages. Very large libraries may benefit
from a larger value, at the expense of disk space.
Syntax
FlatLibPageSize = <value>
Arguments
• The arguments are described as follows:
o <value> — Specifies a library size in Mb where the default value is 8192.
FlatLibPageDeletePercentage
Section [utils]
This variable sets the percentage of total pages deleted before library cleanup can occur. This
setting is applied together with FlatLibPageDeleteThreshold.
Syntax
FlatLibPageDeletePercentage = <value>
Arguments
• The arguments are described as follows:
o <value> — Specifies a percentage where the default value is 50.
FlatLibPageDeleteThreshold
Section [utils]
Set the number of pages deleted before library cleanup can occur. This setting is applied
together with FlatLibPageDeletePercentage.
Syntax
FlatLibPageDeletePercentage = <value>
Arguments
• The arguments are described as follows:
o <value> — Specifies a percentage where the default value is 1000.
floatfixlib
Section [library]
This variable sets the path to the library containing VHDL floating and fixed point packages.
Syntax
floatfixlib = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../floatfixlib. May
include environment variables.
ForceSigNextIter
Section [vsim]
This variable controls the iteration of events when a VHDL signal is forced to a value.
Syntax
ForceSigNextIter = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Update and propagate in the same iteration.
o 1 — On. Update and propagate in the next iteration.
ForceUnsignedIntegerToVHDLInteger
Section [vlog]
This variable controls whether untyped Verilog parameters in mixed-language designs that are
initialized with unsigned values between 2*31-1 and 2*32 are converted to VHDL generics of
type INTEGER or ignored. If mapped to VHDL Integers, Verilog values greater than 2*31-1
(2147483647) are mapped to negative values. Default is to map these parameter to generic of
type INTEGER.
Syntax
ForceUnsignedIntegerToVHDLInteger = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
FsmImplicitTrans
Sections [vcom], [vlog]
This variable controls recognition of FSM Implicit Transitions.
Syntax
FsmImplicitTrans = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On. Enables recognition of implied same state transitions.
Related Topics
vcom
vlog
FsmResetTrans
Sections [vcom], [vlog]
This variable controls the recognition of asynchronous reset transitions in FSMs.
Syntax
FsmResetTrans = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Related Topics
vcom
vlog
FsmSingle
Section [vcom], [vlog]
This variable controls the recognition of FSMs with a single-bit current state variable.
Syntax
FsmSingle = { 0 | 1 }
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Related Topics
vcom
vlog
FsmXAssign
Section [vlog]
This variable controls the recognition of FSMs where a current-state or next-state variable has
been assigned “X” in a case statement.
Syntax
FsmXAssign = { 0 | 1 }
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Related Topics
vlog
GCThreshold
Section [vsim]
This variable sets the memory threshold for SystemVerilog garbage collection.
Syntax
GCThreshold = <n>
Arguments
• The arguments are described as follows:
o <n>
Any positive integer where <n> is the number of megabytes. The default is 100.
You can override this variable with the gc configure command or with vsim
-threshold.
Related Topics
Class Instance Garbage Collection
Changing the Garbage Collector Configuration
ClassDebug
Default Garbage Collector Settings
GCThresholdClassDebug
Section [vsim]
This variable sets the memory threshold for SystemVerilog garbage collection when class
debug mode is enabled with vsim -classdebug.
Syntax
GCThresholdClassDebug = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where <n> is the number of megabytes. The default is
5.
You can override this variable with the gc configure command.
Related Topics
Class Instance Garbage Collection
Changing the Garbage Collector Configuration
ClassDebug
Default Garbage Collector Settings
GenerateFormat
Section [vsim]
This variable controls the format of the old-style VHDL for … generate statement region name
for each iteration.
Syntax
GenerateFormat = <non-quoted string>
Arguments
• The arguments are described as follows:
o <non-quoted string> — The default is %s__%d. The format of the argument must
be unquoted, and must contain the conversion codes %s and %d, in that order. This
string should not contain any uppercase or backslash (\) characters.
The %s represents the generate statement label and the %d represents the generate
parameter value at a particular iteration (this is the position number if the generate
parameter is of an enumeration type). Embedded white space is allowed (but
discouraged) while leading and trailing white space is ignored. Application of the
format must result in a unique region name over all loop iterations for a particular
immediately enclosing scope so that name lookup can function properly.
Related Topics
OldVhdlForGenNames
Naming Behavior of VHDL for Generate Blocks
GenerateLoopIterationMax
Section [vopt]
This variable specifies the maximum number of iterations permitted for a generate loop;
restricting this permits the implementation to recognize infinite generate loops.
Syntax
GenerateLoopIterationMax = <n>
Arguments
• The arguments are described as follows:
o <n> — Any natural integer greater than or equal to 0, where the default is 100000.
GenerateRecursionDepthMax
Section [vopt]
This variable specifies the maximum depth permitted for a recursive generate instantiation;
restricting this permits the implementation to recognize infinite recursions.
Syntax
GenerateRecursionDepthMax = <n>
Arguments
• The arguments are described as follows:
o <n> — Any natural integer greater than or equal to 0, where the default is 200.
GenerousIdentifierParsing
Section [vsim]
Controls parsing of identifiers input to the simulator. If this variable is on (value = 1), either
VHDL extended identifiers or Verilog escaped identifier syntax may be used for objects of
either language kind. This provides backward compatibility with older .do files, which often
contain pure VHDL extended identifier syntax, even for escaped identifiers in Verilog design
regions.
Syntax
GenerousIdentifierParsing = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
GlobalSharedObjectList
Section [vopt]
This variable instructs Questa SIM to load the specified shared objects library with global
symbol visibility. Essentially, setting this variable would be required if the SystemC top is
elaborated in vopt and is depending on the symbols from a common library being loaded with
the GlobalSharedObjectsList variable for vsim (or using vsim -gblso).
Syntax
GlobalSharedObjectList = <filename>
Arguments
• The arguments are described as follows:
o <filename> — A comma separated list of filenames.
o semicolon ( ; ) — (default) Prevents initiation of the variable by commenting the
variable line.
You can override this variable by specifying vopt -gblso.
GlobalSharedObjectsList
Section [vsim]
This variable instructs Questa SIM to load the specified PLI/FLI shared objects with global
symbol visibility. Essentially, setting this variable exports the local data and function symbols
from each shared object as global symbols so they become visible among all other shared
objects. Exported symbol names must be unique across all shared objects.
Syntax
GlobalSharedObjectsList = <filename>
Arguments
• The arguments are described as follows:
o <filename> — A comma separated list of filenames.
o semicolon ( ; ) — (default) Prevents initiation of the variable by commenting the
variable line.
You can override this variable by specifying vsim -gblso.
Hazard
Section [vlog]
This variable turns on Verilog hazard checking (order-dependent accessing of global variables).
Syntax
Hazard = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
ieee
Section [library]
This variable sets the path to the library containing IEEE and Synopsys arithmetic packages.
Syntax
ieee = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path, including environment variables where the default is
$MODEL_TECH/../ieee.
IgnoreError
Section [vsim]
This variable instructs Questa SIM to disable runtime error messages.
Syntax
IgnoreError = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreFailure
Section [vsim]
This variable instructs Questa SIM to disable runtime failure messages.
Syntax
IgnoreFailure = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreNote
Section [vsim]
This variable instructs Questa SIM to disable runtime note messages.
Syntax
IgnoreNote = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnorePragmaPrefix
Section [vcom, vlog]
This variable instructs the compiler to ignore synthesis and coverage pragmas with the specified
prefix name. The affected pragmas will be treated as regular comments.
Syntax
IgnorePragmaPrefix = {<prefix> | "" }
Arguments
• The arguments are described as follows:
o <prefix> — Specifies a user defined string.
"" — (default) No string.
You can override this variable by specifying vcom -ignorepragmaprefix or vlog
-ignorepragmaprefix.
ignoreStandardRealVector
Section [vcom]
This variable instructs ModelSim to ignore the REAL_VECTOR declaration in package
STANDARD when compiling with vcom -2008. For more information refer to the
REAL_VECTOR section in Help > Technotes > vhdl2008migration technote.
Syntax
IgnoreStandardRealVector = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -ignoreStandardRealVector.
IgnoreSVAError
Section [vsim] [vopt]
This variable instructs Questa SIM to disable SystemVerilog assertion messages for Error
severity and suppresses output of elaboration system $error tasks.
Syntax
IgnoreSVAError = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreSVAFatal
Section [vsim] [vopt]
This variable instructs Questa SIM to disable SystemVerilog assertion messages for Fatal
severity (for vsim command) and suppresses output of elaboration system $fatal tasks (for vsim
and vopt commands).
Syntax
IgnoreSVAFatal = 0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. SystemVerilog assertion messages enabled.
o 1 — On. SystemVerilog assertion messages disabled.
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreSVAInfo
Section [vsim] [vopt]
This variable instructs Questa SIM to disable SystemVerilog assertion messages for Info
severity and suppresses output of elaboration system $info tasks.
Syntax
IgnoreSVAInfo = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Info severity messages enabled.
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreSVAWarning
Section [vsim] [vopt]
This variable instructs Questa SIM to disable SystemVerilog assertion messages for Warning
severity and suppresses output of elaboration system $warning tasks.
Syntax
IgnoreSVAWarning = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. SystemVerilog assertion messages for warning severity enabled.
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
IgnoreVitalErrors
Section [vcom]
This variable instructs Questa SIM to ignore VITAL compliance checking errors.
Syntax
IgnoreVitalErrors = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Allow VITAL compliance checking errors.
o 1 — On
You can override this variable by specifying vcom -ignorevitalerrors.
IgnoreWarning
Section [vsim]
This variable instructs Questa SIM to disable runtime warning messages.
Syntax
IgnoreWarning = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Enable runtime warning messages.
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
ImmediateContinuousAssign
Section [vsim]
This variable instructs Questa SIM to run continuous assignments before other normal priority
processes that are scheduled in the same iteration. This event ordering minimizes race
differences between optimized and non-optimized designs and is the default behavior.
Syntax
ImmediateContinuousAssign = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -noimmedca.
IncludeRecursionDepthMax
Section [vlog]
This variable limits the number of times an include file can be called during compilation. This
prevents cases where an include file could be called repeatedly.
Syntax
IncludeRecursionDepthMax = <n>
Arguments
• The arguments are described as follows:
o <n> — An integer that limits the number of loops. A setting of 0 would allow one
pass through before issuing an error, 1 would allow two passes, and so on.
InitOutCompositeParam
Section [vcom]
This variable controls how subprogram output parameters of array and record types are treated.
Syntax
InitOutCompositeParam = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — Use the default for the language version being compiled.
o 1 — (default) Always initialize the output parameter to its default or “left” value
immediately upon entry into the subprogram.
o 2 — Do not initialize the output parameter.
You can override this variable by specifying vcom or vopt -initoutcompositeparam.
IterationLimit
Section [vlog], [vsim]
This variable specifies a limit on simulation kernel iterations allowed without advancing time.
Syntax
IterationLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 10000000.
Related Topics
The Runtime Options Dialog
set Command Syntax
LargeObjectSilent
Section [vsim]
This variable controls whether “large object” warning messages are issued or not. Warning
messages are issued when the limit specified in the variable LargeObjectSize is reached.
Syntax
LargeObjectSilent = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) On
o 1 — Off
LargeObjectSize
Section [vsim]
This variable specifies the relative size of log, wave, or list objects in bytes that will trigger
“large object” messages. This size value is an approximation of the number of bytes needed to
store the value of the object before compression and optimization.
Syntax
LargeObjectSize = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 500000 bytes.
LibrarySearchPath
Section [vlog, vsim]
This variable specifies the location of one or more resource libraries containing a precompiled
package. The behavior of this variable is identical to specifying the -L <libname> command
line option with vlog or vsim.
Syntax
LibrarySearchPath = <variable> | <path/lib> ...
Arguments
• The arguments are described as follows:
o <variable>— Any library variable where the default is:
LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF infact
License
Section [vsim]
This variable controls the license file search.
Usage
License = <license_option>
Arguments
• The arguments are described as follows:
o <license_option> — One or more license options separated by spaces where the
default is to search all licenses.
MaxReportRhsCrossProducts
Section [vsim]
This variable specifies a maximum limit for the number of Cross (bin) products reported against
a Cross when a XML or UCDB report is generated. The warning is issued if the limit is crossed.
Syntax
MaxReportRhsCrossProducts = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 0.
MaxReportRhsSVCrossProducts
Section [vsim]
This variable limits the number of “bin_rhs” values associated with cross bins in the XML
version of the coverage report for a SystemVerilog design. It also limits the values saved to a
UCDB.
Syntax
MaxReportRhsSVCrossProducts = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 0.
MaxSVCoverpointBinsDesign
Section [vsim]
This variable limits the maximum number of Coverpoint bins allowed in the whole design.
Syntax
MaxSVCoverpointBinsDesign = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 2147483648.
MaxSVCoverpointBinsInst
Section [vsim]
This variable limits the maximum number of Coverpoint bins allowed in any instance of a
Covergroup.
Syntax
MaxSVCoverpointBinsInst = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 2147483648.
MaxSVCrossBinsDesign
Section [vsim]
This variable issues a warning when the number of Coverpoint bins in the design exceeds the
value specified by <n>.
Syntax
MaxSVCrossBinsDesign = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 2147483648.
MaxSVCrossBinsInst
Section [vsim]
This variable issues a warning when the number of Coverpoint bins in any instance of a
Covergroup exceeds the value specified by <n>.
Syntax
MaxSVCrossBinsInst = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 2147483648.
MessageFormat
Section [vsim]
This variable defines the format of VHDL/PSL/SVA assertion messages as well as normal error
messages.
Syntax
MessageFormat = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D%I\n.
MessageFormatBreak
Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA assertions that trigger a
breakpoint.
Syntax
MessageFormatBreak = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n
MessageFormatBreakLine
Section [vsim]Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA assertions that trigger a
breakpoint.
Syntax
MessageFormatBreakLine = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n
%L specifies the line number of the assertion or, if the breakpoint is from a
subprogram, the line from which the call is made.
MessageFormatError
Section [vsim]
This variable defines the format of all error messages. If undefined, MessageFormat is used
unless the error causes a breakpoint in which case MessageFormatBreak is used.
Syntax
MessageFormatError = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n
Related Topics
MessageFormatBreak
MessageFormatFail
Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA Fail assertions.
Syntax
MessageFormatFail = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n
Description
If undefined, MessageFormat is used unless assertion causes a breakpoint in which case
MessageFormatBreak is used.
Related Topics
MessageFormatBreak
MessageFormatFatal
Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA Fatal assertions.
Syntax
MessageFormatFatal = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n
Description
If undefined, MessageFormat is used unless assertion causes a breakpoint in which case
MessageFormatBreak is used.
Related Topics
MessageFormatBreak
MessageFormatNote
Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA Note assertions.
Syntax
MessageFormatNote = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D%I\n
Description
If undefined, MessageFormat is used unless assertion causes a breakpoint in which case
MessageFormatBreak is used.
Related Topics
MessageFormatBreak
MessageFormatWarning
Section [vsim]
This variable defines the format of messages for VHDL/PSL/SVA Warning assertions.
Syntax
MessageFormatWarning = <%value>
Arguments
• The arguments are described as follows:
o <%value> — One or more of the variables from Table A-6 where the default is:
** %S: %R\n Time: %T Iteration: %D%I\n
Description
If undefined, MessageFormat is used unless assertion causes a breakpoint in which case
MessageFormatBreak is used.
Related Topics
MessageFormatBreak
MixedAnsiPorts
Section [vlog]
This variable supports mixed ANSI and non-ANSI port declarations and task/function
declarations.
Syntax
MixedAnsiPorts = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vlog -mixedansiports.
modelsim_lib
Section [library]
This variable sets the path to the library containing Mentor Graphics VHDL utilities such as
Signal Spy.
Syntax
modelsim_lib = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../modelsim_lib.
May include environment variables.
MsgLimitCount
Section [msg_system]
This variable limits the number of times warning messages will be displayed. The default limit
value is five.
Syntax
MsgLimitCount = <limit_value>
Arguments
• The arguments are described as follows:
o <limit_value> — Any positive integer where the default limit value is 5.
You can override this variable by specifying vsim -msglimitcount.
Related Topics
Message Viewer Window.
msgmode
Section [msg_system]
This variable controls where the simulator outputs elaboration and runtime messages.
Syntax
msgmode = {tran | wlf | both}
Arguments
• The arguments are described as follows:
o tran — (default) Messages appear only in the transcript.
o wlf — Messages are sent to the wlf file and can be viewed in the MsgViewer.
o both — Transcript and wlf files.
You can override this variable by specifying vsim -msgmode.
Related Topics
Message Viewer Window.
mtiAvm
Section [library]
This variable sets the path to the location of the Advanced Verification Methodology libraries.
Syntax
mtiAvm = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../avm
The behavior of this variable is identical to specifying vlog -L mtiAvm.
mtiOvm
Section [library]
This variable sets the path to the location of the Open Verification Methodology libraries.
Syntax
mtiOvm = <path>
Arguments
• The arguments are described as follows:
o <path> — $MODEL_TECH/../ovm-2.1.2
The behavior of this variable is identical to specifying vlog -L mtiOvm.
mtiPA
Section [library]
This variable sets the path to the location of Power Aware libraries.
Syntax
mtiPA = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../pa_lib. May
include environment variables.
The behavior of this variable is identical to specifying vlog -L mtiPA.
mtiUPF
Section [library]
This variable sets the path to the location of Unified Power Format (UPF) libraries.
Syntax
mtiUPF = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../upf_lib. May
include environment variables.
The behavior of this variable is identical to specifying vlog -L mtiUPF.
Related Topics
Verilog Resource Libraries
VHDL Resource Libraries
mtiUvm
Section [library]
This variable sets the path to the location of the Universal Verification Methodology libraries.
Syntax
mtiUvm = <path>
Arguments
• The arguments are described as follows:
o <path> — $MODEL_TECH/../uvm-1.1d
The behavior of this variable is identical to specifying vlog -L mtiUvm.
MultiFileCompilationUnit
Section [vlog]
This variable controls whether Verilog files are compiled separately or concatenated into a
single compilation unit.
Syntax
MultiFileCompilationUnit = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Single File Compilation Unit (SFCU) mode.
o 1 — Multi File Compilation Unit (MFCU) mode.
You can override this variable by specifying vlog {-mfcu | -sfcu}.
Related Topics
SystemVerilog Multi-File Compilation
MvcHome
Section [vsim]
This variable specifies the location of the installation of Questa Verification IPs (which
previously were known as Multi-View Verification Components (MVC)).
Syntax
MvcHome = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path. May include environment variables.
You can override this variable by specifying vsim -mvchome.
NoCaseStaticError
Section [vcom]
This variable changes case statement static errors to warnings.
Syntax
NoCaseStaticError = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vcom -nocasestaticerror.
Related Topics
PedanticErrors
NoDebug
Sections [vcom], [vlog]
This variable controls inclusion of debugging info within design units.
Syntax
NoDebug = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
NoDeferSubpgmCheck
Section [vcom]
This variable controls the reporting of range and length violations detected within subprograms
as errors (instead of as warnings).
Syntax
NoDeferSubpgmCheck = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vcom -deferSubpgmCheck.
NoIndexCheck
Section [vcom]
This variable controls run time index checks.
Syntax
NoIndexCheck = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override NoIndexCheck = 0 by specifying vcom -noindexcheck.
Related Topics
Compilation of a VHDL Design—the vcom Command
NoOthersStaticError
Section [vcom]
This variable disables errors caused by aggregates that are not locally static.
Syntax
NoOthersStaticError = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -noothersstaticerror.
Related Topics
Message Severity Level
PedanticErrors
NoRangeCheck
Section [vcom]
This variable disables run time range checking. In some designs this results in a 2x speed
increase.
Syntax
NoRangeCheck = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this NoRangeCheck = 1 by specifying vcom -rangecheck.
Related Topics
Compilation of a VHDL Design—the vcom Command
note
Section [msg_system]
This variable changes the severity of the listed message numbers to “note”.
Syntax
note = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable setting by specifying the sccom, vcom, vlog, vopt, or
vsim command with the -note argument.
Related Topics
verror
Message Severity Level
error
fatal
suppress
warning
NoVital
Section [vcom]
This variable disables acceleration of the VITAL packages.
Syntax
NoVital = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -novital.
NoVitalCheck
Section [vcom]
This variable disables VITAL level 0 and VITAL level 1 compliance checking.
Syntax
NoVitalCheck = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vcom -novitalcheck.
NumericStdNoWarnings
Section [vsim]
This variable disables warnings generated within the accelerated numeric_std and numeric_bit
packages.
Syntax
NumericStdNoWarnings = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 —(default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
OldVHDLConfigurationVisibility
Section [vcom]
Controls visibility of VHDL component configurations during compile.
Syntax
OldVHDLConfigurationVisibility = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Use Language Reference Manual compliant visibility rules when processing
VHDL configurations.
o 1 — (default) Force vcom to process visibility of VHDL component configurations
consistent with prior releases.
Related Topics
vcom
OldVhdlForGenNames
The previous style is controlled by the value of the GenerateFormat value. The default behavior
is to use the current style names, which is described in the section “Naming Behavior of
VHDL for Generate Blocks”.
Section [vsim]
This variable instructs the simulator to use a previous style of naming (pre-6.6) for VHDL
for … generate statement iteration names in the design hierarchy.
Syntax
OldVhdlForGenNames = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
GenerateFormat
Naming Behavior of VHDL for Generate Blocks
OnFinish
Section [vsim]
This variable controls the behavior of Questa SIM when it encounters either an assertion failure,
a $finish, or an sc_stop() in the design code.
Syntax
OnFinish = {ask | exit | final | stop}
Arguments
• The arguments are described as follows:
o ask — (default) In batch mode, the simulation exits. In GUI mode, a dialog box pops
up and asks for user confirmation on whether to quit the simulation.
o stop — Causes the simulation to stay loaded in memory. This can make some post-
simulation tasks easier.
o exit — The simulation exits without asking for any confirmation.
o final — The simulation executes all final blocks then exits the simulation.
You can override this variable by specifying vsim -onfinish.
OnFinishPendingAssert
Section [vsim]
This variable prints pending deferred assertion messages. Deferred assertion messages may be
scheduled after the $finish in the same time step. Deferred assertions scheduled to print after the
$finish are printed to the Transcript before exiting. They are printed with severity level NOTE
because it is not known whether the assertion is still valid due to being printed in the active
region instead of the reactive region where they are normally printed.
Syntax
OnFinishPendingAssert = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Optimize_1164
Section [vcom]
This variable disables optimization for the IEEE std_logic_1164 package.
Syntax
Optimize_1164 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
osvvm
Section [Library]
This variable sets the path to the location of the pre-compiled Open Source VHDL Verification
Methodology library.
Syntax
osvvm = <path>
Arguments
• The arguments are described as follows:
o <path> — $MODEL_TECH/../osvvm
The source code for building this library is copied under the Perl foundation's artistic
license from the Open Source VHDL Verification Methodology web site at http://
www.osvvm.org. A copy of the source code is in the directory vhdl_src/
vhdl_osvvm_packages.
ParallelJobs
Section [vopt]
This variable may be set to zero (0) to disable parallel processing during vopt code generation
phase. Normally a heuristic is used to set this value.
Syntax
ParallelJobs = <n>
Arguments
• The arguments are described as follows:
o <n> — Any natural integer greater than or equal to 0 where 0 disables parallel
processing.
PathSeparator
Section [vsim]
This variable specifies the character used for hierarchical boundaries of HDL modules. This
variable does not affect file system paths. The argument to PathSeparator must not be the same
character as DatasetSeparator. This variable setting is also the default for the
SignalSpyPathSeparator variable.
Note
When creating a virtual bus, you must set the PathSeparator variable to either a period (.) or
a forward slash (/). For more information on creating virtual buses, refer to the section
“Combining Objects into Buses”.
Syntax
PathSeparator = <n>
Arguments
• The arguments are described as follows:
o <n> — Any character except special characters, such as backslash ( \ ), brackets ( {}
), and so forth, where the default is a forward slash ( / ).
Related Topics
Using Escaped Identifiers
SignalSpyPathSeparator
DatasetSeparator
Preserving Design Visibility with the Learn Flow
set Command Syntax
PedanticErrors
Section [vcom]
This variable forces display of an error message (rather than a warning) on a variety of
conditions. It overrides the NoCaseStaticError and NoOthersStaticError variables.
Syntax
PedanticErrors = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
See the vcom
NoCaseStaticError
NoOthersStaticError
Enforcing Strict 1076 Compliance
PliCompatDefault
Section [vsim]
This variable specifies the VPI object model behavior within vsim.
Syntax
PliCompatDefault = {1995 | 2001 | 2005 | 2009 | latest}
Arguments
• The arguments are described as follows:
o 1995 — Instructs vsim to use the object models as defined in IEEE Std 1364-1995.
When you specify this argument, SystemVerilog objects will not be accessible.
Aliases include:
95, 1364v1995, 1364V1995, VL1995,
VPI_COMPATIBILITY_VERSION_1364v1995, 1 — On
o 2001 — Instructs vsim to use the object models as defined in IEEE Std 1364-2001.
When you specify this argument, SystemVerilog objects will not be accessible.
Aliases include:
01, 1364v2001, 1364V2001, VL2001,
VPI_COMPATIBILITY_VERSION_1364v2001
Note
There are a few cases where the 2005 VPI object model is incompatible with the
2001 model, which is inherent in the specifications.
o 2005 — Instructs vsim to use the object models as defined in IEEE Std 1800-2005
and IEEE Std 1364-2005. Aliases include:
05, 1800v2005, 1800V2005, SV2005,
VPI_COMPATIBILITY_VERSION_1800v2005
o 2009 — Instructs vsim to use the object models as defined in IEEE Std 1800-2009.
Aliases include:
09, 1800v2009, 1800V2009, SV2009,
VPI_COMPATIBILITY_VERSION_1800v2009
o latest — (default) This is equivalent to the “2009” argument. This is the default
behavior if you do not specify this argument or if you specify the argument without
an argument.
You can override this variable by specifying vsim -plicompatdefault.
Related Topics
Verilog Interfaces to C
PreserveCase
Section [vcom]
This variable instructs the VHDL compiler either to preserve the case of letters in basic VHDL
identifiers or to convert uppercase letters to lowercase.
Syntax
PreserveCase = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vcom -lower or vcom -preserve.
PrintSimStats
Section [vsim]
This variable instructs the simulator to print out simulation statistics at the end of the simulation
before it exits. Statistics are printed with relevant units in separate lines. The Stats variable
overrides the PrintSimStats if the two are both enabled.
Syntax
PrintSimStats = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — print at end of simulation
o 2 — print at end of each run and end of simulation
You can override this variable by specifying vsim -printsimstats.
Related Topics
simstats
Stats
PrintSVPackageLoadingAttribute
Section [vlog]
This variable prints the attribute placed upon SV packages during package import when true (1).
The attribute will be ignored when this variable entry is false (0). The attribute name is
“package_load_message.” The value of this attribute is a string literal.
Syntax
PrintSVPackageLoadingAttribute = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — False
o 1 — (default) True
Protect
Section [vlog]
This variable enables protect directive processing.
Syntax
Protect = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
Compiler Directives
PslOneAttempt
Section [vsim]
This variable affects PSL directives with top level “always/never” properties. As per strict IEEE
Std 1850-2005, an always/never property can either pass or fail. However, by default, Questa
SIM reports multiple passes and/or failures, which corresponds to multiple attempts made while
executing a top level “always/never” property. With this variable, you can force a single attempt
to start at the beginning of simulation. The directive will either match (pass), fail, or vacuously-
match (provided it is not disabled/aborted). If the “always/never” property fails, the directive is
immediately considered a failure and the simulation will not go further. If there is no failure (or
disable/abort) until end of simulation then a match (pass) is reported. By default, this feature is
off and can only be explicitly turned on using this variable or vsim -psloneattempt.
Syntax
PslOneAttempt = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
PslInfinityThreshold
Section [vsim]
This variable allows you to specify the number of clock ticks that will represent infinite clock
ticks. It only affects PSL strong operators, namely eventually!, until! and until_!. If at End of
Simulation an active strong-property has not clocked this number of clock ticks, neither pass
nor fail (that is, vacuous match) is returned; else, respective fail/pass is returned. The default
value is '0' (zero) which effectively does not check for clock tick condition. This feature can
only be explicitly turned on using this variable or vsim -pslinfinitethreshold.
Syntax
PslOneAttempt = {0 | <n>}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o <n> — Any positive integer
Quiet
Sections [vcom], [vlog]
This variable turns off “loading…” messages.
Syntax
Quiet = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vlog -quiet or vcom -quiet.
RequireConfigForAllDefaultBinding
Section [vcom]
This variable instructs the compiler to not generate any default bindings when compiling with
vcom and when elaborating with vsim. All instances are left unbound unless you specifically
write a configuration specification or a component configuration that applies to the instance.
You must explicitly bind all components in the design through either configuration
specifications or configurations. If an explicit binding is not fully specified, defaults for the
architecture, port maps, and generic maps will be used as needed.
Syntax
RequireConfigForAllDefaultBinding = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override RequireConfigForAllDefaultBinding = 1 by specifying vcom
-performdefaultbinding.
Related Topics
Default Binding
BindAtCompile
vcom
Resolution
Section [vsim]
This variable specifies the simulator resolution. The argument must be less than or equal to the
UserTimeUnit and must not contain a space between value and units.
Syntax
Resolution = {[n]<time_unit>}
Arguments
• The arguments are described as follows:
o [n] — Optional prefix specifying number of time units as 1, 10, or 100.
o <time_unit> — fs, ps, ns, us, ms, or sec where the default is ns.
The argument must be less than or equal to the UserTimeUnit and must not contain a
space between value and units, for example:
Resolution = 10fs
You can override this variable by specifying vsim -t. You should set a smaller
resolution if your delays get truncated.
Related Topics
UserTimeUnit
RunLength
Section [vsim]
This variable specifies the default simulation length in units specified by the UserTimeUnit
variable.
Syntax
RunLength = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 100.
You can override this variable by specifying the run command.
Related Topics
UserTimeUnit
The Runtime Options Dialog
set Command Syntax
Sc22Mode
Section [sccom]
This variable enables SystemC-2.2 (the IEEE 1666-2005 standard) for both compiling and
linking.
Syntax
Sc22Mode = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying sccom -sc22.
ScalarOpts
Sections [vcom], [vlog]
This variable activates optimizations on expressions that do not involve signals, waits, or
function/procedure/task invocations.
Syntax
ScalarOpts = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SccomLogfile
Section [sccom]
This variable creates a log file for sccom.
Syntax
SccomLogfile = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying sccom -log.
SccomVerbose
Section [sccom]
This variable prints the name of each sc_module encountered during compilation.
Syntax
SccomVerbose = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying sccom -verbose.
ScEnableScSignalWriteCheck
Section [vsim]
This variable enables a check for multiple writers on a SystemC signal.
Syntax
ScEnableScSignalWriteCheck = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
ScMainFinishOnQuit
Section [vsim]
This variable determines when the sc_main thread exits. This variable is used to turn off the
execution of remainder of sc_main upon quitting the current simulation session. Disabling this
variable (0) has the following effect: If the cumulative length of sc_main() in simulation time
units is less than the length of the current simulation run upon quit or restart, sc_main() is
aborted in the middle of execution. This can cause the simulator to crash if the code in sc_main
is dependent on a particular simulation state.
On the other hand, one drawback of not running sc_main until the end is potential memory leaks
for objects created by sc_main. By default, the remainder of sc_main is executed regardless of
delays.
Syntax
ScMainFinishOnQuit = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
ScMainStackSize
Section [vsim]
This variable sets the stack size for the sc_main() thread process.
Syntax
ScMainStackSize = <n>{Kb | Mb | Gb}
Arguments
• The arguments are described as follows:
o <n> — An integer followed by Kb, Mb, Gb where the default is 1Mb.
ScStackSize
Section [vsim]
This variable sets the stack size for the sc_thread process.
Syntax
ScStackSize = <n>{Kb | Mb | Gb}
Arguments
• The arguments are described as follows:
o <n> — An integer followed by Kb, Mb, Gb. There is no default for ScStackSize.
ScShowIeeeDeprecationWarnings
Section [vsim]
This variable displays warning messages for many of the deprecated features in Annex C of the
IEEE Std 1666-2005, and Std 1666-2011, Standard SystemC Language Reference Manual.
Syntax
ScShowIeeeDeprecationWarnings = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
ScTimeUnit
Section [vsim]
This variable sets the default time unit for SystemC simulations.
Syntax
ScTimeUnit = {[n]<time_unit>}
Arguments
• The arguments are described as follows:
o [<n>] — Optional prefix specifying number of time units as 1, 10, or 100.
o <time_unit> — fs, ps, ns, us, ms, or sec where the default is 1 ns.
ScvPhaseRelationName
Section [vsim]
This variable changes the precise name used by SCV to specify “phase” transactions in the
WLF file.
Syntax
ScvPhaseRelationName = <string>
Arguments
• The arguments are described as follows:
o <string> — Any legal string where the default is mti_phase. Legal C-language
identifiers are recommended.
Related Topics
About Transaction Streams
Writing SCV Transactions
SeparateConfigLibrary
Section [vcom]
This variable allows the declaration of a VHDL configuration to occur in a different library than
the entity being configured. Strict conformance to the VHDL standard (LRM) requires that they
be in the same library.
Syntax
SeparateConfigLibrary = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom -separateConfigLibrary.
Show_BadOptionWarning
Section [vlog]
This variable instructs Questa SIM to generate a warning whenever an unknown plus argument
is encountered.
Syntax
Show_BadOptionWarning = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Show_Lint
Sections [vcom], [vlog]
This variable instructs Questa SIM to display lint warning messages.
Syntax
Show_Lint = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vlog -lint or vcom -lint.
Show_PslChecksWarnings
Section [vcom], [vlog]
This variable instructs Questa SIM to display PSL warning messages.
Syntax
Show_PslChecksWarnings = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_source
Sections [vcom], [vlog]
This variable shows source line containing error.
Syntax
Show_source = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying the vlog -source or vcom -source.
Show_VitalChecksWarnings
Section [vcom]
This variable enables VITAL compliance-check warnings.
Syntax
Show_VitalChecksWarnings = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_Warning1
Section [vcom]
This variable enables unbound-component warnings.
Syntax
Show_Warning1 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_Warning2
Section [vcom]
This variable enables process-without-a-wait-statement warnings.
Syntax
Show_Warning2 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_Warning3
Section [vcom]
This variable enables null-range warnings.
Syntax
Show_Warning3 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_Warning4
Section [vcom]
This variable enables no-space-in-time-literal warnings.
Syntax
Show_Warning4 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Show_Warning5
Section [vcom]
This variable enables multiple-drivers-on-unresolved-signal warnings.
Syntax
Show_Warning5 = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
ShowConstantImmediateAsserts
Section [vcom], [vlog], [vopt]
This variable controls the display of immediate assertions with constant expressions. By default,
immediate assertions with constant expressions are displayed in the GUI, in reports, and in the
UCDB.
Syntax
ShowConstantImmediateAsserts = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
ShowFunctions
Section [vsim]
This variable sets the format for Breakpoint and Fatal error messages. When set to 1 (the default
value), messages will display the name of the function, task, subprogram, module, or
architecture where the condition occurred, in addition to the file and line number. Set to 0 to
revert messages to the previous format.
Syntax
ShowFunctions = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
ShowUnassociatedScNameWarning
Section [vsim]
This variable instructs Questa SIM to display unassociated SystemC name warnings.
Syntax
ShowUnassociatedScNameWarning = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
ShowUndebuggableScTypeWarning
Section [vsim]
This variable instructs Questa SIM to display un-debuggable SystemC type warnings.
Syntax
ShowUndebuggableScTypeWarning = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
ShutdownFile
Section [vsim]
This variable calls the write format restart command upon exit and executes the .do file created
by that command. This variable should be set to the name of the file to be written, or the value
“--disable-auto-save” to disable this feature. If the filename contains the pound sign character
(#), then the filename will be sequenced with a number replacing the #. For example, if the file
is “restart#.do”, then the first time it will create the file “restart1.do” and the second time it will
create “restart2.do”, and so forth.
Syntax
ShutdownFile = <filename>.do | <filename>#.do | --disable-auto-save}
Arguments
• The arguments are described as follows:
o <filename>.do — A user defined filename where the default is restart.do.
o <filename>#.do — A user defined filename with a sequencing character.
o --disable-auto-save — Disables auto save.
Related Topics
write format restart command.
SignalForceFunctionUseDefaultRadix
Section [vsim]
Set this variable to 1 cause the signal_force VHDL and Verilog functions use the default radix
when processing the force value. Prior to 10.2 signal_force used the default radix and now it
always uses symbolic unless the value explicitly indicates a base radix.
Syntax
SignalForceFunctionUseDefaultRadix = { 0 | 1 }
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SignalSpyPathSeparator
Section [vsim]
This variable specifies a unique path separator for the Signal Spy functions. The argument to
SignalSpyPathSeparator must not be the same character as the DatasetSeparator variable.
Syntax
SignalSpyPathSeparator = <character>
Arguments
• The arguments are described as follows:
o <character> — Any character except special characters, such as backslash ( \ ),
brackets
( {} ), and so forth, where the default is to use the PathSeparator variable or a
forward slash ( / ).
Related Topics
Signal Spy
DatasetSeparator
SimulateAssumeDirectives
Section [vsim]
This variable instructs Questa SIM to assume directives are simulated as if they were assert
directives.
Syntax
SimulateAssumeDirectives = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim {-assume | -noassume}.
Related Topics
Processing Assume Directives
SimulateImmedAsserts
Section [vsim]
This variable controls whether or not SVA and VHDL immediate assertion directives will be
simulated.
Syntax
SimulateImmedAsserts = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim {-immedassert | -noimmedassert].
SimulatePSL
Section [vsim]
This variable controls whether or not PSL assertion directives will be elaborated.
Syntax
SimulatePSL = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim {-psl | -nopsl}.
SimulateSVA
Section [vsim]
This variable controls whether or not SVA concurrent assertion directives will be elaborated.
Syntax
SimulateSVA = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim {-sva | -nosva].
SmartDbgSym
This variable reduces the size of design libraries by minimizing the amount of debugging
symbol files generated at compile time. Default is to generate debugging symbol database file
for all design-units.
Syntax
SmartDbgSym = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vcom/vlog -smartdbgsym.
SolveACTMaxOps
Section [vsim]
This variable specifies the maximum number of operations that the ACT solver may perform
before abandoning an attempt to solve a particular constraint scenario. The value is specified in
1,000,000s of operations.
Syntax
SolveACTMaxOps = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 10000 and 0 indicates no limit.
SolveACTMaxTests
Section [vsim]
This variable specifies the maximum number of tests that the ACT solver may evaluate before
abandoning an attempt to solve a particular randomize scenario.
Syntax
SolveACTMaxTests = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where 0 indicates no limit and the default is 2000000.
SolveACTRetryCount
Section [vsim]
This variable specifies the number of times to retry the ACT solver on a randomization scenario
that fails due to the value of the SolveACTMaxTests threshold. The default is 0, meaning that if
the first attempt fails after SolveACTMaxTests tests, no subsequent attempts are made, and the
solver moves on to the next engine (e.g. the BDD engine). This can be useful in scenarios where
the BDD engine is known to fail, and the ACT solver succeeds most of the time. A small
nonzero value of SolveACTRetryCount can decrease the percentage of the time that a
randomize call might not ultimately succeed.
Syntax
SolveACTRetryCount = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 0.
SolveArrayResizeMax
Section [vsim]
This variable specifies the maximum size randomize() will allow a dynamic array to be resized.
If randomize() attempts to resize a dynamic array to a value greater than SolveArrayResizeMax,
an error will be displayed and randomize() will fail.
Syntax
SolveArrayResizeMax = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer (a value of 0 indicates no limit). Default value is 10000.
Related Topics
set Command Syntax
SolveBeforeErrorSeverity
Section [vsim]
This variable modifies the severity of suppressible index, out-of-bounds, null-dereference,
solve/before constraint errors.
Syntax
SolveBeforeErrorSeverity = [0 | 1 | 2 | 3 | 4]
Arguments
• The arguments are described as follows:
o 0 — No error
o 1 — Warning
o 2 — Error
o 3 — (default) Failure
o 4 — Fatal
You can override this variable by specifying vsim -solvebeforeerrorseverity.
SolveEngine
Section [vsim]
This variable specifies which solver engine to use when evaluating randomize calls.
Syntax
SolveEngine = auto | act | bdd
Arguments
• The arguments are described as follows:
o auto — (default) automatically select the best engine for the current randomize
scenario
o act — evaluate all randomize scenarios using the ACT solver engine
o bdd — evaluate all randomize scenarios using the BDD solver engine
You can override this variable by specifying vsim -solveengine at the command line.
SolveFailDebug
Section [vsim]
This variable enables the feature to debug SystemVerilog randomize() failures. Whenever a
randomize() failure is detected during simulation, Questa SIM displays the minimum set of
constraints that caused the randomize() call to fail.
Syntax
SolveFailDebug = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 - (default) Disable solvefaildebug
o 1 - Basic debug (provides a testcase and prints contradicting constraints with no
performance penalty)
o 2 - Enhanced debug (provides constraints in more original form with a runtime
performance penalty)
If no value is specified, basic debug will be enabled. You can override this variable
by specifying vsim -solvefaildebug.
Related Topics
Debugging randomize() Failures
SolveFailDebugMaxSet
Section [vsim]
When SolveFailDebug is enabled, this variable specifies the maximum size of constraint
subsets (in number of constraints) that will be tested for conflicts.
Syntax
SolveFailDebugMaxSet = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SolveFailSeverity
Section [vsim]
This variable allows you to specify the severity of messages that result when a SystemVerilog
call to randomize() fails.
Syntax
SolveFailSeverity = {0 | 1 | 2 | 3 | 4}
Arguments
• The arguments are described as follows:
o 0 — (default) No error
o 1 — Warning
o 2 — Error
o 3 — Failure
o 4 — Fatal
SolveGraphMaxEval
Section [vsim]
This variable specifies the maximum number of evaluations that may be performed on the
solution graph generated during randomize(). This value can be used to force randomize() to
abort if the complexity of the constraint scenario (in time) exceeds the specified limit. The value
is specified in 10000s of evaluations.
Syntax
SolveGraphMaxEval = <n>
Arguments
• The arguments are described as follows:
o <n>— A non-negative integer where 0 indicates no limit and the default is 10000.
SolveGraphMaxSize
Section [vsim]
This variable specifies the maximum size of the solution graph that may be generated during a
SystemVerilog call to randomize(). You can use this value to force randomize() to abort if the
complexity of the constraint scenario exceeds the specified limit. The limit is specified in 1000s
of nodes.
Syntax
SolveGraphMaxSize = <n>
Arguments
• The arguments are described as follows:
o <n> — A non-negative integer (with the unit of 1000 nodes) where 0 indicates no
limit and 10000 is the default.
SolveIgnoreOverflow
Section [vsim]
This variable instructs the solver to ignore calculation overflow or underflow while evaluating
constraints.
Syntax
SolveIgnoreOverflow = 0 | 1
Arguments
• The arguments are described as follows:
o 0 — (default) Do not ignore overflow or underflow.
o 1 — Ignore overflow or underflow.
SolveRev
Section [vsim]
This variable allows you to specify random sequence generator compatibility with a prior letter
release for the SystemVerilog solver. (It does not apply to the SystemC/SCV solver.) This
option is used to get the same random sequences during simulation as a prior letter release.
Syntax
SolveRev = <string> | " "
Arguments
• The arguments are described as follows:
o <string> — A string of a Questa SIM release number and letter, such as 6.4a
(SolveRev = 6.4a).
" " — (default) Off.
Note
Only prior letter releases (within the same number release) are allowed. For
example, in 6.4b you can set “SolveRev= 6.4” or “SolveRev = 6.4a”, but cannot
set “SolveRev = 6.4g”.
SolveTimeout
Section [vsim]
This variable allows you to specify the solver timeout threshold (in seconds), to improve the
handling of randomize() timeouts. A randomize() call will fail if the CPU time required to
evaluate any randset exceeds the specified timeout.
Syntax
SolveTimeout = <val>
Arguments
• The arguments are described as follows:
o <val> — Number of seconds before the randomize() call times out. The default is
500. A setting of 0 disables the timeout feature.
You can override this variable by specifying vsim -solvetimeout.
SparseMemThreshold
Section [vlog]
This variable specifies the size at which memories will automatically be marked as sparse
memory. A memory with depth equal to or more than the sparse memory threshold gets marked
as sparse automatically, unless specified otherwise in source code or by vlog +nonsparse, or
vopt +nonsparse.
Syntax
SparseMemThreshold = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 1048576.
Related Topics
Sparse Memory Modeling
vlog
vopt
StackTraceDepth
Section [vsim]
This variable specifies the depth of stack frames returned by the level argument to the
$stacktrace() function call. The depth specified is used when the optional ‘level’ argument is not
specified or its value is not a positive integer.
Syntax
StackTraceDepth = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative number where the default is 100.
Related Topics
$stacktrace()
Startup
Section [vsim]
This variable specifies a simulation startup DO file.
Syntax
Startup = {do <DO filename>}
Arguments
• The arguments are described as follows:
o <DO filename> — Any valid DO file where the default is to comment out the line ( ;
).
Related Topics
do
Using a Startup File
Stats
Section [sccom, vcom, vlog, vopt, vsim]
This variable controls the display of statistics messages in a logfile and stdout. Stats variable
overrides PrintSimStats variable if both are enabled.
Syntax
Stats [=[+|-]<feature>[,[+|-]<mode>]
Arguments
• The arguments are described as follows:
o [+|-] — Controls activation of the feature or mode. You can also enable a feature or
mode by specifying a feature or mode without the plus (+) character. Multiple
features and modes for each instance of -stats are specified as a comma separated
list.
o <feature>
• all — All statistics features displayed (cmd, msg, perf, time). Mutually exclusive
with none option. When specified in a string with other options, +|-all is applied
first.
• cmd — (default) Echo the command line
• msg — (default) Display error and warning summary at the end of command
execution
• none — Disable all statistics features. Mutually exclusive with all option. When
specified in a string with other options, +|-none is applied first.
• perf — Display time and memory performance statistics
• time — (default) Display Start, End, and Elapsed times
o <mode>
Modes can be set for a specific feature or globally for all features. To add or subtract
a mode for a specific feature, specify using the plus (+) or minus (-) character with
the feature, for example, Stats=cmd+verbose,perf+list. To add or subtract a mode
globally for all features, specify the modes in a comma-separated list, for example,
Stats=time,perf,list,-verbose. You cannot specify global and feature specific modes
together.
• kb — Prints memory statistics in Kb units with no auto-scaling
• list — Display statistics in a Tcl list format when available
• verbose — Display verbose statistics information when available
You can add or subtract individual elements of this variable by specifying the -stats
argument with sccom, vcom, vcover attribute, and other vcover commands,
vencrypt, vhencrypt, vlog, vopt, and vsim.
You can disable all default or user-specified Stats features with the -quiet argument
for:
• vcom
• vencrypt
• vhencrypt
• vlog
• qverilog
• vopt
Description
You can specify modes globally or for a specific feature.
Related Topics
Tool Statistics Messages
PrintSimStats
std
Section [library]
This variable sets the path to the VHDL STD library.
Syntax
std = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../std. May include
environment variables.
std_developerskit
Section [library]
This variable sets the path to the libraries for Mentor Graphics standard developer’s kit.
Syntax
std_developerskit = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../
std_developerskit. May include environment variables.
StdArithNoWarnings
Section [vsim]
This variable suppresses warnings generated within the accelerated Synopsys std_arith
packages.
Syntax
StdArithNoWarnings = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
The Runtime Options Dialog
set Command Syntax
suppress
Section [msg_system]
This variable suppresses the listed message numbers and/or message code strings (displayed in
square brackets).
Syntax
suppress = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable setting by specifying the sccom, vcom, vlog, vopt, or
vsim command with the -suppress argument.
Related Topics
verror
Message Severity Level
error
fatal
note
warning
SuppressFileTypeReg
Section [vsim]
This variable suppresses a prompt from the GUI asking if ModelSim file types should be
applied to the current version.
Syntax
SuppressFileTypeReg = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can suppress the GUI prompt for ModelSim type registration by setting the
SuppressFileTypeReg variable value to 1 in the modelsim.ini file on each server in a
server farm. This variable only applies to Microsoft Windows platforms.
Sv_Seed
Section [vsim]
This is a read-only variable that shows the initial seed specified for the Random Number
Generator (RNG) of the root thread in SystemVerilog. You cannot change its value directly in
the modelsim.ini file.
Syntax
Sv_Seed
Arguments
• none
o This variable assumes the value that you specify with either sv_reseed or vsim
-sv_seed.
Related Topics
Seeding the Random Number Generator (RNG)
sv_std
Section [library]
This variable sets the path to the SystemVerilog STD library.
Syntax
sv_std = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../sv_std. May
include environment variables.
SVAPrintOnlyUserMessage
Section [vsim]
This variable controls the printing of user-defined assertion error messages along with severity
information.
Syntax
SVAPrintOnlyUserMessage = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Prints additional information from LRM-defined (IEEE Std 1800-
2009) Severity System tasks.
o 1 — Prints only the severity information and the user message.
SVCovergroupGetInstCoverageDefault
Section [vlog], [vsim]
This variable allows you to specify an override for the default value of the “get_inst_coverage”
option for Covergroup variables. This is a compile time option which forces
“get_inst_coverage” to a user specified default value and supersedes the SystemVerilog
specified default value of '0' (zero).
Syntax
SVCovergroupGetInstCoverageDefault = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SVCovergroupGoal
Section [vsim]
This variable is used to override both the default value of option.goal (100, unless otherwise set
with the SVCovergroupGoalDefault compiler control variable), as well as any explicit
assignments to covergroup, coverpoint, and cross option.goal placed in SystemVerilog.
Syntax
SVCovergroupGoal = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 100.
Related Topics
SVCovergroupGoalDefault
SVCovergroupGoalDefault
Section [vlog]
This variable is used in conjunction with the SVCovergroupGoal simulator control variable, and
overrides the default value of the SystemVerilog covergroup, coverpoint, and cross option.goal
(defined to be 100 in the IEEE Std 1800-2009). This variable does not override specific
assignments in SystemVerilog source code.
Note
You must re-compile the design after changing the setting of this variable.
Syntax
SVCovergroupGoalDefault = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 100.
Related Topics
SVCovergroupGoal
SVCovergroupMergeInstancesDefault
Section [vsim]
This variable exists in the vsim sections of the modelsim.ini file.
Syntax
SVCovergroupMergeInstancesDefault = {0 | 1 | -1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — On
o -1 — (default) Don't care
Description
For simulation, this variable enforces the default behavior of covergroup get_coverage() built-
in functions, GUI operations, and reports. It sets the default value of
type_option.merge_instances to ensure IEEE 1800-2009 compliant behavior. Two vsim
command line options— -cvgmergeinstances and -nocvgmergeinstances—override this
variable setting.
The default value of this variable, -1 (don't care), allows the tool to determine the effective
value, based on factors related to capacity and optimization. The type_option.merge_instances
appears in the GUI and coverage reports as either auto(1) or auto(0), depending on whether the
effective value was determined to be a 1 or a 0.
Related Topics
vsim command.
SVCovergroupPerInstanceDefault
Section [vlog]
This variable is used to set the default value for SystemVerilog option.per_instance (defined to
be 0 in the IEEE Std 1800-2009). It does not override explicit assignments to
option.per_instance.
Note
You must re-compile the design after changing the setting of this variable.
Syntax
SVCovergroupPerInstanceDefault = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SVCovergroupSampleInfo
Section [vsim]
This variable is used to enable generation of more detailed information about the sampling of
covergroup, cross, and coverpoints. It provides details about the number of times the
covergroup instance and type were sampled, as well as details about why covergroup, cross, and
coverpoint were not covered.
Syntax
SVCovergroupSampleInfo = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 0.
SVCovergroupStrobe
Section [vsim]
This variable is used to override both the default value of type_option.strobe (0, unless
otherwise set with the SVCovergroupStrobeDefault variable), as well as any user assignments
for covergroup, coverpoint, and cross type_option.strobe, placed in SystemVerilog.
Syntax
SVCovergroupStrobe = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 0.
Related Topics
SVCovergroupStrobeDefault
SVCovergroupStrobeDefault
Section [vlog]
This variable is used in conjunction with the SVCovergroupStrobe variable, and overrides the
SystemVerilog covergroup type_option.strobe (defined to be 0 in the IEEE Std 1800-2009). It
does not override explicit assignments to type_option.strobe.
Note
You must re-compile the design after changing the setting of this variable.
Syntax
SVCovergroupStrobeDefault = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 0.
Related Topics
SVCovergroupStrobe
SVCovergroupTypeGoal
Section [vsim]
This variable is used to override both the default value of type_option.goal (100, unless
otherwise set with the SVCovergroupTypeGoalDefault variable), as well as any user
assignments for covergroup, coverpoint, and cross type_option.goal, placed in SystemVerilog.
Syntax
SVCovergroupTypeGoal = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 100.
Related Topics
SVCovergroupTypeGoalDefault
SVCovergroupTypeGoalDefault
Section [vlog]
This variable is used to override the default value of the SystemVerilog covergroup, coverpoint,
and cross type_option.goal (defined to be 100 in the IEEE Std 1800-2009). It does not override
specific assignments in SystemVerilog source code.
Note
You must re-compile the design after changing the setting of this variable.
Syntax
SVCovergroupTypeGoal Default = <n>
Arguments
• The arguments are described as follows:
o <n> — Any integer where the default is 100.
SVCovergroupZWNoCollect
Section [vsim]
This variable is used to disable coverage collection for any coverage item (coverpoint or cross
or the entire covergroup), when 0 is assigned as its option.weight. Item will not be displayed in
any coverage report, nor will it contribute to any coverage score computation.
Syntax
SVCovergroupZWNoCollect = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On - disables coverage collection for coverage item
SVCoverpointAutoBinMax
Section [vsim]
This variable is used to override both the default value of option.auto_bin_max (64), as well as
any explicit assignments in source code to SystemVerilog covergroup option.auto_bin_max.
Syntax
SVCoverpointAutoBinMax = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 64.
SVCoverpointExprVariablePrefix
Section [vlog]
When GenerateLoopIterationMax = 1, this variable sets the prefix in the name of the user-
visible variable generated for the coverpoint expression sampled value.
Note
You must re-compile the design after changing the setting of either this variable or the
EnableSVCoverpointExprVariable.
Syntax
SVCoverpointExprVariablePrefix = [<value><coverpoint name> | expr]
Arguments
• The arguments are described as follows:
o <value> — A user defined string.
o <coverpoint name> — The name of the coverpoint.
o expr — (default)
Description
The current settings for both this variable and the EnableSVCoverpointExprVariable are
displayed in the Objects window.
Related Topics
GenerateLoopIterationMax
EnableSVCoverpointExprVariable
SVCoverpointWildCardBinValueSizeWarn
Section [vsim]
This variable sets the threshold value range beyond which a warning for SV Coverpoint
wildcard bin size is issued. The default threshold is 4096 (12 wildcard bits).
Syntax
SVCoverpointWildCardBinValueSizeWarn = [<value>]
Arguments
• The arguments are described as follows:
o <value> — Any non-negative integer.
SVCrossNumPrintMissing
Section [vsim]
This variable is used to override all other settings for the number of missing values that will be
printed to the coverage report. It overrides both the default value (0, unless otherwise set with
the SVCrossNumPrintMissingDefault variable), as well as any user assignments placed in
SystemVerilog.
Syntax
SVCrossNumPrintMissing = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 0.
Related Topics
SVCrossNumPrintMissingDefault
SVCrossNumPrintMissingDefault
Section [vlog]
This variable is used in conjunction with SVCrossNumPrintMissing variable, and overrides the
default value of the SystemVerilog covergroup option.cross_num_print_missing (defined to be
0 in the IEEE Std 1800-2009).
Note
You must recompile the design after changing the setting of this variable.
Syntax
SVCrossNumPrintMissingDefault = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 0.
Related Topics
SVCrossNumPrintMissing
SvExtensions
Section [vlog], [vopt], [vsim]
This variable enables SystemVerilog language extensions. The extensions enable non-LRM
compliant behavior.
Syntax
SvExtensions = [+|-]<val>[,[+|-]<val>] …
Arguments
• The arguments are described as follows:
o [+ | -] — controls activation of the val.
• + — activates the val.
• - — deactivates the val.
• If you do not specify either a “+” or “-”, the variable assumes you are activating
the specified val.
o <val>
• acum — Specifies that the get(), try_get(), peek(), and try_peek() methods on an
untyped mailbox will return successfully if the argument passed is assignment-
compatible with the entry in the mailbox. The LRM-compliant behavior is to
return successfully only if the argument and entry are of equivalent types.
• atpi — Use type names as port identifiers. Disabled when compiling with
-pedanticerrors.
• catx — Allow an assignment of a single un-sized constant in a concat to be
treated as an assignment of 'default:val'.
• cfce — Error message will be generated if $cast is used as a function and the
casting operation fails.
• daoa — Allows the passing a dynamic array as the actual argument of DPI open
array output port. Without this option, a runtime error, similar to the following, is
generated, which is compliant with LRM requirement.
# ** Fatal: (vsim-2211) A dynamic array cannot be passed as an
argument to the DPI import function 'impcall' because the
formal 'o' is an unsized output.
SVFileSuffixes
Section [vlog]
This variable defines one or more filename suffixes that identify a file as a SystemVerilog file.
To insert white space in an extension, use a backslash (\) as a delimiter. To insert a backslash in
an extension, use two consecutive back-slashes (\\).
Syntax
SVFileSuffixes = sv svp svh
Arguments
• The arguments are described as follows:
o On — Uncomment the variable.
o Off — Comment the variable ( ; ).
Svlog
Section [vlog]
This variable instructs the vlog compiler to compile in SystemVerilog mode. This variable does
not exist in the default modelsim.ini file, but is added when you select Use SystemVerilog in the
Compile Options dialog box > Verilog and SystemVerilog tab.
Syntax
Svlog = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
SVPrettyPrintFlags
Section [vsim]
This variable controls the formatting of '%p' and '%P' conversion specifications used in $display
and similar system tasks.
Syntax
SVPrettyPrintFlags=[I<n><S | T>] [L<numLines>] [C<numChars>] [R{d | b | o | h}]
[F<numFields>] [E<numElements>] [D<depth>]
Arguments
• The arguments are described as follows:
o I <n><S | T> — Expand and indent the format for printing records, structures, and
so forth by <n> spaces (S) or <n> tab stops (T).
o <n> — (required) Any positive integer
o S — (required when indenting with spaces) Indent with spaces.
o T — (required when indenting with tab stops) Indent with tab stops.
o For example, SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation
level.
o L<numLines> — (optional) Limit the number of lines of output to <numLines>.
o R {d | b | o | h} — (optional) Specify a radix for printing the data specified using the
%p format:
d decimal (default)
b binary
o octal
h hexadecimal
For example, SVPrettyPrintFlags=Rh specifies a hexadecimal radix. Further,
SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. It
changes the output in $display and similar systasks. It does not affect formatted
output functions (such as $displayh).
o <numLines> — (required) Any positive integer.
o For example, SVPrettyPrintFlags=L10 will cause the output to be limited to 10 lines.
o C<numChars> — (optional) Limit the number of characters of output to
<numChars>.
o <numChars> — (required) Any positive integer.
o For example, SVPrettyPrintFlags=C256 will limit the output to 256 characters.
SvRandExtensions
Section [vsim]
This variable enables/disables non-LRM compliant SystemVerilog constrained random
language extensions.
Syntax
SvRandExtensions = [+|-]<extension>[, [+|-]<extension>] . . .
Arguments
• The arguments are as follows:
o + — enables the extension
o - — disables the extension
Description
Extension descriptions are as follows:
• <extension>
o <extension>
• forkjoinstab — (enabled by default) Preserves the random stability of the parent
thread when creating the fork/join sub-threads.
• nodist — Interprets ‘dist’ constraint as an ‘inside’ constraint (ACT solver only).
• nonrandstab — (enabled by default) When enabled, the allocation of new “non
random” class instance will not consume a random number from the current
thread context. A class is considered “non random” if it, or its base classes, does
not declare any 'rand' or 'randc' fields, and does not invoke class::randomize()
anywhere.
• noorder — Ignores solve/before ordering constraints (ACT solver only).
• promotedist — Promotes the priority of a 'dist' constraint if its target has no
explicit solve/before constraint.
• randpackidx — (enabled by default) Allows, within the context of a constraint, a
random index expression for any packed variable.
• skew — Skews randomize results (ACT solver only).
These extensions can be overridden with the vsim -svrandext command.
synopsys
Section [vsim]
This variable sets the path to the accelerated arithmetic packages.
Syntax
synopsys = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../synopsys. May
include environment variables.
SyncCompilerFiles
Section [vcom]
This variable causes compilers to force data to be written to disk when files are closed.
Syntax
SyncCompilerFiles = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
ToggleCountLimit
Section [vsim]
This variable limits the toggle coverage count for a toggle node. After the limit is reached,
further activity on the node will be ignored for toggle coverage. All possible transition edges
must reach this count for the limit to take effect. For example, if you are collecting toggle data
on 0->1 and 1->0 transitions, both transition counts must reach the limit. If you are collecting
full data on 6 edge transitions, all 6 must reach the limit. If the limit is set to zero, then it is
treated as unlimited.
Syntax
ToggleCountLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer with a maximum positive value of a 32-bit signed
integer and a default of 1.
You can override this variable by specifying vsim -togglecountlimit or toggle add
-countlimit.
ToggleDeglitchPeriod
Section [vsim]
This variable controls the period of toggle deglitching.
Syntax
ToggleDeglitchPeriod = {“n <time_unit>”}
Arguments
• The arguments are described as follows:
o [n] — A string specifying the number of time units. A value of zero ( 0 ) eliminates
delta cycle glitches.
o <time_unit> — (required) fs, ps, ns, us, ms, or sec.
You must surround n <time_unit> with quotation marks (“ “) when you put a space
between “n” and <time_unit>.
ToggleFixedSizeArray
Section [vsim]
This variable is used to control whether Verilog fixed-size unpacked arrays, VHDL multi-
dimensional arrays, and VHDL arrays-of-arrays are included for toggle coverage.
Syntax
ToggleFixedSizeArray = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim {-togglefixedsizearray |
-notogglefixedsizearray}.
Related Topics
set Command Syntax
ToggleMaxFixedSizeArray
Section [vsim]
This variable is used to control the limit on the size of Verilog fixed-size unpacked arrays,
VHDL multi-dimensional arrays, and VHDL arrays-of-arrays that are included for toggle
coverage. Increasing the size of the limit has the effect of increasing the size of the array that
can be included for toggle coverage.
Syntax
ToggleMaxFixedSizeArray = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 1024.
You can override this variable by specifying vsim -togglemaxfixedsizearray.
Related Topics
set Command Syntax
ToggleMaxIntValues
Section [vsim]
This variable sets the maximum number of unique VHDL integer values to record with toggle
coverage.
Syntax
ToggleMaxIntValues = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 100.
You can override this variable by specifying vsim -togglemaxintvalues.
Related Topics
set Command Syntax
ToggleMaxRealValues
Section [vsim]
This variable sets the maximum number of unique SystemVerilog real values to record with
toggle coverage.
Syntax
ToggleMaxIntValues = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive integer where the default is 100.
You can override this variable by specifying vsim -togglemaxrealvalues.
Related Topics
set Command Syntax
ToggleNoIntegers
Section [vsim]
This variable controls the automatic inclusion of VHDL integer types in toggle coverage.
Syntax
ToggleNoIntegers = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -notoggleints.
TogglePackedAsVec
Section [vsim]
This variable treats Verilog multi-dimensional packed vectors and packed structures as
equivalently sized one_dimensional packed vectors for toggle coverage.
Syntax
TogglePackedAsVec = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -togglepackedasvec.
TogglePortsOnly
Section [vsim]
This variable controls the inclusion into toggle coverage numbers of ports only; when enabled,
all internal nodes are not included in the coverage numbers. When disabled, both ports and
internal nodes are included. In order for this variable to function properly, you must also use
“vopt +acc=p”.
Syntax
TogglePortsOnly = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -toggleportsonly.
ToggleVHDLRecords
Section [vsim]
This variable controls the inclusion of VHDL records in toggle coverage metrics. By default,
VHDL records are included in coverage.
Syntax
ToggleVHDLRecords = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -notogglevhdlrecords.
ToggleVlogEnumBits
Section [vsim]
This variable treats Verilog enumerated types as equivalently sized one-dimensional packed
vectors for toggle coverage.
Syntax
ToggleVlogEnumBits = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -togglevlogenumbits.
ToggleVlogIntegers
Section [vsim]
This variable controls toggle coverage for SystemVerilog integer types (that is, byte, shortint,
int, longint, but not enumeration types).
Syntax
ToggleVlogIntegers = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim [-togglevlogints |
-notogglevlogints}.
ToggleVlogReal
Section [vsim]
This variable controls toggle coverage for SystemVerilog real value types.
Syntax
ToggleVlogReal = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim {-togglevlogreal |
-notogglevlogreal}.
ToggleWidthLimit
Section [vsim]
This variable limits the width of signals that are automatically added to toggle coverage with the
+cover=t argument for vcom or vlog. The limit applies to Verilog registers and VHDL arrays. A
value of 0 is taken as unlimited.
Syntax
ToggleWidthLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer with a maximum positive value of a 32-bit signed
integer and a default of 128.
You can override this variable by specifying vsim -togglewidthlimit.
Related Topics
vcom
vlog
TranscriptFile
Section [vsim]
This variable specifies a file for saving a command transcript. You can specify environment
variables in the pathname.
Note
Once you load a modelsim.ini file with TranscriptFile set to a file location, this location will
be used for all output until you override the location with the transcript file command. This
includes the scenario where you load a new design with a new TranscriptFile variable set to a
different file location. You can determine the current path of the transcript file by executing the
transcript path command with no arguments.
Syntax
TranscriptFile = {<filename> | transcript}
Arguments
• The arguments are described as follows:
o <filename> — Any valid filename where transcript is the default.
Related Topics
Batch Mode
AssertFile
BatchMode
BatchTranscriptFile
transcript file
vsim
UCDBFilename
Section [vsim]
This variable specifies the default unified coverage database file name that is written at the end
of the simulation. If this variable is set, the UCDB is saved automatically at the end of
simulation. All coverage statistics are saved to the specified .ucdb file.
Syntax
UCDBFilename = {<filename> | vsim.ucdb}
Arguments
• The arguments are described as follows:
o <filename> — Any valid filename where vsim.ucdb is the default.
UCDBTestStatusMessageFilter
Section [vsim]
This variable specifies a regular expression which, if matched when compared against all
messages, prevents the status of that message from being propagated to the UCDB
TESTSTATUS. If this variable is set, the matching regular expression is ignored for all
messages which contain that match.
Syntax
UCDBTestStatusMessageFilter =“<subtext>” [“<additional subtext>”]
Arguments
• The arguments are described as follows:
o <subtext> — Subtext of message you wish to be exempt from altering UCDB
TESTSTATUS.
UdpCountLimit
Section [vsim]
This variable limits the number of counts that are tracked for UDP Coverage. Specifically, when
a bin has reached the specified count, coverage will ignore further tracking of the inputs linked
to the bin.
Note
If you change this value from the default you may affect simulation performance.
Syntax
UdpCountLimit = {<n> | 0 }
Arguments
• The arguments are described as follows:
o <n> — Specifies the count limit for UDP coverage. The default is 1
o 0 — Specifies an unlimited count
Related Topics
FecCountLimit
UnattemptedImmediateAssertions
Section [vsim]
This variable controls the inclusion or exclusion of unattempted (un-executed) immediate
assertions from the coverage calculations shown in the UCDB and coverage reports.
Syntax
UnattemptedImmediateAssertions = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off, Excluded
o 1 — On, Included
UnbufferedOutput
Section [vsim]
This variable controls VHDL and Verilog files open for write.
Syntax
UnbufferedOutput = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off, Buffered
o 1 — On, Unbuffered
UndefSyms
Section [vsim]
This variable allows you to manage the undefined symbols in the shared libraries currently
being loaded into the simulator.
Syntax
UndefSyms = {on | off | verbose}
Arguments
• The arguments are described as follows:
o on — Enables automatic generation of stub definitions for undefined symbols and
permits loading of the shared libraries despite the undefined symbols.
o off — (default) Disables loading of undefined symbols. Undefined symbols trigger
an immediate shared library loading failure.
o verbose — Permits loading to the shared libraries despite the undefined symbols and
reports the undefined symbols for each shared library.
UpCase
Section [vlog]
This variable instructs Questa SIM to activate the conversion of regular Verilog identifiers to
uppercase and allows case insensitivity for module names.
Syntax
UpCase = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
Related Topics
Verilog-XL Compatible Compiler Arguments
UserTimeUnit
Section [vsim]
This variable specifies the multiplier for simulation time units and the default time units for
commands such as force and run. Generally, you should set this variable to default, in which
case it takes the value of the Resolution variable.
Note
The value you specify for UserTimeUnit does not affect the display in the Wave window.
To change the time units for the X-axis in the Wave window, choose Wave > Wave
Preferences > Grid & Timeline from the main menu and specify a value for Grid Period.
Syntax
UserTimeUnit = {<time_unit> | default}
Arguments
• The arguments are described as follows:
o <time_unit> — fs, ps, ns, us, ms, sec, or default.
Related Topics
set Command Syntax
Resolution
RunLength
force
run
UseScv
Section [sccom]
This variable enables the use of SCV include files and verification library.
Syntax
UseScv = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying sccom -scv.
UseSVCrossNumPrintMissing
Section [vsim]
Specify whether to display and report the value of the “cross_num_print_missing” option for
the Cross in Covergroups. If not specified then “cross_num_print_missing” is ignored for
creating reports and displaying covergroups in GUI. Default is 0, which means ignore
“cross_num_print_missing.”
Syntax
UseSVCrossNumPrintMissing = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
UseUvmc
Section [sccom]
This variable controls automatic linking of the precompiled UVMC libraries shipped with
Questa SIM.
Usage
UseUvmc = { 0 | 1 }
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
UVMControl
Section [vsim]
This variable controls UVM-Aware debug features. These features work with either a standard
Accelera-released open source toolkit or the pre-compiled UVM library package in Questa
SIM.
Syntax
UVMControl={all | certe | disable | msglog | none | struct | trlog | verbose}
Arguments
• You must specify at least one argument. You can enable or disable some arguments by
prefixing the argument with a dash (-). Arguments may be specified as multiple instances of
-uvmcontrol. Multiple arguments are specified as a comma separated list without spaces.
Refer to the argument descriptions for more information.
o all — Enables all UVM-Aware functionality and debug options except disable and
verbose. You must specify verbose separately.
o certe — Enables the integration of the elaborated design in the Certe tool. Disables
Certe features when specified as -certe.
o disable — Prevents the UVM-Aware debug package from being loaded. Changes
the results of randomized values in the simulator.
o msglog — Enables messages logged in UVM to be integrated into the Message
Viewer. You must also enable wlf message logging by specifying tran or wlf with
vsim -msgmode. Disables message logging when specified as -msglog
o none — Turns off all UVM-Aware debug features. Useful when multiple
-uvmcontrol options are specified in a separate script, makefile or alias and you want
to be sure all UVM debug features are turned off.
o struct — (default) Enables UVM component instances to appear in the Structure
window. UVM instances appear under “uvm_root” in the Structure window.
Disables Structure window support when specified as -struct.
o trlog — Enables or disables UVM transaction logging. Logs UVM transactions for
viewing in the Wave window. Disables transaction logging when specified as -trlog.
o verbose — Sends UVM debug package information to the transcript. Does not
affect functionality. Must be specified separately.
You can also control UVM-Aware debugging with the -uvmcontrol argument to the
vsim command.
verilog
Section [library]
This variable sets the path to the library containing VHDL/Verilog type mappings.
Syntax
verilog = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../verilog. May
include environment variables.
Veriuser
Section [vsim]
This variable specifies a list of dynamically loadable objects for Verilog interface applications.
Syntax
Veriuser = <name>
Arguments
• The arguments are described as follows:
o <name> — One or more valid shared object names where the default is to comment
out the variable.
Related Topics
Registering PLI Applications
vsim
restart
VHDL93
Section [vcom]
This variable enables support for VHDL language version.
Syntax
VHDL93 = {0 | 1 | 2 | 3 | 87 | 93 | 02 | 08 | 1987 | 1993 | 2002 | 2008}
Arguments
• The arguments are described as follows:
o 0 — Support for VHDL-1987. You can also specify 87 or 1987.
o 1 — Support for VHDL-1993. You can also specify 93 or 1993.
o 2 — (default) Support for VHDL-2002. You can also specify 02 or 2002.
o 3 — Support for VHDL-2008. You can also specify 08 or 2008.
You can override this variable by specifying vcom {-87 | -93 | -2002 | -2008}.
VhdlSeparatePduPackage
Section [vsim]
This variable turns off sharing of a package from a library between two or more PDUs. Each
PDU will have a separate copy of the package. By default PDUs calling the same package from
a library share one copy of that package.
Syntax
VhdlSeparatePduPackage = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -vhdlmergepdupackage.
Related Topics
vsim
VhdlVariableLogging
Section [vsim]
This switch makes it possible for process variables to be recursively logged or added to the
Wave and List windows (process variables can still be logged or added to the Wave and List
windows explicitly with or without this switch).
Note
Logging process variables is inherently expensive on simulation performance because of
their nature. It is recommended that they not be logged, or added to the Wave and List
windows. However, if your debugging needs require them to be logged, then use of this switch
will lessen the performance hit in doing so.
Syntax
VhdlVariableLogging = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vsim -novhdlvariablelogging.
Description
For example with this vsim switch, log -r /* will log process variables as long as vopt is
specified with +acc=v and the variables are not filtered out by the WildcardFilter (via the
“Variable” entry).
Related Topics
vsim
vital2000
Section [library]
This variable sets the path to the VITAL 2000 library.
Syntax
vital2000 = <path>
Arguments
• The arguments are described as follows:
o <path> — Any valid path where the default is $MODEL_TECH/../vital2000. May
include environment variables.
vlog95compat
Section [vlog]
This variable instructs Questa SIM to disable SystemVerilog and Verilog 2001 support, making
the compiler revert to IEEE Std 1364-1995 syntax.
Syntax
vlog95compat = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying vlog -vlog95compat.
VoptFlow
Section [vsim]
This variable controls whether Questa SIM operates in optimized mode or full visibility mode.
Syntax
VoptFlow = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off, Design is compiled and simulated without optimizations, maintaining full
visibility.
o 1 — (default) On. Vopt is invoked automatically on the design and the design is
fully optimized.
You can override VoptFlow = 0 by specifying vsim -vopt.
Related Topics
Optimizing Designs with vopt
Optimization with SystemVerilog Bind
WarnConstantChange
Section [vsim]
This variable controls whether a warning is issued when the change command changes the value
of a VHDL constant or generic.
Syntax
WarnConstantChange = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
Related Topics
change
warning
Section [msg_system]
This variable changes the severity of the listed message numbers to “warning”.
Syntax
warning = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable by specifying the sccom, vcom, vlog, vopt, or vsim
command with the -warning argument.
Related Topics
verror
Message Severity Level
error
fatal
note
suppress
WaveSignalNameWidth
Section [vsim]
This variable controls the number of visible hierarchical regions of a signal name shown in the
Wave Window.
Syntax
WaveSignalNameWidth = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 0 (display full path). 1
displays only the leaf path element, 2 displays the last two path elements, and so on.
You can override this variable by specifying configure -signalnamewidth.
Related Topics
verror
Message Severity Level
Wave Window
error
fatal
note
suppress
WildcardFilter
Section [vsim]
This variable sets the default list of object types that are excluded when performing wildcard
matches with simulator commands. The default WildcardFilter variables are loaded every time
you invoke the simulator.
Syntax
WildcardFilter = <object_list>
Arguments
• The arguments are described as follows:
o <object_list> — A space separated list of objects where the default is:
• Variable Constant Generic Parameter SpecParam Memory Assertion Cover
Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
You can override this variable by specifying set WildcardFilter “<object_list>” or by
selecting Tools > Wildcard Filter to open the Wildcard Filter dialog. Refer to Using
the WildcardFilter Preference Variable for more information and a list of other
possible WildcardFilter object types.
Related Topics
Using the WildcardFilter Preference Variable
WildcardSizeThreshold
Section [vsim]
This variable prevents logging of very large non-dynamic objects when performing wildcard
matches with simulator commands, for example, “log -r*” and “add wave *”. Objects of size
equal to or greater than the WildcardSizeThreshold setting will be filtered out of wildcard
matches. The size is a simple calculation of the number of bits or items in the object.
Syntax
WildcardSizeThreshold = <n>
Arguments
• The arguments are described as follows:
o <n> — Any positive whole number where the default is 8192 bits (8 k). Specifying 0
disables the checking of the object size against this threshold and allows logging
objects of any size.
You can override this variable by specifying set WildcardSizeThreshold <n>
where <n> is any positive whole number.
Related Topics
Wildcard Characters
WildcardSizeThresholdVerbose
Section [vsim]
This variable controls whether warning messages are output when objects are filtered out due to
the WildcardSizeThreshold variable.
Syntax
WildcardSizeThresholdVerbose = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off
o 1 — On
You can override this variable by specifying set WildcardSizeThresholdVerbose
with a 1 or a 0.
Related Topics
Wildcard Characters
WLFCacheSize
Section [vsim]
This variable sets the number of megabytes for the WLF reader cache. WLF reader caching
caches blocks of the WLF file to reduce redundant file I/O.
Syntax
WLFCacheSize = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default on Linux systems is 2000M. The
default for Windows platforms is 1000M.
You can override this variable by specifying vsim -wlfcachesize.
Related Topics
WLF File Parameter Overview
WLFCollapseMode
Section [vsim]
This variable controls when the WLF file records values.
Syntax
WLFCollapseMode = {0 | 1 | 2}
Arguments
• The arguments are described as follows:
o 0 — Preserve all events and event order. Same as vsim -nowlfcollapse.
o 1 — (default) Only record values of logged objects at the end of a simulator
iteration. Same as vsim -wlfcollapsedelta.
o 2 — Only record values of logged objects at the end of a simulator time step. Same
as vsim -wlfcollapsetime.
You can override this variable by specifying vsim {-nowlfcollapse |
-wlfcollapsedelta | -wlfcollapsetime}.
Related Topics
WLF File Parameter Overview
WLFCompress
Section [vsim]
This variable enables WLF file compression.
Syntax
WLFCompress = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -nowlfcompress.
Related Topics
The Runtime Options Dialog
WLF File Parameter Overview
WLFDeleteOnQuit
Section [vsim]
This variable specifies whether a WLF file should be deleted when the simulation ends.
Syntax
WLFDeleteOnQuit = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Do not delete.
o 1 — On.
You can override this variable by specifying vsim -nowlfdeleteonquit.
Related Topics
The Runtime Options Dialog
WLF File Parameter Overview
vsim
WLFFileLock
Section [vsim]
This variable controls overwrite permission for the WLF file.
Syntax
WLFFileLock = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Allow overwriting of the WLF file.
o 1 — (default) Prevent overwriting of the WLF file.
You can override this variable by specifying vsim -wlflock or vsim -nowlflock.
Related Topics
WLF File Parameter Overview
vsim
WLFFilename
Section [vsim]
This variable specifies the default WLF file name.
Syntax
WLFFilename = {<filename> | vsim.wlf}
Arguments
• The arguments are described as follows:
o <filename> — User defined WLF file to create.
vsim.wlf — (default) filename
You can override this variable by specifying vsim -wlf.
Related Topics
WLF File Parameter Overview
set Command Syntax
WLFOptimize
Section [vsim]
This variable specifies whether the viewing of waveforms is optimized.
Syntax
WLFOptimize = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — Off
o 1 — (default) On
You can override this variable by specifying vsim -nowlfopt.
Related Topics
WLF File Parameter Overview
WLFSaveAllRegions
Section [vsim]
This variable specifies the regions to save in the WLF file.
Syntax
WLSaveAllRegions = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Only save regions containing logged signals.
o 1 — Save all design hierarchy.
Related Topics
The Runtime Options Dialog
WLFSimCacheSize
Section [vsim]
This variable sets the number of megabytes for the WLF reader cache for the current simulation
dataset only. WLF reader caching caches blocks of the WLF file to reduce redundant file I/O.
This makes it easier to set different sizes for the WLF reader cache used during simulation, and
those used during post-simulation debug. If the WLFSimCacheSize variable is not specified, the
WLFCacheSize variable is used.
Syntax
WLFSimCacheSize = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer where the default is 500.
You can override this variable by specifying vsim -wlfsimcachesize.
Related Topics
WLFCacheSize
WLF File Parameter Overview
WLFSizeLimit
Section [vsim]
This variable limits the WLF file by size (as closely as possible) to the specified number of
megabytes; if both size (WLFSizeLimit) and time (WLFTimeLimit) limits are specified the
most restrictive is used.
Syntax
WLFSizeLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer in units of MB where the default is 0 (unlimited).
You can override this variable by specifying vsim -wlfslim.
Related Topics
WLFTimeLimit
Limiting the WLF File Size
WLF File Parameter Overview
set Command Syntax
WLFTimeLimit
Section [vsim]
This variable limits the WLF file by time (as closely as possible) to the specified amount of
time. If both time and size limits are specified the most restrictive is used.
Syntax
WLFTimeLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer in units of MB where the default is 0 (unlimited).
You can override this variable by specifying vsim -wlftlim.
Related Topics
WLF File Parameter Overview
Limiting the WLF File Size
The Runtime Options Dialog
set Command Syntax
WLFUpdateInterval
Section [vsim]
This variable specifies the update interval for the WLF file. After the interval has elapsed, the
live data is flushed to the .wlf file, providing an up to date view of the live simulation. If you
specify 0, the live view of the wlf file is correct, however the file update lags behind the live
simulation.
Syntax
WLFUpdateInterval = <n>
Arguments
• The arguments are described as follows:
o <n> — Any non-negative integer in units of seconds where the default is 10 and 0
disables updating.
WLFUseThreads
Section [vsim]
This variable specifies whether the logging of information to the WLF file is performed using
multithreading.
Syntax
WLFUseThreads = {0 | 1}
Arguments
• The arguments are described as follows:
o 0 — (default) Off. Windows systems only, or when one processor is available.
o 1 — On Linux systems only, with more than one processor on the system. When this
behavior is enabled, the logging of information is performed by the secondary
processor while the simulation and other tasks are performed by the primary
processor.
You can override this variable by specifying vsim -nowlfopt.
Related Topics
Limiting the WLF File Size
WrapColumn
Section [vsim]
This variable defines the column width when wrapping output lines in the transcript file.
Usage
WrapColumn = <integer>
Arguments
• <integer>
An integer that defines the width, in characters, before forcing a line break. The default
value is 30000.
Description
This column is somewhat soft; the wrap will occur at the first white-space character after
reaching the WrapWSColumn column or at exactly the column width if no white-space is
found.
WrapMode
Section [vsim]
This variable controls wrapping of output lines in the transcript file.
Syntax
WrapMode = {0 | 1 | 2}
Arguments
• 0
(default) Disables wrapping.
• 1
Enables wrapping, based on the value of the WrapColumn variable, which defaults to
30,000 characters.
• 2
Enables wrapping and adds a continuation character (\) at the end of every wrapped line,
except for the last.
WrapWSColumn
Section [vsim]
This variable defines the column width when wrapping output lines in the transcript file.
Usage
WrapWSColumn = <integer>
Arguments
• <integer>
An integer that specifies that the wrap will occur at the first white-space character after
reaching the specified number of characters. If there is no white-space, the wrap will occur
at the WrapColumn variable value. The default value is 27000.
XpropAssertionLimit
Section [vsim]
This variable sets the default fail count limit of X propagated assertions.
Syntax
XpropAssertionLimit = <n>
Arguments
• The arguments are described as follows:
o <n> — (default) 5. Any non-negative integer, or -1. A value of -1 indicates
unlimited assertions.
You can override this variable setting using the xprop assertlimit command.
Related Topics
xprop enable
xprop assertlimit
vopt -xprop
X Propagation in Simulation
Note
The MODEL_TECH environment variable is a special variable that is set by Questa SIM (it
is not user-definable). Questa SIM sets this value to the name of the directory from which
the VCOM or VLOG compilers or the VSIM simulator was invoked. This directory is used by
other Questa SIM commands and operations to find the libraries.
Since the file referred to by the “others” clause may itself contain an “others” clause, you can
use this feature to chain a set of hierarchical INI files for library mappings.
You can prevent overwriting older transcript files by including a pound sign (#) in the name of
the file. The simulator replaces the ’#’ character with the next available sequence number when
saving a new transcript file.
When you invoke vsim using the default modelsim.ini file, a transcript file is opened in the
current working directory. If you then change (cd) to another directory that contains a different
modelsim.ini file with a TranscriptFile variable setting, the simulator continues to save to the
original transcript file in the former location. You can change the location of the transcript file
to the current working directory by:
• changing the preference setting (Tools > Edit Preferences > By Name > Main > file).
• using the transcript file command.
To limit the amount of disk space used by the transcript file, you can set the maximum size of
the transcript file with the transcript sizelimit command.
You can disable the creation of the transcript file by using the following Questa SIM command
immediately after Questa SIM starts:
Related Topics
TranscriptFile
Stats
The line shown above instructs Questa SIM to execute the commands in the DO file named
mystartup.do.
The line shown above instructs VSIM to run until there are no events scheduled.
These variables can also be set interactively using the Tcl set Command Syntax. This capability
provides an answer to a common question about disabling warnings at time 0. You might enter
commands like the following in a DO file or at the Questa SIM prompt:
set NumericStdNoWarnings 1
run 0
set NumericStdNoWarnings 0
run -all
Related Topics
force
where <options> can be one or more of -force, -nobreakpoint, -nofcovers, -nolist, -nolog, and
-nowave.
Example:
Related Topics
restart
VHDL Standard
You can specify which version of the 1076 Std Questa SIM follows by default using the
VHDL93 variable.
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
Related Topics
VHDL93
Related Topics
DelayFileOpen
Pathnames to source files are recorded in libraries by storing the working directory from which
the compile is invoked and the pathname to the file as specified in the invocation of the
compiler. The pathname may be either a complete pathname or a relative pathname.
Referencing Source Files with Location Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
Procedure
1. Set the environment variable MGC_LOCATION_MAP to the path of your location map
file.
2. Specify the mappings from physical pathnames to logical pathnames:
$SRC
/home/vhdl/src
/usr/vhdl/src
$IEEE
/usr/questasim/ieee
Pathname Syntax
The logical pathnames must begin with $ and the physical pathnames must begin with /. The
logical pathname is followed by one or more equivalent physical pathnames. Physical
pathnames are equivalent if they refer to the same physical directory (they just have different
pathnames on different systems).
For mapping from a logical pathname back to the physical pathname, Questa SIM expects an
environment variable to be set for each logical pathname (with the same name). Questa SIM
reads the location map file when a tool is invoked. If the environment variables corresponding
to logical pathnames have not been set in your shell, Questa SIM sets the variables to the first
physical pathname following the logical pathname in the location map. For example, if you
don't set the SRC environment variable, Questa SIM will automatically set it to “/home/vhdl/
src”.
This appendix describes the messages and status information that Questa SIM displays in the
Transcript window.
Message System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
Suppression of Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800
Error Messages from the sccom Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Enforcing Strict 1076 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Message System
The Questa SIM message system helps you identify and troubleshoot problems while using the
application. The messages display in a standard format in the Transcript window.
Accordingly, you can also access them from a saved transcript file (see Saving the Transcript
File for more details).
Message Format
The format for messages consists of several fields.
The fields for a given message appear as:
• Tool — indicates which Questa SIM tool was being executed when the message was
generated. For example, tool could be vcom, vdel, vsim, and so forth.
• Group — indicates the topic to which the problem is related. For example group could
be PLI, VCD, and so forth.
Example
# ** Error: (vsim-PLI-3071) ./src/19/testfile(77): $fdumplimit : Too few
arguments.
% verror 3071
Message # 3071:
Not enough arguments are being passed to the specified system task or
function.
• Use the -error, -fatal, -note, -suppress, and -warning arguments to sccom, vcom, vlog,
vopt, or vsim. See the command descriptions in the Reference Manual for details on
those arguments.
• Use the suppress command.
• Set a permanent default in the [msg_system] section of the modelsim.ini file. See
modelsim.ini Variables for more information.
Related Topics
Suppression of Warning Messages
5. Review the previous line for a malformed token or missing semicolon (;) or other ending
bracket and correct as needed.
6. Review the specific line to ensure the syntax is legal based on the BNF of the language
used and correct as needed.
7. Run the command again and repeat these steps for any further messages.
vcom -nowarn 1
Alternatively, warnings may be disabled for all compiles via the Main window Compile >
Compile Options menu selections or the modelsim.ini file (see modelsim.ini Variables).
1 = unbound component
2 = process without a wait statement
3 = null range
4 = no space in time literal
5 = multiple drivers on unresolved signal
6 = VITAL compliance checks ("VitalChecks" also works)
7 = VITAL optimization messages
8 = lint checks
9 = signal value dependency at elaboration
10 = VHDL-1993 constructs in VHDL-1987 code
11 = PSL warnings
13 = constructs that coverage can’t handle
14 = locally static error deferred until simulation run
These numbers are unrelated to vcom arguments that are specified by numbers, such as vcom -
87 – which disables support for VHDL-1993 and 2002.
11 = PSL warnings
12 = non-LRM compliance in order to match other product behavior
13 = constructs that coverage can’t handle
15 = SystemVerilog assertions using local variable
Alternatively, you can use the +nowarn<CODE> argument with the vlog command to suppress
a specific warning message. Warning messages that can be disabled this way contain the
<CODE> string in square brackets, [ ].
For example:
vlog +nowarnDECAY
vopt -nowarn 1
Alternatively, you can disable warnings for all compiles by choosing Compile > Compile
Options from the main menu in the Main window or by editing the modelsim.ini file (see
modelsim.ini Variables).
1 = unbound component
2 = process without a wait statement
3 = null range
4 = no space in time literal
5 = multiple drivers on unresolved signal
6 = VITAL compliance checks (“VitalChecks” also works)
7 = VITAL optimization messages
8 = lint checks
9 = signal value dependency at elaboration
10 = VHDL-1993 constructs in VHDL-1987 code
11 = PSL warnings
12 = non-LRM compliance in order to match other product behavior
13 = constructs that coverage can’t handle
14 = locally static error deferred until simulation run
15 = SystemVerilog assertions using local variable
Or, you can use the +nowarn<CODE> argument with the vopt command to suppress a specific
warning message. Warnings that can be disabled include the <CODE> name in square brackets
in the warning message. For example:
vopt +nowarnDECAY
vsim +nowarnTFMPC
Exit Codes
When Questa SIM exits a process, it displays a numerical exit code in the Transcript window.
Each code corresponds to a status condition of the process or operation.
Table C-1 lists the exit codes used by Questa SIM commands, processes, and languages.
Miscellaneous Messages
This section describes miscellaneous messages that may appear for various Questa SIM
commands, processes, or design languages.
• Description — Questa SIM was unable to locate a C compiler to compile the DPI
exported tasks or functions in your design.
• Suggested Action —Make sure that a C compiler is visible from where you are running
the simulation.
• Description — Questa SIM reports these warnings if you use the -lint argument to vlog.
It reports the warning for any NULL module ports.
• Suggested action — If you want to suppress this warning, do not use the -lint argument.
Lock message
waiting for lock by user@user. Lockfile is <library_path>/_lock
• Description — Questa SIM creates a _lock file in a library when you begin a
compilation into that library; it is removed when the compilation completes. This
prevents simultaneous updates to the library. If a previous compile did not terminate
properly, Questa SIM may fail to remove the _lock file.
• Suggested action — Manually remove the _lock file after making sure that no one else
is actually using that library.
• Description — Questa SIM displays this message when you use the -check_synthesis
argument to vcom. This warning occurs for any signal that is read by the process but is
not in the sensitivity list.
• Suggested action — There are cases where you may purposely omit signals from the
sensitivity list even though they are read by the process. For example, in a strictly
sequential process, you may prefer to include only the clock and reset in the sensitivity
list because it would be a design error if any other signal triggered the process. In such
cases, your only option is to omit the -check_synthesis argument.
• Description — This message typically occurs when the base file was not included in a
Linux installation. When you install Questa SIM, you need to download and install 3
files from the ftp site. These files are:
questasim-base.mis
questasim-docs.mis
install.<platform>
If you install only the <platform> file, you will not get the Tcl files that are located in the
base file.
This message could also occur if the file or directory was deleted or corrupted.
• Suggested action — Reinstall Questa SIM with all three files.
• Description — This warning occurs when an instantiation has fewer port connections
than the corresponding module definition. The warning does not necessarily mean
anything is wrong; it is legal in Verilog to have an instantiation that does not connect all
of the pins. However, someone that expects all pins to be connected would like to see
such a warning.
The following examples demonstrate legal instantiations that will and will not cause the
warning message.
o Module definition
module foo (a, b, c, d);
o Instantiation that does not connect all pins but will not produce the warning
foo inst1(e, f, g, ); // positional association
foo inst1(.a(e), .b(f), .c(g), .d()); // named association
o Instantiation that does not connect all pins but will produce the warning
foo inst1(e, f, g); // positional association
foo inst1(.a(e), .b(f), .c(g)); // named association
o Any instantiation above will leave pin d unconnected but the first example has a
placeholder for the connection. Another example is:
foo inst1(e, , g, h);
foo inst1(.a(e), .b(), .c(g), .d(h));
• Suggested actions —
o Check for an extra comma at the end of the port list. For example:
model(a,b,)
The extra comma is legal Verilog, but it implies that there is a third port connection
that is unnamed.
o If you are purposefully leaving pins unconnected, you can disable these messages
using the +nowarnTFMPC argument to vsim.
transcript/vsim output:
# ** Error: VSIM license lost; attempting to re-establish.
# Time: 5027 ns Iteration: 2
# ** Fatal: Unable to kill and restart license process.
# Time: 5027 ns Iteration: 2
• Description — Questa SIM queries the license server for a license at regular intervals.
Usually a “License Lost” error message indicates that network traffic is high, and
communication with the license server times out.
• Suggested action — Any action you can take to improve network communication with
the license server has a chance of solving or decreasing the frequency of this problem.
• Description — Questa SIM could not locate the libswift entry and therefore could not
link to the Logic Modeling library.
• Suggested action — Uncomment the appropriate libswift entry in the [lmc] section of
the modelsim.ini or project .mpf file. See VHDL SmartModel Interface for more
information.
• Description — Questa SIM has ended the simulation after 10000000 iterations in a
zero-delay oscillation. The IterationLimit modelsim.ini variable sets the number of
iterations before issuing the error.
• Suggested action — Follow these steps to find and debug the zero-delay loop causing
the error.
1. Re-run vopt with +acc to open full visibility to the design.
2. Re-run vsim with +autofindloop.
This will produce the vsim-3601 error again, but this time with information about zero-
delay loops.
# ** Error: (vsim-3601) Iteration limit reached at time 132025 ps.
3. Use this information to debug any loops in your design. The following are potential
coding techniques that lead to zero-delay loops:
o A missing or incorrectly applied SDF annotation to a netlist.
o An RTL design with an asynchronous feedback loop with no delays.
o Processes without wait statements or sensitivity lists, for example:
a <= not b;
b <= not a;
This section describes error messages that may be associated with Questa SIM when using the
sccom command.
o The order in which you place the -link option within the sccom -link command is
critical. Make sure you have used it appropriately. See sccom for syntax and usage
information. See Misplaced -link Option for further explanation of error and
correction.
• Meaning — The most common type of error found during sccom -link operation is the
multiple symbol definition error. This typically arises when the same global symbol is
present in more than one .o file. Several causes are likely:
o A common cause of multiple symbol definitions involves incorrect definition of
symbols in header files. If you have an out-of-line function (one that isn’t preceded
by the “inline” keyword) or a variable defined (that is, not just referenced or
prototyped, but truly defined) in a .h file, you can't include that .h file in more than
one .cpp file.
o Another cause of errors is due to Questa SIM’s name association feature. The name
association feature automatically generates .cpp files in the work library. These files
include your header files. Thus, while it might appear as though you have included
your header file in only one .cpp file, from the linker’s point of view, it is included in
multiple .cpp files.
• Suggested action — Make sure you don’t have any out-of-line functions. Use the
“inline” keyword. See Multiple Symbol Definitions.
• Type conversion between array types, where the element subtypes of the arrays do not
have identical constraints.
• “Extended identifier terminates at newline character (0xa).”
• “Extended identifier contains non-graphic character 0x%x.”
• “Extended identifier \"%s\" contains no graphic characters.”
• “Extended identifier \"%s\" did not terminate with backslash character.”
• “An abstract literal and an identifier must have a separator between them.”
This is for forming physical literals, which comprise an optional numeric literal,
followed by a separator, followed by an identifier (the unit name). Warning is level 4,
which means “-nowarn 4” will suppress it.
• In VHDL 1993 or 2002, a subprogram parameter was declared using VHDL 1987
syntax (which means that it was a class VARIABLE parameter of a file type, which is
the only way to do it in VHDL 1987 and is illegal in later VHDLs). Warning is level 10.
• “Shared variables must be of a protected type.” Applies to VHDL 2002 only.
• Expressions evaluated during elaboration cannot depend on signal values. Warning is
level 9.
• “Non-standard use of output port '%s' in PSL expression.” Warning is level 11.
• “Non-standard use of linkage port '%s' in PSL expression.” Warning is level 11.
• Type mark of type conversion expression must be a named type or subtype, it can't have
a constraint on it.
• When the actual in a PORT MAP association is an expression, it must be a (globally)
static expression. The port must also be of mode IN.
• The expression in the CASE and selected signal assignment statements must follow the
rules given in Section 8.8 of the IEEE Std 1076-2002. In certain cases we can relax these
rules, but -pedanticerrors forces strict compliance.
• A CASE choice expression must be a locally static expression. We allow it to be only
globally static, but -pedanticerrors will check that it is locally static. Same rule for
selected signal assignment statement choices. Warning level is 8.
• When making a default binding for a component instantiation, Questa SIM's non-
standard search rules found a matching entity. Section 5.2.2 of the IEEE Std 1076-2002
describes the standard search rules. Warning level is 1.
• Both FOR GENERATE and IF GENERATE expressions must be globally static. We
allow non-static expressions unless -pedanticerrors is present.
• When the actual part of an association element is in the form of a conversion function
call [or a type conversion], and the formal is of an unconstrained array type, the return
type of the conversion function [type mark of the type conversion] must be of a
constrained array subtype. We relax this (with a warning) unless -pedanticerrors is
present when it becomes an error.
• OTHERS choice in a record aggregate must refer to at least one record element.
• In an array aggregate of an array type whose element subtype is itself an array, all
expressions in the array aggregate must have the same index constraint, which is the
element's index constraint. No warning is issued; the presence of -pedanticerrors will
produce an error.
• Non-static choice in an array aggregate must be the only choice in the only element
association of the aggregate.
• The range constraint of a scalar subtype indication must have bounds both of the same
type as the type mark of the subtype indication.
• The index constraint of an array subtype indication must have index ranges each of
whose both bounds must be of the same type as the corresponding index subtype.
• When compiling VHDL 1987, various VHDL 1993 and 2002 syntax is allowed. Use
-pedanticerrors to force strict compliance. Warnings are all level 10.
• For a FUNCTION having a return type mark that denotes a constrained array subtype, a
RETURN statement expression must evaluate to an array value with the same index
range(s) and direction(s) as that type mark. This language requirement (Section 8.12 of
the IEEE Std 1076-2002) has been relaxed such that Questa SIM displays only a
compiler warning and then performs an implicit subtype conversion at run time.
To enforce the prior compiler behavior, use vcom -pedanticerrors.
The Questa Verification IP library contains a number of industry standard protocols that you
can use to verify legal protocol activity.
The activity may be between a transaction-level model (TLM) and a wire-level models (WLM),
or activity between WLMs. Each QVIP library protocol has built-in error-checking to cover a
vast range of situations whereby the activity on the protocol signals may be illegal. If illegal
activity occurs, then a QuestaSim 60000 series error code specific to the protocol is normally
reported, along with an explanation of the illegality and a reference to the protocol specification
to assist in the debugging of the testbench or DUT.
There may be a circumstance when a QuestaSim 60000 series error is not reported as a result of
illegal protocol activity. In an attempt to assist in the debugging of such errors, the Questa
Verification IP reports 50000 series errors instead. These 50000 series errors are not protocol
specific and report internal errors found within the Questa Verification IP due to the illegal
protocol activity. To completely understand the meaning of each error would require intimate
knowledge of the Questa Verification IP internal workings, but an understanding of the basic
concepts and terminology used within the 50000 series error messages may help to speed up the
process of debugging your testbench and DUT.
60000 series error protocol specific documentation is supplied with the Questa Verification IP
software (see “Accessing 60000 Series Error Documentation”).
Note
It is more usual for a QuestaSIM 60000 series protocol specific error to be reported than an
internal Questa Verification IP 50000 series error.
This appendix provides an explanation of both the concepts behind the Questa Verification IP
50000 series errors, and the terminology used in the reporting of those errors. The aim of doing
so is to assist you in the debugging of your testbench and DUT.
Procedure
1. Open the QVIP documentation in your web browser using:
<QVIP_install_directory>/docs/index.html
This opens the InfoHub for the QVIP library (Figure D-1).
Figure D-1. InfoHub for QVIP Library
2. Choose the documentation set of the QVIP protocol family you want by clicking on the
appropriate selection on the left hand column titled "Choose Scope," for example,
“AMBA Family QVIPs.”
3. Choose the documentation of the QVIP protocol by clicking on the appropriate item
under the section titled "API Reference Information," for example, AHB QUIP API
Reference.
4. Select "Assertions" on the left hand column (Figure D-3) to see the list of 6000 series
messages.
Figure D-3. Select Assertions
Another example may be a TLM 'generating' protocol activity through a Questa Verification IP
to a WLM DUT. The 'generation' of the wire-level activity may not be allowed to happen within
a certain time frame causing an internal time-out to occur resulting in a 50000 series error. In
return the DUT may cause signal-level activity to occur on the protocol signals to be
'recognized' into completed transactions by the Questa Verification IP that subsequently fail due
to illegal protocol signal activity.
Related Topics
Verifying Designs with Questa Verification IP Library Components
Related Topics
Questa Verification IP Transaction Details in Transaction View Window
Concepts Involved in the Errors
Related Topics
Parents and Children
Questa Verification IP Transaction Details in Transaction View Window
Communication Semantics
Transaction Types and Time Queue ID
Communication Semantics
A Questa Verification IP transmits and receives transactions using communication semantics.
These semantics control the blocking and non-blocking of subsequent transactions being
transmitted and received to model various protocol scenarios.
• Activated Transactions semantics are used for the transmission and reception of bi-
directional MVC_Transaction.
• Uni-directional Transmission of Transactions semantics are used for the transmission of
uni-directional MVC_Message and MVC_Stripe transactions.
• Uni-directional Reception of Transactions semantics are used for the reception of uni-
directional MVC_transaction, MVC_Message and MVC_Stripe transactions.
The communication semantic of a transaction instance may be reported within a 50000 series
error message which can be used to understand if the transaction is being transmitted, received,
or is bi-directional transaction. Communication semantics may be further controlled with any
Now and Using constraints that are also reported within an error message.
Deleted Transactions
A transaction has a simulation ‘start time’ and an ‘end time’. The ‘end time’ indicates that the
transaction has completed. If a transaction has completed and it is subsequently deemed to be
illegal protocol, then the Questa Verification IP can make a decision about whether to tidy up
internally in a silent manner. A ‘volatile’ mechanism may be applied to the transaction so that
the Questa Verification IP will report an error message instead of silently deleting the
transaction.
Another mechanism the Questa Verification IP uses to tidy up internally is ‘throw’ and ‘catch’.
For example, it is used when a reset condition is detected part way through the transmission of a
transaction. The transaction is ‘thrown’ internally and an attempt is made to ‘catch’ it to prevent
an error message from being reported if successfully caught.
Related Topics
Questa Verification IP Transaction Details in Transaction View Window
Transaction Types and Time Queue ID
connected will monitor wire-level signals changes, and attempt to recognize them into
transactions.
Related Topics
Concepts Involved in the Errors
TLM-connected
WLM-connected
Procedure
1. To enable the recording of deleted instances:
2. Right-click the transaction-stream name in the Wave window. This opens the
‘Transaction-Stream Properties window.
3. Select the ‘MVC Logging’ tab.
4. Select the ‘Deletion Logging Enabled’ check box.
For example:
The information given in the error message tells us that the transaction stream
write_command_issue has a transaction instance with a TQ_id of 474, received by the external
method write_cmd_ReceivedReceivingReceive_SystemVerilog with TQ_ID of ‘1’, has gone into
error. Consequently the Questa Verification IP has attempted to recognize the received
write_command_issue but has deemed it to be illegal with regard to the DDR2 protocol. The
start and end times of the illegal write_command_issue instance with a TQ_id of 474 are also
reported.
The simulation ‘start’ and ‘end’ times of the transaction instance TQ_id of 474 assist in finding
the instance in the Wave window. Selecting the transaction instance also highlights ‘parent ‘and
‘child’ relationships. This may give a clue to why this particular instance is illegal within the
protocol specification.
TQ Id Related Errors
Context: The errors in this section are related to the transaction queue id.
Where more than one level of abstraction exists, a ‘relationship’ exists between the different
levels. In the example shown in Figure D-6, a ‘Transfer’ transaction is related to the ‘Address’
and ‘Data’ transactions that communicate the address and data information for that transfer.
These transactions in turn are related to the individual signals which communicate the
equivalent information across the bus. Questa Verification IPs maintain these relationships,
allowing for simulation and debugging across the different levels of abstraction.
The term ‘parent’ describes a related transaction at a higher level of abstraction, and ‘child’
describes a related transaction, or signal, at a lower level of abstraction. Each transaction may
have many related ‘child’ and ‘parent’ transactions. In Figure D-6, the ‘Transfer’ transaction
has two children: an ‘Address’ transaction and a ‘Data’ transaction. It also has one parent:
‘Burst Transfer’. Each ‘Burst Transfer’ transaction can have multiple ‘Transfer’ transactions as
children.
The translation from the signal level up to the transaction level is termed ‘recognition’, causing
equivalent high level activity from low level activity. During the translation ‘parent’
transactions are ‘recognized’ up to the highest transaction level as shown in Figure D-8. At the
bottom of the tree activity on wires ‘CMD’ and ‘ADDRESS’ causes stripe ‘request’ to be
recognized. Activity on wire ‘WDATA’ causes stripe ‘write_data’ to be recognized.
Recognized stripes ‘request’ and ‘write_data’ cause message ‘write’ to be recognized, and so
on.
The ‘generation’ and ‘recognition’ of transactions and signal activity can be viewed within the
Wave window. The color of a transaction object indicates what caused it to exist, if it was
generated from a parent object, or recognized from a child object(s). Refer to “What the Colors
Mean” in Chapter 13 of the Questa SIM User’s Manual for more information.
Knowing how a transaction instance came into existence can assist in the debugging of your
testbench or DUT. For example, Figure D-7 shows the message ‘write’ transaction in blue
because it has been created by a ‘communication semantic’. The generated child stripes
‘request’ and ‘write_data’ are shown in green, as are the generated wire activities ‘CMD’,
‘ADDRESS’ and ‘WDATA’.
Similarly, Figure D-8 shows the wires ‘CMD’, ‘ADDRESS’ and ‘WDATA’ in blue as they
have been created by signal level activity. The recognized parent stripes ‘request’ and
‘write_data’ are shown in light blue, as is the recognized ‘parent’ of message ‘write’.
Understanding Deletions
A transaction instance that completes can subsequently fail to be a parent or child of other
transaction instances, for reasons that are internal to the Questa Verification IP. These ‘failures’
are a part of the normal internal operation of a Questa Verification IP and can be displayed as
‘deleted’ transaction instances in the Wave window. These failed transaction instances have no
detrimental effect on the operation of a Questa Verification IP, but it is useful to know of their
existence when debugging your testbench and DUT.
By default ‘deleted’ transaction instances are hidden in the Wave window. They can be
displayed by right clicking on the transaction stream name in the Wave window and selecting
‘Transaction Properties...’ from the menu to open the Transaction-Stream Properties window.
Selecting the ‘MVC Logging’ tab presents the ‘Deletion Logging Enabled’ check box to enable
the logging of deleted transaction instances for the selected transaction stream.
Note
It is advisable to enable only the transaction stream logging of deleted instances of interest
to assist in debugging. In common with logging any transaction stream information it will
consume additional simulation resources.
Note
Each communication semantic is described below together with a diagram to help
with the explanation. In the diagrams “A” represents a thread of activity that is
happening within a Questa Verification IP prior to the use of the semantic (up to the
dashed line) and “B” represents a thread of activity that happens immediately after the
semantic has completed. The gap between “A” and “B” represents any suspension in
thread activity due to the semantics operation.
Activated Transactions
An “activated” Questa Verification IP transaction is bi-directional and supports the transmission
of the MVC_transaction type between a Questa Verification IP and a DUT. The Questa
Verification IP provides the outbound information, with return information provided by the
DUT to complete the transaction.
There are three different transmission modes, Activate, Activating, and Activates, that a Questa
Verification IP can use to transmit a transaction. Each mode provides a different blocking
mechanism for the internal queuing and transmission of subsequent transactions.
Note
If a QuestaSim 50000 series error reports that an item is “activated” within its error
message, then it can be any of the Activate, Activating, and Activates modes.
Activate
A “wait until transaction transmission complete” mechanism for a bi-directional
MVC_transaction. The Questa Verification IP will internally queue the current transaction and
block the transmission of subsequent transactions until the current transaction has completed.
The start of a transaction is determined by the rules of the protocol and the resources available.
On completion of the transaction the Questa Verification IP will permit the queuing and
transmission of subsequent transactions.
Activating
A “wait until able to start transaction” mechanism for a bi-directional MVC_transaction. The
Questa Verification IP will internally queue the current transaction and block the transmission
of subsequent transactions until the current transaction has started. The start of a transaction is
determined by the rules of the protocol and the resources available.
Activates
A “fire and forget transaction” mechanism for a bi-directional MVC_transaction. The Questa
Verification IP internally queues the current transaction until it is able to be transmitted,
determined by the rules of the protocol and the resources available. The transmission of
subsequent transactions is permitted immediately.
Send
A “fire and forget transaction” mechanism for a uni-directional MVC_message or MVC_stripe
transactions. The Questa Verification IP internally queues the current transaction until it is able
to be transmitted, determined by the rules of the protocol and the resources available. The
transmission of subsequent transactions is permitted immediately.
Sending
A “wait until able to start transaction” mechanism for a uni-directional MVC_message or
MVC_stripe transactions. The Questa Verification IP will internally queue the current
transaction and block the transmission of subsequent transactions until the current transaction
has started. The start of a transaction is determined by the rules of the protocol and the resources
available.
Sent
A “wait until transaction transmission complete” mechanism for a uni-directional
MVC_message or MVC_Stripe transaction. The Questa Verification IP will internally queue
the current transaction and block the transmission of subsequent transactions until the current
transaction has completed. The start of a transaction is determined by the rules of the protocol
and the resources available. On completion the Questa Verification IP will permit the queuing
and transmission of subsequent transactions.
Receive
A “take the next to start transaction” mechanism for a bi-directional MVC_transaction, or uni-
directional MVC_message and MVC_Stripe transactions. The Questa Verification IP will wait
for a transaction to start, ignoring any currently active transactions. Once a transaction starts it
blocks the reception of subsequent transactions until the current transaction has completed.
Receiving
A “take the current or next transaction” mechanism for a bi-directional MVC_transaction, or
uni-directional MVC_message and MVC_Stripe transactions. The Questa Verification IP waits
for the current transaction to complete, blocking the reception of subsequent transactions.
Received
A “take whatever transaction is available” mechanism. The Questa Verification IP takes the
previous transaction that completed, not blocking the reception of subsequent transactions.
Now
If a transaction has to be transmitted at the same time that it is created within a Questa
Verification IP, according to the protocol, the ‘now’ constraining semantic is used to avoid the
transaction queuing internally. If the transaction cannot be transmitted immediately then an
error message is reported.
Using
The ‘using’ constraint is applied to reception semantics within a Questa Verification IP to
model situations where more than one internal resource wants to ‘receive’ the same transaction.
This may be an undesirable side-effect of the protocol, and that only one internal resource
should ‘receive’ the transaction leaving the other resources to wait to ‘receive’ subsequent
transactions.
Figure D-19 shows the ‘start time’ and ‘end time’ of an MVC_Stripe in relation to the protocol
signals. The simulation time at which the protocol permits the MVC_Stripe to start on the
protocol signals defines the ‘start time’. The ‘start time’ coincides with the ‘hold time’ after the
strobe point (in this case the rising edge of the clock signal CLK). The ‘end time’ coincides with
the ‘hold time’ after the following strobe point (in this case the next rising edge of the clock
signal CLK). For the generation and recognition of an MVC_Stripe the start and end time
definitions are the same.
Understanding Activities
Activities within a Questa Verification IP perform tasks and processes to ensure adherence to a
protocol specification, e.g. initialization routines, time-outs, etc. They may consume time, in
that their execution advances simulation time. They can also be timeless in that their execution
consumes no simulation time.
Activity Related Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840
WLM-connected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
TLM-connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
WLM-connected and TLM-connected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
TLM/WLM Related Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
WLM-connected
An interface end that is WLM-connected will monitor wire-level signals changes, and attempt
to recognize them into transaction objects. It expects an externally connected model to drive
wire-level signals:
• directly by SystemVerilog assign statements
• by calls to the XYZ_set_AWIRE_driver() task declared in the Questa Verification IP
interface (where the protocol is called XYZ, and it contains a wire called AWIRE).
A WLM-connected interface end should not attempt to drive a wire-level signal from the Questa
Verification IP as this may cause an ‘X’ to appear on the signal wire(s) due to a clash with the
drivers of the external wire-level model.
Note
Use WLM-connected for a Questa Verification IP interface end where it is connected to an
external model written in RTL code.
TLM-connected
An interface end that is TLM-connected drives the wire-level signals, as a consequence of a
transaction being generated within the Questa Verification IP. It expects an externally
connected model to:
• not attempt to cause signal-changes directly on the connected wires
o by using continuous assignments.
o by calls to the XYZ_set_AWIRE_driver() task declared in the Questa Verification IP
interface
An external model connected to a TLM-connected interface end should not attempt to drive a
wire-level signal as this may cause an ‘X’ to occur on the signal wire(s) due to a clash with the
drivers of the Questa Verification IP interface end.
Note
Use TLM-connected for a Questa Verification IP interface end where it is connected to an
external model written as a Transaction Level Model.
Note
Use both WLM-connected and TLM-connected for a Questa Verification IP interface end
where it is connected to an external model written as both a Transaction level model and an
RTL model.
This appendix describes the Questa SIM implementation of the Verilog interfaces:
• Verilog PLI (Programming Language Interface)
• VPI(Verilog Procedural Interface)
• SystemVerilog DPI (Direct Programming Interface).
These three interfaces provide a mechanism for defining tasks and functions that communicate
with the simulator through a C procedural interface. There are many third party applications
available that interface to Verilog simulators through the PLI (see Third Party PLI
Applications). In addition, you may write your own interface applications.
Implementation Information
This chapter describes only the details of using the Verilog interfaces with Questa SIM Verilog
and SystemVerilog.
• Questa SIM SystemVerilog implements DPI as defined in the IEEE Std 1800-2005.
• The PLI implementation (TF and ACC routines) as defined in IEEE Std 1364-2001 is
retained for legacy PLI applications. However, this interface was deprecated in IEEE
Std 1364-2005 and subsequent IEEE Std 1800-2009 (SystemVerilog) standards.
New applications should not rely on this functionality being present and should instead
use the VPI.
• VPI Implementation — The VPI is partially implemented as defined in the IEEE Std
1364-2005 and IEEE Std 1800-2005. The list of currently supported functionality can be
found in the following file:
<install_dir>/docs/technotes/Verilog_VPI.note
The simulator allows you to specify whether it runs in a way compatible with the IEEE
Std 1364-2001 object model or the combined IEEE Std 1364-2005/IEEE Std 1800-2005
object models. By default, the simulator uses the combined 2005 object models. This
control is accessed through the vsim -plicompatdefault switch or the PliCompatDefault
variable in the modelsim.ini file.
The following table outlines information you should know about when performing a
simulation with VPI and HDL files using the two different object models.
The various callback functions (checktf, sizetf, calltf, and misctf) are described in detail in the
IEEE Std 1364. The simulator calls these functions for various reasons. All callback functions
are optional, but most applications contain at least the calltf function, which is called when the
system task or function is executed in the Verilog code. The first argument to the callback
functions is the value supplied in the data field (many PLI applications don't use this field). The
type field defines the entry as either a system task (USERTASK) or a system function that
returns either a register (USERFUNCTION) or a real (USERREALFUNCTION). The tfname
field is the system task or function name (it must begin with $). The remaining fields are not
used by Questa SIM Verilog.
On loading of a PLI application, the simulator first looks for an init_usertfs function, and then a
veriusertfs array. If init_usertfs is found, the simulator calls that function so that it can call
mti_RegisterUserTF() for each system task or function defined. The mti_RegisterUserTF()
function is declared in veriuser.h as follows:
The storage for each usertf entry passed to the simulator must persist throughout the simulation
because the simulator de-references the usertf pointer to call the callback functions. We
recommend that you define your entries in an array, with the last entry set to 0. If the array is
named veriusertfs (as is the case for linking to Verilog-XL), then you don't have to provide an
init_usertfs function, and the simulator will automatically register the entries directly from the
array (the last entry must be 0). For example,
s_tfcell veriusertfs[] = {
{usertask, 0, 0, 0, abc_calltf, 0, "$abc"},
{usertask, 0, 0, 0, xyz_calltf, 0, "$xyz"},
{0} /* last entry must be 0 */
};
Alternatively, you can add an init_usertfs function to explicitly register each entry from the
array:
void init_usertfs()
{
p_tfcell usertf = veriusertfs;
while (usertf->type)
mti_RegisterUserTF(usertf++);
}
It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs
function.
Since PLI applications are dynamically loaded by the simulator, you must specify which
applications to load (each application must be a dynamically loadable library, see Compiling
and Linking C Applications for Interfaces). The PLI applications are specified as follows (note
that on a Windows platform the file extension would be .dll):
The various methods of specifying PLI applications can be used simultaneously. The libraries
are loaded in the order listed above. Environment variable references can be used in the paths to
the libraries in all cases.
simulation startup. Each registration routine should make one or more calls to
vpi_register_systf() to register user-defined system tasks and functions and vpi_register_cb() to
register callbacks. The registration routines must be placed in a table named
vlog_startup_routines so that the simulator can find them. The table must be terminated with a 0
entry.
Example E-1. VPI Application Registration
vpiHandle tmpH;
s_cb_data callback;
s_vpi_systf_data systf_data;
systf_data.type = vpiSysFunc;
systf_data.sysfunctype = vpiSizedFunc;
systf_data.tfname = "$myfunc";
systf_data.calltf = MyFuncCalltf;
systf_data.compiletf = MyFuncCompiletf;
systf_data.sizetf = MyFuncSizetf;
systf_data.user_data = 0;
tmpH = vpi_register_systf( &systf_data );
vpi_free_object(tmpH);
callback.reason = cbEndOfCompile;
callback.cb_rtn = MyEndOfCompCB;
callback.user_data = 0;
tmpH = vpi_register_cb( &callback );
vpi_free_object(tmpH);
callback.reason = cbStartOfSimulation;
callback.cb_rtn = MyStartOfSimCB;
callback.user_data = 0;
tmpH = vpi_register_cb( &callback );
vpi_free_object(tmpH);
}
void (*vlog_startup_routines[ ] ) () = {
RegisterMySystfs,
0 /* last entry must be 0 */
};
Loading VPI applications into the simulator is the same as described in Registering PLI
Applications.
• If an init_usertfs() function exists, then it is executed and only those system tasks and
functions registered by calls to mti_RegisterUserTF() will be defined.
• If an init_usertfs() function does not exist but a veriusertfs table does exist, then only
those system tasks and functions listed in the veriusertfs table will be defined.
• If an init_usertfs() function does not exist and a veriusertfs table does not exist, but a
vlog_startup_routines table does exist, then only those system tasks and functions and
callbacks registered by functions in the vlog_startup_routines table will be defined.
As a result, when PLI and VPI applications exist in the same application object file, they must
be registered in the same manner. VPI registration functions that would normally be listed in a
vlog_startup_routines table can be called from an init_usertfs() function instead.
Your C code must provide imported functions or tasks. An imported task must return an int
value, "1" indicating that it is returning due to a disable, or "0" indicating otherwise.
The default flow is to supply C/C++ files on the vlog command line. The vlog compiler will
automatically compile the specified C/C++ files and prepare them for loading into the
simulation. For example,
Optionally, DPI C/C++ files can be compiled externally into a shared library. For example, third
party IP models may be distributed in this way. The shared library may then be loaded into the
simulator with either the command line option -sv_lib <lib> or -sv_liblist <bootstrap_file>.
For example,
vlog dut.v
gcc -shared -Bsymbolic -o imports.so imports.c
vsim -sv_lib imports top -do <do_file>
The -sv_lib option specifies the shared library name, without an extension. A file extension is
added by the tool, as appropriate to your platform. For a list of file extensions accepted by
platform, see DPI File Loading.
You can also use the command line options -sv_root and -sv_liblist to control the process for
loading imported functions and tasks. These options are defined in the IEEE Std 1800-2005.
[For WINDOWS platform users:] If a DPI header is not being generated or used, you
need to manually attach DPI_DLLESPEC in front of all DPI routines. DPI_DLLESPEC
is a standard macro defined inside svdpi.h.
The generated DPI header flow is recommended. Failing to do the above will incur the
following warning at elab time:
# ** Warning: (vsim-3770) Failed to find user specified function
'foo' in DPI C/C++ source files.
This vlog command compiles all Verilog files and C/C++ files into the work library. The vsim
command automatically loads the compiled C code at elaboration time.
It is possible to pass custom C compiler flags to vlog using the -ccflags option. vlog does not
check the validity of option(s) you specify with -ccflags. The options are directly passed on to
the compiler, and if they are not valid, an error message is generated by the C compiler.
You can also specify C/C++ files and options in a -f file, and they will be processed the same
way as Verilog files and options in a -f file.
It is also possible to pass custom C/C++ linker flags to vsim using the -ldflags option. For
example,
The qverilog command also accepts C/C++ files on the command line. It works similarly to
vlog, but automatically invokes vsim at the end of compilation.
To determine if you have this type of name aliasing problem, consult the C library
documentation (either the online help or man pages) and look for function names that match any
of your export function names. You should also review any other shared objects linked into
your simulation and look for name aliases there. To get a comprehensive list of your export
functions, you can use the vsim -dpiheader option and review the generated header file.
If you are using an external compilation flow, make sure to use -Bsymbolic on the GCC link
line. For more information, see “Correct Linking of Shared Libraries with -Bsymbolic”.
package cmath;
import "DPI-C" function real sin(input real x);
import "DPI-C" function real sqrt(input real x);
endpackage
package fli;
import "DPI-C" function mti_Cmd(input string cmd);
endpackage
module top;
import cmath::*;
import fli::*;
int status, A;
initial begin
$display("sin(0.98) = %f", sin(0.98));
$display("sqrt(0.98) = %f", sqrt(0.98));
status = mti_Cmd("change A 123");
$display("A = %1d, status = %1d", A, status);
end
endmodule
To simulate, you would simply enter a command such as: vsim top.
Precompiled packages are available with that contain import declarations for certain commonly
used C calls.
<installDir>/verilog_src/dpi_cpack/dpi_cpackages.sv
You do not need to compile this file, it is automatically available as a built-in part of the
SystemVerilog simulator.
Most of the overhead associated with argument passing is eliminated if the following conditions
are met:
This feature is only supported when the vopt flow is used (see Optimizing Designs with vopt).
On occasion, the tool may not be able to resolve type parameters while building the optimized
design, in which case the workaround is to rewrite the function without using parameterized
types. The LRM rules for tf signature matching apply to the finally resolved value of type
parameters. See the IEEE Std 1800-2005, Section 26.4.4 for further information on matching
rules.
See DpiOutOfTheBlue for information about debugging support for a SystemC method or a
SystemC thread.
The following is an example in which PLI code calls a SystemVerilog export function:
vlog test.sv
gcc -shared -o pli.so pli.c
vsim -pli pli.so top -dpioutoftheblue 1
vlog test.sv
sccom test.cpp
sccom -link
vsim top sc_top
One restriction applies: only Verilog functions may be called out-of-the-blue. It is illegal to call
Verilog tasks in this way. The simulator issues an error if it detects such a call.
calling code on the vsim command line after you place the -gblso argument for the called code.
This is because vsim loads the files in the specified order and you must load called code before
calling code in all cases.
Circular references aren't possible to achieve. If you have that kind of condition, you are better
off combining the two shared objects into a single one.
For more information about this topic please refer to the section "Loading Shared Objects with
Global Symbol Visibility."
The usual PLI/VPI symbol (calltf, misctf, checktf, size, and so on) registration mechanisms are
still required when using PLI Autocompile:
The set of all PLI and DPI C/C++ files you submit to the vlog command will be aggregated into
a single autocompile shared object that is loaded at the time you execute vsim.
You can use the method of using a veriusertfs[] table, which declares and registers all system
tasks. The vpi_register_systf() mechanism can be used as well. However, if the veriusertfs[]
registration mechanism is still used, there can only be one veriusertfs[] table in the entire set of
PLI C/C++ files. Otherwise a multiple-defined symbol error will occur upon execution of the
vsim command.
The usual PLI and VPI library registration mechanisms are not required when using PLI
Autocompile, specifically:
The options specified with %CELL, %TASK or <du> are design unit specific and those
specified with <instance> are instance specific.
Access specifications specified for each system task are considered to be independent of each
other and cannot remove an earlier applied access to a certain region. Similarly, the command-
line access specifications are considered to be independent of PLI catalog file access
specifications. The effects of command-line options won't be removed by PCAT options.
or
$<name> <access_specification>
Parameters
• PLI Catalog File Line
Each line of the PCAT File may include the following arguments
• PLI_Linkage
You can use these keys or key/value pairs on your PLI Catalog File Line
• access_specification
The access_specification takes the form:
acc{ = | += | -= | :=}<accesscodes>[:<objectselection>]
Argument Description
acc A literal string that starts the access specification
Argument Description
{ = | += | -= | :=} Defines how to treat the <accesscodes> argument.
• = — Adds the <accesscodes> to the selected objects.
• += — Adds the specified <accesscodes> to the selected objects.
• -= — Removes the specified <accesscodes> from the selected
objects.
• := — Replaces any existing <accesscodes> with the specified
<accesscodes> on the selected objects.
<accesscodes> Specifies any access rules, in a comma-separated list, where the
arguments include:
• r — Specifies read access.
• w — Specifies write access
• c — Specifies connectivity access (such as callback, bind, pdu href.).
:<objectselection> Specifies the objects to which the access information applies. Note the
preceding colon (:) character.
You can specify multiple design units within a comma-separated list,
where the arguments can be:
• %CELL — literal string that allows the systf to access objects within
library cells, i.e. modules defined within the scope of a `celldefine
compiler directive, or Verilog modules picked up by vlog -y or vlog
-v.
• %TASK — literal string that identifies all instances of du's that
contain the specified user-defined system task or function. It is only
valid on a line that contains PLI linkage for a specific systf.
• [<du>][+|,<hierlevel>] — specifies the design unit and any recursion
rules. Note that there is no space between the <du> and subsequent
argument.
• <du> — design unit name, that can take one of these forms:
<instance>
[<libname>.]<primary>[(secondary)]
Examples
• This example defines a system task that will collect design-wide statistics. It can visit
the entire design and perform read accesses on all values.
• This example defines a system task that implements an FPU model. It can read and write
all signals in instances of the module where it is declared. It can also set callbacks on
signals in those instances.
$fpumodel call=fpucall check=fpucheck acc+=r,w,c:%TASK
• This example defines a system function that adds bits together. It has no right to access
any design objects. It will work purely based on the arguments it is passed during
simulation.
$addbits call=addbits size=32
• This example adds read access to top1 and 3 levels of hierarchy underneath it. It adds
read access to top2 and all of its descendants. The access is unconditionally performed,
as if "vopt -access=r+top1+3+top2." was specified on the command line.
acc=r:top1,3,top2+
where $<name> is the name of the system task or function and <access_specification>
defines the access requirements for the systf to interact with the design
Refer to “PLI Catalog File Reference” for more information.
2. Specify your PCAT file by using the -P argument to the vopt command (note that this
argument is case-sensitive).
vopt <standard_arguments> -P filename.pcat
The vopt command reads the access specifications portion of the PCAT file, and it
ignores the linkage specifications.
3. (optional) Specify your PCAT file to use the linkage specifications, by using the -P
argument to the vsim command (note that this argument is case-sensitive).
vsim <standard_arguments> -P filename.pcat
If you are using the 2-step flow, vsim automatically forwards the PCAT file to vopt.
Examples
You can run a simulation, such that a system task $printreg can print values of all the registers
in the scope in which it is instantiated. You just need to create a PCAT file that allows the
implementer of that system task to request the defined access option. For example, if
filename.pcat file contains the line:
$printreg acc=read:%TASK
read access is applied to only the scopes (if any), in which this system task is instantiated. If the
implementer wants to print values of all the registers in that scope and those under this scope,
you could rewrite the line by appending a +, as shown:
$printreg acc=read:%TASK+
The vopt command reads the access specifications portion of the PCAT file, and it
ignores the linkage specifications.
3. (optional) Specify your PCAT file to use the linkage specifications, by using the -P
argument to the vsim command (note that this argument is case-sensitive).
vsim <standard_arguments> -P filename.pcat
If you are using the 2-step flow, vsim automatically forwards the PCAT file to vopt.
Examples
• For this example:
vlib work
vlog test.sv pliapp.c -ccflags "-I /u/apps/include"
vsim -vopt top -c -P pliapp.pcat -do "run -all; quit -f"
Although compilation and simulation switches are platform-specific, loading shared libraries is
the same for all platforms. For information on loading libraries for HDL interface see PLI and
VPI File Loading. For DPI loading instructions, see DPI File Loading.
app.so
If app.so is not in your current directory, you must tell the OS where to search for the shared
object. You can do this one of two ways:
• Add a path before app.so in the command line option or control variable (The path may
include environment variables.)
• Put the path in a UNIX shell environment variable:
LD_LIBRARY_PATH_32= <library path without filename> (for 32-bit)
or
When using the -Bsymbolic option, the linker may warn about symbol references that are not
resolved within the local shared library. It is safe to ignore these warnings, provided the
symbols are present in other shared libraries or the vsimk executable. (An example of such a
warning would be a reference to a common API call such as vpi_printf()).
Windows Platforms — C
Windows platforms for C are supported for Microsoft Visual Studio and MinGW.
• Microsoft Visual Studio 2013
Refer to the section “Creating .dll or .exe Files using Compiled .lib files on Windows
Platforms” in the Installation and Licensing Guide for information on using Microsoft
Visual Studio 2013.
For 32-bit:
cl -c -I<install_dir>\questasim\include app.c
link -dll -export:<init_function> app.obj
<install_dir>\win32\mtipli.lib -out:app.dll
For 64-bit:
cl -c -I<install_dir>\questasim\include app.c
link -dll -export:<init_function> app.obj
<install_dir>\win64\mtipli.lib -out:app.dll
For the Verilog PLI, the <init_function> should be "init_usertfs". Alternatively, if there
is no init_usertfs function, the <init_function> specified on the command line should be
"veriusertfs".
For the Verilog VPI, the <init_function> should be "vlog_startup_routines". These
requirements ensure that the appropriate symbol is exported, and thus Questa SIM can
find the symbol when it dynamically loads the DLL.
If you need to run the profiler (see Profiling Performance and Memory Use) on a design
that contains interface code, add these two switches to the link commands shown above:
/DEBUG /DEBUGTYPE:COFF
These switches add symbols to the .dll that the profiler can use in its report.
If you have Cygwin installed, make sure that the Cygwin link.exe executable is not in
your search path ahead of the Microsoft Visual Studio 2013 link executable. If you
mistakenly bind your dll's with the Cygwin link.exe executable, the .dll will not function
properly. It may be best to rename or remove the Cygwin link.exe file to permanently
avoid this scenario.
• MinGW
For 32-bit:
gcc -c -I<install_dir>\include app.c
gcc -shared -Bsymbolic -o app.dll app.o -L<install_dir>\win32
-lmtipli
The Questa SIM tool requires the use of the MinGW gcc compiler rather than the
Cygwin gcc compiler. Remember to add the path to your gcc executable in the Windows
environment variables.
Refer to SystemC Supported Platforms for more information.
For 64-bit:
gcc -c -I<install_dir>\include app.c
gcc -shared -Bsymbolic -o app.dll app.o -L<install_dir>\win64
-lmtipli
Linux Platforms — C
If your HDL interface application uses anything from a system library, you must specify that
library when you link your HDL interface application.
• For 32-bit — using the standard C library, when linking the shared object:
gcc -c -I<install_dir>/questasim/include app.c
gcc -shared -Bsymbolic -o app.so app.o -lc
The compiler switch -freg-struct-return must be used when compiling any FLI
application code that contains foreign functions that return real or time values.
• For 64-bit:
gcc -c -fPIC -I<install_dir>/questasim/include app.c
gcc -shared -Bsymbolic -o app.so app.o
To compile 64-bit systems for 32-bit operation, specify the -m32 argument on both the
compile and link gcc command lines.
extern "C"
{
<HDL interface application function prototypes>
}
The header files veriuser.h, acc_user.h, and vpi_user.h, svdpi.h, and dpiheader.h already
include this type of extern. You must also put the HDL interface shared library entry point
(veriusertfs, init_usertfs, or vlog_startup_routines) inside of this type of extern.
You must also place an ‘extern “C”’ declaration immediately before the body of every import
function in your C++ source code, for example:
extern "C"
int myimport(int i)
{
vpi_printf("The value of i is %d\n", i);
}
The following platform-specific instructions show you how to compile and link your
HDL interface C++ applications so that they can be loaded by Questa SIM.
Although compilation and simulation switches are platform-specific, loading shared libraries is
the same for all platforms. For information on loading libraries, see DPI File Loading.
For 64-bit:
cl -c [-GX] -I<install_dir>\questasim\include app.cxx
link -dll -export:<init_function> app.obj
<install_dir>\questasim\win64\mtipli.lib /out:app.dll
These switches add symbols to the .dll that the profiler can use in its report.
If you have Cygwin installed, make sure that the Cygwin link.exe executable is not in
your search path ahead of the Microsoft Visual C link executable. If you mistakenly bind
your dll's with the Cygwin link.exe executable, the .dll will not function properly. It may
be best to rename or remove the Cygwin link.exe file to permanently avoid this scenario.
• MinGW
For 32-bit:
g++ -c -I<install_dir>\questasim\include app.cpp
g++ -shared -Bsymbolic -o app.dll app.o
-L<install_dir>\questasim\win32 -lmtipli
For 64-bit:
g++ -c -I<install_dir>\questasim\include app.cpp
g++ -shared -Bsymbolic -o app.dll app.o
-L<install_dir>\questasim\win64 -lmtipli
Questa SIM requires the use of the MinGW gcc compiler rather than the Cygwin gcc
compiler.
• For 64-bit — the GNU C compiler and link commands might be:
g++ -c -fPIC -I<install_dir>/questasim/include app.cpp
g++ -shared -Bsymbolic -o app.so app.o
To compile 64-bit systems for 32-bit operation, specify the -m32 argument on both the
g++ compiler command line as well as the g++ -shared linker command line.
If your HDL interface application requires a user or vendor-supplied C library, or an
additional system library, you will need to specify that library when you link your HDL
interface application. For example, to use the system math library libm, specify -lm with
the link command:
g++ -c -fPIC -I<install_dir>/questasim/include math_app.cpp
g++ -shared -Bsymbolic -o math_app.so math_app.o -lm
Note
On Windows platforms, the file names shown above should end with .dll rather than
.so.
The various methods of specifying PLI/VPI applications can be used simultaneously. The
libraries are loaded in the order listed above. Environment variable references can be used in the
paths to the libraries in all cases.
See also “modelsim.ini Variables” for more information on the modelsim.ini file.
DPI applications are specified to vsim using the following SystemVerilog arguments:
Table E-4. vsim Arguments for DPI Application Using External Compilation
Flows
Argument Description
-sv_lib <name> specifies a library name to be searched and used. No filename
extensions must be specified. (The extensions Questa SIM expects
are: .dll for Win32/Win64, .so for all other platforms.)
-sv_root <name> specifies a new prefix for shared objects as specified by -sv_lib
-sv_liblist specifies a “bootstrap file” to use. See The format for
<bootstrap_file> <bootstrap_file> is as follows:
#!SV_LIBRARIES
<path>/<to>/<shared>/<library>
<path>/<to>/<another>
...
No extension is expected on the shared library.
When the simulator finds an imported task or function, it searches for the symbol in the
collection of shared objects specified using these arguments.
It is a mistake to specify DPI import tasks and functions (tf) inside PLI/VPI shared objects.
However, a DPI import tf can make calls to PLI/VPI C code, providing that vsim -gblso was
used to mark the PLI/VPI shared object with global symbol visibility. See Loading Shared
Objects with Global Symbol Visibility.
The -gblso argument works in conjunction with the GlobalSharedObjectList variable in the
modelsim.ini file. This variable allows user C code in other shared objects to refer to symbols in
a shared object that has been marked as global. All shared objects marked as global are loaded
by the simulator earlier than any non-global shared objects.
PLI Example
The following example shows a small but complete PLI application for Linux.
hello.c:
#include "veriuser.h"
static PLI_INT32 hello()
{
io_printf("Hi there\n");
return 0;
}
s_tfcell veriusertfs[] = {
{usertask, 0, 0, 0, hello, 0, "$hello"},
{0} /* last entry must be 0 */
};
hello.v:
module hello;
initial $hello;
endmodule
Compile the PLI code for a 32-bit Linux Platform:
% gcc -c -I <install_dir>/questasim/include hello.c
% gcc -shared -Bsymbolic -o hello.so hello.o -lc
Compile the Verilog code:
% vlib work
% vlog hello.v
Simulate the design:
vsim -c -pli hello.so hello
# Loading ./hello.so
VPI Example
The following example is a trivial, but complete VPI application. A general VPI example can be
found in <install_dir>/questasim/examples/verilog/vpi.
hello.c:
#include "vpi_user.h"
static PLI_INT32 hello(PLI_BYTE8 * param)
{
vpi_printf( "Hello world!\n" );
return 0;
}
void RegisterMyTfs( void )
{
s_vpi_systf_data systf_data;
vpiHandle systf_handle;
systf_data.type = vpiSysTask;
systf_data.sysfunctype = vpiSysTask;
systf_data.tfname = "$hello";
systf_data.calltf = hello;
systf_data.compiletf = 0;
systf_data.sizetf = 0;
systf_data.user_data = 0;
systf_handle = vpi_register_systf( &systf_data );
vpi_free_object( systf_handle );
}
void (*vlog_startup_routines[])() = {
RegisterMyTfs,
0
};
hello.v:
module hello;
initial $hello;
endmodule
Compile the Verilog code:
% vlib work
% vlog hello.v
Simulate the design:
% vsim -c -pli hello.sl hello
# Loading work.hello
# Loading ./hello.sl
VSIM 1> run -all
# Hello world!
VSIM 2> quit
DPI Example
The following example is a trivial but complete DPI application. For additional examples, see
the <install_dir>/questasim/examples/systemverilog/dpi directory.
hello_c.c:
#include "svdpi.h"
#include "dpiheader.h"
int c_task(int i, int *o)
{
printf("Hello from c_task()\n");
verilog_task(i, o); /* Call back into Verilog */
*o = i;
return(0); /* Return success (required by tasks) */
}
hello.v:
module hello_top;
int ret;
export "DPI-C" task verilog_task;
task verilog_task(input int i, output int o);
#10;
$display("Hello from verilog_task()");
endtask
import "DPI-C" context task c_task(input int i, output int o);
initial
begin
c_task(1, ret); // Call the c task named 'c_task()'
end
endmodule
Compile the Verilog code:
% vlib work
% vlog -sv -dpiheader dpiheader.h hello.v hello_c.c
Simulate the design:
% vsim -c hello_top -do "run -all; quit -f"
# Loading work.hello_c
VSIM 1> run -all
# Hello from c_task()
# Hello from verilog_task()
VSIM 2> quit
reason_finish
For the execution of the $finish system task or the quit command.
reason_startofsave
For the start of execution of the checkpoint command, but before any of the simulation state
has been saved. This allows the PLI application to prepare for the save, but it shouldn't save
its data with calls to tf_write_save() until it is called with reason_save.
reason_save
For the execution of the checkpoint command. This is when the PLI application must save
its state with calls to tf_write_save().
reason_startofrestart
For the start of execution of the restore command, but before any of the simulation state has
been restored. This allows the PLI application to prepare for the restore, but it shouldn't
restore its state with calls to tf_read_restart() until it is called with reason_restart. The
reason_startofrestart value is passed only for a restore command, and not in the case that the
simulator is invoked with -restore.
reason_restart
For the execution of the restore command. This is when the PLI application must restore its
state with calls to tf_read_restart().
reason_reset
For the execution of the restart command. This is when the PLI application should free its
memory and reset its state. We recommend that all PLI applications reset their internal state
during a restart as the shared library containing the PLI code might not be reloaded. (See the
-keeploaded and -keeploadedrestart arguments to vsim for related information.)
reason_endofreset
For the completion of the restart command, after the simulation state has been reset but
before the design has been reloaded.
reason_interactive
For the execution of the $stop system task or any other time the simulation is interrupted and
waiting for user input.
reason_scope
For the execution of the environment command or selecting a scope in the structure
window. Also for the call to acc_set_interactive_scope() if the callback_flag argument is
non-zero.
reason_paramvc
reason_synch
reason_rosynch
reason_reactivate
reason_paramdrc
reason_force
reason_release
reason_disable
objects are created on demand, and the handles to these objects become invalid after acc_close()
is called. The following object types are created on demand in Questa SIM Verilog:
accOperator (acc_handle_condition)
accWirePath (acc_handle_path)
accTerminal (acc_handle_terminal, acc_next_cell_load, acc_next_driver, and
acc_next_load)
accPathTerminal (acc_next_input and acc_next_output)
accTchkTerminal (acc_handle_tchkarg1 and acc_handle_tchkarg2)
accPartSelect (acc_handle_conn, acc_handle_pathin, and acc_handle_pathout)
If your PLI application uses these types of objects, then it is important to call acc_close() to free
the memory allocated for these objects when the application is done using them.
If your PLI application places value change callbacks on accRegBit or accTerminal objects, do
not call acc_close() while these callbacks are in effect.
The PLI application is now ready to be run with Questa SIM Verilog. All that's left is to specify
the resulting object file to the simulator for loading using the Veriuser entry in the modesim.ini
file, the -pli simulator argument, or the PLIOBJS environment variable (see Registering PLI
Applications).
The following table lists the VHDL objects for which handles may be obtained and their type
and fulltype constants:
The type and fulltype constants for VHDL objects are defined in the acc_vhdl.h include file. All
of these objects (except signals) are scope objects that define levels of hierarchy in the structure
window. Currently, the PLI ACC interface has no provision for obtaining handles to generics,
types, constants, variables, attributes, subprograms, and processes.
However, some of these objects can be manipulated through the Questa SIM VHDL foreign
interface (mti_* routines). See the FLI Reference Manual for more information.
This routine provides similar functionality to the Verilog-XL acc_decompile_expr routine. The
condition argument must be a handle obtained from the acc_handle_condition routine. The
value returned by acc_decompile_exp is the string representation of the condition expression.
char *tf_dumpfilename(void)
void tf_dumpflush(void)
A call to this routine flushes the VCD file buffer (same effect as calling $dumpflush in the
Verilog code).
This routine gets the current simulation time as a 64-bit integer. The low-order bits are returned
by the routine, while the high-order bits are stored in the aof_hightime argument.
PLI/VPI Tracing
The foreign interface tracing feature is available for tracing PLI and VPI function calls. Foreign
interface tracing creates two kinds of traces: a human-readable log of what functions were
called, the value of the arguments, and the results returned; and a set of C-language files that can
be used to replay what the foreign interface code did.
The Purpose of Tracing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Invoking a Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Invoking a Trace
Context: PLI/VPI debugging
To invoke the trace, call vsim with the -trace_foreign argument.
Syntax
vsim
Arguments
<action>
Examples
vsim -trace_foreign 1 mydesign
Creates a logfile.
The tracing operations will provide tracing during all user foreign code-calls, including PLI/VPI
user tasks and functions (calltf, checktf, sizetf and misctf routines), and Verilog VCL callbacks.
Related Topics
vsim
PLI/VPI Tracing
You can use the FLI interface mti_AddDPISaveRestoreCB() to save and restore the states of C
code. This DPI checkpoint/restore support is limited to linux and linux_x86_64 platforms if
there are active DPI threads at the time of creating simulation checkpoint.
In order to debug your HDL interface application code in a debugger, you must first:
1. Compile the application code with debugging information (using the -g option) and
without optimizations (for example, don’t use the -O option).
2. Load vsim into a debugger.
Even though vsim is stripped, most debuggers will still execute it. You can invoke the
debugger directly on vsimk, the simulation kernel where your application code is loaded
(for example, "ddd `which vsimk`"), or you can attach the debugger to an already
running vsim process. In the second case, you must attach to the PID for vsimk, and you
must specify the full path to the vsimk executable (for example, "gdb
<modelsim_install_directory>/<platform>/vsimk 1234").
On Linux systems you can use either gdb or ddd.
3. Set an entry point using breakpoint.
Since initially the debugger recognizes only vsim's HDL interface function symbols,
when invoking the debugger directly on vsim you need to place a breakpoint in the first
HDL interface function that is called by your application code. An easy way to set an
entry point is to put a call to acc_product_version() as the first executable statement in
your application code. Then, after vsim has been loaded into the debugger, set a
breakpoint in this function. Once you have set the breakpoint, run vsim with the usual
arguments.
When the breakpoint is reached, the shared library containing your application code has
been loaded.
4. In some debuggers, you must use the share command to load the application's symbols.
At this point all of the application's symbols should be visible. You can now set breakpoints in
and single step through your application code.
Related Topics
vsim
C Debug
PLI/VPI Tracing
Questa SIM goes through numerous steps as it initializes the system during startup. It accesses
various files and environment variables to determine library mappings, configure the GUI,
check licensing, and so forth.
Files Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
Table F-1. Files That Questa SIM Accesses During Startup (cont.)
File Description
<project_name>.mpf If available, loads last project file which is specified in
the registry (Windows) or $(HOME)/.modelsim
(UNIX); see What are Projects? for details on project
settings
Initialization Sequence
The numberd items listed below describe the initialization sequence for Questa SIM. The
sequence includes a number of conditional structures, the results of which are determined by the
existence of certain files and the current settings of environment variables.
Names that appear in uppercase denote environment variables (except MTI_LIB_DIR which is
a Tcl variable). Instances of $(NAME) denote paths that are determined by an environment
variable (except $(MTI_LIB_DIR) which is determined by a Tcl variable).
• When you change the working directory within Questa SIM, it reads the [library],
[vcom], and [vlog] sections of the local modelsim.ini file. When you make changes in
the compiler or simulator options dialog box or use the vmap command, Questa SIM
updates the appropriate sections of the file.
• The pref.tcl file references the default .ini file by using the [GetPrivateProfileString] Tcl
command. The .ini file that is read will be the default file defined at the time pref.tcl is
loaded.
Environment Variables
When you install Questa SIM, the installation process creates and reads several environment
variables for the operating system of your computer. Most of these variables have default
values, which you can change to customize Questa SIM operation.
Expansion of Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
Creating Environment Variables in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Library Mapping with Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Referencing Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Removal of Temporary Files (VSOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909
If a file or path name contains the dollar sign character ($), and must be used in one of the places
listed above that accepts environment variables, then the explicit dollar sign must be escaped by
using a double dollar sign ($$).
Related Topics
Creating Environment Variables in Windows
edit
Location Mapping
modelsim.ini Variables
vlog
Setting Environment Variables
• Windows — use the System control panel, refer to “Creating Environment Variables in
Windows” for more information.
• Linux — typically, by modifying the .login script in a shell window.
Tip
The LM_LICENSE_FILE variable requires a value; all other variables are optional.
DISABLE_ELAB_DEBUG
The DISABLE_ELAB_DEBUG environment variable, if set, disables vsim elaboration error
debugging capabilities using the find insource and typespec commands.
DOPATH
The toolset uses the DOPATH environment variable to search for DO files. DOPATH consists
of a colon-separated (semi-colon for Windows) list of paths to directories. You can override this
environment variable with the DOPATH Tcl preference variable.
The DOPATH environment variable isn’t accessible when you invoke vsim from a UNIX shell
or from a Windows command prompt. It is accessible once Questa SIM or vsim is invoked. If
you need to invoke from a shell or command line and use the DOPATH environment variable,
use the following syntax:
DP_INIFILE
The DP_INIFILE environment variable points to a file that contains preference settings for the
Source window. By default, this file is created in your $HOME directory. You should only set
this variable to a different location if your $HOME directory does not exist or is not writable.
EDITOR
The EDITOR environment variable specifies the editor to invoke with the edit command
From the Windows platform, you could set this variable from within the Transcript window
with the following command:
where you would replace the path with that of your desired text editor. The braces ( {} ) are
required because of the spaces in the pathname
HOME
The toolset uses the HOME environment variable to look for an optional graphical preference
file (see Saving GUI Preferences in an Alternate Location) and optional location map file (see
Location Mapping and MGC_LOCATION_MAP). If $HOME is not present in the
environment, then the toolset will revert to using the current working directory (./). Refer to
modelsim.ini Variables for additional information.
ITCL_LIBRARY
Identifies the pathname of the [incr]Tcl library; set by Questa SIM to the same path as
MODEL_TECH_TCL; must point to libraries supplied by Mentor Graphics.
ITK_LIBRARY
Identifies the pathname of the [incr]Tk library; set by Questa SIM to the same pathname as
MODEL_TECH_TCL; must point to libraries supplied by Mentor Graphics.
LD_LIBRARY_PATH
A UNIX shell environment variable setting the search directories for shared libraries. It
instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is
used for both 32-bit and 64-bit shared libraries on Linux systems.
LD_LIBRARY_PATH_32
A UNIX shell environment variable setting the search directories for shared libraries. It
instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is
used only for 32-bit shared libraries on Linux systems.
LD_LIBRARY_PATH_64
A UNIX shell environment variable setting the search directories for shared libraries. It
instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is
used only for 64-bit shared libraries on Linux systems.
LM_LICENSE_FILE
The toolset’s file manager uses the LM_LICENSE_FILE environment variable to find the
location of the license file. The argument may be a colon-separated (semi-colon for Windows)
set of paths, including paths to other vendor license files. The environment variable is required.
MGC_AMS_HOME
Specifies whether vcom adds the declaration of REAL_VECTOR to the STANDARD package.
This is useful for designers using VHDL-AMS to test digital parts of their model.
MGC_HOME
Identifies the pathname of the Mentor product suite.
MGC_LOCATION_MAP
The toolset uses the MGC_LOCATION_MAP environment variable to find source files based
on easily reallocated “soft” paths.
MGC_WD
Identifies the Mentor Graphics working directory. This variable is used in the initialization
sequence.
MODEL_TECH
Do not set this variable. The toolset automatically sets the MODEL_TECH environment
variable to the directory in which the binary executable resides.
MODEL_TECH_OVERRIDE
Provides an alternative directory path for the binary executables. Upon initialization, the
product sets MODEL_TECH to this path, if set.
MODEL_TECH_TCL
Specifies the directory location of Tcl libraries for Tcl/Tk and vsim, and may also be used to
specify a startup DO file. This variable defaults to <installDIR>/tcl, however you may set it to
an alternate path.
MODELSIM
The toolset uses the MODELSIM environment variable to find the modelsim.ini file. The
argument consists of a path including the file name.
An alternative use of this variable is to set it to the path of a project file (<Project_Root_Dir>/
<Project_Name>.mpf). This allows you to use project settings with command line tools.
However, if you do this, the .mpf file will replace modelsim.ini as the initialization file for all
tools.
MODELSIM_PREFERENCES
The MODELSIM_PREFERENCES environment variable specifies the location to store user
interface preferences. Setting this variable with the path of a file instructs the toolset to use this
file instead of the default location (your HOME directory in UNIX or in the registry in
Windows). The file does not need to exist beforehand, the toolset will initialize it. Also, if this
file is read-only, the toolset will not update or otherwise modify the file. This variable may
contain a relative pathname – in which case the file will be relative to the working directory at
the time Questa SIM is started.
MODELSIM_TCL
identifies the pathname to a user preference file (for example, C:\questasim\modelsim.tcl); can
be a list of file pathnames, separated by semicolons (Windows) or colons (UNIX); note that user
preferences are now stored in the .modelsim file (Unix) or registry (Windows); QuestaSim will
still read this environment variable but it will then save all the settings to the .modelsim file
when you exit Questa SIM.
MTI_COSIM_TRACE
The MTI_COSIM_TRACE environment variable creates an mti_trace_cosim file containing
debugging information about FLI/PLI/VPI function calls. You should set this variable to any
value before invoking the simulator.
MTI_LIB_DIR
Identifies the path to all Tcl libraries installed with Questa SIM.
MTI_LIBERTY_PATH
Identifies the pathname of the Liberty library containing Liberty logic cell definitions. Refer to
Liberty Library Models for more information about the Liberty library modeling standard.
MTI_TF_LIMIT
The MTI_TF_LIMIT environment variable limits the size of the VSOUT temp file (generated
by the toolset’s kernel). Set the argument of this variable to the size of k-bytes
The environment variable TMPDIR controls the location of this file, while STDOUT controls
the name. The default setting is 10, and a value of 0 specifies that there is no limit. This variable
does not control the size of the transcript file.
MTI_RELEASE_ON_SUSPEND
The MTI_RELEASE_ON_SUSPEND environment variable allows you to turn off or modify
the delay for the functionality of releasing all licenses when operation is suspended. The default
setting is 10 (in seconds), which means that if you do not set this variable your licenses will be
released 10 seconds after your run is suspended. If you set this environment variable with an
argument of 0 (zero) Questa SIM will not release the licenses after being suspended. You can
change the default length of time (number of seconds) by setting this environment variable to an
integer greater than 0 (zero).
MTI_USELIB_DIR
The MTI_USELIB_DIR environment variable specifies the directory into which object libraries
are compiled when using the -compile_uselibs argument to the vlog command
MTI_VCO_MODE
The MTI_VCO_MODE environment variable specifies which version of the toolset to use on
platforms that support both 32- and 64-bit versions when the executables are invoked from the
questasim/bin directory by a Unix shell command (using full path specification or PATH
search). Acceptable values are either "32" or "64" (do not include quotes). If you do not set this
variable, the default is to use 32-bit mode, even on 64-bit machines.
NOMMAP
When set to 1, the NOMMAP environment variable disables memory mapping in the toolset.
You should only use this variable when running on Linux 7.1 because it will decrease the speed
with which Questa SIM reads files.
PLIOBJS
The toolset uses the PLIOBJS environment variable to search for PLI object files for loading.
The argument consists of a space-separated list of file or path names
STDOUT
The argument to the STDOUT environment variable specifies a filename to which the simulator
saves the VSOUT temp file information. Typically this information is deleted when the
simulator exits. The location for this file is set with the TMPDIR variable, which allows you to
find and delete the file in the event of a crash, because an unnamed VSOUT file is not deleted
after a crash.
TCL_LIBRARY
Identifies the pathname of the Tcl library; set by Questa SIM to the same pathname as
MODEL_TECH_TCL; must point to libraries supplied by Mentor Graphics.
TK_LIBRARY
Identifies the pathname of the Tk library; set by Questa SIM to the same pathname as
MODEL_TECH_TCL; must point to libraries supplied by Mentor Graphics.
TMP
(Windows environments) The TMP environment variable specifies the path to a generated file
(VSOUT) containing all stdout from the simulation kernel.
TMPDIR
(UNIX environments) The TMPDIR environment variable specifies the path to a generated file
(VSOUT) containing all stdout from the simulation kernel. The priority for temporary file and
directory creation is as follows:
• $TMPDIR — if defined
• /var/tmp — if available
• /tmp — if available
VSIM_LIBRARY
Identifies the pathname of the Tcl files that are used by Questa SIM; set by Questa SIM to the
same pathname as MODEL_TECH_TCL; must point to libraries supplied by Mentor Graphics.
6. OK (New User Variable, Environment Variable, and System Properties dialog boxes)
You can easily add additional hierarchy to the path with an environment variable. For example:
Use braces ({}) for cases where the path contains multiple items that need to be escaped, such as
spaces in the pathname or backslash characters. For example:
Related Topics
Setting Environment Variables
use std.textio.all;
entity test is end;
architecture only of test is
begin
process
FILE in_file : text is in "$ENV_VAR_NAME";
begin
wait;
end process;
end;
Environment variables may also be referenced from the Questa SIM command line or in DO
files using the Tcl env array mechanism. For example:
echo "$env(ENV_VAR_NAME)"
Note
Environment variable expansion does not occur in files that are referenced via the -f
argument to vcom, vlog, or vsim.
This appendix provides information about using Questa SIM with the Synopsys SmartModels
and Synopsys hardware modeling.
Synopsys SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
VHDL SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
Verilog SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Synopsys Hardware Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
VHDL Hardware Model Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
hm_entity Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
Synopsys SmartModels
You can use the Synopsys SWIFT-based SmartModel library with Questa SIM. The
SmartModel library is a collection of behavioral models supplied in binary form with a
procedural interface that is accessed by the simulator.
This section only describes the specifics of using SmartModels with Questa SIM.
Note
A 32-bit SmartModel will not run with a 64-bit version of the simulator. When trying to
load the operating system specific 32-bit library into the 64-bit executable, the pointer sizes
will be incorrect.
2. Compile the entity and foreign architecture into a library named lmc.
For example, the following commands compile the entity and foreign architecture:
vlib lmc
vcom -work lmc sml.vhd
sm_entity Syntax
Context: Synopsys SmartModel Interfaces
The syntax for sm_entity is as follows.
Syntax
sm_entity [-] [-xe] [-xa] [-c] [-all] [-v] [-93] [-modelsimini <ini_filepath>] [<SmartModelName>...]
Arguments
• -
Read SmartModel names from standard input.
• -xe
Do not generate entity declarations.
• -xa
Do not generate architecture bodies.
• -c
Generate component declarations.
• -all
Select all models installed in the SmartModel library.
• -v
Display progress messages.
• -93
Use extended identifiers where needed.
• -modelsimini <ini_filepath>
Load an alternate initialization file that replaces the current initialization file. Overrides the
file path specified in the MODELSIM environment variable. Specify either an absolute or
relative path the initialization file. On Windows systems the path separator should be a
forward slash (/).
• <SmartModelName>
Name of a SmartModel.
Examples
The following is an example of an entity and foreign architecture created by sm_entity for the
cy7c285 SmartModel.
library ieee;
use ieee.std_logic_1164.all;
entity cy7c285 is
generic (TimingVersion : STRING := "CY7C285-65";
DelayRange : STRING := "Max";
MemoryFile : STRING := "memory" );
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
A7 : in std_logic;
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
A11 : in std_logic;
A12 : in std_logic;
A13 : in std_logic;
A14 : in std_logic;
A15 : in std_logic;
CS : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
O4 : out std_logic;
O5 : out std_logic;
O6 : out std_logic;
O7 : out std_logic;
WAIT_PORT : inout std_logic );
end;
architecture SmartModel of cy7c285 is
attribute FOREIGN : STRING;
attribute FOREIGN of SmartModel : architecture is
"sm_init $MODEL_TECH/libsm.sl ; cy7c285";
begin
end SmartModel;
Based on the above example, the following are details about the entity:
• The port types are std_logic. This data type supports the full range of SmartModel logic
states.
• The DelayRange, TimingVersion, and MemoryFile generics represent the SmartModel
attributes of the same name. Sm_entity creates a generic for each attribute of the
particular SmartModel. The default generic value is the default attribute value that the
SmartModel has supplied to sm_entity.
Based on the above example, the following are details about the architecture:
• The first part of the foreign attribute string (sm_init) is the same for all SmartModels.
• The second part ($MODEL_TECH/libsm.sl) is taken from the libsm entry in the
initialization file, modelsim.ini.
• The third part (cy7c285) is the SmartModel name. This name correlates the architecture
with the SmartModel at elaboration.
The following is an example component declaration and specification that groups the address
and data ports of the CY7C285 SmartModel:
component cy7c285
generic ( TimingVersion : STRING := "CY7C285-65";
DelayRange : STRING := "Max";
MemoryFile : STRING := "memory" );
port ( A : in std_logic_vector (15 downto 0);
CS : in std_logic;
O : out std_logic_vector (7 downto 0);
WAIT_PORT : inout std_logic );
end component;
Command Channel
The command channel lets you invoke SmartModel specific commands. Questa SIM provides
access to the Command Channel from the command line.
The form of a SmartModel command is:
• -all — applies the command to all SmartModel instances. For example, to turn timing
checks off for all SmartModel instances:
lmc -all "SetConstraints Off"
There are also some SmartModel commands that apply globally to the current simulation
session rather than to models. The form of a SmartModel session command is:
SmartModel Windows
Some models in the SmartModel library provide access to internal registers with a feature called
SmartModel Windows. The simulator interface to this feature is described below.
Window names that are not valid VHDL or Verilog identifiers are converted to VHDL extended
identifiers. For example, with a window named z1I10.GSR.OR, the tool treats the name as
\z1I10.GSR.OR\ (for all commands including lmcwin, add wave, and examine). You must then
use that name in all commands. For example:
ReportStatus
The ReportStatus command displays model information, including the names of window
registers.
For example:
This model contains window registers named wa, wb, and wc. These names can be used in
subsequent window (lmcwin) commands.
The optional radix argument is -binary, -decimal, or -hexadecimal (these names can be
abbreviated). The default is to display the value using the std_logic characters. For
example, the following command displays the 64-bit window wc in hexadecimal:
lmcwin read /top/u1/wc -h
The format of the value argument is the same as used in other simulator commands that
take value arguments. For example, to write 1 to window wb, and all 1’s to window wc:
lmcwin write /top/u1/wb 1
lmcwin write /top/u1/wc X"FFFFFFFFFFFFFFFF"
The specified window is added to the model instance as a signal (with the same name as
the window) of type std_logic or std_logic_vector. This signal's values can then be
referenced in simulator commands that read signal values, such as the add list command
shown below. The window signal is continuously updated to reflect the value in the
model. For example, to list window wa:
lmcwin enable /top/u1/wa
add list /top/u1/wa
The window signal is not deleted, but it no longer is updated when the model’s window
register changes value. For example, to disable continuous monitoring of window wa:
lmcwin disable /top/u1/wa
• lmcwin release — disables the effect of a previous lmcwin write command on a window
net.
lmcwin release <window_instance>
Some windows are actually nets, and the lmcwin write command behaves more like a
continuous force on the net.
Memory Arrays
A memory model usually makes the entire register array available as a window. In this case, the
window commands operate only on a single element at a time. The element is selected as an
array reference in the window instance specification. For example, to read element 5 from the
window memory mem:
lmcwin read /top/u2/mem(5)
Omitting the element specification defaults to element 0. Also, continuous monitoring is limited
to a single array element. The associated window signal is updated with the most recently
enabled element for continuous monitoring.
The simulator automatically loads both the libhm and libsfi libraries when it elaborates a
hardware model foreign architecture.
• libhm — This variable points to the dynamic link library that interfaces the foreign
architecture to the hardware modeler software.
By default, libhm points to the libhm.sl supplied in the installation directory indicated by
the MODEL_TECH environment variable. The tool automatically sets the
MODEL_TECH environment variable to the appropriate directory containing the
executables and binaries for the current operating system. If you are running the
Windows operating system, then you must comment out the default libhm entry
(precede the line with the “;” character) and uncomment the libhm entry for the
Windows operating system.
• libsfi — This variable points to the dynamic link library software that accesses the
hardware modeler.
Uncomment the appropriate libsfi setting for your operating system, and replace
<sfi_dir> with the path to the hardware modeler software installation directory.
In addition, you must set the LM_LIB and LM_DIR environment variables as described in
Synopsys hardware modeling documentation.
hm_entity Tool
The hm_entity tool creates entities and foreign architectures for hardware models.
Creating Foreign Architectures with hm_entity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
hm_entity Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
Hardware Model Vector Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
Hardware Model Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
2. Compile the entity and foreign architecture into a library named lmc.
For example, the following commands compile the entity and foreign architecture:
vlib lmc
vcom -work lmc lmtest.vhd
hm_entity Syntax
The hm_entity tool automatically creates entities and foreign architectures for hardware models.
Syntax
hm_entity [-xe] [-xa] [-c] [-93] [-modelsimini <ini_filepath>] <shell
software filename>
Arguments
• -xe
Do not generate entity declarations.
• -xa
Do not generate architecture bodies.
• -c
Generate component declarations.
• -93
Use extended identifiers where needed.
• -modelsimini <ini_filepath>
Load an alternate initialization file that replaces the current initialization file. Overrides the
file path specified in the MODELSIM environment variable. Specify either an absolute or
relative path the initialization file. On Windows systems the path separator should be a
forward slash (/).
• <shell software filename>
Hardware model shell software filename.
Examples
The following is an example of the entity and foreign architecture created by hm_entity for the
CY7C285 hardware model:
library ieee;
use ieee.std_logic_1164.all;
entity cy7c285 is
generic ( DelayRange : STRING := "Max" );
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
A7 : in std_logic;
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
A11 : in std_logic;
A12 : in std_logic;
A13 : in std_logic;
A14 : in std_logic;
A15 : in std_logic;
CS : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
O4 : out std_logic;
O5 : out std_logic;
O6 : out std_logic;
O7 : out std_logic;
W : inout std_logic );
end;
architecture Hardware of cy7c285 is
attribute FOREIGN : STRING;
attribute FOREIGN of Hardware : architecture is
"hm_init $MODEL_TECH/libhm.sl ; CY7C285.MDL";
begin
end Hardware;
Based on the above example, the following are details about the entity:
• The entity name is the hardware model name (you can manually change this name if you
like).
• The port names are the same as the hardware model port names (these names must not
be changed). If the hardware model port name is not a valid VHDL identifier, then
hm_entity issues an error message. If hm_entity is invoked with the -93 option, then the
identifier is converted to an extended identifier, and the resulting entity must also be
compiled with the -93 option. Another option is to create a pin-name mapping file.
• The port types are std_logic. This data type supports the full range of hardware model
logic states.
• The DelayRange generic selects minimum, typical, or maximum delay values. Valid
values are “min”, “typ”, or “max” (the strings are not case-sensitive). The default is
“max”.
Based on the above example, the following are details about the architecture:
• The first part of the foreign attribute string (hm_init) is the same for all hardware
models.
• The second part ($MODEL_TECH/libhm.sl) is taken from the libhm entry in the
initialization file, modelsim.ini.
• The third part (CY7C285.MDL) is the shell software filename. This name correlates the
architecture with the hardware model at elaboration.
The following is an example component declaration and specification that groups the address
and data ports of the CY7C285 hardware model:
component cy7c285
generic ( DelayRange : STRING := "Max");
port ( A : in std_logic_vector (15 downto 0);
CS : in std_logic;
O : out std_logic_vector (7 downto 0);
WAIT_PORT : inout std_logic );
end component;
for all: cy7c285
use entity work.cy7c285
port map (A0 => A(0),
A1 => A(1),
A2 => A(2),
A3 => A(3),
A4 => A(4),
A5 => A(5),
A6 => A(6),
A7 => A(7),
A8 => A(8),
A9 => A(9),
A10 => A(10),
A11 => A(11),
A12 => A(12),
A13 => A(13),
A14 => A(14),
A15 => A(15),
CS => CS,
O0 => O(0),
O1 => O(1),
O2 => O(2),
O3 => O(3),
O4 => O(4),
O5 => O(5),
O6 => O(6),
O7 => O(7),
WAIT_PORT => W );
displaymsgmode, 1528
Index
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disclosure or use. Customer acknowledges that Software provided hereunder may contain source code which is proprietary and
its confidentiality is of the highest importance and value to Mentor Graphics. Customer acknowledges that Mentor Graphics
may be seriously harmed if such source code is disclosed in violation of this Agreement. Except as otherwise permitted for
purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble,
disassemble, reverse-compile, or reverse-engineer any Product, or in any way derive any source code from Software that is not
provided to Customer in source code form. Log files, data files, rule files and script files generated by or for the Software
(collectively “Files”), including without limitation files containing Standard Verification Rule Format (“SVRF”) and Tcl
Verification Format (“TVF”) which are Mentor Graphics’ trade secret and proprietary syntaxes for expressing process rules,
constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding
Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as
Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer
may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use
Products or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way
competitive with Products, or disclose to any third party the results of, or information pertaining to, any benchmark.
4.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software
errors and enhance or modify the Software for the authorized use, or as permitted for Embedded Software under separate
embedded software terms or an embedded software supplement. Customer shall not disclose or permit disclosure of source
code, in whole or in part, including any of its methods or concepts, to anyone except Customer’s employees or on-site
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in
any manner except to support this authorized use.
4.3. Customer agrees that it will not subject any Product to any open source software (“OSS”) license that conflicts with this
Agreement or that does not otherwise apply to such Product.
4.4. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense, or otherwise transfer the
Products, whether by operation of law or otherwise (“Attempted Transfer”), without Mentor Graphics’ prior written consent and
payment of Mentor Graphics’ then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor
Graphics’ prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics’ option, result in the
immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms of this Agreement,
including without limitation the licensing and assignment provisions, shall be binding upon Customer’s permitted successors in
interest and assigns.
4.5. The provisions of this Section 4 shall survive the termination of this Agreement.
5. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer with updates and
technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics’ then
current End-User Support Terms located at http://supportnet.mentor.com/supportterms.
6. OPEN SOURCE SOFTWARE. Products may contain OSS or code distributed under a proprietary third party license agreement, to
which additional rights or obligations (“Third Party Terms”) may apply. Please see the applicable Product documentation (including
license files, header files, read-me files or source code) for details. In the event of conflict between the terms of this Agreement
(including any addenda) and the Third Party Terms, the Third Party Terms will control solely with respect to the OSS or third party
code. The provisions of this Section 6 shall survive the termination of this Agreement.
7. LIMITED WARRANTY.
7.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed,
will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not
warrant that Products will meet Customer’s requirements or that operation of Products will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must
notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty
applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a)
Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty
shall not be valid if Products have been subject to misuse, unauthorized modification, improper installation or Customer is not in
compliance with this Agreement. MENTOR GRAPHICS’ ENTIRE LIABILITY AND CUSTOMER’S EXCLUSIVE
REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON
RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE
PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY. MENTOR GRAPHICS MAKES NO WARRANTIES
WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF
WHICH ARE PROVIDED “AS IS.”
7.2. THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS
LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY
DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
8. LIMITATION OF LIABILITY. TO THE EXTENT PERMITTED UNDER APPLICABLE LAW, IN NO EVENT SHALL
MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER
LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS
AGREEMENT EXCEED THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR
SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS
LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8
SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
9.1. Customer acknowledges that Mentor Graphics has no control over the testing of Customer’s products, or the specific
applications and use of Products. Mentor Graphics and its licensors shall not be liable for any claim or demand made against
Customer by any third party, except to the extent such claim is covered under Section 10.
9.2. In the event that a third party makes a claim against Mentor Graphics arising out of the use of Customer’s products, Mentor
Graphics will give Customer prompt notice of such claim. At Customer’s option and expense, Customer may take sole control
of the defense and any settlement of such claim. Customer WILL reimburse and hold harmless Mentor Graphics for any
LIABILITY, damages, settlement amounts, costs and expenses, including reasonable attorney’s fees, incurred by or awarded
against Mentor Graphics or its licensors in connection with such claims.
9.3. The provisions of this Section 9 shall survive any expiration or termination of this Agreement.
10. INFRINGEMENT.
10.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired
by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics
will pay costs and damages finally awarded against Customer that are attributable to such action. Customer understands and
agrees that as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify Mentor Graphics
promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend the
action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.
10.2. If a claim is made under Subsection 10.1 Mentor Graphics may, at its option and expense: (a) replace or modify the Product so
that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the
Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
10.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any
product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of
other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that
Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor
Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; (h) OSS, except to the extent that
the infringement is directly caused by Mentor Graphics’ modifications to such OSS; or (i) infringement by Customer that is
deemed willful. In the case of (i), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs
related to the action.
10.4. THIS SECTION 10 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS, AND CUSTOMER’S SOLE AND EXCLUSIVE REMEDY, FOR DEFENSE,
SETTLEMENT AND DAMAGES, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
11.1. If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized
term. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon
written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement
upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement
or any license granted hereunder will not affect Customer’s obligation to pay for Products shipped or licenses granted prior to
the termination, which amounts shall be payable immediately upon the date of termination.
11.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination of this Agreement and/or any license granted under this Agreement, Customer shall ensure that
all use of the affected Products ceases, and shall return hardware and either return to Mentor Graphics or destroy Software in
Customer’s possession, including all copies and documentation, and certify in writing to Mentor Graphics within ten business
days of the termination date that Customer no longer possesses any of the affected Products or copies of Software in any form.
12. EXPORT. The Products provided hereunder are subject to regulation by local laws and European Union (“E.U.”) and United States
(“U.S.”) government agencies, which prohibit export, re-export or diversion of certain products, information about the products, and
direct or indirect products thereof, to certain countries and certain persons. Customer agrees that it will not export or re-export Products
in any manner without first obtaining all necessary approval from appropriate local, E.U. and U.S. government agencies. If Customer
wishes to disclose any information to Mentor Graphics that is subject to any E.U., U.S. or other applicable export restrictions, including
without limitation the U.S. International Traffic in Arms Regulations (ITAR) or special controls under the Export Administration
Regulations (EAR), Customer will notify Mentor Graphics personnel, in advance of each instance of disclosure, that such information
is subject to such export restrictions.
13. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
14. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
15. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customer’s
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customer’s
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics’ request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 15 shall survive the termination of this Agreement.
16. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America or Japan, and the laws of Japan if Customer is located in Japan. All disputes arising out of or in relation to this
Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin,
Ireland when the laws of Ireland apply, or the Tokyo District Court when the laws of Japan apply. Notwithstanding the foregoing, all
disputes in Asia (excluding Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a
single arbitrator to be appointed by the chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the
English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be
incorporated by reference in this section. Nothing in this section shall restrict Mentor Graphics’ right to bring an action (including for
example a motion for injunctive relief) against Customer in the jurisdiction where Customer’s place of business is located. The United
Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
17. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
18. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Any translation of this Agreement is provided to comply with local legal requirements only. In the
event of a dispute between the English and any non-English versions, the English version of this Agreement shall govern to the extent
not prohibited by local law in the applicable jurisdiction. This Agreement may only be modified in writing, signed by an authorized
representative of each party. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver
or excuse.