SV For Verificaation LabManual v3.0
SV For Verificaation LabManual v3.0
SV For Verificaation LabManual v3.0
Authors:
Loganath Ramachandran
Restricted Distribution. Not to be distributed to anyone without the express approval of Verikwest
Management.
Not to be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others
without the express written permission of VeriKwest
1 Overview........................................................................................................... 5
1.1 Outline .......................................................................................................................... 5
1.2 Design description ........................................................................................................ 5
1.3 AHB I/O ports description ............................................................................................ 7
1.3.1 Overview of AHB write and read operations .................................................... 8
1.4 Genif port description ................................................................................................... 9
1.5 Lab Exercises .............................................................................................................. 10
1.6 Assumptions................................................................................................................ 10
6 Lab .................................................................................................................. 20
1 Overview
1.1 Outline
This document contains 4 lab exercises that supplement the “Fundamentals of
SystemVerilog”, an onsite course offered by VeriKwest Systems Inc. This course is
intended for beginners who are interested in learning the basics of the SystemVerilog
language. It gives a broad perspective on the language, and can be taken by both design
and verification engineers for getting introduced to the basics of the SystemVerilog
language.
This course focuses on these important topics: (a) SystemVerilog scalar and array data
types, (b) SystemVerilog tasks and functions, (c) SystemVerilog packages and finally (d)
SystemVerilog interfaces.
For the purposes of these lab exercises, we will use a very small portion of the AMBA AHB
protocol. The complete AHB protocol is far more complex. You may obtain the complete
details of the AMBA architecture from ARM ™ Limited (http://www.arm.com).
ahb_slave_top
clk_gen
ahb_to_genif
reset_gen
flow_control
genif_monitor
genif_memory
The test bench module instantiates the slave (“ahb_slave_top”) and all the modules
needed to drive transactions into the slave. The different blocks used in the test bench
are:
Module Filename Description
ahb_slave_top ahb_slave_top.sv This module represents the AHB slave. It has
the I/O pins shown in Section 1.3.
ahb_to_genif ahb_to_genif.sv This module converts the AHB read/write
transactions to a transaction on the genif
interface.
genif_monitor genif_monitor.sv Monitors the genif interface bus and displays
a message when it observes a read or write
transactions
genif_memory genif_memory.sv This is the actual memory module where the
slave data is stored. It is attached to the genif
interface bus.
clock_gen clock_gen.sv A simple clock generator
reset_gen reset_gen.sv A reset generator which activates the reset for
the first few cycles
flow_control_block flow_control_block.sv Controls the flow of transactions on the slave
by setting the hready_in to be low at certain
times during the simulation.
hclk
hreset_n
hwrite
haddr
htrans
hburst AHB
hwdata
Slave
hrdata
hresp
hready hready_in
hresp logic[1:0] Indicates status of the transfer. Types are {OKAY, ERROR,
RETRY, SPLIT}. We will set this signal to 0 to indicate
OKAY response for this lab.
hburst logic[2:0] Type of burst. We will not be supporting burst transfers in
this labl
For a write operation the AHB protocol has two phases: (a) the address phase, where the
master writes the address on the haddr bus, and (b) the data phase where the
corresponding data is written. In the figure below, the master (or the test bench) sets the
haddr to 21 in the first cycle. It then sets the hwdata to 31 in the next cycle. Thus the first
two cycles represent a write operation where DATA (31) is written to ADDR (21).
If hreadyis not high, then the master is expected to hold the hwdata and haddr signals
steady. During the second write operation where the data value (32) is being written to
address 22, the master holds the data till the slave is ready.
hclk
haddr 21 22 23 24
(ADDR-A) (ADDR-B) (ADDR-C) (ADDR-D)
31 32 33
hwdata (DATA-A) (DATA-B)) (DATA-C)
hwrite
hready
The read operation shown below is very similar to the write operation. During the address
phase the master writes the address on the haddr bus, and during the data phase the
slave returns the value. In the figure shown below, the master sets the haddr is set to 21
in the first cycle. The slave sets the hrdata to 31 in the next cycle. Thus the first two cycles
represent a read operation where DATA (31) was read from ADDR (21).
If hready is low, then the master is expected to hold the hwdata and haddr signals steady.
hclk
haddr 21 22 23 24
(ADDR-A) (ADDR-B) (ADDR-C) (ADDR-D)
31 32 33
hrdata (DATA-A) (DATA-B)) (DATA-C)
hwrite
hready
Lab Description
1.6 Assumptions
The labs are tool agnostic. You can use a simulator of your choice. We will not cover the
details of any simulators. Separate courses offered by tool vendors can help you learn
more about Modelsim (Mentor Graphics), IUS (Cadence Design Systems) and VCS
(Synopsys).
Before running any of the exercises in this module you must checkout the lab data.
Follow the steps below to check out lab1. (You will need a linux shell to execute the
following commands).
$ mkdir svtb_training_labs
$ cd svtb_training_labs
4. Change to the appropriate lab directory. For example if you workin on lab1, cd to
that directory.
$ cd lab1
5. You will find init.csh in each of the lab directories. Please modify the init.csh to ensure that
the simulation environments are correctly initialized for your company enviromnment.
Then source the init.csh using the following command.
$ source init.csh
Implement the print function in the class. The print function is expected to print
the m_id and m_name with the following format
Name :: aaaa
Id :: 3
Hint: use $display with appropriate formatting
--------------------
# Transaction::
# Name :: trans3
# Id :: 3
# Type :: 0
# Address :: 20
# rData :: 200
# --------------------
#
# MONITOR: ( 66) Reading data ( 200) from address 20
# -----------------
# Test Passed
# -----------------
3.5 Summary
In this lab exercise you learned how to use SystemVerilog classes. You created two
classes and create a couple of objects. After initializing the objects you used it to drive
the transaction onto the bus.
Declare new variables to hold m_address, m_type, m_wdata, m_rdata. These should
be declared with the rand keyword in this lab as they will be randomized.
Declare two constraints c_m_address and c_m_type. Hint do not use the keyword
extern, although we will be defining these constraints outside the class.
--------------------
Transaction::
Name :: trans1
Id :: 1
Type :: 1
Address :: 100
wData :: 200
--------------------
4.5 Summary
In this lab exercise you learned how to define and use a System Verilog randomize()
method on the ahb_transaction object. This is the beginning of constrained driven
verification.
1. Create a cover point - create a coverpoint on haddr signal and name it as cp_haddr
2. Create 16 equal sized coverbins on it
Hint : Use haddr_rngVal defined above, to get size of the bins
Use haddr_maxVal define above, to get the max value of the bin
5.5 Summary
In this lab exercise you learned how to define and use a System Verilog functional
coverage. This is an important part of constrained driven verification.
6 Lab
Specify the clocking event for the clocking block of the AHB Interface
1. Specify the sampling edge of the clock
2. Specify the inputs skew as input #1 and output skew as output #2
3. List the signals of the interface that are sampled and driven
- Hint : HADDR, HTRANS
7.5 Summary
In this lab exercise you learned how to define and use a System Verilog clocking blocks.