See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/220849794

Performance Analysis of Fast Adders Using VHDL

Conference Paper · January 2009

DOI: 10.1109/ARTCom.2009.132 · Source: DBLP

CITATIONS READS
17 1,910

3 authors, including:

Raminder Singh Balwinder singh Lakha

Sri Sai University Centre for Development of Advanced Computing
31 PUBLICATIONS   142 CITATIONS    126 PUBLICATIONS   326 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Design and Development of Pesticide Residue Detection System using EC and pH Sensor View project

Image Processing on FPGA View project

All content following this page was uploaded by Raminder Singh on 19 February 2019.

The user has requested enhancement of the downloaded file.

 2009 International Conference on Advances in Recent Technologies in Communication and Computing

Performance Analysis Of Fast Adders

Using VHDL
R.P.P. Singh Parveen Kumar Balwinder Singh
ECE Department ECE Department VLSI-ES Division, Centre for
Sri Sai College of Engg. & Tech. Beant College of Engg. & Tech. Development & Advanced Computing
Badhani (Pathankot), India Gurdaspur (Punjab), India (CDAC), Mohali
[email protected] [email protected] [email protected]

demand or application some compromise between

Abstract—This paper presents performance analysis of constraints has to be made.
different Fast Adders. The comparison is done on the basis
of three performance parameters i.e. Area, Speed and Power II PRIOR WORK
consumption. Further, we present a design methodology of In 1990, modified Carry-Skip Adders was presented by
hybrid carry lookahead/carry skip adders (CLSKAs). This reducing first block delay with carry-lookahead adders
modified carry skip adder is modeled by using both fix and using multidimensional dynamic programming [12]. In
variable block size. In conventional carry skip adder, each 1996, transistor-level simulation of the adders using
block consists of ripple carry adder and skip logic is used
HSPICE is done for area, time and power trade-off
after each block to generate carry for next block. The speed
between different fast adders [6]. In 2002, a new concept
of operation depends on carry propagation from previous
block to next block. In CLSKAs, we use carry lookahead
of hybrid adders is presented to speed up addition process
logic in each block to generate carry for next block. The by Wang et al. that gives hybrid carry look-ahead/carry-
modified carry skip adders presented in this paper provides select adders design [7]. In 2007, a new 54×54-bit
better speed and power consumption as compare to multiplier is designed using high-speed carry-look-ahead
conventional carry skip adder and other adders like ripple adder and has been fabricated by CMOS technology [4]. In
carry adder, carry lookahead adder, Ling adder, carry select 2008, low power multipliers based on new hybrid full
adder. The modified carry skip adders with fix block require adders is presented [5]. In 2008, Hasan Krad et al worked
few more CLB’s because of Carry lookahead logic, whereas on the performance analysis for a 32-Bit Multiplier with a
with variable block scheme, area optimization is achieved. Carry-Look-Ahead Adder and a 32-bit Multiplier with a
Ripple Adder using VHDL [3].
Keywords— Adder, Ripple Carry Adder, Look Ahead
Carry Adder, VHDL Simulation III FAST PARALLEL ADDERS
I. INTRODUCTION A. Ripple Carry Adder (RCA)
Adders are most commonly used in various electronic Ripple carry adder can be designed by cascading full
applications e.g. Digital signal processing in which adders adder in series i.e. carry from previous full adder is
are used to perform various algorithms like FIR, IIR etc. In connected as input carry for the next stage. Full adder is a
past, the major challenge for VLSI designer is to reduce basic building block of Ripple carry adder. Therefore, to
area of chip by using efficient optimization techniques. design n-bit parallel adder, it requires n full adders. In our
Then the next phase is to increase the speed of operation to design we use 16 full adders to design a 16-bit parallel
achieve fast calculations like, in today’s microprocessors adder. The major limitation of Ripple carry adder is that
millions of instructions are performed per second. Speed as the bit length goes on increases, delay also increases.
of operation is one of the major constraints in designing Therefore, Ripple carry adder is not suitable if large
DSP processors. Now, as most of today’s commercial number bits are to be added.
electronic products are portable like Mobile, Laptops etc. The major element that causes delay is carry propagation,
that require more battery back up. Therefore, lot of therefore it is important to calculate carry delay from input
research is going on to reduce power consumption. to output. For n-bit Ripple carry adder, Delay for carry can
Therefore, there are three performance parameters on be calculated as: -
which a VLSI designer has to optimize their design i.e.
Area, Speed and Power. It is very difficult to achieve all TC = TFA ((x0, y0) to c0) + (n-2) * TFA (cin to cout)) +
constraints for particular design, therefore depending on TFA (cin to sout (n-1)) (1)

978-0-7695-3845-7/09 $26.00
$25.00 © 2009 IEEE 189
DOI 10.1109/ARTCom.2009.132
 Ci+1 = Gi or (Pi and Ci)--Next Carry (8)
Figure.3 shows 16-bit look ahead carry adder that consists
of four 4-bit adders each 4-bit look ahead carry generator.
The latency through this 16-bit adder consists of the time
required for:
1. Producing the G and P for individual bit
positions (1 gate level).
FIGURE 1: Schematic block diagram of 16-bit ripple carry adder . 2. Producing the G and P signals for 4-bit blocks (2
gate levels).
Where TFA (input to output) represent the delay of full
adder on the path between it’s specified input and output.
A. Condition Carry Adder (CCA)
Condition carry adder is based on the principle shown
in figure.2. In this case instead of computing sum and
carry directly by using full adder, it computes sum and
carry depending upon status of previous carry i.e.
1. If ci = 0 then
Si = ai xor bi & ci+1 = ai and bi (2)
2. If ci = 1 then
Si = ai xnor bi & ci+1 = ai or bi (3)
FIGURE 3: Schematic block diagram of 16-bit carry look ahead adder
A logarithmic time condition sum adder results if we divided into 4 blocks [2].
proceed to the extreme of having single-bit adder at the
very top. Thus taking the delay of 2-to-1 multiplexer as 3. Predicting the carry-in signals c4, c8 and c12 for
our units, the delay of a condition sum adder are the blocks (2 gate levels).
characterized by the following recurrences: 4. Predicting the internal carries within each 4-bit
T (k) = Log2 k + T (1) (4) block (2 gate levels).
5. Computing the sum bits (2 gate levels).
Thus the total latency for 16-bit adder is a 9-gate level
that is very less as compared to 16-bit ripple carry adder
that is 32 gate levels. Thus, the delay of N-bit carry look-
ahead adder based on 4-bit look-ahead blocks is:
TCLA = 4 log4 N + 1 gate levels (9)

C. Ling Adder Design

FIGURE 2: Single-bit position of Condition sum adder [1]. The Ling Adder is a type of Look-Ahead Adder with a
slight modification that results in significant hardware
saving. Ling’s modification consists of propagating hi = ci
Where T (1) is the delay of circuit shown in figure.2, + ci-1 instead of ci. This results in reduction of number of
which is used at the top to derive the sum and carry bits gates required for implementation. Therefore, the Boolean
with a carry-in of 0 and 1. An exact analysis leads to a expression for calculating next carry and sum are:
comparable count for the number of single-bit multiplexers Ci = hi (Gi-1 + Pi-1) (10)
needed in a condition-sum adder. Assuming that K is a Si = Pi xor hi (Gi-1 + Pi-1) (11)
power of 2, the required number of multiplexers for a k-bit
adder is: D. Manchester Carry Chain Adder
Similar to Ling’s adder design, Manchester adder is also a
(k - 1)(Log2 k + 1) (5) type of Carry look-ahead adder. Manchester adder gives
B. Lookahead Carry Adder (CLA) slight modification in calculating next carry to be
Lookahead carry algorithm speed up the operation to propagated i.e. instead of using Boolean expression Ci+1 =
perform addition, because in this algorithm carry for the Gi + Ci Pi to calculate next carry Manchester carry adder
next stages is calculated in advance based on input signals. uses expression:
If X and Y are two inputs, “ci” is initial carry, “sout” and Ci+1=Gi +Ci ti (12)
“cout” are output sum and carry respectively, then Boolean ti = Xi + Yi (13)
expression for calculating next carry and addition is: Thus, we can say that carry recurrence can be written in
terms of ti instead of Pi, which leads to slightly faster
Pi = xi xor yi --- Carry Propagation (6)
adder because in binary addition, ti is easier to produce
Gi = xi and yi --- Carry Generate (7) than Pi (OR instead of XOR). Table1 and figure.4 shows
comparative study of 16-bit Manchester carry adder with

190
Carry look-ahead adder in terms of delay. CPLD XC9572 block width, then more number of blocks are required to
is used for implementation. make N bit adder which results in increase in latency
because more number of skips are required between stages
TABLE1: 16-BIT CARRY LOOK-AHEAD AND MANCHESTER ADDER and vice-versa. Figure6 and table2 shows the simulated
DESIGN COMPARISON FOR AREA AND DELAY
results in terms of delay achieved for 16-bit Carry skip
adder-using width of 4 blocks, 2 blocks and 8 blocks.
Adders Macrocells Used Pad Delay Delay (ns) TABLE2: 16-BIT CARRY SKIP ADDER USING 4 BLOCKS, 2 BLOCKS AND 8
Delay (ns) BLOCKS.
Sum Carry
CLA 31/72 (44%) 52 52 51 Carry Skip Delay Delay Power Power
Adder CLB'S (ns) (ns) (mW) (mW)
MCA 35/72 (49%) 53 51 33
16-bit Sum Carry Dynamic Static
4 blocks 23 23.2 23.1 16.3 219.71
60 52 53 52 51 51 2 blocks 26 20.8 21.7 16.1 219.69
50
35
8 blocks 24 26.6 24.5 14.8 219.54
40 31 33
CLA
30
MCA
20
10
0
30
Sum Carry
25
Macrocells tPD Delay (ns) Delay (ns)
Used 20 CLB'S
Delay (ns) Sum
15
Delay (ns) Carry
FIGURE 4: Graphical representation of Simulated results 10 Power (mW) Dynamic

E. Conventional Carry Skip Adder(CCSKA) 0

4 blocks 2 blocks 8 blocks
In case of N-bit Ripple carry adder, carry has to
propagate through all N stages, which results in large
delay in performing binary addition. In contrast, it is
possible to skip carry over group of n-bits in case of Carry FIGURE 6: Simulated Results of Table1
Skip Adder.
F. Modified Carry Skip Adder (CLSKAs)
This results in less delay as compare to ripple carry
adder. The worst-case carry propagation delay in a N-bit In conventional carry skip adder, each block consists
carry skip adder with fixed block width b, assuming that of ripple carry adder and skip logic is used after each block
one stage of ripple has the same delay as one skip, can be to generate carry for next block. The speed of operation
derived: depends on carry propagation from previous block to next
block. In CLSKAs, we use carry lookahead scheme in
TCSKA =(b -1)+0.5+(N/b-2)+(b -1) (14) each block to generate carry for next block. This result in
= 2b + N/b – 3.5 Stages (15) better performance in terms of speed as look ahead carry
Therefore, 8.5 Stages are required for 16-bit Carry adder is faster than ripple carry adder. Figure7 shows
Skip Adder that results in latency of 17 gate levels as modified CLSKA with fixed block size i.e. 4-bit each.
compare to 32 gate levels required for 16-bit Ripple carry
adder. Figure.5 shows 16-bit Carry-Skip Adder divided
into 4 blocks and each block are a 4-bit Ripple Carry
Adder.

FIGURE 5: 16-Bit Carry-Skip Adder [1]. FIGURE 7: A 16-bit hybrid CLSKA with 4-bit block adders.

From equation (xi), it is observed that latency is

directly proportional to block width i.e. if we decrease

191
 Now, next is another concept of designing adder by Si = xi xor yi (16)
using variable block size [12]. Figure8 shows CLSKA
model in which size of block is variable. Here, we use two
full adders Ci = xi and yi (17)
The final addition is then computed as:

1. Shifting the carry sequence C left by one place.

2. Placing a 0 to the front (MSB) of the partial sum
sequence S.
3. Finally, a ripple carry adder is used to add these
two together and computing the resulting sum.

TABLE 3: CSA COMPUTATION

X: 10011
Y: + 11001
S: 01010
C: 10001
Sum: 101100
FIGURE 8: A 16-bit hybrid CLSKA with variable block size.

G. Carry Select Adder (CSA)

Carry select adder is based on the principle to
calculate sum that is based on assuming input carry from
previous stage. One adder calculates the sum assuming
input carry of 0 while the other calculates the sum
assuming input carry of 1. Then, the actual carry triggers a
multiplexer that selects the appropriate sum [2]. Fig.9
shows the schematic block diagram of 16-bit Carry select
adder consists of 4-blocks each of 4-bit Look ahead carry
adder [11]. Carry output of each block is fed into next
block as input carry.
FIGURE 10: Computation flow of CSA

When adding together two numbers, using a half adder

followed by a ripple carry adder is faster than using two
ripple carry adders. This is because a ripple carry adder
cannot compute a sum bit without waiting for the previous
carry bit to be produced, and thus has a delay equal to that
of n full adders. A carry-save adder, however, produces all
of its output values in parallel, thus the total computation
time for a carry-save adder is less than ripple carry adders.
IV. RESULTS AND DISCUSSION
FIGURE 9: Schematic block diagram of 16-bit Carry select adder [2].
To demonstrate the performance of modified carry skip
I. CARRY SAVE ADDER adder we compare it with other adders like ripple carry
Basically, carry save adder is used to compute sum of adder, lookahead carry adder Ling adder, carry select
adder, carry save adder. We design all adders using VHDL
three or more n-bit binary numbers. Carry save adder is
(Very High Speed Integration Hardware Description
same as a full adder. But as shown in figure.10, here we Language) for 16-bit unsigned data. To get power, delay
are computing sum of two 16-bit binary numbers, so we and area report, we use XILINX 9.1 i as synthesis tool and
take 16 half adders at first stage instead of using 16 full Modelsim XE III 6.2g for simulation. FPGA-Spartan III is
adders. Therefore, carry save unit consists of 16 half used for implementation. The modified Carry Skip adder
adders, each of which computes single sum and carry bit architecture (hybrid carry lookahead/carry skip adders)
based only on the corresponding bits of the two input with fix block size (four blocks of 4-bit each) gives better
numbers. Let x and y are two 16 bit numbers and produces result than other adders in terms of Speed (Delay=15.0 ns)
partial sum and carry as s and c as shown in table3: but require more Area (29 CLB’s) and power consumption
(Dynamic Power=13.9mW) whereas with variable block

192
 size architecture, power consumption and area (26 CLB’s) V. CONCLUSION
also improve. From the results and discussion, it is observed that
there are trade-offs between performance parameters i.e.
TABLE 4: AREA, POWER AND DELAY REPORT FOR ADDERS
Area, Power and Delay. For designing delay efficient
ADDERS (With Fix Delay Delay Power Power adder, we have proposed a hybrid carry lookahead/carry
Block Size) CLB'S (ns) (ns) (mW) (mW) skip adders in which carry lookahead logic is used instead
Block Size = 4-Bit Sum Carry Dynamic Static of ripple carry adder in each block to generate output sum
Ripple Carry 24 24.1 23.5 7.6 218.7 and carry bit for next block. This result in fast operation
Conditional carry 24 23.9 23.3 7.6 218.7 but at the cost of few more CLB’s due to carry lookahead
Look Ahead 26 20.9 20.6 13.3 219.4 logic.
Lings 20 23.3 23.1 13.3 219.4
Carry Select 27 17.1 17.7 10.1 219 VI. REFERENCES
Carry Save 29 23.1 22.8 9 218.9
Conventional Carry [1] B. Parhami, Computer Arithmetic, Algorithm and Hardware
Skip Adder 23 23.2 23.1 16.3 219.7
Design, Oxford University Press, New York, pp. 91-119, 2000.
Modified carry Skip
Adder 29 15 14.6 13.9 219.4 [2] Pong P. Chu “RTL Hardware Design Using VHDL: coding for
Efficiency, Portability and Scalability” Wiley-IEEE Press, New
Jercy, 2006
[3] Hasan Krad and Aws Yousif Al-Taie, “Performance Analysis of a
TABLE 5: AREA, POWER AND DELAY REPORT FOR ADDERS 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit
ADDERS (With Multiplier with a Ripple Adder using VHDL”, Journal of
Variable Block Delay Delay Power Power Computer Science 4 (4): 305-308, 2008
Size) CLB'S (ns) (ns) (mW) (mW) [4] Asadi, P. and K. Navi “A novel high-speed 54-54-bit multiplier”,
2 Χ 7-bit + 2 Χ 1-bit Sum Carry Dynamic Static Am. J. Applied Sci., 4 (9): 666-672, 2007
Ripple Carry 24 22.9 22.5 7.9 218.7 [5] Z. Abid, H. El-Razouk and D.A. El-Dib, “Low power multipliers
Look Ahead 24 25.3 24.3 7.6 218.7 based on new hybrid full adders”, Microelectronics Journal,
Conventional Carry Volume 39, Issue 12, Pages 1509-1515, 2008
Skip Adder 26 22.3 20.5 14.9 219.5 [6] Nagendra, C.; Irwin, M.J.; Owens, R.M.,“Area-time-power
Modified carry Skip tradeoffs in parallel adders”, Circuits and Systems II: Analog and
Adder 26 16.8 12.2 13.8 219.5 Digital Signal Processing, IEEE Transactions on Volume 43, Issue
10, Page(s): 689 – 702, 1996
[7] Wang, Y.; Pai, C.; Song, X., “The design of hybrid carry look-
ahead/carry-select adders, Circuits and Systems II: Analog and
40 Digital Signal Processing, IEEE Transactions on Volume 49,
30 Page(s): 16-24, 2002.
20 [8] May Phyo Thwal, Khin Htay Kyi, and Kyaw Swar Soe,
“Implementation of Adder-Subtracter design with VerilogHDL”,
10 International Journal of Electronics, Circuits and Systems Volume
0 2 number 3, 2008
[9] Min Cha and Earl E. Swartzlander, Jr, “Modified Carry Skip
s
A

LA

LA

A
ng

CS
RC

SK

SK

Adder for reducing first block delay”, Proc. 43rd IEEE Midwest
C

CS
C

Li

CL
CC

Symp. on Circuits and Systems, Lansing MI, Page(s): 346-348,

2000
CLB'S Delay (ns) Sum [10] Behnam Amelifard, Farzan Fallah, Massoud Pedram, “Closing the
Delay (ns) Carry Power (mW) Dynamic gap between Carry Select Adder and Ripple Carry Adder: A new
class of Low-power and High-performance Adders”, Proceedings
of the Sixth International Symposium on Quality Electronic Design
(ISQED’05) , 2005
FIGURE 11: Performance comparison of adders
[11] Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang, “A Design Methodology
for Hybrid Carry-Lookahead/Carry-Select Adders with
Reconfigurability”, IEEE, 2005
[12] Pak K. Chan, et al, Delay Optimization of Carry-Skip Adders and
30
Block Carry-Lookahead Adders Using Multidimensional Dynamic
Programming, IEEE Transactions on Computers, vol. 41, No. 8,
25
pp. 920-93, 1992
20
15
10
5
0
Ripple Carry Look Ahead CCSKA CLSKA

CLB'S Delay (ns) Sum

Delay (ns) Carry Power (mW) Dynamic

FIGURE 12: Performance comparison of adders

193

View publication stats