(Dot Matrix Liquid Crystal Display Controller/Driver) : Description

HD66710
(Dot Matrix Liquid Crystal Display Controller/Driver)
Description
The HD66710 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,
numbers, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control
of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and
liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one
chip, a minimum system can be interfaced with this controller/driver.
A single HD66710 is capable of displaying a single16-character line, two 16-character lines, or up to four
8-character lines.
The HD66710 software is upwardly compatible with the LCD-II (HD44780) which allows the user to
easily replace an LCD-II with an HD66710. In addition, the HD66710 is equipped with functions such as
segment displays for icon marks, a 4-line display mode, and a horizontal smooth scroll, and thus supports
various display forms. This achieves various display forms. The HD66710 character generator ROM is
extended to generate 240 5 × 8 dot characters.
The low voltage version (2.7V) of the HD66710, combined with a low power mode, is suitable for any
portable battery-driven product requiring low power dissipation.
Features
• 5 × 8 dot matrix possible
• Low power operation support:
 2.7V to 5.5V (low voltage)
• Booster for liquid crystal voltage
 Two/three times (13V max.)
• Wide range of liquid crystal display driver voltage
 3.0V to 13V
• Extension driver interface
• High-speed MPU bus interface (2 MHz at 5-V operation)
• 4-bit or 8-bit MPU interface capability
• 80 × 8-bit display RAM (80 characters max.)
291
HD66710
• 9,600-bit character generator ROM
 240 characters (5 × 8 dot)
• 64 × 8-bit character generator RAM
 8 characters (5 × 8 dot)
• 8 × 8-bit segment RAM
 40-segment icon mark
• 33-common × 40-segment liquid crystal display driver
• Programmable duty cycle (See List 1)
• Wide range of instruction functions:
 Functions compatible with LCD-II: Display clear, cursor home, display on/off, cursor on/off,
display character blink, cursor shift, display shift
 Additional functions: Icon mark control, 4-line display, horizontal smooth scroll, 6-dot character
width control, white-black inverting blinking cursor
• Software upwardly compatible with HD44780
• Automatic reset circuit that initializes the controller/driver after power on
• Internal oscillator with an external resistor
• Low power consumption
• QFP1420-100 pin, TQFP1414-100 pin bare-chip
List 1 Programmable Duty Cycles
Number of Displayed Maximum Number of Displayed Characters

Lines Duty Ratio Character Single-Chip Operation
1 1/17 5 × 8-dot One 16-character line + 40 segments
2 1/33 5 × 8-dot Two 16-character lines + 40 segments
4 1/33 5 × 8-dot Four 8-character lines + 40 segments
Ordering Information
Type No. Package CGROM
HD66710A00FS QFP1420-100 (FP-100A) Japanese standard
HD66710A00TF TQFP1414-100 (TFP-100B)
HCD66710A00 Chip
292
HD66710
LCD-II Family Comparison

LCD-II
Item (HD44780U) HD66702R HD66710 HD66712U
Power supply voltage 2.7V to 5.5V 5V ±10% 2.7V to 5.5V 2.7V to 5.5V
(standard)
2.7V to 5.5V
(low voltage)
Liquid crystal drive 3.0V to 11V 3.0V to 8.3V 3.0V to 13.0V 2.7V to 11.0V
voltage
Maximum display 8 characters 20 characters 16 characters × 24 characters ×
digits per chip × 2 lines × 2 lines 2 lines/ 2 lines/
8 characters × 12 characters ×
4 lines 4 lines
Segment display None None 40 segments 60 segments
Display duty cycle 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 1/17 and 1/33
CGROM 9,920 bits 7,200 bits 9,600 bits 9,600 bits
(208 5 × 8 dot (160 5 × 7 dot (240 5 × 8 dot (240 5 × 8 dot
characters and characters and characters) characters)
32 5 × 10 dot 32 5 × 10 dot
characters) characters)
CGRAM 64 bytes 64 bytes 64 bytes 64 bytes
DDRAM 80 bytes 80 bytes 80 bytes 80 bytes
SEGRAM None None 8 bytes 16 bytes
Segment signals 40 100 40 60
Common signals 16 16 33 34
Liquid crystal drive A B B B
waveform
Bleeder resistor for External External External External
LCD power supply (adjustable) (adjustable) (adjustable) (adjustable)
Clock source Extenal resistor or External resistor or External resistor or External resistor or
external clock external clock external clock external clock
Rf oscillation 270 kHz ±30% 320 kHz ±30% 270 kHz ±30% 270 kHz ±30%
frequency (frame (59 to 110 Hz for (70 to 130 Hz for (56 to 103 Hz for (56 to 103 Hz for
frequency) 1/8 and 1/16 duty 1/8 and 1/16 duty 1/17 duty cycle; 57 1/17 duty cycle; 57
cycle; 43 to 80 Hz cycle; 51 to 95 Hz to 106 Hz for 1/33 to 106 Hz for 1/33
for 1/11 duty cycle) for 1/11 duty cycle) duty cycle) duty cycle)
Rf resistance 91 kΩ: 5-V 68 kΩ: 5-V 91 kΩ: 5-V 130 kΩ: 5-V
operation; operation; operation; operation;
75 kΩ: 3-V 56 kΩ: (3-V 75 kΩ: 3-V 110 kΩ: 3-V
operation operation) operation) operation
Liquid crystal voltage None None 2-3 times step- 2-3 times step-
booster circuit up circuit up circuit
293
HD66710
LCD-II
Item (HD44780U) HD66702R HD66710 HD66712U
Extension driver Independent Independent Used in common Independent
control signal control signal control signal with a driver control signal
output pin
Reset function Power on Power on Power on Power on
automatic reset automatic reset automatic reset automatic reset
or reset input
Instructions LCD-II Fully compatible Upper compatible Upper compatible
(HD44780) with the LCD-II with the LCD-II with the LCD-II
Number of displayed 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4
lines
Low power mode None None Available Available
Horizontal scroll Character unit Character unit Dot unit Dot unit
Bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits Serial;
4 bits/8 bits
CPU bus timing 2 MHz: 5-V 1 MHz 2 MHz: 5-V 2 MHz: 5-V
operation; operation; operation;
1 MHz: 3-V 1 MHz: 3-V 1 MHz: 3-V
operation operation operation
Package QFP-1420-80 LQFP-2020-144 QFP-1420-100 TCP-128
80-pin bare chip 144-pin bare chip 100-pin bare chip 128-pin bare chip
TQFP1414-100
294
HD66710
HD66710 Block Diagram
OSC1 OSC2 EXT
CPG
Reset circuit
ACL
Timing generator
7
Instruction register Instruction
(I R) decoder
COM1–
Display data RAM COM33
8 (DDRAM) 33-bit Common
80 × 8 bits shift signal
register driver
Address counter
7
RS MPU
R/W interface 7
8
E
SEG1–
SEG36
40-bit 40-bit
8 Data 8 shift latch Segment
DB4–DB7 SEG37/CL1
register register circuit signal
(DR) driver SEG38/CL2
Input/ SEG39/D
output 8
DB3–DB0 8 8
buffer 3 7 SEG40/M
Busy
flag
Segment Character Character Cursor and LCD drive

RAM generator RAM generator ROM bling voltage
(SGRAM) (CGRAM) (CGROM) controller selector
Vci 8 bytes 64 bytes 9,600 bytes
C1
Booster
C2 5
5/6
V5OUT2
Parallel/serial
V5OUT3
converter
and attribute circuit
VCC
GND
V1 V2 V3 V4 V5
295
HD66710
HD66710 Pin Arrangement
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SEG27 1 80 SEG6
SEG28 2 79 SEG5
SEG29 3 78 SEG4
SEG30 4 77 SEG3
SEG31 5 76 SEG2
SEG32 6 75 SEG1
SEG33 7 74 VCC
SEG34 8 73 TEST
SEG35 9 72 EXT
SEG36 10 71 DB7
SEG37/CL1 11 70 DB6
SEG38/CL2 12 69 DB5
SEG39/D 13 68 DB4
SEG40/M 14 HD66710 67 DB3
COM9 15 66 DB2
(FP-100A)
COM10 16 65 DB1
COM11 17 64 DB0
COM12 18 63 E
COM13 19 62 R/W
COM14 20 61 RS
COM15 21 60 OSC2
COM16 22 59 OSC1
COM25 23 58 Vci
COM26 24 57 C2
COM27 25 56 C1
COM28 26 55 GND
COM29 27 54 V5OUT2
COM30 28 53 V5OUT3
COM31 29 52 V5
COM32 30 51 V4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM33
V1
V2
V3
(Top view)
296
HD66710
HD66710 Pin Arrangement (TQFP1414-100 Pin)
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SEG29 1 75 SEG3
SEG30 2 74 SEG2
SEG31 3 73 SEG1
SEG32 4 72 VCC
SEG33 5 71 TEST
SEG34 6 70 EXT
SEG35 7 69 DB7
SEG36 8 68 DB6
SEG37/CL1 9 67 DB5
SEG38/CL2 10 66 DB4
SEG39/D 11 65 DB3
SEG40/M 12 HD66710 64 DB2
COM9 13 (TFP-100B) 63 DB1
COM10 14 62 DB0
COM11 15 61 E
COM12 16 60 R/W
COM13 17 59 RS
COM14 18 58 OSC2
COM15 19 57 OSC1
COM16 20 56 Vci
COM25 21 55 C2
COM26 22 54 C1
COM27 23 53 GND
COM28 24 52 V5OUT2
COM29 25 51 V5OUT3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM30
COM31
COM32
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM33
V1
V2
V3
V4
V5
(Top view)
297
HD66710
HD66710 Pad Arrangement
Chip size (X × Y) : 5.36 mm × 6.06 mm

Coordinate : Pad center
Origin : Chip center
Pad size (X × Y) : 100 µm × 100 µm
1 100 81 80
2 79
HD66710
Type code
29 52
30 31 50 51
X
298
HD66710
HD66710 Pad Location Coordinates

Pin No. Pad Name X Y Pin No. Pad Name X Y
1 SEG27 –2495 2910 51 V4 2458 –2910
2 SEG28 –2695 2730 52 V5 2660 –2731
3 SEG29 –2695 2499 53 V5OUT3 2660 –2500
4 SEG30 –2695 2300 54 V5OUT2 2660 –2300
5 SEG31 –2695 2100 55 GND 2640 –2090
6 SEG32 –2695 1901 56 C1 2650 –1887
7 SEG33 –2695 1698 57 C2 2675 –1702
8 SEG34 –2695 1498 58 Vci 2675 –1502
9 SEG35 –2695 1295 59 OSC1 2675 –1303
10 SEG36 –2695 1099 60 OSC2 2675 –1103
11 SEG37 –2695 900 61 RS 2675 –900
12 SEG38 –2695 700 62 :
R/ 2675 –701
13 SEG39 –2695 501 63 E 2675 –501
14 SEG40 –2695 301 64 DB0 2675 –302
15 COM9 –2695 98 65 DB1 2675 –99
16 COM10 –2695 –113 66 DB2 2675 98
17 COM11 –2695 –302 67 DB3 2675 301
18 COM12 –2695 –501 68 DB4 2675 501
19 COM13 –2695 –701 69 DB5 2675 700
20 COM14 –2695 –900 70 DB6 2675 900
21 COM15 –2695 –1100 71 DB7 2675 1099
22 COM16 –2695 –1303 72 EXT 2675 1299
23 COM25 –2695 –1502 73 TEST 2675 1502
24 COM26 –2695 –1702 74 VCC 2695 1698
25 COM27 –2695 –1901 75 SEG1 2695 1901
26 COM28 –2695 –2101 76 SEG2 2695 2104
27 COM29 –2695 –2300 77 SEG3 2695 2300
28 COM30 –2695 –2500 78 SEG4 2695 2503
29 COM31 –2695 –2731 79 SEG5 2695 2730
30 COM32 –2495 –2910 80 SEG6 2495 2910
31 COM24 –2051 –2910 81 SEG7 2049 2910
32 COM23 –1701 –2910 82 SEG8 1699 2910
33 COM22 –1498 –2910 83 SEG9 1499 2910
34 COM21 –1302 –2910 84 SEG10 1300 2910
35 COM20 –1102 –2910 85 SEG11 1100 2910
36 COM19 –899 –2910 86 SEG12 901 2910
37 COM18 –700 –2910 87 SEG13 701 2910
38 COM17 –500 –2910 88 SEG14 502 2910
39 COM8 –301 –2910 89 SEG15 299 2910
40 COM7 –101 –2910 90 SEG16 99 2910
41 COM6 99 –2910 91 SEG17 –101 2910
42 COM5 302 –2910 92 SEG18 –301 2910
43 COM4 502 –2910 93 SEG19 –500 2910
44 COM3 698 –2910 94 SEG20 –700 2910
45 COM2 887 –2910 95 SEG21 –899 2910
46 COM1 1077 –2910 96 SEG22 –1099 2910
47 COM33 1266 –2910 97 SEG23 –1302 2910
48 V1 1488 –2910 98 SEG24 –1501 2910
49 V2 1710 –2910 99 SEG25 –1701 2910
50 V3 2063 –2910 100 SEG26 –2051 2910
299
HD66710
Pin Functions
Table 1 Pin Functional Description
Device
Signal I/O Interfaced with Function
RS I MPU Selects registers
0: Instruction register (for write)
Busy flag: address counter (for read)
1: Data register (for write and read)
R/ : I MPU Selects read or write
0: Write
1: Read
E I MPU Starts data read/write
DB4 to DB7 I/O MPU Four high order bidirectional tristate data bus pins. Used for
data transfer between the MPU and the HD66710. DB7 can
be used as a busy flag.
DB0 to DB3 I/O MPU Four low order bidirectional tristate data bus pins. Used for
data transfer between the MPU and the HD66710. These
pins are not used during 4-bit operation.
COM1 to COM33 O LCD Common signals; those are not used become non-selected
waveforms. At 1/17 duty rate, COM1 to COM16 are used for
character display, COM17 for icon display, and COM18 to
COM33 become non-selected waveforms. At 1/33 duty rate,
COM1 to COM32 are used for character display, and
COM33 for icon display.
SEG1 to SEG35 O LCD Segment signals
SEG36 O LCD Segment signal. When EXT = high, the same data as that of
the first dot of the extension driver is output.
SEG37/CL1 O LCD/ Segment signal when EXT = low. When EXT = high, outputs
Extension driver the extension driver latch pulse.
SEG38/CL2 O LCD/ Segment signal when EXT = low. When EXT = high, outputs
Extension driver the extension driver shift clock.
SEG39/D O LCD/ Segment signal at EXT = low. At EXT = high, the extension
Extension driver driver data. Data on and after the 36th dot is output.
SEG40/M O LCD/ Segment signal when EXT = low. When EXT = high, outputs
Extension driver the extension driver AC signal.
EXT I — Extension driver enable signal. When EXT = high, SEG37 to
SEG40 become extension driver interface signals. At this
time, make sure that V5 level is lower than GND level (0 V).
V5 (low) ≤ GND (high).
V1 to V5 — Power supply Power supply for LCD drive
VCC – V5 = 13V (max)
300
HD66710
Table 1 Pin Functional Description (cont)
Device
Signal I/O Interfaced with Function
VCC, GND — Power supply VCC: +2.7V to 5.5V, GND: 0V
OSC1, OSC2 — Oscillation When CR oscillation is performed, a resistor must be
resistor clock connected externally. When the pin input is an external
clock, it must be input to OSC1.
Vci I — Input voltage to the booster, from which the liquid crystal
display drive voltage is generated.
Vci is reference voltage and power supply for the booster.
Vci = 1.0V to 5.0V ≤ VCC
V5OUT2 O V5 pin/ Voltage input to the Vci pin is boosted twice and output
Booster When the voltage is boosted three times, the same capacity
capacitance as that of C1–C2 should be connected.
V5OUT3 O V5 pin Voltage input to the Vci pin is boosted three times and
output.
C1/C2 — Booster External capacitance should be connected when using the
capacitance booster.
TEST I — Test pin. Should be wired to ground.
301
HD66710
Function Description
Registers
The HD66710 has two 8-bit registers, an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for the
display data RAM (DDRAM), the character generator RAM (CGRAM), and the segment RAM
(SEGRAM). The MPU can only write to IR, and cannot be read from.
The DR temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM. Data written into the
DR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM by an internal
operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or
SEGRAM. When address infor-mation is written into the IR, data is read and then stored into the DR
from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between the MPU is then
completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the
next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these
two registers can be selected (Table 2).
Busy Flag (BF)
When the busy flag is 1, the HD66710 is in the internal operation mode, and the next instruction will not
:
be accepted. When RS = 0 and R/ = 1 (Table 2), the busy flag is output from DB7. The next instruction
must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When an address of an
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of
DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented
by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/ = 1 :
(Table 2).
Table 2 Register Selection
RS R/ : Operation
0 0 IR write as an internal operation (display clear, etc.)
0 1 Read busy flag (DB7) and address counter (DB0 to DB6)
1 0 DR write as an internal operation (DR to DDRAM, CGRAM, or SEGRAM)
1 1 DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)
302
HD66710
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 80 ×
8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used
as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the
liquid crystal display.
The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal.
• 1-line display (N = 0) (Figure 2)

 When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the HD66710, 16 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
High order Low order

bits bits Example: DDRAM address 4E
AC
(hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0
Figure 1 DDRAM Address
Display position
(digit) 1 2 3 4 5 79 80
DDRAM ..................
00 01 02 03 04 4E 4F
address
(hexadecimal)
Figure 2 1-Line Display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display position
COM1 to 8 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F COM9 to 16
DRAM address
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COM1 to 8 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 COM9 to 16 (Left shift display)
COM1 to 8 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E COM9 to 16 (Right shift display)
Figure 3 1-line by 16-Character Display Example
303
HD66710
• 2-line display (N = 1, and NW = 0)
 Case 1: The first line is displayed from COM1 to COM16, and the second line is displayed from
COM17 to COM32. Care is required because the end address of the first line and the start address
of the second line are not consecutive. For example, the case is shown in Figure 5 where 16 × 2-
line display is performed using the HD66710. When a display shift operation is performed, the
DDRAM address shifts. See Figure 4.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display position
DDRAM address
COM1 to 8 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 COM9 to 16
(Left shift display)
COM17 to 24 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 COM25 to 32
COM1 to 8 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E COM9 to 16
(Right shift display)
COM17 to 24 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E COM25 to 32
Figure 4 2-line by 16-Character Display Example
 Case 2: Figure 5 shows the case where the EXT pin is fixed to high, the HD66710 and the 40-
output extension driver are used to extend the number of display characters.
In this case, the start address from COM9 to COM16 of the HD66710 is 0AH, and that from
COM25 to COM32 of the HD66710 is 4AH. To display 24 characters, the addresses starting at
SEG11 should be used.
When a display shift operation is performed, the DDRAM address shifts. See Figure 5.
1 2 3 4 5 6 7 8 9 10 1112 1314 15 16 17 18 19 20 21 22 23 24 Display position

COM1 to 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 COM9 to COM16
COM8 DDRAM address
HD66710 Extension HD66710 Extension
SEG1 to SEG35 driver (1) SEG11 to SEG35 driver (1)
Seg1 to Seg25 (SEG1 to SEG10: Seg1 to Seg35
skip)
1 2 3 4 5 6 7 8 9 10 11 12 1314 15 1617 18 19 20 21 22 23 24
COM1 to COM9 to
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
COM8 COM16 (Left shift display)
COM17 to COM25 to
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
COM24 COM32
COM1 to COM9 to
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16
COM8 COM16 (Right shift display)
COM17 to 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56
COM25 to
COM24 COM32
Figure 5 2-Line by 24 Character Display Example
304
HD66710
• 4-line display (NW = 1)
 Case 1: The first line is displayed from COM1 to COM8, the second line is displayed from COM9
to COM16, the third line is displayed from COM17 to COM24, and the fourth line is displayed
from COM25 to COM32. Care is required because the DDRAM addresses of each line are not
consecutive. For example, the case is shown in Figure 6 where 8 × 4-line display is performed
using the HD66710.
1 2 3 4 5 6 7 8 Display position
COM1 to 8 00 01 02 03 04 05 06 07
COM9 to 16 20 21 22 23 24 25 26 27
DDRAM address
COM17 to 24 40 41 42 43 44 45 46 47
COM25 to 32 60 61 62 63 64 65 66 67
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
COM1 to 8 01 02 03 04 05 06 07 08 13 00 01 02 03 04 05 06
COM9 to 16 21 22 23 24 25 26 27 28 33 20 21 22 23 24 25 26
(Left shift display) (Right shift display)
COM17 to 24 41 42 43 44 45 46 47 48 53 40 41 42 43 44 45 46
COM25 to 32 61 62 63 64 65 66 67 68 73 60 61 62 63 64 65 66
Figure 6 4-Line Display
305
HD66710
 Case 2: The case is shown in figure where the EXT pin is fixed high, and the HD66710 and the
40-output extension driver are used to extend the number of display characters.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 17 18 19 20 Display position

COM1 to 8 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
COM9 to 16 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
DDRAM address
COM17 to 24 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
COM25 to 32 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
HD66710 Extension driver (1) Extension driver (2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00 13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20 33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40 53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60 73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72
(Display shift left) (Display shift right)
Figure 7 4-Line by 20-Character Display Example
306
HD66710
Character Generator ROM (CGROM)
The character generator ROM generates 5 × 8 dot character patterns from 8-bit character codes (Table 3).
It can generate 240 5 × 8 dot character patterns. User-defined character patterns are also available using a
mask-programmed ROM.
Character Generator RAM (CGRAM)
The character generator RAM allows the user to redefine the character patterns. In the case of 5 × 8
characters, up to eight may be redefined.
Write the character codes at the addresses shown as the left column of Table 3 to show the character
patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns.
Segment RAM (SEGRAM)
The segment RAM (SEGRAM) is used to enable control of segments such as an icon and a mark by the
user program.
For a 1-line display, SEGRAM is read from the COM17 output, and as for 2- or 4-line displays, it is from
the COM33 output, to performs 40-segment display.
As shown in Table 6, bits in SEGRAM corresponding to segments to be displayed are directly set by the
MPU, regardless of the contents of DDRAM and CGRAM.
SEGRAM data is stored in eight bits. The lower six bits control the display of each segment, and the
upper two bits control segment blinking.
Modifying Character Patterns
• Character pattern development procedure

The following operations correspond to the numbers listed in Figure 8:
1. Determine the correspondence between character codes and character patterns.
2. Create a listing indicating the correspondence between EPROM addresses and data.
3. Program the character patterns into an EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing of the EPROM is performed at Hitachi to create a character pattern listing,
which is sent to the user.
6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and
samples are sent to the user for evaluation. When it is confirmed by the user that the character
patterns are correctly written, mass production of the LSI will proceed at Hitachi.
307
HD66710
Hitachi User
Start
Computer Determine
1
processing character patterns
Create character Create EPROM

5 2
pattern listing address data listing
Evaluate Write EPROM 3

character
patterns
EPROM → Hitachi 4
No
OK?
Yes
Art work
M/T
Masking
Trial
Sample
Sample 6
evaluation
No
OK?
Yes
Mass
production
Note: For a description of the numbers used in this figure, refer to the preceding page.
Figure 8 Character Pattern Development Procedure
308
HD66710
Table 3 Correspondence between Character Codes and Character Patterns (Hitachi Standard
HD66710)
Upper 4
Lower Bits 0001
4 Bits
0000 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
CG
RAM
xxxx0000 (1)
xxxx0001 (2)
xxxx0010 (3)
xxxx0011 (4)
xxxx0100 (5)
xxxx0101 (6)
xxxx0110 (7)
xxxx0111 (8)
xxxx1000 (1)
xxxx1001 (2)
xxxx1010 (3)
xxxx1011 (4)
xxxx1100 (5)
xxxx1101 (6)
xxxx1110 (7)
xxxx1111 (8)
Note: The user can specify any pattern in the character-generator RAM.
309
HD66710
• Programming character patterns
This section explains the correspondence between addresses and data used to program character
patterns in EPROM. The HD66710 character generator ROM can generate 240 5 × 8 dot character
patterns.
 Character patterns
EPROM address data and character pattern data correspond with each other to form a 5 × 8 dot
character pattern (Table 4).
Table 4 Example of Correspondence between EPROM Address Data and Character Pattern
(5 × 8 Dots)
EPROM Address MSB Data LSB

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O4 O3 O2 O1 O0
0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1
0 0 0 1 1 0 0 0 1
0 0 1 0 1 0 0 0 1
0 0 1 1 0 1 0 1 0
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 0
0 1 1 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0
Character code “0” Line position
Notes: 1. EPROM addresses A11 to A4 correspond to a character code.

2. EPROM addresses A2 to A0 specify a line position of the character pattern. EPROM address
A3 should be set to 0.
3. EPROM data O4 to O0 correspond to character pattern data.
4. Area which are lit (indicated by shading) are stored as 1, and unlit are as 0.
5. The eighth line is also stored in the CGROM, and should also be programmed. If the eighth line
is used for a cursor, this data should all be set to zero.
6. EPROM data bits O7 to O5 are invalid. 0 should be written in all bits.
310
HD66710
 Handling unused character patterns
1. EPROM data outside the character pattern area: This is ignored by the character generator ROM
for display operation so any data is acceptable.
2. EPROM data in CGRAM area: Always fill with zeros. (EPROM addresses 00H to FFH.)
3. Treatment of unused user patterns in the HD66710 EPROM: According to the user application,
these are handled in either of two ways:
a. When unused character patterns are not programmed: If an unused character code is written
into DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased.
b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused
character codes are written into DDRAM. (This is equivalent to a space.)
Table 5 Example of Correspondence between Character Code and Character Pattern (5 × 8
Dots) in CGRAM
a) When Character Pattern in 5 × 8 Dots
Character code (DDRAM data) CGRAM address MSB CGRAM data LSB
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 0 * 0 0 0 0 0 0 0 0 0 * * * 1 0 0 0 1
0 0 1 1 0 0 0 1
0 1 0 1 0 0 0 1
Character
0 1 1 0 1 0 1 0
pattern
1 0 0 0 0 1 0 0 (1)
1 0 1 0 0 1 0 0
1 1 0 0 0 1 0 0
1 1 1 0 0 0 0 0
0 0 0 0 * 1 1 1 1 1 1 0 0 0 * * * 1 0 0 0 1
0 0 1 1 0 0 0 1
0 1 0 1 0 0 0 1
0 1 1 0 1 0 1 0 Character
1 0 0 0 0 1 0 0 pattern
1 0 1 0 0 1 0 0 (8)
1 1 0 0 0 1 0 0
1 1 1 0 0 0 0 0
311
HD66710
Table 5 Example of Correspondence between Character Code and Character Pattern (5 × 8
Dots) in CGRAM (cont)
b) When Character Pattern in 6 × 8 Dots
Character code (DDRAM data) CGRAM address MSB CGRAM data LSB
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 0 * 0 0 0 0 0 0 0 0 0 * * 0 1 0 0 0 1
0 0 1 0 1 0 0 0 1
0 1 0 0 1 0 0 0 1 Character
0 1 1 0 0 1 0 1 0 pattern
1 0 0 0 0 0 1 0 0 (1)
1 0 1 0 0 0 1 0 0
1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0
0 0 0 0 * 1 1 1 1 1 1 0 0 0 * * 0 1 0 0 0 1
0 0 1 0 1 0 0 0 1
0 1 0 0 1 0 0 0 1
0 1 1 0 0 1 0 1 0 Character
1 0 0 0 0 0 1 0 0 pattern
(8)
1 0 1 0 0 0 1 0 0
1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0
Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor.
3. The character data is stored with the rightmost character element in bit 0, as shown in Table 5.
Characters with 5 dots in width (FW = 0) are stored in bits 0 to 4, and characters with 6 dots in
width (FW = 1) are stored in bits 0 to 5.
4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected.
Bit 3 of the character code is invalid (*). Therefore, for example, the character codes 00
(hexadecimal) and 08 (hexadecimal) correspond to the same CGRAM address.
5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection.
6. When the BE bit of the function set register is 1, pattern blinking control of the lower six bits is
controlled using the upper two bits (bits 7 and 6) in CGRAM.
When bit 7 is 1, of the lower six bits, only those which are set are blinked on the display.
When bit 6 is 1, a bit 4 pattern can be blinked as for a 5-dot font width, and a bit 5 pattern can
be blinked as for a 6-dot font width.
* Indicates no effect.
312
HD66710
Table 6 Relationships between SEGRAM Addresses and Display Patterns
SEGRAM SEGRAM data

address a) 5-dot font width b) 6-dot font width
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 B1 B0 * S1 S2 S3 S4 S5 B1 B0 S1 S2 S3 S4 S5 S6
Blinking control Pattern on/off Blinking control Pattern on/off
Notes: 1. Data set to SEGRAM is output when COM17 is selected, as for a 1-line display, and output
when COM33 is selected, as for a 2-line or a 4-line display.
2. S1 to S48 are pin numbers of the segment output driver.
S1 is positioned to the left of the monitor.
S37 to S48 are extension driver outputs for a 6-dot character width.
3. After S40 output at 5-dot font and S48 output at 6-dot font, S1 output is repeated again.
4. As for a 5-dot font width, lower five bits (D4 to D0) are display on.off information of each
segment. For a 6-dot character width, the lower six bits (D5 to D0) are the display information
for each segment.
5. When the BE bit of the function set register is 1, pattern blinking of the lower six bits is
controlled using the upper two bits (bits 7 and 6) in SEGRAM.
When bit 7 is 1, only a bit set to “1” of the lower six bits is blinked on the display.
When bit 6 is 1, only a bit 4 pattern can be blinked as for a 5-dot font width, and only a bit 5
pattern can be blinked as for 6-dot font width.
6. Bit 5 (D5) is invalid for a 5-dot font width.
7. Set bits in the CGRAM data correspond to display selection, and zeros to non-selection.
313
HD66710
i) 5-dot font width (FW = 0)
S5 S10 S40 S5
S1 S2 S3 S4 S6 S7 S8 S9 S36 S37 S38 S1 S2 S3 S4
S39
SEG10
SEG36
SEG37
SEG38
SEG39
SEG40
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
ii) 6-dot font width (FW = 1)
S5 S11 S47 S5
S1 S2 S3 S4 S6 S7 S8 S9 S12 S43 S44 S45 S48 S1 S2 S3 S6
S10 S46 S4
SEG10
SEG11
SEG12
Seg10
Seg11
Seg12
Seg13
Seg14
Seg15
Seg16
Seg17
Seg18
Seg19
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
Seg8
Seg9
<< Extension driver >>
Figure 9 Relationships between SEGRAM Data and Display
314
HD66710
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing
by MPU access are generated separately to avoid interfering with each other. Therefore, when writing
data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas
other than the display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 33 common signal drivers and 40 segment signal
drivers. When the character font and number of lines are selected by a program, the required common
signal drivers automatically output drive waveforms, while the other common signal drivers continue to
output non-selection waveforms.
Character pattern data is sent serially through a 40-bit shift register and latched when all needed data has
arrived. The latched data then enables the driver to generate drive waveform outputs.
Sending serial data always starts at the display data character pattern corresponding to the last address of
the display data RAM (DDRAM).
Since serial data is latched when the display data character pattern corresponding to the starting address
enters the internal shift register, the HD66710 drives from the head display.
Cursor/Blink Control Circuit
The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the
display at a position corresponding to the location in stored in the address counter (AC).
For example (Figure 10), when the address counter is 08H, a cursor is displayed at a position
corresponding to DDRAM address 08H.
315
HD66710
AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC 0 0 0 1 0 0 0
For a 1-line display

Display position 1 2 3 4 5 6 7 8 9 10 11
DDRAM address
(hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A
Cursor position
For a 2-line display
Display position 1 2 3 4 5 6 7 8 9 10 11
00 01 02 03 04 05 06 07 08 09 0A
DDRAM address
(hexadecimal)
40 41 42 43 44 45 46 47 48 49 4A
Cursor position
Note: Even if the address counter (AC) points to an address in the character generator RAM (CGRAM) or
segment RAM (SEGRAM), cursor/blink black-white inversion will still occur, although it will produce
meaningless results.
Figure 10 Cursor/Blink Display Example
316
HD66710
Interfacing to the MPU

The HD66710 can send data in either two 4-bit operations or one 8-bit operation, thus allowing
interfacing with 4- or 8-bit MPUs.
• For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the HD66710 and the MPU is completed after the 4-bit data
has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit
operation, DB4 to DB7) are transfered before the four low order bits (for 8-bit operation, DB0 to
DB3).
The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two
more 4-bit operations then transfer the busy flag and address counter data.
• For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
RS
R/W
DB7 IR7 IR3 BF AC3 DR7 DR3
DB6 IR6 IR2 AC6 AC2 DR6 DR2
Instruction register (IR) Busy flag (BF) and Data register (DR)
write address counter (AC) read
read
Figure 11 4-Bit Transfer Example
317
HD66710
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the HD66710 when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state
until the initialization ends (BF = 1). The busy state lasts for 15 ms after VCC rises to 4.5V or 40 ms after
the VCC rises to 2.7V.
1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
RE = 0; Extension register write disable
3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
BE = 0; CGRAM/SEGRAM blinking off
LP = 0; Not in low power mode
4. Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
5. Extension function set:
FW = 0; 5-dot character width
B/W = 0; Normal cursor (eighth line)
NW = 0; 1- or 2-line display (depending on N)
6. SEGRAM address set:
HDS = 000; No scroll
Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the HD66710. For such a case, initialization must be performed by the MPU as
explained in the section, Initializing by Instruction.
318
HD66710
Instructions
Outline
Only the instruction register (IR) and the data register (DR) of the HD66710 can be controlled by the
MPU. Before starting internal operation of the HD66710, control information is temporarily stored in
these registers to allow interfacing with various MPUs, which operate at different speeds, or various
peripheral control devices. The internal operation of the HD66710 is determined by signals sent from the
:
MPU. These signals, which include register selection (RS), read/write (R/ ), and the data bus (DB0 to
DB7), make up the HD66710 instructions (Table 7). There are four categories of instructions that:
• Designate HD66710 functions, such as display format, data length, etc.

• Set internal RAM addresses
• Perform data transfer with internal RAM
• Perform miscellaneous functions
Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-
incrementation by 1 (or auto-decrementation by 1) of internal HD66710 RAM addresses after each data
write can lighten the program load of the MPU. Since the display shift instruction (Table 7) can perform
concurrently with display data write, the user can minimize system development time with maximum
programming efficiency.
When an instruction is being executed for internal operation, no instruction other than the busy
flag/address read instruction can be executed.
Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0
before sending another instruction from the MPU.
Note: Be sure the HD66710 is not in the busy state (BF = 1) before sending an instruction from the
MPU to the HD66710. If an instruction is sent without checking the busy flag, the time between
the first instruction and next instruction will take much longer than the instruction time itself.
Refer to Table 7 for the list of each instruction execution time.
319
HD66710
Table 7 Instructions
Execution Time
Code (Max) (when fcp or
Instruction RS R/ : DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description fOSC is 270 kHz)
Clear 0 0 0 0 0 0 0 0 0 1 Clears entire display and 1.52 ms
display sets DDRAM address 0 in
address counter.
Return 0 0 0 0 0 0 0 0 1 — Sets DDRAM address 0 in 1.52 ms
home address counter. Also
returns display from being
shifted to original position.
DDRAM contents remain
unchanged.
Entry mode 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction 37 µs
set and specifies display shift.
These operations are
performed during data write
and read.
Display 0 0 0 0 0 0 1 D C B Sets entire display (D) on/off, 37 µs
on/off cursor on/off (C), and
control blinking of cursor position
(RE = 0) character (B).
Extension 0 0 0 0 0 0 1 FW B/W NW Sets a font width, a black- 37 µs
function set white inverting cursor (B/W),
(RE = 1) a 6-dot font width (FW), and
a 4-line display (NW).
Cursor or 0 0 0 0 0 1 S/C R/L — — Moves cursor and shifts 37 µs
display display without changing
shift DDRAM contents.
Function 0 0 0 0 1 DL N RE — — Sets interface data length 37 µs
set (DL), number of display lines
(RE = 0) (N), and extension register
write enable (RE).
(RE = 1) 0 0 0 0 1 DL N RE BE LP Sets CGRAM/SEGRAM 37 µs
blinking enable (BE), and low
power mode (LP). LP is
available when the EXT pin
is low.
Set 0 0 0 1 ACG ACG ACG ACG ACG ACG Sets CGRAM address. 37 µs
CGRAM CGRAM data is sent and
address received after this setting.
(RE = 0)
Set 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address. 37 µs
DDRAM DDRAM data is sent and
(RE = 0)
Set 0 0 1 HDS HDS HDS *— ASG ASG ASG Sets SEGRAM address. 37 µs
SEGRAM DDRAM data is sent and
(RE = 1) Also sets a horizontal dot
scroll quantity (HDS).
320
HD66710
Table 7 Instructions (cont)
Execution Time
Code (max) (when fcp or
Instruction RS R/ : DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description fOSC is 270 kHz)
Read busy 0 1 BF AC AC AC AC AC AC AC Reads busy flag (BF) 0 µs
flag & indicating internal operation
address is being performed and reads
address counter contents.
Write data 1 0 Write data Writes data into DDRAM, 37 µs
to RAM CGRAM, or SEGRAM. To tADD = 5.5 µs*
(RE = 0/1) write data to DDRAM
CGRAM, clear RE to 0; or to
write data to SEGRAM, set
RE to 1.
Read data 1 1 Read data Reads data from DDRAM, 37 µs
from RAM CGRAM, or SEGRAM. To tADD = 5.5 µs*
(RE = 0/1) read data from DDRAM or
CGRAM, clear RE to 0; to
read data from SEGRAM,
set RE to 1.
I/D = 1: Increment DDRAM: Display data
I/D = 0: Decrement RAM
S = 1: Accompanies display shift CGRAM: Character
D = 1: Display on generator RAM
C = 1: Cursor on SEGRAM: Segment RAM
B = 1: Blink on
FW = 1: 6-dot font width
B/W = 1: Black-white inverting cursor on
NW = 1: Four lines
NW = 0: One or two lines
S/C = 1: Display shift ACG: CGRAM address
S/C = 0: Cursor move
R/L = 1: Shift to the right ADD: DDRAM address
R/L = 0: Shift to the left (corresponds to
DL = 1: 8 bits, DL = 0: 4 bits cursor address)
N = 1: 2 lines, N = 0: 1 line ASEG: Segment RAM
RE = 1: Extension register access enable address
BE = 1: CGRAM/SEGRAM blinking enable HDS: Horizontal dot scroll
LP = 1: Low power mode quantity
BF = 1: Internally operating AC: Address counter
BF = 0: Instructions acceptable used for both DD,
CG, and SEGRAM
addresses.
Notes: 1. — indicates no effect.
* After execution of the CGRAM/DDRAM/SEGRAM data write or read instruction, the RAM
address counter is incremented or decremented by 1. The RAM address counter is updated
after the busy flag turns off.
In Figure 12, tADD is the time elapsed after the busy flag turns off until the address counter is
updated.
2. Extension time changes as frequency changes. For example, when f is 300 kHz, the execution
time is: 37 µs × 270/300 = 33 µs.
3. Execution time in a low power mode (LP = 1 & EXT = low) becomes four times as long as for a
1-line mode, and twice as long as for a 2- or 4-line mode.
321
HD66710
Busy state Busy state

(DB7 pin)
Address counter
(DB0 to DB6 pins) A A+1
t ADD
Note: t ADD depends on the operation frequency

t ADD = 1.5/(f cp or f OSC ) seconds
Figure 12 Address Counter Update
322
HD66710
Instruction Description
Clear Display
Clear display writes space code (20)H (character pattern for character code (20)H must be a blank
pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns
the display to its original status if it was shifted. In other words, the display disappears and the cursor or
blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1
(increment mode) in entry mode. S of entry mode does not change. It resets the extended register enable
bit (RE) to 0 in function set.
Return Home
Return home sets DDRAM address 0 into the address counter, and returns the display to its original status
if it was shifted. The DDRAM contents do not change.
The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). It resets
the extended register enable bit (RE) to 0 in function set. In addition, flicker may occur in a moment at
the time of this instruction issue.
Entry Mode Set
I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is
written into or read from DDRAM.
The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1.
The same applies to writing and reading of CGRAM and SEGRAM.
S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1 during DDRAM
write. The display does not shift if S is 0.
If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when
reading from DDRAM. Also, writing into or reading out from CGRAM and SEGRAM does not shift the
display. In a low power mode (LP = 1), do not set S = 1 because the whole display does not normally
shift.
Display On/Off Control
When extension register enable bit (RE) is 0, bits D, C, and B are accessed.
D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM,
but can be displayed instantly by setting D to 1.
C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the
function of I/D or other specifications will not change during display data write. The cursor is displayed
using 5 dots in the 8th line for 5 × 8 dot character font.
323
HD66710
B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as
switching between all blank dots and displayed characters at a speed of 370-ms intervals when f cp or fOSC is
270 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes
according to fOSC or the reciprocal of fcp. For example, when fcp is 300 kHz, 370 × 270/300 = 333 ms.)
Extended Function Set
When the extended register enable bit (RE) is 1, FW, B/W, and NW bit shown below are accessed. Once
these registers are accessed, the set values are held even if the RE bit is set to zero.
FW: When FW is 1, each displayed character is controlled with a 6-dot width. The user font in CGRAM
is displayed with a 6-bit character width from bits 5 to 0. As for fonts stored in CGROM, no display area
is assigned to the leftmost bit, and the font is displayed with a 5-bit character width. If the FW bit is
changed, data in DDRAM and CGRAM SEGRAM is destroyed. Therefore, set FW before data is written
to RAM. When font width is set to 6 dots, the frame frequency decreases to 5/6 compared to 5-dot time.
See “Oscillator Circuit” for details.
B/W: When B/W is 1, the character at the cursor position is cyclically displayed with black-white
invertion. At this time, bits C and B in display on/off control register are “Don’t care”. When fCP or fOSC is
270 kHz, display is changed by switching every 370 ms.
NW: When NW is 1, 4-line display is performed. At this time, bit N in the function set register is “Don’t
care”.
Note: After changing the N or NW or LP bit, please issue the return home or clear display instructions
to cancel to shift display.
Alternating
display
i) Cursor display example ii) Blink display example
Alternating
display
iii) White-black inverting

display example
Figure 13 Cursor Blink Width Control
324
HD66710
i) 5-dot character width ii) 6-dot character width
Figure 14 Character Width Control
Cursor or Display Shift
Cursor or display shift shifts the cursor position or display to the right or left without writing or reading
display data (Table 8). This function is used to correct or search the display. In a 2-line display, the
cursor moves to the second line when it passes the 40th digit of the first line. In a 4-line display, the
cursor moves to the second line when it passes the 20th character of the line. Note that, all line displays
will shift at the same time. When the displayed data is shifted repeatedly each line moves only
horizontally. The second line display does not shift into the first line position.
These instruction reset the extended register enable bit (RE) to 0 in function set.
The address counter (AC) contents will not change if the only action performed is a display shift.
In low power mode (LP = 1), whole-display shift cannot be normally performed.
Function Set
Only when the extended register enable bit (RE) is 1, the BE bit shown below can be accessed. Bits DL
and N can be accessed regardless of RE.
DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1,
and in 4-bit lengths (DB7 to DB4) when DL is 0.
When 4-bit length is selected, data must be sent or received twice.
Table 8 Shift Function
S/C R/L
0 0 Shifts the cursor position to the left. (AC is decremented by one.)
0 1 Shifts the cursor position to the right. (AC is incremented by one.)
1 0 Shifts the entire display to the left. The cursor follows the display shift.
1 1 Shifts the entire display to the right. The cursor follows the display shift.
325
HD66710
N: When bit NW in the extended function set is 0, a 1- or a 2-line display is set. When N is 0, 1-line
display is selected; when N is 1, 2-line display is selected. When NW is 1, a 4-line display is set. At this
time, N is “Don’t care”.
RE: When the RE bit is 1, bit BE and LP in the extended function set registe, the SEGRAM address set
register, and the extended function set register can be accessed. When bit RE is 0, the registers described
above cannot be accessed, and the data in these registers is held.
To maintain compatibility with the HD44780, the RE bit should be fixed to 0.
Clear display, return home and cursor or display shift instruction a reset the RE bit to 0.
BE: When the RE bit is 1, this bit can be rewritten. When this bit is 1, the user font in CGRAM and the
segment in SEGRAM can be blinked according to the upper two bits of CGRAM and SEGRAM.
LP: When the RE bit is 1, this bit can be rewritten. When LP is set to 1 and the EXT pin is low (without
an extended driver), the HD66710 operates in low power mode. In 1-line display mode, the HD66710
operates on a 4-division clock, and in a 2-line or a 4-line display mode, the HD66710 operates on a 2-
division clock. According to these operations, instruction execution takes four times or twice as long.
Notice that in a low power mode, display shift cannot be performed.
Note: Perform the DL, N, NW, FW functions at the head of the program before executing any
instructions (except for the read busy flag and address instruction). From this point, if bit N, NW,
or FW is changed after other instructions are executed, RAM contents may be lost.
After changing the N or NW or LP bit, please issue the return home or clear display instruction
cancel to shift display.
Set CGRAM Address
A CGRAM address can be set while the RE bit is cleared to 0. Set CGRAM address sets the CGRAM
address binary AAAAAA into the address counter.
Data is then written to or read from the MPU for CGRAM.
Table 9 Display Line Set
No. of
Display Character Duty Maximum Number of Characters/1
N NW Lines Font Factor Line with Extended Drivers
0 0 1 5 × 8 dots 1/17 50 characters
1 0 2 5 × 8 dots 1/33 30 characters
* 1 4 5 × 8 dots 1/33 20 characters
Note: * Indicates don’t care.
326
HD66710
Set DDRAM Address
Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter while the RE
bit is cleared to 0.
Data is then written to or read from the MPU for DDRAM.
However, when N and NW is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 and NW is
0 (2-line display), AAAAAAA is (00)H to (27)H for the first line, and (40)H to (67)H for the second line.
When NW is 1 (4-line display), AAAAAAA is (00)H to (13)H for the first line, (20)H to (33)H for the
second line, (40)H to (53)H for the third line, and (60)H to (73)H for the fourth line.
Set SEGRAM Address
Only when the extended register enable bit (RE) is 1, HS2 to HS0 and the SEGRAM address can be set.
The SEGRAM address in the binary form AAA is set to the address counter. SEGRAM can then be
written to or read from by the MPU.
Note: When performing a horizontal scroll is described above by connecting an extended driver, the
maximum number of characters per line decreases by one. In other words, 49 characters, 29
characters, and 19 characters are displayed in 1-line, 2-line, and 4-line modes, respectively.
Notice that in low power mode (LP = 1), the display shift and scroll cannot be performed.
Read Busy Flag and Address
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating
on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction
will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the
same time, the value of the address counter in binary AAAAAAA is read out. This address counter is
used by all CG, DD, and SEGRAM addresses, and its value is determined by the previous instruction.
The address contents are the same as for CGRAM, DDRAM, and SEGRAM address set instructions.
Table 10 HS2 to HS0 Settings
HS2 HS1 HS0 Description

0 0 0 No shift.
0 0 1 Shift the display position to the left by one dot.
0 1 0 Shift the display position to the left by two dots.
0 1 1 Shift the display position to the left by three dots.
1 0 0 Shift the display position to the left by four dots.
1 0 1 Shift the display position to the left by five dots.
1 1 0 or 1 No shift.
327
HD66710
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Code 0 0 0 0 0 0 0 0 0 1
display
Return Code 0 0 0 0 0 0 0 0 1 * Note: * Don’t care.

home
Entry 0 0 0 0 0 0 0 1 I/D S
Code
mode set
Display 0 0 0 0 0 0 1 D C B
Code
on/off control

Extended RE = 1
function set Code 0 0 0 0 0 0 1 FW B/W NW
Cursor or
Code 0 0 0 0 0 1 3/C R/L * * Note: * Don’t care.
display shift
Function set Code 0 0 0 0 0 DL N RE BE* LP* Note: * BE and LP

can be rewritten
while RE = 1.
Set CGRAM
RE = 0 0 0 0 1 A A A A A A
address Code
Highest Lowest
order bit order bit
Figure 15 Character Width Control
328
HD66710
Set DDRAM RE = 0 0 0 1 A A A A A A A
address
Highest Lowest
order bit order bit
Set SEGRAM RE = 1 0 0 1 HS2 HS1 HS0 A A A

*
address
Read busy flag Code 0 1 BF A A A A A A A

and address
Highest Lowest
order bit order bit
Figure 15 Character Width Control (cont)
329
HD66710
Write Data to CG, DD, or SEGRAM
This instruction writes 8-bit binary data DDDDDDDD to CG, DD or SEGRAM. If the RE bit is cleared,
CG or DDRAM is selected, as determined by the previous specification of the address set instruction; if
the RE bit is set, SEGRAM is selected. After a write, the address is automatically incremented or
decremented by 1 according to the entry mode. The entry mode also determines the display shift
direction.
Read Data from CG, DD, or SEGRAM
This instruction reads 8-bit binary data DDDDDDDD from CG, DD, or SEGRAM. If the RE bit is
cleared, CG or DDRAM is selected, as determined by the previous specification of the address set
instruction; if the RE bit is set, SEGRAM is selected. If no address is specified, the first data read will be
invalid. When executing serial read instructions, the next address is normally read from the next address.
An address set instruction need not be executed just before this read instruction when shifting the cursor
by a cursor shift instruction (when reading from DDRAM). A cursor shift instruction is the same as a set
DDRAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1. However, a display
shift is not executed regardless of the entry mode.
Note: The address counter (AC) is automatically incremented or decremented after write instructions to
CG, DD or SEGRAM. The RAM data selected by the AC cannot be read out at this time even if
read instructions are executed. Therefore, to read data correctly, execute either an address set
instruction or a cursor shift instruction (only with DDRAM), or alternatively, execute a
preliminary read instruction to ensure the address is correctly set up before accessing the data.
Write data to RE = 0/1 1 0 D D D D D D D D

CG, DD, or SEGRAM Code
Higher Lower
order bits order bits
Read data from RE = 0/1 1 0 D D D D D D D D

CG, DD, or SEGRAM Code
Higher Lower
order bits order bits
Figure 15 Character Width Control (cont)
330
HD66710
Interfacing the HD66710
1) Interface to 8-Bit MPUs

HD66710 can interface to 8-bit MPU directly with E clock, or to 8-bit MCU through I/O port. When
number of I/O port in MCU, or interfacing bus width, 4-bit interface function is useful.
RS
R/W
Internal Internal operation

signal
Not
DB7 Data Busy Busy Busy Data
Instruction Instruction
Busy flag check Busy flag check Busy flag check
write write
Figure 16 Example of 8-Bit Data Transfer Timing Sequence
Connection to H8/325 with port (when single chip mode)
C0 E
H8/325 C1 RS HD66710
C2 R/W
8
A0–A7 DB0–DB7
Figure 17 8-Bit MPU Interface
331
HD66710
2) Interface to 4-Bit MPUs
HD66710 can interface to 4-bit MCU through I/O port. 4-bit data for high and low order must be
transferred twice continuously. The DL bit in function set selects the interface data length.
RS
R/W
Internal Internal operation

signal
Not
DB7 IR7 IR3 Busy AC3 Busy AC3 D7 D3
Instruction Instruction
Busy flag check Busy flag check
write write
Figure 18 Example of 4-Bit Data Transfer Timing Sequence
HMCS4019R HD66710
16
D15 RS COM1–
D14 R/W COM16
Connected to
D13 E
40 the LCD
4 SEG1–
R10–R13 DB4 –DB7 SEG40
Figure 19 Interface to HMCS4019R
332
HD66710
Oscillator Circuit
• Relationship between Oscillation frequency and Liquid Crystal Display Frame Frequency
The liquid crystal display frame frequencies of Figure 21 apply only when the oscillation frequency is
270 kHz (one clock period: 3.7 µs).
1) When an external clock is used 2) When an internal oscillator is used The oscillator frequency can be
adjusted by oscillator resistance
(Rf). If Rf is increased or power
supply voltage is decreased, the
Clock OSC1 OSC1 oscillator frequency decreases.
Rf
OSC2 The recommended oscillator
resistor is as follows.
HD66710 HD66710 • Rf = 91 kΩ ± 2% (VCC = 5V)
• Rf = 75 kΩ ± 2% (VCC = 3V)
Figure 20 Oscillator Circuit
(1) 1 /17 duty cycle

200 clocks (6-dot font width: 240 clocks)
1 2 3 4 16 17 1 2 3 16 17
VCC
V1
COM1
V4
V5
1 frame 1 frame
Normal Display Mode (LP = 0) Low Power Mode (LP = 1)

Item 5-Dot Font Width 6-Dot Font Width 5-Dot Font Width 6-Dot Font Width
Line selection period 200 clocks 240 clocks 50 clocks 60 clocks
Frame frequency 79.4 Hz 66.2 Hz 79.4 Hz 66.2 Hz
(2) 1 /33 duty cycle

100 clocks (6-dot font width: 120 clocks)
1 2 3 4 32 33 1 2 3 32 33
VCC
V1
COM1
V4
V5
1 frame 1 frame
Normal Display Mode (LP = 0) Low Power Mode (LP = 1)

Item 5-Dot Font Width 6-Dot Font Width 5-Dot Font Width 6-Dot Font Width
Line selection period 100 clocks 120 clocks 50 clocks 60 clocks
Frame frequency 81.8 Hz 68.2 Hz 81.8 Hz 68.2 Hz
Figure 21 Frame Frequency
333
HD66710
Power Supply for Liquid Crystal Display Drive

1) When an external power supply is used
VCC VCC
R
V1
R
V2
R0
V3
R
V4
R
V5
VR
VEE
2) When an internal booster is used
(Boosting twice) (Boosting three times)
VCC VCC
VCC VCC
NTC-type Vci NTC-type Vci
R R
V1 V1
thermistor GND R thermistor GND R
V2 V2
GND C1 R0 GND C1 R0
1 µF V3 1 µF V3
+ C2 + C2
R R
V4 V4
V5OUT2 R V5OUT2 R
V5OUT3 V5 1 µF + V5OUT3 V5
1 µF + 1 µF
+
GND GND
Notes: 1. Boosting output voltage should not exceed the power supply voltage (2) (13V max.)
in the absolute maximum ratings. Especially, voltage of over 4.3V should not be input
to the reference voltage (Vci) when boosting three times.
2. Vci input terminal is used for reference voltage and power supply for the internal booster.
Input current into the Vci pin needs three times or more of load current through the
bleeder resistor for LCD. So, when it adjusts LCD driving voltage (Vlcd), input voltage
should be controlled with transistor to supply LCD load current.
3. Please notice connection (+/–) when it uses capacitors with poler.
334
HD66710
Table 11 Duty Factor and Power Supply for Liquid Crystal Display Drive
Item Data
Number of Lines 1 2/4
Duty factor 1/17 1/33
Bias 1/5 1/6.7
Divided resistance R R R
R0 R 2.7R
Note: R changes depending on the size of liquid crystal penel. Normally, R must be 4.7 kΩ to 20 kΩ.
335
HD66710
Extension Driver LSI Interface

By bringing the EXT pin high, segment driver pins (SEG37 to SEG40) functions as the extended driver
interface outputs. From these pins, a latch pulse (CL1), a shift clock (CL2), data (D), and an AC signal
(M) are output. The same data is output from the SEG36 pin of the HD66710 and the start segment pin
(Seg1) of the extension driver. Due to the character baundary, the Seg1 output is used for the 5-dot font
width. For the 6-dot font width, the SEG36 output is used, and the Seg1 output of the extension driver
must not be used. When the extension driver LSI interface is used, ground level (GND) must be higher
than the V5 level.
Table 12 Required Number of 40-Output Extension Driver
Controller HD66710* HD44780 HD66702

Display Line 5-Dot Width 6-Dot Width 5-Dot Width 5-Dot Width
16 × 2 lines Not required 1 1 Not required
20 × 2 lines 1 1 2 Not required
24 × 2 lines 1 2 2 1
40 × 2 lines Disabled Disabled 4 3
12 × 4 lines 1 1 Disabled Disabled
Note: * The number of display lines can be extended to 30 × 2 lines or 20 × 4 lines.
1) 1-chip operation 2) When using the extension driver

(EXT = Low, 5-dot font width) (EXT = High, 5-dot font width)
VCC
EXT
GND HD66710
SEG37/CL1
SEG38/CL2
EXT COM1–
24 × 2-line display
SEG39/D
SEG40/M
COM33
COM1– SEG1–
HD66710 16 × 2-line display SEG35
COM33
SEG1–
SEG40
M
D Seg1–
SEG1–SEG40 CL2 Seg35
CL1
Extension driver
Figure 22 HD66710 and the Extension Driver Connection
336
HD66710
When using one HD66710, the start address of COM9–COM16/COM25–COM33 is calculated by adding
8 to the start address of COM9–COM16 COM25–COM32. When extending the address, the start address
is calculated by adding A(10) to COM9–COM16/COM25 to COM32. The relationship betweenmodes
and display start addresses is shown below.
Table 13 Display Start Address in Each Mode
Number of Lines
1-Line Mode 2-Line Mode 4-Line Mode
Output EXT Low EXT High EXT Low EXT High EXT Low/High
COM1–COM8 D00±1 D00±1 D00±1 D00±1 D00±1
COM9–COM16 D08±1 D0A±1 D08±1 D0A±1 D20±1
COM17–COM24 — — D40±1 D40±1 D40±1
COM25–COM32 — — D48±1 D4A±1 D60±1
COM17 S00 S00 — — —
COM33 — — S00 S00 S00
Notes: 1. When an EXT pin is low, the extension driver is not used; otherwise, the extension driver is
used.
2. D— is the start address of display data RAM (DDRAM) for each display line.
3. S— is the start address of segment RAM (SEGRAM).
4. ±1 following D— indicates increment or decrement at display shift.
337
HD66710
Interface to Liquid Crystal Display
• Example of 5-dot font width connection

1 8 9 16
HD66710
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17 ± + – x ÷ = ≠
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG40
COM9
COM10
COM11
COM12
COM13
COM14
COM15
EXT COM16
a) 16 × 1-line + 40-segment display (5-dot font, 1/17 duty)
HD66710 1 8 9 16
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM33 ± + – x ÷ = ≠
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG40
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
EXT
b) 16 × 2-line + 40-segment display (5-dot font, 1/33 duty)
Figure 23 Liquid Crystal Display and HD66710 Connections (Single-Chip Operation)
338
HD66710
• Example of 6-dot font width connection
HD66710 1 2 6 7 8 12
Note: The DDRAM address between
COM1 6th and 7th digits is not contiguous.
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM33 ± + – x ÷ = ≠
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG36
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
EXT COM31
COM32
a) 12 × 2-line + 36-segment display (6-dot font, 1/33 duty)
Figure 24 Liquid Crystal Display and HD66710 Connections (6-Dot Font Width)
339
HD66710
Instruction and Display Correspondence

• 8-bit operation, 16-digit × 1-line display with internal reset
Refer to Table 14 for an example of an 16-digit × 1-line display in 8-bit operation. The HD66710
functions must be set by the function set instruction prior to the display. Since the display data RAM
can store data for 80 characters, a character unit scroll can be performed by a display shift instruction.
A dot unit smooth scroll can also be performed by a horizontal scroll instruction. Since data of display
RAM (DDRAM) is not changed by a display shift instruction, the display can be returned to the first
set display when the return home operation is performed.
The program must set all functions prior to the 4-bit operation (Table 15). When the power is turned
on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation.
Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is
completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 15).
Thus, DB4 to DB7 of the function set instruction is written twice.
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th
digit of the first line has been written. Thus, if there are only 16 characters in the first line, the
DDRAM address must be again set after the 16th character is completed (See Table 16).
The display shift is performed for the first and second lines. If the shift is repeated, the display of the
second line will not move to the first line. The same display will only shift within its own line for the
number of times the shift is repeated.
The RE bit must be set by the function set instruction and then the NW bit must be set by an
extension function set instruction. In this case, 4-line display is always performed regardless of the N
bit setting (Table 17).
In a 4-line display, the cursor automatically moves from the first to the second line after the 20th digit
of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM
address must be set again after the 8th character is completed. Display shifts are performed on all
lines simultaneously.
Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using
Internal Reset Circuit table must be satisfied. If not, the HD66710 must be initialized by
instructions. See the section, Initializing by Instruction.
340
HD66710
Table 14 8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset
Instruction
Step
No. RS R/ : D7 D6 D5 D4 D3 D2 D1 D0 Display Operation
1 Power supply on (the HD66710 is initialized by the internal reset Initialized. No display.
circuit)
2 Function set Sets to 8-bit operation and
0 0 0 0 1 1 0 0 * * selects 1-line display.
Bit 2 must always be cleared.
3 Display on/off control Turns on display and cursor.
_
0 0 0 0 0 0 1 1 1 0 Entire display is in space mode
because of initialization.
4 Entry mode set Sets mode to increment the
_
0 0 0 0 0 0 0 1 1 0 address by one and to shift the
cursor to the right at the time of
write to the RAM.
Display is not shifted.
5 Write data to CGRAM/DDRAM Writes H. DDRAM has already
H_
1 0 0 1 0 0 1 0 0 0 been selected by initialization
when the power was turned on.
6 Write data to CGRAM/DDRAM Writes I.
HI_
1 0 0 1 0 0 1 0 0 1
7 · ·
· ·
· ·
· ·
· ·
HITACHI_
1 0 0 1 0 0 1 0 0 1
9 Entry mode set Sets mode to shift display at the
HITACHI_
0 0 0 0 0 0 0 1 1 1 time of write.
10 Write data to CGRAM/DDRAM Writes a space.
ITACHI _
1 0 0 0 1 0 0 0 0 0
341
HD66710
Table 14 8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset (cont)
Instruction
Step
11 Write data to CGRAM/DDRAM Writes M.
TACHI M_
1 0 0 1 0 0 1 1 0 1
12 ·
·
·
·
·
·
·
·
·
·
13 Write data to CGRAM/DDRAM Writes O.
MICROKO_
1 0 0 1 0 0 1 1 1 1
14 Cursor or display shift Shifts only the cursor position to
MICROKO
_
0 0 0 0 0 1 0 0 * * the left.
15 Cursor or display shift Shifts only the cursor position to
MICROKO
_
0 0 0 0 0 1 0 0 * * the left.
16 Write data to CGRAM/DDRAM Writes C over K.
ICROCO
_
1 0 0 1 0 0 0 0 1 1 The display moves to the left.
17 Cursor or display shift Shifts the display and cursor
MICROCO
_
0 0 0 0 0 1 1 1 * * position to the right.
18 Cursor or display shift Shifts the display and cursor
MICROCO_
0 0 0 0 0 1 0 1 * * position to the right.
ICROCOM_
1 0 0 1 0 0 1 1 0 1
20 ·
·
·
·
·
·
·
·
·
·
21 Return home Returns both display and cursor
HITACHI
_
0 0 0 0 0 0 0 0 1 0 to the original position (address
0).
342
HD66710
Instruction
Step
circuit)
2 Function set Sets to 4-bit operation.
0 0 0 0 1 0 — — — — Clear bit 2. In this case,
— — — — — — — — — — operation is handled as 8 bits by
initialization. *
3 Function set Sets 4-bit operation and
0 0 0 0 1 0 — — — — selects1-line display. Clear BE,
0 0 0 1 0 0 — — — — LP bits. 4-bit operation starts
from this step.
4 Function set Sets 4-bit operation and
0 0 0 0 1 0 — — — — selects1-line display. Clear RE
0 0 0 0 * * — — — — bit.
0 0 0 0 0 0 — — — — to the original position (address
0 0 0 0 1 0 — — — — 0).
_
0 0 0 0 0 0 — — — — Entire display is in space mode
0 0 1 1 1 0 — — — — because of initialization.
_
0 0 0 0 0 0 — — — — address by one and to shift the
0 0 0 1 1 0 — — — — cursor to the right at the time of
write to the DD/CGRAM.
8 Write data to CGRAM/DDRAM Writes H.
H_
1 0 0 1 0 0 — — — — DDRAM has already been
1 0 1 0 0 0 — — — — selected by initialization.
Note: 1. The control is the same as for 8-bit operation beyond step #8.
2. When DB3 to DB0 pins are open in 4-bit mode, the RE, BE, LP bits are set to “1” at step #2.
So, these bits are clear to “0” at step #3.
343
HD66710
Instruction
Step
circuit)
2 Function set Sets to 8-bit operation and

0 0 0 0 1 1 1 0 * * selects 1-line display.
Clear bit 2.
3 Display on/off control Turns on display and cursor. All
_
0 0 0 0 0 0 1 1 1 0 display is in space mode
_
write to the RAM.
H_
6 ·
·
·
·
·
·
·
·
·
·
HITACHI_
1 0 0 1 0 0 1 0 0 1
8 Set DDRAM address Sets RAM address so that the

HITACHI
0 0 1 1 0 0 0 0 0 0 cursor is positioned at the head
_
of the second line.
344
HD66710
Instruction
Step
No. RS R/: D7 D6 D5 D4 D3 D2 D1 D0 Display Operation
9 Write data to CGRAM/DDRAM Writes a space.
HITACHI
1 0 0 1 0 0 1 1 0 1
M_
10 · ·
· ·
· ·
· ·
· ·
11 Write data to CGRAM/DDRAM Writes O.
HITACHI
1 0 0 1 0 0 1 1 1 1
MICROCO_
12 Entry mode set Sets mode to shift display at the

HITACHI
0 0 0 0 0 0 0 1 1 1 time of write.
MICROCO_

ITACHI
1 0 0 1 0 0 1 1 0 1
ICROCOM_
14 · ·
· ·
· ·
· ·
· ·
HITACHI
_
0 0 0 0 0 0 0 0 1 0 to the original position (address
MICROCOM
0).
345
HD66710
Instruction
Step
circuit)
2 Function set Sets to 8 bit operation and the

0 0 0 0 1 1 0 1 * * extended register enable bit.
3 4-line mode set Sets 4-line display.

0 0 0 0 0 0 1 0 0 1
4 Function set Clears the extended register

Clear extended register enable bit enable bit. Setting the N bit is
0 0 0 0 1 1 0 0 * * “don’t care”.

_
0 0 0 0 0 0 1 1 1 0 Entire display is in space mode

_
write to the RAM. Display is not
shifted.
H_
8 —
346
HD66710
Instruction
Step
No. RS R/: D7 D6 D5 D4 D3 D2 D1 D0 Display Operation
HITACHI_
1 0 0 1 0 0 1 0 0 1
10 Set DDRAM address Sets RAM address so that the

HITACHI
0 0 1 0 1 0 0 0 0 0 cursor is positioned at the head
_
of the second line.
11 Write data to CGRAM/DDRAM Writes 0.

HITACHI
1 0 0 0 1 1 0 0 0 0
0_
347
HD66710
Initializing by Instruction
If the power supply conditions for correctly operating the internal reset circuit are not met, initialization
by instructions becomes necessary.
Power on
• Wait for more than 15 ms

after VCC rises to 4.5V
(VCC = 5V)
• Wait for more than 40 ms
(VCC = 3V)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction.
0 0 0 0 1 1 * * * * Function set (Interface is 8 bits long.)
Wait for more than 4.1 ms
Wait for more than 100 µs
BF can be checked after the following instructions.

When BF is not checked, the waiting time between
instructions is longer than the execution instuction
time. (See Table 7.)

Function set
0 0 0 0 1 1 N 0 * *
0 0 0 0 0 0 1 0 0 0 Display off
0 0 0 0 0 0 0 0 0 1 Display clear
0 0 0 0 0 0 0 1 I/D S Entry mode set
Initialization ends
Figure 25 8-Bit Interface
348
HD66710
Power on Important Notice

Notes: 1. When DB3 to DB0 pins are open in 4-bit mode,
the N, RE, BE, LP bits are set to “1”. In this case,
• Wait for more than 15 ms instruction time becomes four times in a low
after VCC rises to 4.5V power mode (LP = “1”).
(VCC = 5V) 2. The low power mode is available in this step, so
• Wait for more than 40 ms instruction time takes four times.
(VCC = 3V)
RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction.
0 0 0 0 1 1 Function set (Interface is 8 bits long.)
Wait for more than 4.1 ms
Wait for more than 100 µs
*1
BF can be checked after the following instructions.

When BF is not checked, the waiting time between
instructions is longer than the execution instuction
RS R/W DB7 DB6 DB5 DB4 time. (See Table 7.)
0 0 0 0 1 0 *1
Function set (4-bit mode).
0 0 0 0 1 0
*2 Function set (4-bit mode, N specification).
0 0 N 1 0 0
BE, LP are clear to “0”
0 0 0 0 1 0
Function set (4-bit mode, N specification).
0 0 N 0 * *
0 0 0 0 0 0
Display off
0 0 1 0 0 0
0 0 0 0 0 0
Display clear
0 0 0 0 0 1
0 0 0 0 0 0
Entry mode set (I/D, S specification)
0 0 0 1 I/D S
Initialization ends
Figure 26 4-Bit Interface
349
HD66710
Horizontal Dot Scroll

Dot unit shifts are performed by setting the horizontal dot scroll bit (HDS) when the extension register is
enabled (RE = 1). By combining this with character unit display shift instructions, smooth horizontal
scrolling can be performed on a 6-dot font width display as shown below.
5-dot font width (FW = 0) 6-dot font width (FW = 1)
No shift performed No shift performed
Shift to the left by one dot Shift to the left by one dot
Shift to the left by two dots Shift to the left by two dots
Shift to the left by three dots Shift to the left by three dots
Shift to the left by four dots Shift to the left by four dots
Shift to the left by five dots
Figure 27 Shift in 5- and 6-Dot Font Width
(1) Method of smooth scroll to the left
1 0 0 0 0 1 DL N 1 * * Enable the extension register
2 0 0 1 0 0 1 * * * * Shift the whole display to the left by one dot
CPU Wait
3 0 0 1 0 1 0 * * * * Shift the whole display to the left by two dots
CPU Wait
4 0 0 1 0 1 1 * * * * Shift the whole display to the left by three dots
CPU Wait
5 0 0 1 1 0 0 * * * * Shift the whole display to the left by four dots
CPU Wait
6 0 0 1 1 0 1 * * * * Shift the whole display to the left by five dots *1
CPU Wait
7 0 0 1 0 0 0 * * * * Perform no shift
8 0 0 0 0 0 1 1 0 * * Shift the whole display to the left by one character *2
CPU Wait
Notes: 1. When the font width is five (FW = 0), this step is skipped.
2. The extended register enable bit (RE) is cleared.
Figure 28 Smooth Scroll to the Left
350
HD66710
(2) Method of smooth scroll to the right

Shift the whole display to the right by one
1 0 0 0 0 0 1 1 1 * * character *2
2 0 0 0 0 1 DL N 1 * * Enable the extension register
CPU Wait
3 0 0 1 1 0 1 * * * * Shift the whole display to the left by five dots *1
CPU Wait
4 0 0 1 1 0 0 * * * * Shift the whole display to the left by four dots
CPU Wait
5 0 0 1 0 1 1 * * * * Shift the whole display to the left by three dots
CPU Wait
6 0 0 1 0 1 0 * * * * Shift the whole display to the left by two dots
CPU Wait
7 0 0 1 0 0 1 * * * * Shift the whole display to the left by one dot

CPU Wait
8 0 0 1 0 0 0 * * * * Perform no shift
Notes: 1. When the font width is five (FW = 0), this step is skipped.
2. The extended register enable bit (RE) is cleared.
Figure 28 Smooth Scroll to the Left (cont)
351
HD66710
Low Power Mode

When LP bit is 1 and the EXT pin is low (without an extended driver), the HD66710 operates in low
power mode. In 1-line display mode, the HD66710 operates on a 4-division clock, and in 2-line or 4-line
display mode, it operates on 2-division clock. So, instruction execution takes four times or twice as long.
Notice that in this mode, display shift and scroll cannot be performed. Clear display shift with the return
home instruction, and the horizontal scroll quantity.

Extended register enable 0 0 0 0 1 DL N 1 BE 0

Clear horizontal scroll quantity
HDS = “000” 0 0 1 0 0 0 0 AS2 AS1 AS0

Set a low power mode
0 0 0 0 1 DL N 1 BE 1

Return home
0 0 0 0 0 0 0 0 1 0
Note: In this operation, instruction execution time

Low power operation
takes four times or twice as long.

Reset a power mode 0 0 0 0 1 DL N 1 BE 0

Return home
0 0 0 0 0 0 0 0 1 0
Figure 29 Low Power Mode Operation
352
HD66710
Absolute Maximum Ratings

Item Symbol Value Unit Notes*
Power supply voltage (1) VCC –0.3 to +7.0 V 1
Power supply voltage (2) VCC–V5 –0.3 to +15.0 V 1, 2
Input voltage Vt –0.3 to VCC +0.3 V 1
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C 4
Notes: If the LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limits is strongly recommended for normal
operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction
and cause poor reliability.
* Refer to the Electrical Characteristics Notes section following these tables.
353
HD66710
DC Characteristics (VCC = 2.7V to 5.5V, Ta = –20°C to +75°C*3)

Item Symbol Min Typ Max Unit Test Condition Notes*
Input high voltage (1) VIH1 0.7VCC — VCC V 6
(except OSC1)
Input low voltage (1) VIL1 –0.3 — 0.2VCC V 6
(except OSC1) –0.3 — 0.6
Input high voltage (2) VIH2 0.7VCC — VCC V 15
(OSC1)
Input low voltage (2) VIL2 — — 0.2VCC V 15
(OSC1)
Output high voltage (1) VOH1 0.75VCC — — V –IOH = 0.1 mA 7
(D0–D7)
Output low voltage (1) VOL1 — — 0.2VCC V IOL = 0.1 mA 7
(D0–D7)
Output high voltage (2) VOH2 0.8VCC — — V –IOH = 0.04 mA 8
(except D0–D7)
Output low voltage (2) VOL2 — — 0.2VCC V IOL = 0.04 mA 8
(except D0–D7)
Driver on resistance RCOM — 2 20 kΩ ±Id = 0.05 mA (COM) 13
(COM) VLCD = 4V
Driver on resistance RSEG — 2 30 kΩ ±Id = 0.05 mA (SEG) 13
(SEG) VLCD = 4V
I/O leakage current ILI –1 — 1 µA VIN = 0 to VCC 9
:
Pull-up MOS current –Ip 5 50 120 µA VCC = 3V
(D0–D7, RS, R/ ) VIN = 0V
Power supply current ICC — 150 300 µA Rf oscillation, external clock 10, 14
VCC = 3V, fOSC = 270 kHz
ILP1 — 80 — µA LP mode, 1/17 duty
ILP2 — 100 — µA LP mode, 1/33 duty
LCD voltage VLCD1 3.0 — 13.0 V VCC–V5, 1/5 bias 16
VLCD2 3.0 — 13.0 V VCC–V5, 1/6.7 bias
Note: * Refer to the Electrical Characteristics Notes section following these tables.
Booster Characteristics

Output voltage VUP2 7.5 8.7 — V Vci = 4.5V, I0 = 0.25 mA, 18, 19
(V5OUT2 pin) C = 1 µF, fOSC = 270 kHz,
Ta = 25°C
Output VUP3 7.0 7.7 — V Vci = 2.7V, I0 = 0.25 mA, 18, 19
voltage(V5OUT3 pin) C = 1 µF, fOSC = 270 kHz,
Ta = 25°C
Input voltage VCi 1.0 — 5.0 V 18, 19,
20
354
HD66710
AC Characteristics (VCC = 2.7V to 5.5V, Ta = –20°C to +75°C*3)
Clock Characteristics

External External clock frequency fcp 125 270 350 kHz 11
clock External clock duty Duty 45 50 55 %
operation
External clock rise time trcp — — 0.2 µs
External clock fall time tfcp — — 0.2 µs
Rf Clock oscillation frequency fOSC 190 270 350 kHz Rf = 91 kΩ, 12
oscillation VCC = 5V
Bus Timing Characteristics (1) (VCC = 2.7V to 4.5V, Ta = –20°C to +75°C*3)
Write Operation
Item Symbol Min Typ Max Unit Test Condition

Enable cycle time tcycE 1000 — — ns Figure 30
Enable pulse width (high level) PWEH 450 — —
Enable rise/fall time tEr, tEf — — 25
Address set-up time (RS, R/ : to E) tAS 60 — —
Address hold time tAH 20 — —
Data set-up time tDSW 195 — —
Data hold time tH 10 — —
Read Operation

Data delay time tDDR — — 360
Data hold time tDHR 5 — —
355
HD66710
Bus Timing Characteristics (2) (VCC = 4.5V to 5.5V, Ta = –20°C to +75°C*3)
Write Operation

Data set-up time tDSW 80 — —
Data hold time tH 10 — —
Read Operation

Data delay time tDDR — — 160
Data hold time tDHR 5 — —
Segment Extension Signal Timing (VCC = 2.7V to 5.5V, Ta = –20°C to +75°C*3)

Clock pulse width High level tCWH 500 — — ns Figure 32
Low level tCWL 500 — —
Clock set-up time tCSU 500 — —
Data set-up time tSU 300 — —
Data hold time tDH 300 — —
M delay time tDM –1000 — 1000
Clock rise/fall time tct — — 600
356
HD66710
Power Supply Conditions Using Internal Reset Circuit

Power supply rise time trCC 0.1 — 10 ms Figure 33
Power supply off time tOFF 1 — —
Electrical Characteristics Notes

1. All voltage values are referred to GND = 0V. If the LSI is used above these absolute maximum
ratings, it may become permanently damaged. Using the LSI within the following electrical
characteristic limits is strongly recommended for normal operation. If these electrical characteristic
conditions are also exceeded, the LSI will malfunction and cause poor reliability.
2. VCC ≥ V5 must be maintained. In addition, if the SEG37/CL1, SEG38/CL2, SEG39/D, and SEG40/M
are used as extension driver interface signals (EXT = high), GND ≥ V5 must be maintained.
3. For die products, specified up to 75°C.
4. For die products, specified by the die shipment specification.
5. The following four circuits are I/O pin configurations except for liquid crystal display output.
Input pin
Pin: E (MOS without pull-up) Pins: RS, R/W (MOS with pull-up)
VCC VCC VCC
PMOS PMOS PMOS
(pull up MOS)
NMOS NMOS
I/O pin
Pins: DB0 –DB7 VCC VCC
(MOS with pull-up) (input circuit)
(pull-up MOS) PMOS PMOS
Input enable
NMOS
VCC
NMOS
PMOS Output enable
data
NMOS
(output circuit)
(tristate)
357
HD66710
6. Applies to input pins and I/O pins, excluding the OSC1 pin.
7. Applies to I/O pins.
8. Applies to output pins.
9. Current flowing through pull-up MOSs, excluding output drive MOSs.
10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive
current flows through the input circuit to the power supply. To avoid this from happening, the input
level must be fixed high or low.
11. Applies only to external clock operation.
Th Tl
Oscillator OSC1
0.7 VCC
0.5 VCC
Open OSC2 0.3 VCC
t rcp t fcp
Th
Duty = × 100%
Th + Tl
12. Applies only to the internal oscillator operation using oscillation resistor Rf.
R f : 75 k Ω ± 2% (when VCC = 3 V to 4V)
OSC1
R f : 91 k Ω ± 2% (when VCC = 4 V to 5V)
Rf Since the oscillation frequency varies depending on the OSC1 and
OSC2 pin capacitance, the wiring length to these pins should be minimized.
OSC2
VCC = 5V VCC = 3V
500 500
400 400
fOSC (kHz)
fOSC (kHz)
300 300
(270) max. (270)
max.
typ.
200 200
typ.
min.
min.
100 100 (75)
50 (91)100 150 50 100 150
R f (k Ω) R f (k Ω)
358
HD66710
13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal
pin (COM1 to COM33).
RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin
(SEG1 to SEG40).
14. The following graphs show the relationship between operation frequency and current consumption.
VCC = 5V VCC = 3V
1.8 1.8
1.6 1.6
1.4 1.4
1.2 max. 1.2
Icc (mA)
Icc (mA)
1.0 1.0
0.8 0.8
0.6 typ. 0.6 max.
0.4 0.4
typ.
0.2 0.2
typ. (LP mode)
0.0 0.0
0 100 200 300 400 500 0 100 200 300 400 500
fOSC or fcp (kHz) fOSC or fcp (kHz)
15. Applies to the OSC1 pin.

16. Each COM and SEG output voltage is within ±0.15V of the LCD voltage (VCC, V1, V2, V3, V4, V5)
when there is no load.
17. The TEST pin must be fixed to the ground, and the EXT or VCC pin must also be connected to the
ground.
18. Booster characteristics test circuits are shown below.
Boosting twice Boosting three times
VCC Vci Rload VCC Vci Rload

IO IO
C1 C1
1 µF 1 µF
+ +
C2 C2
V5OUT2 V5OUT2
1 µF 1 µF
+ +
V5OUT3 V5OUT3
1 µF
GND GND +
359
HD66710
19. Reference data
The following graphs show the liquid crystal voltage booster characteristics.
VUP2 = VCC–V5OUT2
VUP3 = VCC–V5OUT3
(1) VUP2, VUP3 vs Vci
11 typ. 15 typ.
10 14
13
9
VUP2 (V)
VUP3 (V)
12
8 11
7 10
6 9
8
5 7
4 6
2.0 3.0 4.0 5.0 2.0 3.0 4.0 5.0
Vci (V) Vci (V)
Test condition: Vci = VCC, fcp = 270 kHz Test condition: Vci = VCC, fcp = 270 kHz
Ta = 25°C, Rload = 25 kΩ Ta = 25°C, Rload = 25 kΩ
(2) VUP2, VUP3 vs Io

9.0 8.0
8.5 typ. 7.5
min.
VUP2 (V)
VUP3 (V)
8.0 7.0
7.5 6.5
typ.
7.0 6.0 min.
6.5 5.5
6.0 5.0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
Io (mA) Io (mA)
Test condition: Vci = VCC = 4.5V Test condition: Vci = VCC = 2.7V
Rf = 91 kΩ, Ta = 25°C Rf = 75 kΩ, Ta = 25°C
(3) VUP2, VUP3 vs Ta

9.0 8.0
typ.
8.5 min. typ.
7.5 min.
VUP2 (V)
VUP3 (V)
8.0 7.0
7.5 6.5
7.0 6.0
–60 –20 0 20 60 100
–60 –20 0 20 60 100
Ta (°C)
Ta (°C)
Test condition: Vci = VCC = 4.5V
Rf = 91 kΩ, Io = 0.25 mA Test condition: Vci = VCC = 2.7V
Rf = 75 kΩ, Io = 0.25 mA
360
HD66710
(4) VUP2, VUP3 vs Capacitance
9.0
typ. 8.0 typ.
min. min.
8.5 7.5
VUP2 (V)
VUP2 (V)
8.0 7.0
7.5 6.5
7.0 6.0
0.5 1.0 1.5 0.5 1.0 1.5
C (µF) C (µF)
Test condition: Vci = VCC = 4.5V Test condition: Vci = VCC = 2.7V
Rf = 91 kΩ, Io = 0.25 mA Rf = 75 kΩ, Io = 0.25 mA
20. Vci ≤ VCC must be maintained.
Load Circuits
AC Characteristics Test Load Circuits
Data bus: DB0–DB7 Segment extension signals: CL1, CL2, D, M
Test Test
point point
50 pF 30 pF
361
HD66710
Timing Characteristics
VIH1 VIH1
RS VIL1 VIL1
t AS t AH
R/W VIL1 VIL1
PWEH t AH
t Ef
E VIH1 VIH1
VIL1 VIL1 VIL1
t Er
t DSW tH
VIH1 VIH1
DB0 to DB7 Valid data
VIL1 VIL1
t cycE
Figure 30 Write Operation
VIH1 VIH1
RS VIL1 VIL1
t AS t AH
R/W VIH1 VIH1
PWEH t AH
t Ef
E VIH1 VIH1
VIL1 VIL1 VIL1
t Er
t DDR t DHR
VOH1 VOH1
DB0 to DB7 VOL1* Valid data * VOL1
t cycE
Note: VOL1 is assumed to be 0.8V at 2 MHz operation.
Figure 31 Read Operation
362
HD66710
t ct
VOH2 VOH2
CL1 VOL2
t CWH
t CWH
CL2 VOH2
VOL2
t CSU t CWL
t ct
D VOH2
VOL2
t DH
t SU
M
VOL2
t DM
Figure 32 Interface Timing with External Driver
*2
2.7V/4.5V
VCC
0.2V 0.2V 0.2V
t rcc t OFF *1
0.1 ms ≤ t rcc ≤ 10 ms t OFF ≥ 1 ms
Notes: 1. t OFF compensates for the power oscillation period caused by momentary power
supply oscillations.
2. Specified at 4.5V for standard voltage operation, and at 2.7V for low voltage operation.
3. If the above electrical conditions are not satisfied, the internal reset circuit will not
operate normally. In this case, the LSI must be initialized by software. (Refer to the
Initializing by Instruction section.)
Figure 33 Power Supply Sequemce
363

(Dot Matrix Liquid Crystal Display Controller/Driver) : Description

Uploaded by

Copyright:

Available Formats

(Dot Matrix Liquid Crystal Display Controller/Driver) : Description

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

(Dot Matrix Liquid Crystal Display Controller/Driver) : Description

Uploaded by

Copyright:

Available Formats

HD66710

(Dot Matrix Liquid Crystal Display Controller/Driver)

List 1 Programmable Duty Cycles

Number of Displayed Maximum Number of Displayed Characters

LCD-II Family Comparison

HD66710 Block Diagram

OSC1 OSC2 EXT

Segment Character Character Cursor and LCD drive

Vci 8 bytes 64 bytes 9,600 bytes

HD66710 Pin Arrangement

HD66710 Pin Arrangement (TQFP1414-100 Pin)

HD66710 Pad Arrangement

Chip size (X × Y) : 5.36 mm × 6.06 mm

HD66710 Pad Location Coordinates

Busy Flag (BF)

Address Counter (AC)

Table 2 Register Selection

Display Data RAM (DDRAM)

• 1-line display (N = 0) (Figure 2)

High order Low order

Figure 1 DDRAM Address

Figure 2 1-Line Display

COM1 to 8 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E COM9 to 16 (Right shift display)

Figure 3 1-line by 16-Character Display Example

Figure 4 2-line by 16-Character Display Example

1 2 3 4 5 6 7 8 9 10 1112 1314 15 16 17 18 19 20 21 22 23 24 Display position

Figure 5 2-Line by 24 Character Display Example

Figure 6 4-Line Display

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 17 18 19 20 Display position

HD66710 Extension driver (1) Extension driver (2)

(Display shift left) (Display shift right)

Figure 7 4-Line by 20-Character Display Example

Character Generator ROM (CGROM)

Character Generator RAM (CGRAM)

Segment RAM (SEGRAM)

Modifying Character Patterns

• Character pattern development procedure

Create character Create EPROM

Evaluate Write EPROM 3

Figure 8 Character Pattern Development Procedure

EPROM Address MSB Data LSB

Character code “0” Line position

Notes: 1. EPROM addresses A11 to A4 correspond to a character code.

a) When Character Pattern in 5 × 8 Dots

b) When Character Pattern in 6 × 8 Dots

SEGRAM SEGRAM data

Blinking control Pattern on/off Blinking control Pattern on/off

i) 5-dot font width (FW = 0)

Figure 9 Relationships between SEGRAM Data and Display

Timing Generation Circuit

Liquid Crystal Display Driver Circuit

Cursor/Blink Control Circuit

AC6 AC5 AC4 AC3 AC2 AC1 AC0

For a 1-line display

Figure 10 Cursor/Blink Display Example

Interfacing to the MPU

DB7 IR7 IR3 BF AC3 DR7 DR3

DB6 IR6 IR2 AC6 AC2 DR6 DR2

DB5 IR5 IR1 AC5 AC1 DR5 DR1