Quectel BC66-OpenCPU Hardware Design V1.2

BC66-OpenCPU
Hardware Design
LPWA Module Series
Rev. BC66-OpenCPU_Hardware_Design_V1.2
Date: 2019-05-06
Status: Released
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LPWA Module Series
BC66-OpenCPU Hardware Design
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BC66-OpenCPU_Hardware_Design 1 / 62
LPWA Module Series
About the Document
History
Revision Date Author Description
Brooke WANG/
1.0 2018-08-31 Initial
Newgate HUA
Updated supported bands and involved RF
1.1 2018-11-14 Newgate HUA
parameters of BC66-OpenCPU.
1. Enabled USB interface and added its related
description (Chapters 2.3, 3.2, 3.3 & 3.7).
2. Enabled additional five GPIO interfaces.
3. Optimized the description of the module’s
operating modes (Chapter 3.4).
4. Added a note for the reference design of power
supply (Chapter 3.6.2).
Speed SUN/
1.2 2019-05-06 5. Added ADC sample range (Chapter 3.12).
Allan LIANG
6. Added the current consumption values for band 4
and the testing conditions (Chapter 5.2).
7. Updated the module’s recommended stencil
thickness and peak reflow temperatures (Chapter
7.2).
8. Updated multiplexed pins and their functions
(Appendix B).
LPWA Module Series
Contents
About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3
Table Index ................................................................................................................................................... 5
Figure Index ................................................................................................................................................. 6
1 Introduction .......................................................................................................................................... 7
1.1. Safety Information ....................................................................................................................... 8
2 Product Concept .................................................................................................................................. 9

2.1. General Description .................................................................................................................... 9
2.2. Key Features ............................................................................................................................. 10
2.3. Functional Diagram ................................................................................................................... 12
2.4. Development Board .................................................................................................................. 12
3 Application Interfaces ....................................................................................................................... 13

3.1. General Description .................................................................................................................. 13
3.2. Pin Assignment ......................................................................................................................... 14
3.3. Pin Description .......................................................................................................................... 15
3.4. Operating Modes....................................................................................................................... 19
3.5. Power Saving Mode (PSM)....................................................................................................... 20
3.6. Power Supply ............................................................................................................................ 21
3.6.1. Power Supply Pins ......................................................................................................... 21
3.6.2. Reference Design for Power Supply .............................................................................. 22
3.7. Power on/off Scenarios ............................................................................................................. 23
3.7.1. Turn on ........................................................................................................................... 23
3.7.2. Turn off ........................................................................................................................... 24
3.7.3. Reset the Module ........................................................................................................... 25
3.8. USB Interface ............................................................................................................................ 27
3.9. UART Interfaces ........................................................................................................................ 28
3.9.1. Main UART Port ............................................................................................................. 29
3.9.2. Debug UART Port .......................................................................................................... 29
3.9.3. Auxiliary UART Port ....................................................................................................... 30
3.9.4. UART Application ........................................................................................................... 30
3.10. SPI Interface ............................................................................................................................. 32
3.11. USIM Interface .......................................................................................................................... 33
3.12. ADC Interface............................................................................................................................ 35
4 Antenna Interface ............................................................................................................................... 36

4.1. Pin Definition ............................................................................................................................. 36
4.2. Operating Frequencies ............................................................................................................. 36
4.3. RF Antenna Reference Design ................................................................................................. 37
4.4. Reference Design of RF Layout ............................................................................................... 38
4.5. Antenna Requirements ............................................................................................................. 40
LPWA Module Series
4.6. RF Output Power ...................................................................................................................... 41

4.7. RF Receiving Sensitivity ........................................................................................................... 42
4.8. Recommended RF Connector for Antenna Installation ............................................................ 43
5 Electrical and Reliability Characteristics ........................................................................................ 45

5.1. Operation and Storage Temperatures....................................................................................... 45
5.2. Current Consumption ................................................................................................................ 45
5.3. Electrostatic Discharge ............................................................................................................. 47
6 Mechanical Dimensions .................................................................................................................... 49

6.1. Mechanical Dimensions of the Module ..................................................................................... 49
6.2. Recommended Footprint .......................................................................................................... 51
6.3. Top and Bottom Views of the Module ....................................................................................... 52
7 Storage, Manufacturing and Packaging .......................................................................................... 53

7.1. Storage ...................................................................................................................................... 53
7.2. Manufacturing and Soldering .................................................................................................... 54
7.3. Packaging ................................................................................................................................. 55
7.3.1. Tape and Reel Packaging .............................................................................................. 55
8 Appendix A References..................................................................................................................... 57
9 Appendix B Multiplexed Pins ........................................................................................................... 60
LPWA Module Series
Table Index
TABLE 1: FREQUENCY BANDS OF BC66-OPENCPU MODULE ..................................................................... 9

TABLE 2: BC66-OPENCPU KEY FEATURES .................................................................................................. 10
TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 15
TABLE 4: PIN DESCRIPTION ........................................................................................................................... 15
TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................. 19
TABLE 6: POWER SUPPLY PINS..................................................................................................................... 22
TABLE 7: PWRKEY PIN .................................................................................................................................... 23
TABLE 8: RESET PIN ........................................................................................................................................ 25
TABLE 9: PIN DEFINITION OF USB INTERFACE ........................................................................................... 27
TABLE 10: PIN DEFINITION OF UART INTERFACES..................................................................................... 28
TABLE 11: PIN DEFINITION OF SPI INTERFACE ........................................................................................... 33
TABLE 12: PIN DEFINITION OF USIM INTERFACE ........................................................................................ 34
TABLE 13: PIN DEFINITION OF ADC INTERFACE ......................................................................................... 35
TABLE 14: PIN DEFINITION OF NB-IOT ANTENNA INTERFACE ................................................................... 36
TABLE 15: MODULE OPERATING FREQUENCIES ........................................................................................ 36
TABLE 16: ANTENNA CABLE INSERTION LOSS REQUIREMENTS ............................................................. 40
TABLE 17: REQUIRED ANTENNA PARAMETERS .......................................................................................... 40
TABLE 18: RF OUTPUT POWER ..................................................................................................................... 41
TABLE 19: RF RECEIVING SENSITIVITY (WITH RF RETRANSMISSIONS) ................................................. 42
TABLE 20: OPERATION AND STORAGE TEMPERATURES .......................................................................... 45
TABLE 21: MODULE CURRENT CONSUMPTION (3.3V VBAT POWER SUPPLY)........................................ 46
TABLE 22: ELECTROSTATIC DISCHARGE CHARACTERISTICS (25ºC, 45% RELATIVE HUMIDITY) ........ 48
TABLE 23: RECOMMENDED THERMAL PROFILE PARAMETERS ............................................................... 54
TABLE 24: RELATED DOCUMENTS ................................................................................................................ 57
TABLE 25: TERMS AND ABBREVIATIONS ...................................................................................................... 57
TABLE 26: MULTIPLEXED PINS AND THEIR FUNCTIONS ............................................................................ 60
LPWA Module Series
Figure Index
FIGURE 1: BC66-OPENCPU FUNCTIONAL DIAGRAM .................................................................................. 12

FIGURE 2: PIN ASSIGNMENT ......................................................................................................................... 14
FIGURE 3: MODULE OPERATING MODES .................................................................................................... 20
FIGURE 4: MODULE POWER CONSUMPTION IN DIFFERENT MODES ...................................................... 20
FIGURE 5: TIMING OF WAKING UP MODULE FROM PSM ........................................................................... 21
FIGURE 6: REFERENCE CIRCUIT FOR POWER SUPPLY ............................................................................ 22
FIGURE 7: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 23
FIGURE 8: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 24
FIGURE 9: POWER ON TIMING ...................................................................................................................... 24
FIGURE 10: POWER OFF TIMING (TURN OFF BY AT COMMAND) .............................................................. 25
FIGURE 11: POWER OFF TIMING (POWER OFF BY DISCONNECTING VBAT) .......................................... 25
FIGURE 12: REFERENCE DESIGN OF RESET WITH A DRIVING CIRCUIT ................................................. 26
FIGURE 13: REFERENCE DESIGN OF RESET WITH A BUTTON ................................................................. 26
FIGURE 14: RESET TIMING............................................................................................................................. 26
FIGURE 15: USB INTERFACE REFERENCE DESIGN ................................................................................... 27
FIGURE 16: REFERENCE DESIGN OF MAIN UART PORT ........................................................................... 29
FIGURE 17: REFERENCE DESIGN OF DEBUG UART PORT ....................................................................... 30
FIGURE 18: REFERENCE DESIGN OF AUXILIARY UART PORT .................................................................. 30
FIGURE 19: REFERENCE CIRCUIT WITH VOLTAGE LEVEL TRANSLATOR CHIP ...................................... 31
FIGURE 20: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 31
FIGURE 21: SKETCH MAP FOR RS-232 INTERFACE MATCH ...................................................................... 32
FIGURE 22: REFERENCE DESIGN OF SPI INTERFACE WITH A TRANSLATOR CHIP ............................... 33
FIGURE 23: REFERENCE DESIGN OF USIM INTERFACE WITH A 6-PIN USIM CARD CONNECTOR ...... 34
FIGURE 24: REFERENCE DESIGN OF NB-IOT ANTENNA INTERFACE ...................................................... 38
FIGURE 25: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ...................................................................... 38
FIGURE 26: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB .................................................. 39
FIGURE 27: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE
GROUND) .................................................................................................................................................. 39
FIGURE 28: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE
GROUND) .................................................................................................................................................. 39
FIGURE 29: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ................................................ 43
FIGURE 30: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 43
FIGURE 31: BC66-OPENCPU TOP AND SIDE DIMENSIONS (UNIT: MM) .................................................... 49
FIGURE 32: TAPE DIMENSIONS (UNIT: MM).................................................................................................. 56
FIGURE 33: REEL DIMENSIONS (UNIT: MM) ................................................................................................. 56
LPWA Module Series
1 Introduction
This document defines the BC66-OpenCPU module and describes its air interface and hardware
interfaces which are connected with customers’ applications.
This document can help customers quickly understand BC66-OpenCPU module interface specifications,
electrical and mechanical details, as well as other related information of the module. Associated with
application notes and user guides, customers can use BC66-OpenCPU to design and set up mobile
applications easily.
LPWA Module Series
1.1. Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating BC66-OpenCPU module. Manufacturers of the
cellular terminal should send the following safety information to users and operating personnel, and
incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no
liability for customers’ failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If the device offers an Airplane Mode, then it should be
enabled prior to boarding an aircraft. Please consult the airline staff for more
restrictions on the use of wireless devices on boarding the aircraft.
Wireless devices may cause interference on sensitive medical equipment, so

please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, please remember using emergency call. In order to make or receive a
call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.
LPWA Module Series
2 Product Concept
2.1. General Description
OpenCPU is a solution where the module acts as a main processor. With the development of
communication technology and the ever-changing market demands, more and more customers have
realized the advantages of OpenCPU solution. Especially, its advantage in reducing the product cost is
greatly valued by customers. With OpenCPU solution, development flow for wireless application and
hardware design will be simplified. Main features of OpenCPU solution are listed below:
 Simplifies the development of embedded applications, and shortens product development cycle
 Simplifies circuit design, and reduces product cost
 Decreases the size of terminal products
 Reduces power consumption
 Supports firmware and APP bin upgrade via DFOTA
 Anti-copy technology to enhance product safety
 Improves products’ cost-performance ratio, and enhances products’ competitiveness
BC66-OpenCPU is a high-performance NB-IoT module with extremely low power consumption. It is

designed to communicate with infrastructures of mobile network operators through NB-IoT radio protocols
(3GPP Rel.13 and 3GPP Rel.14*). And it supports a broad range of frequency bands as listed below.
Table 1: Frequency Bands of BC66-OpenCPU Module
Mode BC66-OpenCPU
H-FDD B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B19/B20/B25/B26*/B28/B66
BC66-OpenCPU is an SMD type module with LCC package, and has an ultra-compact profile 17.7mm ×
15.8mm × 2.0mm. These make it can be easily embedded into size-constrained applications and provide
reliable connectivity with the applications.
BC66-OpenCPU provides abundant external interfaces (USB, UART, GPIO, SPI, ADC, etc.) and protocol
stacks (UDP/TCP, MQTT, LwM2M, etc.), which provide great convenience for customers' applications.
LPWA Module Series
Due to compact form factor, ultra-low power consumption and extended temperature range,
BC66-OpenCPU is a best choice for a wide range of IoT applications, such as smart metering, bike
sharing, smart wearables, smart parking, smart city, security and asset tracking, home appliances,
agricultural and environmental monitoring, etc. It is able to provide a complete range of SMS* and data
transmission services to meet customers’ demands.
The module fully complies with the RoHS directive of the European Union.
NOTE
“*” means under development.
2.2. Key Features
The following table describes the detailed features of BC66-OpenCPU module.
Table 2: BC66-OpenCPU Key Features
Feature Details
 Supply voltage: 2.1V ~ 3.63V

Power Supply
 Typical supply voltage: 3.3V
Power Saving  Typical power consumption: 3.5uA
LTE Cat NB1:

Frequency bands
 B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B19/B20/B25/B26*/B28/B66
Transmitting Power  23dBm±2dB
USIM Interface  Support 1.8V USIM card
 Conform to USB 1.1 specifications, with maximum data transfer rate up to

12Mbps
USB Interface
 Used for software debugging and upgrading
 Support USB serial driver under Windows/Linux operating systems
Main UART Port:
 Used for AT command communication and data transmission.
 By default, the module is in auto-baud mode, and it supports automatic
UART Interfaces baud rates not exceeding 115200bps. When powering on the module, the
MCU has to send AT command consecutively to synchronize baud rate
with the module. When OK is returned, it indicates the baud rate has been
synchronized successfully. When the module is woken up from PSM or
LPWA Module Series
idle mode, the baud rate synchronized during start-up will be used directly.
 Also can be used for firmware upgrade, and in such case, the baud rate is
921600bps by default.
Debug UART Port:
 Used for firmware debugging
 Default baud rate: 115200bps
Auxiliary UART Port:
 Used for firmware debugging
 Hardware flow control* supported
 Default baud rate: 115200bps
Network Protocols  UDP/TCP/LwM2M/MQTT/DTLS/SNTP/CoAP*/PPP*/TLS*/HTTP*/HTTPS*
SMS*  Text/PDU Mode
 Single-tone: 25.5kbps (DL)/16.7kbps (UL)

Data Transmission
 Multi-tone: 25.5kbps (DL )/62.5kbps (UL)
 3GPP TS 27.005/3GPP TS 27.007 AT commands (3GPP Rel. 13/Rel.14*)
AT Commands
and Quectel enhanced AT commands
Firmware Upgrade  Upgrade firmware via DFOTA, USB or main UART port
Real Time Clock  Supported
Physical  Size: (17.7±0.15)mm × (15.8±0.15)mm × (2.0±0.2)mm

Characteristics  Weight: 1.2g±0.2g
 Operation temperature range: -35°C ~ +75°C 1)
Temperature Range  Extended temperature range: -40°C ~ +85°C 2)
 Storage temperature range: -40°C ~ +90°C
Antenna Interface  50Ω impedance control
RoHS  All hardware components are fully compliant with EU RoHS directive
NOTES
1. 1) Withinoperation temperature range, the module is 3GPP compliant.

2. 2) Within extended temperature range, the module remains the ability to establish and maintain an
SMS*, data transmission, etc. There is no unrecoverable malfunction. There are also no effects on
radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in
their value and exceed the specified tolerances. When the temperature returns to normal operation
temperature levels, the module will meet 3GPP specifications again.
3. "*" means under development.
LPWA Module Series
2.3. Functional Diagram
The following figure shows a block diagram of BC66-OpenCPU and illustrates the major functional parts.
 Radio frequency
 Baseband
 Power management
 Peripheral interfaces
VBAT Boost ASM RF_ANT

Enable PA
RX
TX
XO
26MHz
XTAL
RF Transceiver
and Subsystem
BUCK
MAIN_UART
Baseband
LDO
PMU AUX_URAT
VDD_EXT
Flash
DBG_UART
PSRAM
SPI
USB
RTC BLOCK USIM GPIOs
32KHz
PSM_ENIT PWRKEY RESET NETLIGHT ADC USIM
Figure 1: BC66-OpenCPU Functional Diagram
NOTE
2.4. Development Board
Quectel provides a complete set of development tools to facilitate the use and testing of BC66-OpenCPU
module. The development tool kit includes the TE-B board, USB cable, antenna and other peripherals.
For more details, please refer to document [1].
LPWA Module Series
3 Application Interfaces
3.1. General Description
BC66-OpenCPU is equipped with a total of 58 pins, including 44 LCC pins and 14 LGA pins. The
subsequent chapters will provide detailed descriptions of the following functions/pins/interfaces:
 PSM
 Power Supply
 PWRKEY
 RESET
 USB Interface
 UART Interfaces
 SPI Interface
 USIM Interface
 ADC Interface
LPWA Module Series
3.2. Pin Assignment
RESERVED
RXD_DBG
TXD_DBG
VBAT_RF
VBAT_BB
GND
GND
GND
GND
44
43
42
40
37
41
39
38
36
GND 1 35 RF_ANT
RESERVED 2 34 GND
SPI_MISO 3 33 GPIO5
SPI_MOSI 4 58 57 56 32 GPIO4
45 55
SPI_SCLK 5 31 GPIO3
SPI_CS 6 46 Module 54 GPIO8 30 GPIO2
PWRKEY 7 Top View 29 TXD_AUX
USB_MODE 47 53 GPIO7
GPIO0 8 28 RXD_AUX
ADC0* 9 48 52 GPIO6 27 GND
SIM_GND 10 49 50 51 26 GPIO1
SIM_DATA 11 25 RESERVED
USB_DM
VUSB_3V3
USB_DP
SIM_RST 12 24 VDD_EXT
SIM_CLK 13 23 RTS_AUX*
15
16
17
18
20
14
19
21
22
RESET
NETLIGHT
RI
SIM_VDD
RXD
TXD
PSM_EINT
CTS_AUX*
DCD*
POWER GND UART USIM ANT
USB RESERVED SPI GPIO OTHERS
Figure 2: Pin Assignment
NOTES
1. Keep all reserved pins unconnected.

2. “*” means under development.
LPWA Module Series
3.3. Pin Description
The following table describes the pin definition of BC66-OpenCPU module in details.
Table 3: I/O Parameters Definition
Type Description
AI Analog input
AO Analog output
DI Digital input
DO Digital output
IO Bidirectional
PI Power input
PO Power output
Table 4: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
Power supply for Vmax=3.63V

VBAT_BB 42 PI the module’s Vmin=2.1V
baseband part Vnorm=3.3V
Power supply for Vmax=3.63V
VBAT_RF 43 PI the module’s RF Vmin=2.1V
part Vnorm=3.3V
No voltage output in
PSM mode.
It is intended to supply
power for the module’s
1.8V output power
VDD_EXT 24 PO Vnorm=1.8V pull-up circuits, and is
supply
thus not recommended
to be used as the
power supply for
external circuits.
GND 1, 27, 34, GND
LPWA Module Series
36, 37, 40,

41
Power Key Interface
Pull down
VILmax=0.3*VBAT
PWRKEY 7 DI PWRKEY to turn on
VIHmin=0.7*VBAT
the module
Reset Interface
RESET 15 DI Reset the module Active low.
PSM_EINT Interface
Dedicated external
interrupt pin.
PSM_EINT 19 DI Used to wake up
the module from
PSM.
Network Status Indication
Network status
NETLIGHT 16 DO
indication
ADC Interface
General purpose
Voltage range:
ADC0 9 AI analog to digital
0V~1.4V
converter interface
Main UART Port
Receive data from

RXD 18 DI
TXD of DTE
1.8V power domain.
Transmit data to
TXD 17 DO
RXD of DTE
Auxiliary UART Port
LPWA Module Series
Receive data from

RXD_AUX 28 DI
TXD of DTE
Transmit data to
TXD_AUX 29 DO
RXD of DTE
CTS_AUX* 22 DO Clear to send 1.8V power domain.
RTS_AUX* 23 DI Request to send
Data carrier
DCD* 21 DO
detection
Debug UART Port
RXD_DBG 38 DI Receive data

1.8V power domain.
TXD_DBG 39 DO Transmit data
Ringing Signal
Ring indication
RI 20 DO 1.8V power domain.
signal
USIM Interface
USIM card power

SIM_VDD 14 DO Vnorm=1.8V
supply
USIM card reset VOLmax=0.15×SIM_VDD
SIM_RST 12 DO
signal VOHmin=0.85×SIM_VDD
VILmax=0.25×SIM_VDD
USIM card data VIHmin=0.75×SIM_VDD
SIM_DATA 11 IO
signal VOLmax=0.15×SIM_VDD
VOHmin=0.85×SIM_VDD
USIM card clock VOLmax=0.15×SIM_VDD
SIM_CLK 13 DO
signal VOHmin=0.85×SIM_VDD
Specified ground
SIM_GND 10 GND
for USIM card
Antenna Interface
RF antenna 50Ω characteristic

RF_ANT 35 IO
interface impedance.
LPWA Module Series
GPIO Interfaces
GPIO0 8 IO
GPIO1 26 IO
GPIO2 30 IO
GPIO3 31 IO
General purpose
GPIO4 32 IO Input/output 1.8V power domain.
interfaces
GPIO5 33 IO
GPIO6 52 IO
GPIO7 53 IO
GPIO8 54 IO
SPI Interface
Master input slave

SPI_MISO 3 DI output of SPI
interface
Master output slave
SPI_MOSI 4 DO input of SPI
1.8V power domain.
interface
Serial clock signal
SPI_SCLK 5 DO
of SPI interface
Chip selection of
SPI_CS 6 DO
SPI interface
USB Interface
Pull down the pin to

USB_MODE 47 DI achieve USB 1.8V power domain.
download function
VUSB_3V3 49 PI USB power supply Vnorm=3.3V
USB differential Conform to USB 1.1

USB_DP 50 IO
data (+) specifications.
Request 90 Ω
USB differential
USB_DM 51 IO differential
data (-)
impedance.
LPWA Module Series
Reserved Pins
2, 25,
44~46, Keep these pins
RESERVED
48, unconnected.
55~58
NOTE
BC66-OpenCPU provides 23 GPIOs, some of which can be multiplexed into other functions. When the
default function is not used, the corresponding pin can be configured into GPIO. For details about
multiplexed pins, please refer to Appendix B.
3.4. Operating Modes
The following table briefly describes the three operating modes of the module.
Table 5: Overview of Operating Modes
Mode Description of Operating Modes
In connected mode, the module is in “Active” status. All functions of the

module are available and all processors are active; radio transmission
Connected
and reception can be performed. Transitions to idle mode or PSM can
be initiated in connected mode.
In idle mode, the module is in “Light Sleep” status and network
Normal connection is maintained in DRX/eDRX state; paging messages can be
Idle
Operation received. Transitions to connected mode or PSM can be initiated in idle
mode.
In PSM, the module is in “Deep Sleep” status and only the 32kHz RTC
is working. CPU is powered off; the network is disconnected and thus
PSM
cannot receive downlink data. Transitions to connected mode can be
initiated in PSM.
LPWA Module Series
Connected
Software control
CPU PSM
Active
1. RTC event CPU
2. PSM_EINT
Deep Sleep
Only 32KHz RTC is

Software active
control
Idle
CPU
Light Sleep
Figure 3: Module Operating Modes
3.5. Power Saving Mode (PSM)
Based on system performance, the module consumes an ultra-low current (3.5μA typical power
consumption) in PSM. PSM is designed to reduce power consumption of the module and improve battery
life. The following figure shows the power consumption of the module in different modes.
Power Consumption
Transmission
Reception
Idle PSM
Idle
T3324
UE inactive time T3412 TAU
Figure 4: Module Power Consumption in Different Modes
The procedure for entering PSM is as follows: the module requests to enter PSM in “ATTACH REQUEST”
message during attach/TAU (Tracking Area Update) procedure. Then the network accepts the request
and provides an active time value (T3324) to the module and the mobile reachable timer starts. When the
T3324 timer expires, the module enters PSM for duration of T3412 (periodic TAU timer). Please note that
LPWA Module Series
the module cannot request PSM when it is establishing an emergency attachment or initializing the PDN
(Public Data Network) connection.
When the module is in PSM, it cannot be paged and stops access stratum activities such as cell
reselection, but T3412 is still active.
Either of the following methods can make the module exit from PSM:
 After the T3412 timer expires, the module will exit PSM automatically.
 Pulling down PSM_EINT (falling edge) will wake the module up from PSM. The timing of waking up
the module from PSM is illustrated below.
VBAT
4ms
PSM_EINT
VDD_EXT
Module
OFF RUNNING
Status
Figure 5: Timing of Waking up Module from PSM
NOTE
Among all GPIO interrupts, only the dedicated external interrupt pin PSM_EINT can successfully wake up
the module from PSM. The module cannot be woken up by any other general purpose GPIO interrupts.
3.6. Power Supply
3.6.1. Power Supply Pins
BC66-OpenCPU provides two VBAT pins for connection with an external power supply. The table below
describes the module's VBAT and ground pins.
LPWA Module Series
Table 6: Power Supply Pins
Pin Name Pin No. Description Min. Typ. Max. Unit

Power supply for the module’s
VBAT_BB 42 2.1 3.3 3.63 V
baseband part
Power supply for the module’s
VBAT_RF 43 2.1 3.3 3.63 V
RF part
1, 27, 34,
GND GND
36, 37, 40, 41
3.6.2. Reference Design for Power Supply
Power design for a module is critical to its performance. It is recommended to use a low quiescent current
LDO with output current capacity of 0.5A as the power supply for the module. A Li-MnO2/2S alkaline
battery can also be used as the power supply. The supply voltage of the module ranges from 2.1V to
3.63V. When the module is working, please make sure its input voltage will never drop below 2.1V,
otherwise the module will be abnormal.
For better power performance, it is recommended to place a 100uF tantalum capacitor with low ESR
(ESR=0.7Ω) and three ceramic capacitors (100nF, 100pF and 22pF) near the VBAT pins. Also, it is
recommended to add a TVS diode on the VBAT trace (near VBAT pins) to improve surge voltage
withstand capability. In principle, the longer the VBAT trace is, the wider it should be. A reference circuit
for power supply is illustrated in the following figure.
Module
VBAT
VBAT_RF
VBAT_BB
D1 + C1 C2 C3 C4
TVS
100uF 100nF 100pF 22pF
0402 0402
GND
GND
Figure 6: Reference Circuit for Power Supply
NOTE
During the module’s power-on or reset, an instantaneous current of 700mA will be generated for a period
LPWA Module Series
of 200us. To decrease the current, it is recommended to connect a large-capacitance capacitor to VBAT. If

the load capacity of power supply is insufficient, then a 100uF tantalum capacitor is recommended.
3.7. Power on/off Scenarios
3.7.1. Turn on
BC66-OpenCPU can be turned on by driving the PWRKEY pin to a low level voltage for at least 500ms.
Table 7: PWRKEY Pin
Pin Name Pin No. Description PWRKEY Pull-down Time
Pull down PWRKEY to turn

PWRKEY 7 ≥500ms
on the module
It is recommended use an open drain/collector driver to control the PWRKEY. A simple reference design
is illustrated in the following figure.
PWRKEY
4.7K
Turn on pulse
47K
Figure 7: Turn on the Module Using Driving Circuit
Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike
may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference design is shown in the following figure.
LPWA Module Series
S1
PWRKEY
TVS
Close to S1
Figure 8: Turn on the Module Using Keystroke
The power on timing is illustrated in the following figure.
≥500ms
VBAT
PWRKEY
42ms
VDD_EXT
Module OFF BOOTING RUNNING

Status
Figure 9: Power on Timing
NOTE
PWRKEY cannot be pulled down all the time, otherwise the module will not be able to enter into PSM.
3.7.2. Turn off
BC66-OpenCPU can be turned off through any of the following methods:
 Turn off the module by AT+QPOWD=0.

 In emergent conditions, the module can be powered off through disconnecting VBAT power supply.
 The module will be powered off automatically when VBAT drops below 2.1V.
LPWA Module Series
VBAT
1.02s
AT+QPOWD=0
VDD_EXT
Module
Status RUNNING OFF
Figure 10: Power off Timing (Turn off by AT Command)
≥5ms
VBAT
VDD_EXT
Module
Status RUNNING OFF
Figure 11: Power off Timing (Power off by Disconnecting VBAT)
3.7.3. Reset the Module
Driving the RESET pin to a low level voltage for at least 50ms will reset the module.
Table 8: Reset Pin
Pin Name Pin No. Description Reset Pull-down Time
Reset the module.

RESET 15 ≥50ms
Active low.
The recommended circuits of resetting the module are shown below. An open drain/collector driver or
LPWA Module Series
button can be used to control the RESET pin.
RESET
4.7K
Reset pulse
47K
Figure 12: Reference Design of RESET with a Driving Circuit
S1
RESET
TVS
Close to S1
Figure 13: Reference Design of RESET with a Button
The reset timing is illustrated in the following figure.
VBAT
≥50ms
20ms
RESET
VDD_EXT
············
Module
Running Resetting Restart
Status
Figure 14: Reset Timing
LPWA Module Series
3.8. USB Interface
The USB interface of BC26-OpenCPU module conforms to USB 1.1 specifications and supports full
speed (12Mbps) mode. The interface can be used for software debugging and software upgrading, and
supports USB serial driver under Windows/Linux operating systems.
The following table is the pin definition of USB interface:
Table 9: Pin Definition of USB Interface
Pin Name Pin No. I/O Description Note
Pull down the pin to achieve USB

USB_MODE 47 DI 1.8V power domain.
download function
VUSB_3V3 49 PI USB power supply Vnorm=3.3V
USB_DP 50 IO USB differential data (+) Conform to USB 1.1

specifications.
Require 90Ω differential
USB_DM 51 IO USB differential data (-)
impedance.
The following is a reference design of USB interface:
Module PC
3.3V
VUSB_3V3 ESD Array
USB_DM USB_DM
USB_DP USB_DP
GND GND
Figure 15: USB Interface Reference Design
In the circuit design of USB interface, in order to ensure the performance of USB, the following principles
are suggested in the circuit design:
 It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
LPWA Module Series
 Do not route signal traces under power supply, RF signal traces and other sensitive signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
 Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 3pF.
 Keep the ESD protection components as close to the USB connector as possible.
NOTES
1. USB_MODE must be pulled down so as to realize USB download function.
2. When the USB interface is used for log capturing, the module will not be able to enter PSM.
3. When using USB function of the module, an external 3.3V power supply should be provided.
3.9. UART Interfaces
The module provides three UART ports: main UART port, debug UART port and auxiliary UART port. The
module is designed as DCE (Data Communication Equipment), following the traditional DCE-DTE (Data
Terminal Equipment) connection.
Table 10: Pin Definition of UART Interfaces
Interface Pin Name Pin No. Description Comment
TXD 17 Transmit data to RXD of DTE

Main UART Port
RXD 18 Receive data from TXD of DTE
RXD_DBG 38 Receive data from TXD of DTE

Debug UART Port
TXD_DBG 39 Transmit data to RXD of DTE
RXD_AUX 28 Receive data from TXD of DTE

1.8V power
TXD_AUX 29 Transmit data to RXD of DTE domain
Clear to send (connect to CTS of

Auxiliary UART Port CTS_AUX* 22
DTE)
Request send data (connect to RTS
RTS_AUX* 23
of DTE)
DCD* 21 Data carrier detection
Ringing Signal RI 20 Ring indication signal
LPWA Module Series
NOTE
3.9.1. Main UART Port
The main UART port supports AT command communication, data transmission and firmware upgrade.
 By default, the module is in auto-baud mode and it supports automatic baud rates not exceeding
115200bps. When powering on the module, the MCU has to send AT command consecutively to
synchronize baud rate with the module. When OK is returned, it indicates the baud rate has been
synchronized successfully. When the module is woken up from PSM or idle mode, the baud rate
synchronized during start-up will be used directly.
 When the port is used for firmware upgrade, the baud rate is 921600bps by default.
The figure below shows the connection between DCE and DTE.
Module (DCE) DTE

Main port Serial port
TXD TXD
RXD RXD
GND GND
Figure 16: Reference Design of Main UART Port
3.9.2. Debug UART Port
Through debug tools, the debug UART port can be used to output logs for firmware debugging. Its baud
rate is 115200bps by default. The following is a reference design of debug UART port.
LPWA Module Series
Module DTE
TXD_DBG TXD
RXD_DBG RXD
GND GND
Figure 17: Reference Design of Debug UART Port
3.9.3. Auxiliary UART Port
The auxiliary UART port is designed as a general purpose UART for communication with DTE. It also
supports log output for firmware debugging, and hardware flow control*. Its baud rate is 115200bps by
default. The following is a reference design of auxiliary UART port.
Module DTE
TXD_AUX TXD
RXD_AUX RXD
CTS_AUX GPIO1
RTS_AUX GPIO2
DCD GPIO3
GND GND
Figure 18: Reference Design of Auxiliary UART Port
3.9.4. UART Application
The module provides 1.8V UART interfaces. A level translator should be used if the application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
(please visit http://www.ti.com for more information) is recommended. The following figure shows a
reference design.
LPWA Module Series
Module DTE
VDD_EXT VCCA VCCB VDD
0.1uF
0.1uF
OE GND
RXD A1 B1 TXD
TXD A2 B2 RXD
RXD_DBG A3 Translator B3 TXD_DBG
TXD_DBG A4 B4 RXD_DBG
RXD_AUX A5 B5 TXD_AUX
TXD_AUX A6 B6 RXD_AUX
RI A7 B7 GPIO
51K 51K
GND A8 B8 GND
Figure 19: Reference Circuit with Voltage Level Translator Chip
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.
4.7K
VDD_EXT VDD_EXT
1nF
Module DTE
10K
RXD TXD
TXD RXD
1nF
10K
VDD_EXT
4.7K VCC_DTE
RXD_DBG TXD_DBG
TXD_DBG RXD_DBG
RXD_AUX TXD_AUX
TXD_AUX RXD_AUX
RI GPIO
GND GND
Figure 20: Reference Circuit with Transistor Circuit
The following circuit shows a reference design for the communication between the module and a PC with
standard RS-232 interface. Please make sure the I/O voltage of level shifter which connects to module is
1.8V.
LPWA Module Series
C1+ V+ GND
C1- GND GND
C2+ VCC 3.3V

Module
C2- V- GND
T1IN T2OUT
TXD T2IN T1OUT
T3IN T5OUT
To PC Main Serial Port
RI T4IN T3OUT
Level Shifter
T5IN T4OUT
(1.8V~3.3V)
6 1
/R1OUT
2
RXD R1OUT R1IN
7
3
R2OUT R2IN
8
4
R3OUT R3IN
9
5
GND
RS-232
GND
Transceiver
Figure 21: Sketch Map for RS-232 Interface Match
Please visit vendors’ websites to select a suitable RS-232 transceiver, such as: http://www.exar.com and
http://www.maximintegrated.com.
NOTES
1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
2. In the above voltage level translation reference circuits, the circuit design for DCD and CTS_AUX is
similar to that of TXD_AUX, and the design for RTS_AUX is similar to that of RXD_AUX.
3. “ ” represents the test point of UART interfaces. It is recommended to reserve the test points of
VBAT and PWRKEY, for convenient firmware upgrade and debugging when necessary.
3.10. SPI Interface
BC66-OpenCPU provides one SPI master interface. The following table shows the pin definition of SPI
interface.
LPWA Module Series
Table 11: Pin Definition of SPI Interface
Pin Name Pin No. I/O Description Comment
SPI_MISO 3 DI Master input slave output of SPI interface
SPI_MOSI 4 DO Master output slave input of SPI interface

1.8V power domain
SPI_SCLK 5 DO Clock signal of SPI interface
SPI_CS 6 DO Chip selection of SPI interface
The module provides a 1.8V SPI interface. A level translator between the module and host should be
used if the application is equipped with a 3.3V processor or device interface. A voltage level translator that
supports SPI data rate is recommended. The following figure shows a reference design.
Module DTE
VDD_EXT VCCA VCCB VDD
0.1uF
0.1uF
OE GND
SPI_CS A1 B1 CS_SPI
Translator
SPI_SCLK A2 B2 SCLK_SPI
SPI_MISO A3 B3 MISO_SPI
SPI_MOSI A4 B4 MOSI_SPI
Figure 22: Reference Design of SPI Interface with a Translator Chip
3.11. USIM Interface
The module provides a USIM interface compliant to ISO/IEC 7816-3, enabling the module to access to
external USIM cards.
The external USIM card is powered by an internal regulator in the module and supports 1.8V power
supply.
LPWA Module Series
Table 12: Pin Definition of USIM Interface
Pin Name Pin No. Description Comment
Voltage accuracy: 1.8V±5%.

SIM_VDD 14 Power supply for USIM card
Maximum supply current: about 60mA.
SIM_CLK 13 Clock signal of USIM card
SIM_DATA 11 Data signal of USIM card
SIM_RST 12 Reset signal of USIM card
SIM_GND 10 Specified ground for USIM card
A reference design for USIM interface with a 6-pin USIM card connector is illustrated below.
SIM_GND 100nF USIM Card Connector

SIM_VDD
VCC GND
SIM_RST 22R
RST VPP
Module SIM_CLK 22R
CLK IO
10K
SIM_DATA 22R
33pF33pF 33pF 33pF
TVS
GND GND
Figure 23: Reference Design of USIM Interface with a 6-pin USIM Card Connector
For more information of USIM card connector, please visit http://www.amphenol.com or

http://www.molex.com.
In order to enhance the reliability and availability of USIM card in application, please follow the criteria
below in USIM circuit design:
 Keep the placement of USIM card connector as close as possible to the module. Keep the trace
length as less than 200mm as possible.
 Keep USIM card signals away from RF and VBAT traces.
 Assure the trace between the ground of module and that of USIM card connector is short and wide.
Keep the trace width of ground no less than 0.5mm to maintain the same electric potential. The
decouple capacitor between SIM_VDD and GND should be not more than 1μF and be placed close
to the USIM card connector.
 To avoid cross talk between SIM_DATA and SIM_CLK, keep them away from each other and shield
them separately with surrounded ground.
 In order to offer good ESD protection, it is recommended to add a TVS diode array. For more
LPWA Module Series
information of TVS diode, please visit http://www.onsemi.com. The ESD protection device should be
placed as close to USIM card connector as possible, and make sure the USIM card signal lines go
through the ESD protection device first and then to the module. The 22Ω resistors should be
connected in series between the module and the USIM card connector so as to suppress EMI
spurious transmission and enhance ESD protection. Please note that the USIM peripheral circuit
should be close to the USIM card connector.
 Place the RF bypass capacitors (33pF) close to the USIM card connector on all signal traces to
improve EMI suppression.
3.12. ADC Interface
The module provides a 10-bit ADC input channel to read the voltage value. The interface is available in
active mode only and must be woken up first in sleep modes.
Table 13: Pin Definition of ADC Interface
Pin Name Pin No. Description Sample Range
ADC0 9 Analog to digital converter interface 0V ~ 1.4V
LPWA Module Series
4 Antenna Interface
The pin 35 is the RF antenna pad. The antenna port has an impedance of 50Ω.
4.1. Pin Definition
Table 14: Pin Definition of NB-IoT Antenna Interface
Pin Name Pin No. Description
RF_ANT 35 NB-IoT antenna interface
GND 34, 36, 37 Ground
4.2. Operating Frequencies
Table 15: Module Operating Frequencies
Frequency Band Receiving Frequency Transmitting Frequency
B1 2110MHz~2170MHz 1920MHz~1980MHz
B2 1930MHz~1990MHz 1850MHz~1910MHz
B3 1805MHz~1880MHz 1710MHz~1785MHz
B4 2110MHz~2155MHz 1710MHz~1755MHz
B5 869MHz~894MHz 824MHz~849MHz
B8 925MHz~960MHz 880MHz~915 MHz
LPWA Module Series
B25 1930MHz~1995MHz 1850MHz~1915MHz
B26* 859MHz~894MHz 814MHz~849MHz
B66 2110MHz~2200MHz 1710MHz~1780MHz
NOTE
4.3. RF Antenna Reference Design
BC66-OpenCPU provides an RF antenna pad for external NB-IoT antenna connection.
 The RF trace on host PCB connected to the module’s RF antenna pad should be coplanar
waveguide or microstrip, whose characteristic impedance should be close to 50Ω.
 BC66-OpenCPU comes with ground pads which are next to the antenna pad in order to give a better
grounding.
 In order to achieve better RF performance, it is recommended to reserve a π type matching circuit
and place the π-type matching components (R1/C1/C2) as close to the antenna as possible. By
default, the capacitors (C1/C2) are not mounted and a 0Ω resistor is mounted on R1.
LPWA Module Series
A reference design of the RF interface is shown as below.
GND R1 0R
RF_ANT
GND
C1 C2
Module NM NM
Figure 24: Reference Design of NB-IoT Antenna Interface
4.4. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the distance between signal layer and reference ground (H), and the clearance between RF trace and
ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic
impedance control. The following are reference designs of microstrip line or coplanar waveguide line with
different PCB structures.
Figure 25: Microstrip Line Design on a 2-layer PCB
LPWA Module Series
Figure 26: Coplanar Waveguide Line Design on a 2-layer PCB
Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 28: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
LPWA Module Series
 Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω.
 The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
 The distance between the RF pins and the RF connector should be as short as possible, and all the
right angle traces should be changed to curved ones.
 There should be clearance area under the signal pin of the antenna connector or solder joint.
 The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).
For more details, please refer to document [2].
4.5. Antenna Requirements
To minimize the loss on RF trace and RF cable, please pay attention to the antenna design. The following
tables show the requirements on NB-IoT antenna.
Table 16: Antenna Cable Insertion Loss Requirements
Band Requirements
LTE B5/B8/B12/B13/B17/B18/B19/B20/B26*/B28 Cable Insertion loss <1dB
LTE B1/B2/B3/B4/B25/B66 Cable Insertion loss <1.5dB
NOTE
Table 17: Required Antenna Parameters
Parameters Requirements
Frequency Range 699MHz~2200MHz
VSWR ≤2
Efficiency > 30%
Max Input Power (W) 50
Input Impedance (Ω) 50
LPWA Module Series
4.6. RF Output Power
Table 18: RF Output Power
Frequency Band Max. Min.
B1 23dBm±2dB <-39dBm
B26* TBD TBD
NOTES
1. The design conforms to the NB-IoT radio protocols in 3GPP Rel.13 and 3GPP Rel.14.
LPWA Module Series
4.7. RF Receiving Sensitivity
Table 19: RF Receiving Sensitivity (with RF Retransmissions)
Frequency Band Receiving Sensitivity
B1 -129dBm
B2 -129dBm
B3 -129dBm
B4 -129dBm
B5 -129dBm
B8 -129dBm
B12 -129dBm
B13 -129dBm
B17 -129dBm
B18 -129dBm
B19 -129dBm
B20 -129dBm
B25 -129dBm
B26* TBD
B28 -129dBm
B66 -129dBm
NOTE
LPWA Module Series
4.8. Recommended RF Connector for Antenna Installation
If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector
provided by HIROSE.
Figure 29: Dimensions of the U.FL-R-SMT Connector (Unit: mm)
U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.
Figure 30: Mechanicals of U.FL-LP Connectors
LPWA Module Series
The following figure describes the space factor of mated connector.
Figure 28: Space Factor of Mated Connector (Unit: mm)
For more details, please visit http://www.hirose.com.
LPWA Module Series
5 Electrical and Reliability

Characteristics
5.1. Operation and Storage Temperatures
The following table lists the operation and storage temperatures of the module.
Table 20: Operation and Storage Temperatures
Parameter Min. Typ. Max. Unit
Operation Temperature Range 1) -35 +25 +75 ºC
Extended Temperature Range 2) -40 +85 ºC
Storage Temperature Range -40 +90 ºC
NOTES
1) Within
1. operation temperature range, the module is 3GPP compliant.
2) Within
2. extended temperature range, the module remains the ability to establish and maintain an
SMS*, data transmission, etc. There is no unrecoverable malfunction. There are also no effects on
radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in
their value and exceed the specified tolerances. When the temperature returns to normal operation
temperature levels, the module will meet 3GPP specifications again.
5.2. Current Consumption
The table below lists the current consumption of BC66-OpenCPU under different states.
LPWA Module Series
Table 21: Module Current Consumption (3.3V VBAT Power Supply)
Parameter Mode Description Min. Ave. Max. 2) Unit
PSM Deep Sleep 3.5 μA
eDRX=81.92s, PTW=40.96s 288 µA
Idle @DRX=1.28s 541 μA
@DRX=2.56s 434 μA
B1 @23dBm 100 285 mA
B2 @23dBm 103 294 mA
B3 @23dBm 107 308 mA
B4 @23dBm 107 307 mA
B5 @23dBm 107 303 mA
B8 @23dBm 113 325 mA
B12 @23dBm 134 393 mA
IVBAT Single-tone B13 @23dBm 111 319 mA

(15kHz subcarrier
spacing) B17 @23dBm 133 392 mA
Active 1) B18 @23dBm 110 316 mA
B19 @23dBm 109 311 mA
B20 @23dBm 109 301 mA
B25 @23dBm 103 293 mA
B26* @23dBm TBD TBD mA
B28 @23dBm 128 375 mA
B66 @23dBm 109 312 mA
B1 @23dBm 193 302 mA

Single-tone
(3.75kHz subcarrier B2 @23dBm 187 296 mA
spacing)
B3 @23dBm 215 335 mA
LPWA Module Series
Parameter Mode Description Min. Ave. Max. 2) Unit
B4 @23dBm 237 311 mA
B5 @23dBm 215 330 mA
B8 @23dBm 224 344 mA
B12 @23dBm 250 395 mA
B13 @23dBm 203 316 mA
B17 @23dBm 258 409 mA
B18 @23dBm 198 313 mA
B19 @23dBm 198 314 mA
B20 @23dBm 215 329 mA
B25 @23dBm 187 297 mA
B26* @23dBm 200 313 mA
B28 @23dBm 250 398 mA
B66 @23dBm 200 316 mA
NOTES
1) Power
1. consumption under instrument test condition.
2. 2)
The “maximum value” in “Connected” mode refers to the maximum pulse current during RF
emission.
5.3. Electrostatic Discharge
The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject
to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and
packaging procedures must be applied throughout the processing, handling and operation of any
application that incorporates the module.
The following table shows the module’s electrostatic discharge characteristics.
LPWA Module Series
Table 22: Electrostatic Discharge Characteristics (25ºC, 45% Relative Humidity)
Test Contact Discharge Air Discharge Unit
VBAT, GND ±5 ±10 kV
Antenna interface ±5 ±10 kV
Other interfaces ±0.5 ±1 kV
LPWA Module Series
6 Mechanical Dimensions
This chapter describes the mechanical dimensions of the module. All dimensions are measured in
millimetre (mm), and the tolerances for dimensions without tolerance values are ±0.05mm.
6.1. Mechanical Dimensions of the Module
Figure 31: BC66-OpenCPU Top and Side Dimensions (Unit: mm)
LPWA Module Series
Figure 30: Module Bottom Dimension (Bottom View)
LPWA Module Series
6.2. Recommended Footprint
Figure 31: Recommended Footprint (Unit: mm)
NOTE
The module should be kept about 3mm away from other components on the host PCB.
LPWA Module Series
6.3. Top and Bottom Views of the Module
Figure 32: Top View of the Module
Figure 33: Bottom View of the Module
NOTE
These are renderings of BC66-OpenCPU module. For authentic dimension and appearance, please refer
to the module that you receive from Quectel.
LPWA Module Series
7 Storage, Manufacturing and

Packaging
7.1. Storage
BC66-OpenCPU module is stored in a vacuum-sealed bag. It is rated at MSL 3, and storage restrictions
are shown as below.
1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH.
2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other
high temperature processes must be:
 Mounted within 168 hours at the factory environment of ≤30ºC/60%RH.

 Stored at <10%RH.
3. Devices require baking before mounting, if any circumstance below occurs.
 When the ambient temperature is 23ºC±5ºC and the humidity indication card shows the humidity
is >10% before opening the vacuum-sealed bag.
 Device mounting cannot be finished within 168 hours at factory conditions of ≤30ºC/60%.
4. If baking is required, devices may be baked for 8 hours at 120ºC±5ºC.
NOTE
As the plastic package cannot be subjected to high temperature, it should be removed from devices
before high temperature (120ºC) baking. If shorter baking time is desired, please refer to
IPC/JEDECJ-STD-033 for baking procedure.
LPWA Module Series
7.2. Manufacturing and Soldering
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the
thickness of stencil for the module is recommended to be 0.18mm~0.20mm. For more details, please
refer to document [3].
It is suggested that the peak reflow temperature is 238~245ºC, and the absolute maximum reflow
temperature is 245ºC. To avoid damage to the module caused by repeated heating, it is strongly
recommended that the module should be mounted after reflow soldering for the other side of PCB has
been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and
related parameters are shown below.
Temp. (°C)
Reflow Zone
Max slope: Cooling down
2~3°C/sec C slope: 1~4°C/sec
245
238
220
B D
200
Soak Zone
150 A
100
Max slope: 1~3°C/sec
Figure 34: Recommended Reflow Soldering Thermal Profile
Table 23: Recommended Thermal Profile Parameters
Factor Recommendation
Soak Zone
Max slope 1 to 3°C/sec
Soak time (between A and B: 150°C and 200°C) 60 to 120 sec
LPWA Module Series
Reflow Zone
Max slope 2 to 3°C/sec
Reflow time (D: over 220°C) 40 to 60 sec
Max temperature 238°C ~ 245°C
Cooling down slope 1 to 4°C/sec
Reflow Cycle
Max reflow cycle 1
NOTES
1. During manufacturing and soldering, or any other processes that may contact the module directly,
NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol,
isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted.
2. The shielding can for the module is made of Cupro-Nickel base material. It is tested that after 12
hours’ Neutral Salt Spray test, the laser engraved label information on the shielding can is still clearly
identifiable and the QR code is still readable, although white rust may be found.
7.3. Packaging
The modules are stored in a vacuum-sealed bag which is ESD protected. The bag should not be opened
until the devices are ready to be soldered onto the application.
7.3.1. Tape and Reel Packaging
The reel is 330mm in diameter and each reel contains 250 modules.
LPWA Module Series
Figure 32: Tape Dimensions (Unit: mm)
Figure 33: Reel Dimensions (Unit: mm)
LPWA Module Series
8 Appendix A References
Table 24: Related Documents
SN Document Name Remark
[1] Quectel_BC66-TE-B_User_Guide BC66-TE-B User Guide
[2] Quectel_RF_Layout_Application_Note RF Layout Application Note
[3] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide
Table 25: Terms and Abbreviations
Abbreviation Description
ADC Analog-to-Digital Converter
CoAP Constrained Application Protocol
DCE Data Communications Equipment (typically module)
DTE Data Terminal Equipment (typically computer, external controller)
DTLS Datagram Transport Layer Security
EMI Electromagnetic Interference
ESD Electrostatic Discharge
FTP File Transfer Protocol
H-FDD Half Frequency Division Duplexing
HTTP Hyper Text Transfer Protocol
HTTPS Hyper Text Transfer Protocol over Secure Socket Layer
I/O Input/Output
kbps Kilo Bits Per Second
LPWA Module Series
LED Light Emitting Diode
Li-MnO2 Lithium-manganese Dioxide
Li-2S Lithium Sulfur
LTE Long Term Evolution
LwM2M Lightweight M2M
MQTT Message Queuing Telemetry Transport
NB-IoT Narrow Band- Internet of Things
PCB Printed Circuit Board
PDU Protocol Data Unit
PPP Point-to-Point Protocol
PSM Power Save Mode
RF Radio Frequency
RTC Real Time Clock
RXD Receive Data
SMS Short Message Service
SSL Secure Sockets Layer
TCP Transmission Control Protocol
TE Terminal Equipment
TXD Transmitting Data
UART Universal Asynchronous Receiver & Transmitter
UDP User Datagram Protocol
URC Unsolicited Result Code
USIM Universal Subscriber Identification Module
VSWR Voltage Standing Wave Ratio
Vmax Maximum Voltage Value
LPWA Module Series
Vnorm Normal Voltage Value
Vmin Minimum Voltage Value
VIHmax Maximum Input High Level Voltage Value
VIHmin Minimum Input High Level Voltage Value
VILmax Maximum Input Low Level Voltage Value
VILmin Minimum Input Low Level Voltage Value
VImax Absolute Maximum Input Voltage Value
VInorm Absolute Normal Input Voltage Value
VImin Absolute Minimum Input Voltage Value
VOHmax Maximum Output High Level Voltage Value
VOHmin Minimum Output High Level Voltage Value
VOLmax Maximum Output Low Level Voltage Value
VOLmin Minimum Output Low Level Voltage Value
LPWA Module Series
9 Appendix B Multiplexed Pins
Table 26: Multiplexed Pins and Their Functions
Pin Default Reset Driving

Pin Name Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
No. Mode State 1) Current
3 SPI_MISO 0 GPIO / SPI_ MISO / / / / EINT I,PD 4mA
4 SPI_MOSI 0 GPIO / SPI_ MOSI / / / / EINT I,PD 4mA
5 SPI_SCLK 0 GPIO / SPI_ SCLK / / / / EINT I,PD 4mA
6 SPI_CS 0 GPIO / SPI_ CS / / / / EINT I,PD 4mA
8 GPIO0 0 GPIO / / / / / / / I,PD 4mA
16 NETLIGHT 0 GPIO / / I2S0_RX PWM / EINT I,PU 4mA
20 RI 0 GPIO / / I2S0_WS I2C_SCL / / EINT I,PD 4mA
21 DCD* 0 GPIO / / I2S0_TX I2C_SDA / / EINT I,PD 4mA
UART1_RT
22 CTS_AUX* 2) 0 GPIO / / / / / EINT I,PD 4mA
S
23 RTS_AUX* 2) 0 GPIO / / UART1_CT / PWM/ / EINT I,PD 4mA
LPWA Module Series
26 GPIO1 0 GPIO I2S0_MCLK / / / / / EINT I,PD 4mA
UART1_RX
28 RXD_AUX 3) 3 GPIO / / / / / / I,PD 4mA
D
UART1_TX
29 TXD_AUX 3) 3 GPIO / / / / / / I,PD 4mA
D
30 GPIO2 0 GPIO I2S0_CK UART2_CTS / / / / EINT I,PD 4mA
31 GPIO3 0 GPIO I2S0_WS UART2_RTS / / PWM EINT I,PD 4mA
32 GPIO4 0 GPIO I2S0_RX / / / / / / I,PD 4mA
33 GPIO5 0 GPIO I2S0_TX / / / / / EINT I,PD 4mA
UART2_RX
38 RXD_DBG 3) 3 GPIO / / / / / / I,PD 4mA
D
UART2_
39 TXD_DBG 3) 5 GPIO / / / / / / I,PD 4mA
TXD
47 USB_MODE 0 GPIO / / / / / / EINT I,PU 4mA
52 GPIO6 0 GPIO / / / / / / / I,PU 4mA
53 GPIO7 0 GPIO / / / / / / / I,PU 4mA
54 GPIO8 0 GPIO / / / / / / / I,PU 4mA
LPWA Module Series
NOTES
1)
1. Indicates the status of each pin after reset. ("I" means "input "; "PD" means "internal pull-down"; and "PU" means "internal pull-up".)
2)
2. Pins 22 and 23 have exchanged the pin function inside the module. Therefore, during external circuit design, please connect pin 22 (CTS_AUX) to CTS
of DTE and pin 23 (RTS_AUX) to RTS of DTE.
3)
3. Pins 28/29/38/39 are configured as UART pins by default. After power-on, they will change from LOW to HIGH level and then maintain high level status.
4. Except the default mode, the pin functions in other modes take effect only after software configuration.
5. "*" means under development.

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BC66-OpenCPU

LPWA Module Series

Quectel Wireless Solutions Co., Ltd.

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About the Document

Revision Date Author Description

About the Document ................................................................................................................................... 2

2 Product Concept .................................................................................................................................. 9

3 Application Interfaces ....................................................................................................................... 13

4 Antenna Interface ............................................................................................................................... 36

4.6. RF Output Power ...................................................................................................................... 41

5 Electrical and Reliability Characteristics ........................................................................................ 45

6 Mechanical Dimensions .................................................................................................................... 49

7 Storage, Manufacturing and Packaging .......................................................................................... 53

TABLE 1: FREQUENCY BANDS OF BC66-OPENCPU MODULE ..................................................................... 9

FIGURE 1: BC66-OPENCPU FUNCTIONAL DIAGRAM .................................................................................. 12

1.1. Safety Information

Wireless devices may cause interference on sensitive medical equipment, so

2.1. General Description

BC66-OpenCPU is a high-performance NB-IoT module with extremely low power consumption. It is

Table 1: Frequency Bands of BC66-OpenCPU Module

“*” means under development.

2.2. Key Features

The following table describes the detailed features of BC66-OpenCPU module.

Table 2: BC66-OpenCPU Key Features

 Supply voltage: 2.1V ~ 3.63V

Power Saving  Typical power consumption: 3.5uA

LTE Cat NB1:

Transmitting Power  23dBm±2dB

USIM Interface  Support 1.8V USIM card

 Conform to USB 1.1 specifications, with maximum data transfer rate up to

Network Protocols  UDP/TCP/LwM2M/MQTT/DTLS/SNTP/CoAP*/PPP*/TLS*/HTTP*/HTTPS*

SMS*  Text/PDU Mode

 Single-tone: 25.5kbps (DL)/16.7kbps (UL)

Real Time Clock  Supported

Physical  Size: (17.7±0.15)mm × (15.8±0.15)mm × (2.0±0.2)mm

Antenna Interface  50Ω impedance control

1. 1) Withinoperation temperature range, the module is 3GPP compliant.

2.3. Functional Diagram

VBAT Boost ASM RF_ANT

PSM_ENIT PWRKEY RESET NETLIGHT ADC USIM

Figure 1: BC66-OpenCPU Functional Diagram

“*” means under development.

2.4. Development Board

3.1. General Description

3.2. Pin Assignment

POWER GND UART USIM ANT

USB RESERVED SPI GPIO OTHERS

Figure 2: Pin Assignment

1. Keep all reserved pins unconnected.

3.3. Pin Description

Table 3: I/O Parameters Definition

Table 4: Pin Description

Pin Name Pin No. I/O Description DC Characteristics Comment

Power supply for Vmax=3.63V

GND 1, 27, 34, GND

36, 37, 40,

Power Key Interface

Network Protocols  UDP/TCP/LwM2M/MQTT/DTLS/SNTP/CoAP/PPP/TLS/HTTP/HTTPS*