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    Unit2 CA

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    IT HOD Nandha College of Technology
    The document discusses computer arithmetic including addition, subtraction, multiplication, and division algorithms using sign-magnitude, 2's complement, floating point, and decimal representations. It also covers the hardware implementation of these arithmetic operations using logic gates, registers, and adders. Examples are provided to illustrate the binary, hexadecimal, and decimal arithmetic algorithms.

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    Unit2 CA

    Uploaded by

    IT HOD Nandha College of Technology
    25 views34 pages
    The document discusses computer arithmetic including addition, subtraction, multiplication, and division algorithms using sign-magnitude, 2's complement, floating point, and decimal representations. It also covers the hardware implementation of these arithmetic operations using logic gates, registers, and adders. Examples are provided to illustrate the binary, hexadecimal, and decimal arithmetic algorithms.

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    Computer Architecture

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    unit2 CA

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    The document discusses computer arithmetic including addition, subtraction, multiplication, and division algorithms using sign-magnitude, 2's complement, floating point, and decimal representations. It also covers the hardware implementation of these arithmetic operations using logic gates, registers, and adders. Examples are provided to illustrate the binary, hexadecimal, and decimal arithmetic algorithms.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    25 views34 pages

    Unit2 CA

    Uploaded by

    IT HOD Nandha College of Technology
    The document discusses computer arithmetic including addition, subtraction, multiplication, and division algorithms using sign-magnitude, 2's complement, floating point, and decimal representations. It also covers the hardware implementation of these arithmetic operations using logic gates, registers, and adders. Examples are provided to illustrate the binary, hexadecimal, and decimal arithmetic algorithms.

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    © All Rights Reserved
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    of 34

    Chapter 10:

    Computer Arithmetic
    Sign-magnitude

    Addition and Subtraction


    2’s complement
    Hardware implementation: Sign flip flop

    Overflow FF

    XOR gates
    Algorithm:

    Like as: A= -2 , B=5


    2’s complement addition and subtraction:
    Multiplication algorithms:
    A binary example:

    Partial product
    Hardware implementation
    #of bit in multiplier

    multiplier

    Partial product
    Algorithm:

    B=11011 Q=00111
    4 Q4=1,A=0,Qs=1
    EA=A+B=1011
    EAQ= 0 1011 0111
    Shr EAQ= 0 0101 1011
    3 Q3=1
    EA = 1 0000
    EAQ 1 0000 1011
    Shr EAQ 0 1000 0101
    2 Q2=1
    EA= 1 0011
    EAQ 1 0011 01 01
    shr EAQ 0 1001 101 0
    1 Q1=0
    Shr EAQ 0 0100 1101=77
    0
    Booth multiplication algorithm

    A= 00011 B= 00111 => A*B= A*(7)=A* (8-1)=A*8-A*1

    In 2’s compl. representation, we can use Booth alg. without change.


    Hardware
    Algorithm
    An example:
    Array multiplier: Fast approach
    Division algorithms:
    A/B = q , r ; A: Dividend , B: Divisor, q: quotient, r: remainder
    Restoring method:
    Algorithm:

    If A-B>= 0 then DVF1


    Other methods:
    • Comparison
    • Non-restoring: in the restoring method when
    A<B  2(A-B+B)-B=2A-B,
    A<B  2(A-B)+B=2A-B
    Floating point operations
    • The standard format:
    IEEE 754 single precision

    • F=0 : E=0 & f=0


    •F=denormalized : E=0 & f≠0
    •F= ±∞ : E=255 & f=0
    •F=NAN: E=255 & f ≠0
    Hardware:
    Addition and subtraction
    Multiplication:
    Division:
    Decimal Arithmetic Unit
    BCD Adder
    Hardware:
    BCD subtractor:
    A-B = A+ 9’s compl. of B
    B’+ 1010= 15-B+1010=9-B+16
    9’ compl.(B) = (B+ 0110)’ = 15 – B- 0110 =9-B
    logic circuit
    An example: -(0111) =
    1000+1010=(0111+0110)’=0010
    Decimal arithmetic operation
    Decimal arithmetic operation

    dshr (7680)  0768


    Addition and Subtraction
    Parallel adder:
    Digit serial bit parallel:
    All serial:
    Multiplication:
    Ai *Bi = [0,81]!
    4bit

    9’s compl. Of B
    Adder

    Overflow detection
    Algorithm:

    K: # 0f digits

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