IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO.

4, NOVEMBER 2013 2165

Hardware/Software Codesign Guidelines for

System on Chip FPGA-Based Sensorless
AC Drive Applications
Imen Bahri, Member, IEEE, Lahoucine Idkhajine, Member, IEEE, Eric Monmasson, Senior Member, IEEE, and
Mohamed El Amine Benkhelifa

Abstract—This paper aims to provide Hardware/Software Three-phase stator voltages.

(Hw/Sw) codesign guidelines for system-on-chip field-pro-
grammable gate array-based sensorless ac drive applications. d-q stator voltages.
Among these guidelines, an efficient Hw/Sw partitioning proce- Switching signals for the VSI.
dure is presented. This Hw/Sw partitioning is performed taking
into account both the control requirements (bandwidth and d-q stator inductances.
stability margin) and the architectural constraints (e.g., avail-
able area, memory, and hardware multipliers). A nondominated Msr Mutual inductance.
sorting genetic algorithm (NSGA-II) is used to solve the corre- Rs Stator resistance.
sponding multi-objective optimization problem. The proposed
Hw/Sw partitioning approach is then validated on a sensorless Electrical position and speed.
control algorithm for a synchronous motor based on an extended x, u, y State space vector, system input, and output
Kalman filter. Among the nondominated implementation solu-
tions supplied by the NSGA-II, those that are considered as the vectors.
most interesting are synthesized. Their time/area performances f(x,u), H State space matrix and system output matrix.
after synthesis are compared with success to their predictions.
In addition, one of these optimal solutions is also tested on an w, v State and output noise vectors.
experimental setup. k/k-1, k/k Predicted and estimated quantities.
Index Terms—Codesign guidelines, extended Kalman filter
K, Fd Kalman gain and Jacobian matrices.
(EKF), field-programmable gate array (FPGA), hardware/soft-
ware (Hw/Sw) partitioning, nondominated sorting genetic algo- State error and initial covariance matrices.
rithm (NSGA-II), soft-core processor, system-on-chip (SoC).
Q, R Model noise and measurement noise
covariance matrices.
NOMENCLATURE

s, r Stator and rotor index. I. INTRODUCTION

d,q Synchronous reference frame index.

a, b, c
Reference quantity, estimated quantity.
Three-phase reference frame index.
N OWADAYS, embedded control systems are becoming
more and more sophisticated. This is a direct conse-
quence of the rising of industrial requirements [1], [2]. These
requirements are not just always limited to a higher level of
Stator and rotor currents.
performance. Indeed, the flexibility of the controller, its cost,
d-q stator currents. and its time-to-market reduction are also of prime importance.
DC link voltage. To cope with all of these different challenges, a relevant use of
the current digital technologies becomes crucial.
Among all of these digital technologies, field-programmable
gate arrays (FPGAs) present the advantage to include both
Manuscript received July 20, 2012; revised November 17, 2012; accepted
December 21, 2012. Date of publication February 08, 2013; date of current ver- hardware and software resources. Hardware resources are
sion October 14, 2013. Paper no. TII-12-0489. usually used to accelerate the processing time by exploiting the
I. Bahri is with the Laboratoire de Génie électrique de Paris (LGEP), Univer-
inherent parallelism of the control algorithm to be implemented.
sity of Paris-Sud XI, 91400 Orsay, France (e-mail: [email protected]).
L. Idkhajine and E. Monmasson are with the Systèmes et Applications des This FPGA-based implementation has already been the focus
Technologies de l’Information et de l’Energie (SATIE), University of Cergy- of many researches in the field of ac drive applications [3]–[5].
Pontoise, 95031 Cergy-Pontoise, France (e-mail: [email protected];
More recently, it has also become typical to implement pro-
[email protected]).
M. El Amine Benkhelifa is with the Equipes Traitement de l’Information et cessor cores within FPGAs. Thus, FPGAs can now be consid-
Systèmes (ETIS), University of Cergy-Pontoise, 95031 Cergy-Pontoise, France ered as full system-on-chip (SoC) solutions, always allowing
(e-mail: [email protected]).
more flexibility for the embedded controllers. These SoC-based
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. solutions include varied components like one or several proces-
Digital Object Identifier 10.1109/TII.2013.2245908 sors, memories, hardware multiplier blocks, analog–digital con-

1551-3203 © 2013 IEEE

2166 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

verters, matrix of programmable logic elements (FPGA Fabric), and its validation. Then, Section V presents the architectural
and busses, all in the same chip. To this purpose, FPGA manu- exploration, where software, hardware, and mixed Hw/Sw
facturers provide more open and efficient platforms introducing SoC implementations are discussed. Section VI presents the
several RISC processor cores. The hard-core processors such as experimental results. Finally, conclusions and perspectives are
Xilinx’s PowerPC 440, Microsemi’s Cortex-M3, and Xilinx’s given in Section VII.
dual ARM Cortex-A9 cores have a custom very large-scale in-
tegration (VLSI) layout that is integrated within the FPGA. As II. HW/SW CODESIGN GUIDELINES PRESENTATION
a general rule, these hard-core processors offer higher clock The proposed Hw/Sw codesign guidelines aims to find an op-
speeds with less flexibility. The soft-core processors such as Al- timal partitioning of control algorithm between modules to be
tera’s Nios-II, Xilinx’s MicroBlaze processors, and Microsemi’s implemented in software and those to be implemented in hard-
Cortex-M1 use existing FPGA logic cells to implement the pro- ware. This method defines a set of steps and rules to be fol-
cessor cores [6]–[9]. The advantage of such approach is the flex- lowed in order to make the design process more manageable and
ibility but this implies slower clock rates. Additionally, hetero- less intuitive. It consists of a top-down design process that starts
geneous multiprocessing architectures (MPSoCs) offer better from the specifications of the control application to the final ex-
performance especially in the case of complex digital applica- perimental validation. As shown in Fig. 1, this method is de-
tions. Indeed, MPSoC architectures provide a high level of scal- composed into four main steps: 1) specifications of the control
ability compared with monolithic cores, in particular in terms of application; 2) algorithm development; 3) architectural explo-
power and performance [10]. ration; and 4) Hw/Sw integration and experimental validation.
To take full advantages of these SoC approaches and to ac- The proposed approach allows an automatic architectural ex-
commodate the ever more demanding control applications, the ploration that integrates both the control (stability margin/band-
use of hardware/software (Hw/Sw) codesign methodology is width) and the resource (time/area) constraints. This automatic
crucial. Along this line, a major issue to be addressed is to ob- architectural exploration allows obtaining an optimal Hw/Sw
tain an efficient partitioning of the control algorithm between partitioning of the functional modules with the help of an ef-
software and hardware resources. During a decade, the Hw/Sw ficient evolutionary algorithm (NSGA-II). Thus, this automatic
partitioning has been addressed by several methods using auto- architectural exploration avoids the manual portioning that is
mated heuristic approaches. These approaches are based on op- one of the SoC design bottlenecks. In the four following sec-
timization algorithms, such as simulated annealing algorithm, tions, each step of the proposed design guidelines is explained
Tabu search algorithm and Genetic Algorithm (GA) [11]–[14]. optimal Hw/Sw partitioning of the functional modules with the
These works focused on optimizing the processing time, the area help of an efficient evolutionary algorithm (NSGA-II). Thus,
and the power consumption. this automatic architectural exploration avoids the manual por-
The majority of these works have been proposed for signal tioning that is one of the major SoC design bottlenecks.
and image processing applications but to our best knowledge, no
optimized Hw/Sw partitioning strategy has been yet proposed III. SPECIFICATIONS OF THE CONTROL APPLICATION
for ac drives applications. Indeed, up to now, the partitioning be- The structure of the developed sensorless control system is
tween Hw/Sw resources for FPGA-based controllers dedicated first overviewed and depicted in Fig. 2. Its hardware and algo-
to power electronics and drives applications was made only on rithm specifications are discussed below.
the expertise of the designer [15]–[18], guided by engineering
experience like implementing PWM and current control in hard- A. Hardware Specifications
ware and position control in software. The power stage consists of a salient pole synchronous
In this paper, we propose Hw/Sw codesign guidelines for motor (SM) mechanically (see Table I) loaded by a powder
SoC FPGA-based sensorless ac drive applications. The main brake and electrically fed by a Voltage Source Inverter (VSI).
contribution of this work is to propose a systematic architec- It consists in a SEMIKRON VSI module (IGBT modules,
tural exploration of the controller. Optimal architectural solu- 800 V, 30 A). The used electrical
tions are obtained via a nondominated sorting genetic algorithm sensors provide measurements of stator currents and dc link
(NSGA-II). The proposed Hw/Sw partitioning procedure takes voltage. The analog-to-digital converter (ADC) board is com-
into account heterogeneous constraints such as the control re- posed of four AD9221 12-b ADCs. In this study, the digital
quirements (bandwidth and stability margin) and the Hw re- control unit is based on a Xilinx Virtex-5 FPGA (XC5VSX50T).
sources (available logic cells, memories, and hardware multi- It consists of 32640 lookup tables (LUTs) of six-input, 32640
pliers). It was tested on a sensorless speed controller of a syn- flip-flops, 288 DSP48E (hardware multiplier and accumulator
chronous machine using an extended Kalman filter (EKF). In- units), 4752-Kb blocks RAM. A transmission interface is
deed, this type of control strategy is representative in terms scheduled so as to ensure a real-time data transfer between the
of complexity of what can be found in current ac drives. The controller and the Host-PC.
FPGA-based SoC platform used in this project consists of a
Xilinx Virtex-5 embedding a Microblaze soft-core processor. B. Algorithm Specifications
The remainder of this paper is organized as follows. The developed sensorless speed controller is composed of the
Section II presents the proposed Hw/Sw codesign guidelines. following subparts:
The specifications of the control application are detailed in • speed controller based on Proportional-Proportional Inte-
Section III. Section IV synthesizes the algorithm development gral (P-PI) speed regulator.
BAHRI et al.: HARDWARE/SOFTWARE CODESIGN GUIDELINES FOR SYSTEM ON CHIP FPGA-BASED SENSORLESS AC DRIVE APPLICATIONS 2167

Fig. 1. Hw/Sw codesign guidelines flow

• voltage interface that aims to generate the three-phase

stator voltages from the duty cycles and the dc link voltage
measurement.
• EKF module which estimates the rotor position and speed.
The equations of this module are recalled in Table II.

IV. ALGORITHM DEVELOPMENT

During the algorithm development process, the designer
makes the functional validation and prepares the algorithm for
digital implementation. The different steps of this process are
presented in the following subsections.

A. Algorithm Modular Prepartitioning

The algorithm modular prepartitioning aims to decompose
the design into functional modules with different levels of gran-
Fig. 2. Overview of the developed control application. ularity. It consists of independent and reusable modules. As
shown in Fig. 3, the control algorithm can be divided into four
levels of granularity. The first level corresponds to the scalar
TABLE I
SYNCHRONOUS MACHINE PARAMETERS
arithmetic operators such as multiplier, adder, and subtractor,
for example. The second level is related to the matrix operators
needed especially by the EKF treatment. The third level consists
of the functional modules used by the current and the speed con-
trollers and the EKF estimator. To provide more manageable
matrix treatment, the Kalman gain module (see Table II) was
split into four submodules as can be seen in Fig. 4. Finally, the
highest level corresponds to the whole sensorless controller. All
of the Hw modules of this library are written in VHDL.
• stator current controller based on Anti-windup PI regula-
tors, reference frame transformations and a space vector B. Continuous-Time Functional Validation
modulation (SVM) module. The control algorithm has to This step aims to design the complete control system and
be synchronized with the PWM carrier avoiding the acqui- to verify its functionality in continuous-time domain, using
sition of ripples in the current data acquisitions. MATLAB/Simulink tools. The design objectives are a high
2168 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

TABLE II
MAIN EQUATIONS OF THE EKF MODULE

Fig. 4. Partitioning of the Kalman gain module into four submodules.

To design the PI regulators of the current loop, two metrics

were taken into account: the phase margin “ ” and the desired
closed loop bandwidth “ ,” which is more or less equal to the
open-loop crossover frequency .
In practice, the closed-loop bandwidth must be much lower
than the sampling frequency as

(10)

This rule of thumb leads to the maximum bandwidth value

allowing a sufficient disturbance rejection. For the considered
system, this leads to a bandwidth equal to 500 Hz. This value is
used to determine the gain of the PI regulator. On the other hand,
having fixed the desired bandwidth “ ” and the phase margin
“ ” (set to 60 ), the maximum allowable time delay can be
derived from the phase relation of the open loop transfer func-
tion of the controlled system

(11)

The exceeding of this limit decreases the desired phase

margin and in some cases can cause system instability. Consid-
ering the effect caused by the digital PWM, the maximum
execution time devoted to the control algorithm can be
derived from the previous expressions, yielding
Fig. 3. Algorithm modular prepartitioning.

(12)
bandwidth, sufficient stability margin, and a good disturbance
rejection. However, the stability of the controlled loop is af- As said before, the algorithm treatment is synchronized with
fected by the time delay . is the sum of the following two the PWM carrier. Knowing that in this case, the sampling period
terms: and the switching period have been fixed to 100 s, it yields that
• Sample and hold delay resulting from the PWM. is equal to 116.67 s.
This introduces a time delay expressed by
, where is the sampling period. C. Digital Realization of the Controller
• Computing time delay of the digital control which The digital realization is the design step where the discretiza-
depends on the complexity of the algorithm and on the tion, the normalization and the data quantization of the con-
performance of the used digital device. troller are achieved.
BAHRI et al.: HARDWARE/SOFTWARE CODESIGN GUIDELINES FOR SYSTEM ON CHIP FPGA-BASED SENSORLESS AC DRIVE APPLICATIONS 2169

Fig. 5. Validation of the EKF Estimation of (a) speed and (b) position.

TABLE III
BIT NUMBER AND FIXED-POINT FORMATS OF THE CONTROLLER

Fig. 6. Features of the functional module “ ”.

Regarding the discretization, the Forward Euler approxima-

and their corresponding granularity level. Thus, the use of a fine-
tion is selected for the EKF predictor (see Table II). As for the
grained population of modules, typically the arithmetic mod-
controller, the Tustin approximation is used.
ules of the level-1 library (Fig. 3), expands the exploration do-
The fixed-point format of variables and coefficients is set
main but at the cost of a higher complexity of the optimization
based on a trial and test procedure. Several simulations, with dif-
problem formulation. Indeed, the corresponding synchronous
ferent formats, are executed in order to find the smallest format
data flow graph (SDFG) can no longer be executed manually.
which respects the control specifications for all quantities in
In addition, the functional modules of level 3, which are the
terms of dynamic range and accuracy. The used representation
ones used by the control engineer for establishing the control
is labelled as for signed data. is the total
strategy and the control specifications are no longer visible in
data size, is the number of bits of the integer part and is the
this case. This leads to the loss of the physical meaning of the
number of bits of the fractional part. In the case of a Sw imple-
architecture. From the point of view of the authors, this loss is
mentation, the format is imposed by the chosen microcontroller
a real issue since the proposed design guidelines are think as a
(here, 32b). The chosen formats for the controller and the EKF
whole, allowing the control engineer himself to master the to-
modules are summarized in Table III.
tality of the design process. Along this line, using the level-3
D. Discrete-Time and Fixed-Point Validation modules (Fig. 3) is a good compromise since the limited number
of modules is more manageable and their physical meaning is
After having developed the digital controller, the designer has preserved. In this context, the characterization of each func-
to make a final functional verification by simulating the devel- tional module “ ” is of prime importance. Fig. 6 presents the
oped algorithm in the discrete-time and fixed-point domain with related metrics used for characterizing each block, both in hard-
the help of MATLAB/Simulink tools. In this case, the obtained ware and in software, where
simulation results are shown in Fig. 5, where the waveforms of • represents the consumed resources of module , in the
the measured and estimated rotor speed and position are given. case of hardware implementation (6-b LUT & FF).
• represents the used memory blocks used by module ,
V. ARCHITECTURAL EXPLORATION
in the case of software implementation.
In order to efficiently explore different architectures, we pro- • represents the execution time taken by the module
pose the following steps. when executed in Hw.
• represents the execution time taken by the module
A. Characterization and Performance Estimation of when executed in Sw.
Functional Modules • represents the consumed hardware multiplier (DSP
The difficulty of the architectural exploration is mainly linked units) of module , in the case of hardware implementation.
to the search for an optimized Hw/Sw partitioning. This parti- • represents the number of inputs and outputs of
tioning depends strongly on the number of involved modules module .
2170 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

TABLE IV
FEATURES OFCONTROL MODULES

Table IV presents the set of the metrics of each functional sum is taken in the case of a serial implementation (see Fig. 7).
module . All the times are given as number of clock cy- A parallel execution of modules can be assigned to two modules
cles. The exploitation of the concurrency between the func- both implemented in hardware or one in software and the other
tional modules can reduce the execution time. To this purpose, a one in hardware. The case of Sw–Sw modules was not taken
parallelism variable “ ” is introduced. This parameter depends into account since the multiprocessors approach is not studied
on the scheduling and the data dependency between the dif- here.
ferent modules. The variable y is a vector of n-1 components,
. Each of these components is charac- B. SDFG Representation of the Control Algorithm
terized by a binary value {0,1}. The component is equal to 1
(resp. 0) when “ ” can be executed in parallel (resp. in series) In order to prepare the partitioning task, the whole EKF-
with “ .” based sensorless control algorithm was translated into a SDFG.
Thus, in the case of parallel modules, the total execution time As shown in Fig. 8, the proposed SDFG is composed of a set
is the maximum execution time of the two modules. The of nodes and edges. The nodes present the functional modules
BAHRI et al.: HARDWARE/SOFTWARE CODESIGN GUIDELINES FOR SYSTEM ON CHIP FPGA-BASED SENSORLESS AC DRIVE APPLICATIONS 2171

TABLE V
TIME/AREA PERFORMANCES (XILINX VIRTEX-5, XC5VSX50T)

improve the execution time of the design, the concurrency be-

tween some functional modules is exploited providing an im-
provement of the execution time.
Each module is characterized by a number which is reflecting
its natural order within the control process. Also, it has to be
mentioned that the acquisition and the SVM modules ( and
) are directly implemented in hardware. Indeed, the reso-
lution and the functional performances required by these mod-
ules cannot be provided by software. Thus they are not consid-
ered in the Hw/Sw partitioning process. Consequently, the func-
tional modules considered by the Hw/Sw partitioning process
Fig. 7. Parallelism parameter.
are modules to .

C. Hw/Sw Partitioning
Once the characterization of functional modules and the
SDFG representation are performed, the designer can begin the
Hw/Sw partitioning process. They are three possible types of
implementations:
• full software implementation of the controller using the
soft-core processor.
• full hardware implementation of the controller using only
the FPGA fabric.
• mixed Hw/Sw implementation using the soft-core pro-
cessor and the FPGA fabric.
An in-depth study of the full hardware implementation and
of the software implementation has already been proposed [19],
[20]. These architectures were designed based on a dedicated
design methodology beginning from the system specifications
up to the experimentations. Table V summarizes the obtained
time/area performances of the full software and the full hard-
ware implementation of the sensorless control algorithm. One
can note that a full hardware design takes 25.1% of the FPGA
resources and the software design uses 12.4%. This should be
interpreted by the fact that 12.4% is occupied by the soft-core
processor and its peripherals. As for the execution time, the full
hardware controller has an execution time of 13.4 s and the full
software controller has an execution time of 137 s. It should
be noted that 5 s of the execution time of the Sw implementa-
tion is devoted to the format adaptation of data exchanged be-
tween Sw/Hw and Hw/Sw parts and the context switch. This
latter presents the computing time needed to store and restore
the state of the processor.
The obtained results demonstrate that a full hardware imple-
mentation provides a significant reduction of the execution time
Fig. 8. SDFG of the EKF-based sensorless current controller. but it requires the use of much more resources. This is related
to the complexity of the algorithm. A compromise is the parti-
tioning of functional modules between the modules to be exe-
“ ” while the edges denote the data dependencies and the cuted in software and those to be executed in hardware. This al-
number of exchanged data between the different modules. To lows the controller to reach the expected level of performances
2172 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

using only a reasonable fraction of the available internal re-

sources. For the remainder, the interest of Hw/Sw partitioning
to find relevant solutions is demonstrated.
Problem Formalization: The goal of the Hw/Sw partitioning
procedure is to find an optimal architectural implementation
among all of the design alternatives which satisfy the objec-
tives regarding the considered constraints. In this case, these
constraints are expressed in terms of control performance re-
quirements and consumed FPGA resources. Hence, this Hw/Sw
partitioning consists in a multi-objectives optimization problem.
In order to formalize it, and in addition to the variables defined Fig. 9. Chromosome representation.
in Section V-A, let us define the following variables:
• : the group of the functional
modules ( is here equal to 15). formalized as given by (13), shown at the bottom of the page,
• : the binary individuals that represent the where , , and are, respectively, the area, memory size,
solution of the partitioning problem where . and number of hardware multipliers available in the FPGA
(resp. ) means that the th module has to be (Virtex-5, XC5VSX50T). corresponds to the maximum al-
implemented in Hw (resp in Sw). lowable execution time. This time corresponds to the maximum
• : the hardware resources consumed by the Microblaze time delay that satisfies the control performance requirements
soft-core, the associated bus and the peripherals. Note that (bandwidth and stability margin).
the Sw implementation of one module requires the whole NSGA-II Algorithm: To deal with this multi-objectives opti-
use of . mization problem, the NSGA-II has been adopted. Such a ge-
• Area: the total consumed hardware resources. netic algorithm has been successfully used for solving several
• : the total consumed hardware multipliers (DSP optimization problems in the field of VLSI systems such as
units). the placement/routing, digital signal processor (DSP) code op-
• : the total consumed hardware multipliers (DSP timization, the area–time optimization of FPGA design [14].
units) by the processor. In our case, the NSGA-II is used offline for the Hw/Sw par-
• Memory: the total memory use. titioning under multiple objectives and constraints. It aims to
• : the total execution time. find out the corresponding Pareto front. The Pareto front of a
Area, , Memory, and are derived from expres- multi-objective optimization problem corresponds to the set of
sion (13) and Table III. and are given in Table IV the nondominated solutions after completion of the optimiza-
(Sw implementation column). Thus, for given constraints tion algorithm. These Pareto solutions present a tradeoffs (time/
(available area, memory, multiplier blocks, and maximum area): the cost of one solution cannot be improved in one di-
allowable execution time), the optimization problem can be mension without being made worse in another. The NSGA-II is

(13)
BAHRI et al.: HARDWARE/SOFTWARE CODESIGN GUIDELINES FOR SYSTEM ON CHIP FPGA-BASED SENSORLESS AC DRIVE APPLICATIONS 2173

Fig. 10. Pareto-front of nondominated solutions.

characterized by a new ranking function. It classifies the can- TABLE VI

didate solutions considering all of the objectives. One impor- EXAMPLES OF OPTIMIZATION SOLUTIONS
tant feature of the NSGA-II is the elitism which means that the
best solutions within one population are conserved for the next
generation. After that, the population random selection (mu-
tation, crossover) will guarantee the diversity of the popula-
tion. This procedure is iterated until finding the Pareto-optimal
front. Thus, the principle of NSGA-II is to compare each so-
lution with the others in order to see whether it is dominated
or not. Thus, it performs comparisons, where is the
number of populations and is the number of objectives. This
optimization algorithm is based on chromosome’s representa-
tion. As shown in Fig. 9, each chromosome represents a spe-
cific partitioning solution. A chromosome is constituted of
genes, where is the total number of modules to be imple-
mented (here, is equal to 15). Each gene of the chromo-
some is a binary variable that represents the state of the cor-
responding module architecture. That is to say, when the th
gene is equal to 1 (resp. 0), the module is implemented in
Hw (resp. in Sw). From the genetic algorithm perspective, each
chromosome is viewed as an individual of a given generation.
The NSGA-II configuration was done considering the following
parameters values: number of generations , population
, crossover rate , and mutation rate .
Partitioning Results: The Hw/Sw partitioning tests were
performed over the Xilinx FPGA (Virtex-5, XC5VSX50T)
including a Microblaze soft-core. Fig. 10 presents the
Pareto-Front of nondominated implementation solutions. Fig. 11. Scheduling diagram of the solution “ ”.
The time taken to obtain the Pareto front for a population and
a number of generations both equal to 200 is 1 mn, 38 s, and
68 ms. This was obtained with the following PC: Intel core fixed by the control performances. The remaining SoC avail-
(TM) i3 CPU 350 @2.27 GHZ processor, and 4 GB of RAM. able resources will be used to integrate other functions such as
The NSGA-II algorithm provides a space exploration covering monitoring communication process that are not presented here.
a good number of feasible solutions. Thus, the designer can Table VI presents examples of nondominated solutions. In
choose the appropriate allocation and scheduling which best Fig. 11 is shown the scheduling diagram of the solution .
suit his application. Considering an area/time-constrained ex- Among all the nondominated solutions that still satisfy the area
ploration: the maximum allowable consumed resources (linked constraint, is the fastest. has a speedup factor of 2.38.
to the cost) are fixed here to 7500 six-input LUTs and the max- The speedup factor is the ratio between the execution time of a
imum execution time is set to maximum allowable time delay Hw/Sw solution with regard to the execution time of the full
2174 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

TABLE VII
COMPARISON BETWEEN ACTUAL AND PREDICTED HW/SW ARCHITECTURES

Fig. 12. Prototyping platform.

Fig. 13. Experimental results—waveforms of the estimated (red curve) and the
measured rotor position (blue curve).

Fig. 14. synthesized architecture.

Sw-implementation, taken as baseline. It can be also noticed
from Table VI that there are always one or more computation-
ally intensive modules (M6 to M9) executed in Sw. Indeed, gorithm. Along this line, Table VII presents for three nondom-
these modules, which are used in the Kalman gain computation inated solutions ( to ) the comparison between their
(Fig. 4), are consuming an important number of LUTs and hard- estimated performances directly derived from the results of the
ware multipliers when implemented in Hw. Thus, in order to sat- NSGA-II algorithm and their actual performances obtained after
isfy the resource constraint, the NSGA-II algorithm is placing synthesis.
some of these greedy modules in Sw while keeping the global It can be seen from these results a good matching in terms
execution time below . of area since the maximum error is equal to 2.3%. The error is
higher in terms of timing, reaching 5.6% for the solution.
VI. EXPERIMENTAL VALIDATION However, this value is still acceptable knowing that the com-
munication times between modules have not been taken into
Experimental validation of the solution “ ” has been car- account in the prediction. gives better results compared
ried out with the platform presented in Fig. 12. Fig. 13 shows the to and because it is a more homogeneous solution.
good matching of the estimated and the measured angular po- Indeed, as can be seen on the genes of the solutions (Table VI),
sition at 500 rpm. The characteristics of the motor and its load is concentrating all its Sw modules which is not the case
are given in Table VII. of the two other solutions. Thus, the number of Sw-to-Hw and
However, in this work, the most important validation con- Hw-to-Sw communications is reduced which implies a better
cerns the quality of the performance prediction of the nondom- prediction.
inated solutions obtained by the NSGA-II algorithm. Indeed, as Finally, Fig. 14 presents the solution once implemented
shown in (13), the objective functions of the Hw/Sw partitioning on the Virtex-5, the dotted line represents the area constraints
optimization problem are strongly dependent of the functional in terms of LUTs (here 7500 LUTs). The compactness of the
module characteristics (Table III). If these characteristics are in- architecture can be observed.
accurate, then the architectures proposed by the NSGA-II algo-
rithm will be questionable. Conversely, if these characteristics
VII. CONCLUSION
are accurate, then it means that the NSGA-II has worked with
correct data and as a consequence the designer can be confi- Hardware/software codesign guidelines for SoC FPGA-
dent in the architectural solutions proposed by the NSGA-II al- based sensorless ac drive applications were proposed. The most
BAHRI et al.: HARDWARE/SOFTWARE CODESIGN GUIDELINES FOR SYSTEM ON CHIP FPGA-BASED SENSORLESS AC DRIVE APPLICATIONS 2175

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of the communication time within the partitioning problem is Imen Bahri (M’13) was born in Tunisia in 1982.
one of the direct perspectives to this work. Another one is to She received the Ing. and M.S degrees in electrical
engineering from the National School Engineers of
integrate to the Hw/Sw partitioning other functions that are not
Tunis (ENIT), Tunis, Tunisia, in 2006 and 2007,
directly related to the control of the drive like the interface with respectively, and the Ph.D. degree from Cergy-Pon-
the supervisor and the diagnosis module. toise University, Cergy-Pontoise, France, in 2011.
She is currently an Assistant Professor with
Paris-XI University, Orsay, France, and a member
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laga, “Fully integrated FPGA-based controller for synchronous motor sistant Lecturer with Arts et Métiers ParisTech, Lille,
drives,” IEEE Trans. Ind. Electron., vol. 56, no. 10, pp. 4006–4017, France. He is currently an Assistant Professor with
Oct. 2009. Cergy-Pontoise University, Cergy-Pontoise, France,
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pp. 415–329, May 2005. Ing. and Ph.D. degrees from the Ecole Nationale
[9] R. Lysecky and F. Vahid, “A study of the speedups and competitive- Supérieure d’Ingénieurs d’Electrotechnique d’Elec-
ness of FPGA soft processor cores using dynamic hardware/software tronique d’Informatique et d’Hydraulique de
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[10] R. Obermaisser and P. Gutwenger, “Model-based development of and 1993, respectively. \
MPSoCs with support for early validation,” in Proc. IEEE IECON’09 He is currently a Full Professor and the Head of
Conf., 2009, CD-ROM. the Institut Universitaire Professionnalisé de Génie
[11] K. Deb, A. Pratap, S. Argarwal, and T. Meyarivan, “A fast and Electrique et d’Informatique Indutrielle (IUP GEII),
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2176 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 9, NO. 4, NOVEMBER 2013

des Technologies de l’Information et de l’Energie laboratory (SATIE, UMR Mohamed El Amine Benkhelifa received the elec-
CNRS8029). He is the author or coauthor of three books and more than 150 tronics engineer degree from the U.S.T.O., Oran,
scientific papers. His current research interests include the advanced control Algeria, in 1987, and the Ph.D. degree in physics
of electrical motors and generators and the use of FPGAs for energy control from Paris-V University, Paris, France, in 1992.
systems. He is now an Assistant Professor of elec-
Prof. Monmasson was the chair of the technical committee on Electronic Sys- trical engineering and computer science with the
tems-on-Chip of the IEEE Industrial Electronics Society (2008–2011). He is ETIS Laboratory, University of Cergy-Pontoise,
also a member of the steering committee of the European Power Electronics Cergy-Pontoise, France. His research interests
Association and the chair of the number one technical committee of the Interna- include coarse-grained and fine reconfigurable
tional Association for Mathematics and Computers in Simulation (IMACS). He arrays, domain-specific FPGAs, reconfigurable
was the general chair of ELECTRIMACS 2011 Conference. He is an associate computing architectures, and operating systems for
editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and the IEEE reconfigurable architectures.
TRANSACTIONS ON INDUSTRIAL INFORMATICS.