COPYRIGHT © 2019

Sipeed lichee Zero Plus Datasheet

v1.0

Key Features：
◼ CPU: ARM Cortex-A7 processor, 1.2Ghz frequency,
◼ Storage: Built-in 128MB DDR3 memory, optional SPI Flash/SD Nand/TF card/eMMC boot
◼ Multimedia: RGB/LVDS LCD interface, DVP/MIPI camera interface, built-in Codec, I2S/PCM
interface
◼ Communication: 100M Ethernet (built-in phy), USB OTG
◼ Other peripherals: UART, GPIO, SPI, I2C, SDIO, RTC, PWM etc.
◼ Connector interface: M.2 B KEY x 2

Sipeed Technology www.sipeed.com

Sipeed lichee Zero Plus Datasheet v1.0

UPDATE

V1.0 Edited March 16, 2019; original document

SPECIFICATION

ARM Cortex-A7 processor (1.2Ghz), VFPv4 floating point

CPU
processor
four audio inputs and two audio outputs
Audio processing
Support for analog/digital volume control
Support video decoding H.264/JPEG/MJPEG
Support H.264 BP/MP/HP up to 1080p@60fps
Support H.264 output format: NV21, NV12, YU12, YV12
Video encoding/decoding
Support JPEG/MJPEG up to 1080p@30fps
Support H.264 video encoding up to 1080p@60fps,
720p@120fps
Support 8/10/12-bit yuv422 CMOS sensor interface
MIPI/CSI Support parallel interface up to 5M bandwidth
Support MIPI interface to support up to 8M bandwidth
Support RGB/i80/LVDS screen interface
Display
Up to 1024x768@60fps

Onboard information

Built-in 128Mbyte DDR3 memory (clock frequency up to

RAM
672MHz)
Optional SPI Nor Flash (8/16/32MB),
SD Nand (128/512MB),
storage
eMMC (4/8GB)
Micro SD card

power supply 5V power input, 3 DCDC regulated output (1.2, 1.5, 3.3)

Reset Onboard reset chip

Crystal oscillator Onboard 24M main crystal, 32.768KHz RTC crystal

NGFF M.2 B KEY x 2 Totally 67x2=134pin

interface Onboard micro usb interface and system serial port for
downloading firmware and debugging

Sipeed Technology 1
Sipeed lichee Zero Plus Datasheet v1.0

Support for the latest Linux 5.2 mainline kernel, Linux 3.4 bsp
System Support kernel
Support for debian distributions

Working environment

Supply voltage of external power

4.8V ~ 5.2V
supply
Supply current of external power
>500mA
supply

Temperature rise <30K

Range of working temperature -30℃ ~ 85℃

Size Information

Length 45mm

Width 31mm

Height 2.5mm

Sipeed Technology 2
Sipeed lichee Zero Plus Datasheet v1.0

PIN Information

# PIN # PIN # PIN # PIN

1 5V_IN 2 5V_IN 68 PE17/CSI_D13/LCD_D19 69 PE9/CSI_D5/LCD_D7

3 5V_IN 4 5V_IN 70 PE19/CSI_D15/LCD_D21 71 PE4/CSI_D0/LCD_D2

5 GND 6 GND 72 PE18/CSI_D14/LCD_D20 73 PE7/CSI_D3/LCD_D5

PE3/CSI_VSYNC/LCD_VS
7 GND 8 GND 74 75 PE8/CSI_D4/LCD_D6
YNC

9 1V2_OUT 10 3V3_OUT 76 PE0/CSI_PCLK/LCD_CLK 77 PE10/CSI_D6/LCD_D10

PB13/JTAG_DI/PB_EI PE21/CSI_SCK/TWI1_SCK
11 1V5_OUT 12 78 79 PE11/CSI_D7/LCD_D11
NT13 /UART1_TX

PB0/UART2_TX/PB_EI
13 MCSI_D3N 14 80 PE12/CSI_D8/LCD_D12 81 PE23/LCD_D22/UART1_RTS
NT0

PB1/UART2_RX/PB_EI PE20/CSI_FIELD/CSI_MIP
15 MCSI_D3P 16 82 83 PE24/LCD_D23/UART1_CTS
NT1 I_MCLK

PB10/JTAG_MS/PB_EI PE22/CSI_SDA/TWI1_SDA/
17 MCSI_D2N 18 84 85 PE13/CSI_D9/LCD_D13
NT10 UART1_RX

PB12/JTAG_DO/PB_EI
19 MCSI_D2P 20 86 PE14/CSI_D10/LCD_D14 87 PE15/CSI_D11/LCD_D15
NT12

PB8/TWI1_SCK/UART PG6/UART1_TX/PG_EINT
21 22 88 89 PE1/CSI_MCLK/LCD_DE
MCSI_CKN 0_TX/PB_EINT8 6

PB6/TWI0_SCK/PB_EI PG7/UART1_RX/PG_EINT
23 MCSI_CKP 24 90 91 PG13/PCM_EIN/PG_EINT13
NT6 7

PB7/TWI0_SDA/PB_EI
25 MCSI_D1N 26 92 PG3/SDC1_D1/PG_EINT3 93 PG8/UART1_RTS/PG_EINT8
NT7

PB2/UART2_RTS/PB_E PG1/SDC1_CMD/PG_EINT PG11/PCM_BCLK/PG_EINT1

27 MCSI_D1P 28 94 95
INT2 1 1

PB3/UART2_CTS/PB_E PG0/SDC1_CLK/PG_EINT
29 MCSI_D0N 30 96 97 HPOUTL
INT3 0

PB11/JTAG_CK/PB_EI
31 MCSI_D0P 32 98 PG2/SDC1_D0/PG_EINT2 99 HPOUTR
NT11

PB9/TWI1_SDA/UART 10
33 EPHY_RXN 34 PG5/SDC1_D3/PG_EINT5 101 HPOUTR
0_RX/PB_EINT9 0

10 PG12/PCM_DOUT/PG_EIN
35 EPHY_RXP 36 PB5/PWM1/PB_EINT5 103 HPCOMFB
2 T12

10
37 EPHY_TXN 38 PB4/PWM0/PB_EINT4 PG4/SDC1_D2/PG_EINT4 105 MBIAS
4

PD7/LCD_D11/RGMII_ 10 PG10/PCM_SYNC/PG_EIN
39 EPHY_TXP 40 107 HBIAS
TXD3/RMII_NULL 6 T10

PD6/LCD_D10/RGMII_ 10 PG9/UART1_CTS/PG_EIN
41 EPHY_SPD_LED 42 109 LRADC1
NULL/RMII_RXER 8 T9

Sipeed Technology 3
Sipeed lichee Zero Plus Datasheet v1.0

PD1/LCD_D3/RGMII_ 11
43 EPHY_LINK_LED 44 LINEINR 111 LRADC0
RXD2/RMII_NULL 0

PD21/LCD_VSYNC/LVDS PD8/LCD_D12/RGMII_ 11
45 46 LINEINL 113 LINEOUTR
_VN3 TXD2/RMII_NULL 2

PD20/LCD_HSYNC/LVD PD11/LCD_D15/RGMII 11
47 48 MICIN1N 115 LINEOUTL
S_VP3 _NULL/RMII_CRS_D 4

PD18/LCD_CLK/LVDS_V PD10/LCD_D14/RGMII 11
49 50 MICIN1P 117 AVCC
PC _TXD0/RMII_TXD0 6

PD19/LCD_DE/LVDS_VN PD4/LCD_D6/RGMII_ 11
51 52 X32KFOUT 119 PF4/SDC0_D3/UART0_RX
C RXCK/RMII_NULL 8

PD16/LCD_D22/LVDS_V PD5/LCD_D7/RGMII_ 12
53 54 PF0/SDC0_D1/JTAG_MS 121 PF3/SDC0_CMD/JTAG_DO
P2/MDC RXCTL/RMII_NULL 0

PD17/LCD_D23/LVDS_V PD2/LCD_D4/RGMII_ 12 PF2/SDC0_CLK/UART0_T

55 56 123 PF5/SDC0_D2/JTAG_CK
N2/MDIO RXD1/RMII_RXD1 2 X

PD15/LCD_D21/LVDS_V
PD3/LCD_D5/RGMII_ 12
57 N1/RGMII_CLKIN/RMII 58 PF1/SDC0_D0/JTAG_DI 125 PC2/SDC2_RST/SPI0_CS
RXD0/RMII_RXD0 4
_NULL
PD14/LCD_D20/LVDS_V
PD0/LCD_D2/RGMII_ 12
59 P1/RGMII_NULL/RMII_ 60 VCC_RTC 127 PC1/SDC2_CMD/SPI0_CLK
RXD3/RMII_NULL 6
NULL
PD13/LCD_D19/LVDS_D
PD9/LCD_D13/RGMII_ 12
61 N0/RGMII_TXCTL/RMII 62 RESET 129 PC0/SDC2_CLK/SPI0_MISO
TXD1/RMII_TXD1 8
_TXEN
PD12/LCD_D18/LVDS_V
13
63 P0/RGMII_TXCK/RMII_ 64 PE5/CSI_D1/LCD_D3 PF6 131 PC3/SDC2_D0/SPI0_MOSI
0
TXCK
PE2/CSI_HSYNC/LCD_H 13
65 66 PE6/CSI_D2/LCD_D4 USB_DP 133 GND
SYNC 2

13
67 PE16/CSI_D12/LCD_D18 USB_DM
4

Sipeed Technology 4
Sipeed lichee Zero Plus Datasheet v1.0

Resource

Official website www.sipeed.com

Github https://github.com/sipeed

BBS http://bbs.sipeed.com

Wiki http://lichee.sipeed.com

SDK Information http://dl.sipeed.com/LICHEE/ZeroPlus/SDK

HDK Information http://dl.sipeed.com/LICHEE/ZeroPlus/HDK

E-mail [email protected]

telgram link https://t.me/sipeed

Linux QQ Group 488268051

Disclaimer and copyright notice

The information in this document, including the URL address for reference, is
subject to change without notice.
The documentation is provided by Sipeed without warranty of any kind, including
any warranties of merchantability, and any proposal, specification or sample
referred to elsewhere. This document is not intended to be a liability, including the
use of information in this document to infringe any patent rights.

Copyrights © 2019 Sipeed Limited. All rights reserved.

Sipeed Technology 5