Freescale Semiconductor EB659

Rev. 1, 11/2006
Engineering Bulletin

MPC5500 Family Overview

by: Randy Dees
32-bit Automotive Applications

Ray Marshall
TSPG Powertrain Systems

1 Introduction 1
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
The MPC5554 microcontroller (MCU) was the first MPC5500 Roadmap. . . . . . . . . . . . . . . . . . . . . . 2
MPC5533 Block Diagram . . . . . . . . . . . . . . . . . 3
member of the MPC5500 family of next generation
MPC5534 Block Diagram . . . . . . . . . . . . . . . . . 4
microcontrollers based on Power Architecture ™ MPC5553 Block Diagram . . . . . . . . . . . . . . . . . 5
technology initially designed for next generation MPC5554 Block Diagram . . . . . . . . . . . . . . . . . 6
automotive powertrain applications. More devices in the MPC5551 Block Diagram . . . . . . . . . . . . . . . . . 7
MPC5565 Block Diagram . . . . . . . . . . . . . . . . . 8
family have been introduced, including the MPC5533, MPC5566 Block Diagram . . . . . . . . . . . . . . . . . 9
MPC5534, MPC5553, MPC5561, MPC5565, MPC5567 Block Diagram . . . . . . . . . . . . . . . . 10
MPC5566, and MPC5567 (all included in this 2 MPC5500 Family Comparison . . . . . . . . . . . . . . 11
document). 3 MPC5500 Family Memory Map . . . . . . . . . . . . . 12
4 Package Options. . . . . . . . . . . . . . . . . . . . . . . . . 16
The host processor core of the MPC5500 family devices 4.1 416 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 17
4.2 324 PBGA Ball Maps . . . . . . . . . . . . . . . . . . 20
is compatible with the Power Architecture technology. It
4.3 208 MAP BGA Ball Map . . . . . . . . . . . . . . . 21
is 100 percent user-mode compatible (with floating point Appendix A: Revision History
library) with the PowerPC ISA. This core has
instructions beyond the classic PowerPC ISA, including
digital signal processing (DSP) instructions.
The MPC553x and MPC556x devices include the
variable length encoding (VLE) option for improved
code density.

© Freescale Semiconductor, Inc., 2006. All rights reserved.

Introduction

MPC557x

MPC5500 Family
MPC5566

MPC5567
MPC5554

MPC5565
Performance/Integration

MPC5553
MPC5561

MPC5534

MPC5533

MPC5510
Family

MPC500 MPC565
Family
MPC563
MPC555
MPC561

1999 • • • • • • • 2005 2006 • • • • • • •

Availability

Figure 1. MPC5500 Roadmap

MPC5500 Family Overview, Rev. 1

2 Freescale Semiconductor
 Introduction

e200z3 Core
MPC5533
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction

JTAG Branch Load/Store

Prediction Unit Unit

Nexus
Interface Nexus Memory Management Unit

Calibration
Bus

External External
eDMA
Master Master Master Bus
32 Channels
Interface Interface

Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
768-Kb Integration 48-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

2.5-Kb eQADC
FlexCAN

FlexCAN

Data RAM ADCi

DSPI

DSPI

eSCI

eTPU
(32 Ch) 12-Kb ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z3 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eQADC – Enhanced queued analog/digital converter WDT – Watchdog timer
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 2. MPC5533 Block Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 3
Introduction

e200z3 Core
MPC5534
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction

JTAG Branch Load/Store

Prediction Unit Unit

Nexus
Interface Nexus Memory Management Unit

Calibration
Bus

External External
eDMA
Master Master Master Bus
32 Channels
Interface Interface

Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
1-Mb Integration 64-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

2.5-Kb eQADC
FlexCAN

FlexCAN

Data RAM ADCi

DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eMIOS
(32 Ch) 12-Kb (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z3 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 3. MPC5534 Block Diagram

MPC5500 Family Overview, Rev. 1

4 Freescale Semiconductor
 Introduction

e200z6 Core
MPC5553
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Multiply Instruction Unified
Unit Unit 8-Kb
Cache
JTAG Branch
Prediction Unit
Memory
Nexus Load/Store Management
Interface Nexus
Unit Unit

Fast External External

eDMA
Ethernet Master Master Bus
32 Channels
Controller Interface Interface

Master Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
1.5-Mb Integration 64-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

2.5-Kb eQADC
FlexCAN

FlexCAN

Data RAM ADCi

DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eMIOS
(32 Ch) 12-Kb (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 4. MPC5553 Block Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 5
Introduction

e200z6 Core
MPC5554
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Unified
Multiply Instruction
32-Kb
Unit Unit
Cache

JTAG Branch Load/Store

Prediction Unit Unit

Nexus
Interface Nexus Memory Management Unit

External External
eDMA
Master Master Bus
64 Channels
Interface Interface

Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
2-Mb Integration 64-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

3-Kb eQADC
FlexCAN

FlexCAN

FlexCAN
Data RAM ADCi
DSPI

DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eTPU eMIOS

(32 Ch) 16-Kb (32 Ch) (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 5. MPC5554 Block Diagram

MPC5500 Family Overview, Rev. 1

6 Freescale Semiconductor
 Introduction

e200z6 Core
MPC5561
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction
Unified
JTAG Branch
32-Kb
Prediction Unit
Cache
Nexus Memory
Nexus Load/Store
Interface Management
Unit
Unit

Calibration
Bus

External External
eDMA
Master FlexRay Master Bus
32 Channels
Interface Interface

Master Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave Slave SRAM
Assist
1-Mb Integration 192-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

eQADC
FlexCAN

FlexCAN

ADCi
DSPI

DSPI

eSCI

eSCI

eSCI

eSCI

eMIOS
(24 Ch) PDI
ADC ADC
AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 6. MPC5561 Block Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 7
Introduction

e200z6 Core
MPC5565
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction
Unified
JTAG Branch
8-Kb
Prediction Unit
Cache
Nexus Memory
Nexus Load/Store
Interface Management
Unit
Unit
Calibration
Bus

External External
eDMA
Master Master Bus
32 Channels
Interface Interface

Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
2-Mb Integration 64-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

2.5-Kb eQADC
FlexCAN

FlexCAN

FlexCAN
Data RAM ADCi
DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eMIOS
(32 Ch) 12-Kb (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 7. MPC5565 Block Diagram

MPC5500 Family Overview, Rev. 1

8 Freescale Semiconductor
 Introduction

e200z6 Core
MPC5566
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction
Unified
JTAG Branch
32-Kb
Prediction Unit
Cache
Nexus Memory
Nexus Load/Store
Interface Management
Unit
Unit
Calibration
Bus

Fast External External

eDMA
Ethernet Master Master Bus
64 Channels
Controller Interface Interface

Master Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
3-Mb Integration 128-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

4-Kb eQADC
FlexCAN

FlexCAN

FlexCAN

Data RAM FlexCAN ADCi

DSPI

DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eTPU eMIOS

(32 Ch) 20-Kb (32 Ch) (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 8. MPC5566 Block Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 9
Introduction

e200z6 Core
MPC5567
Signal 64-bit Core Timers
1.5V Processing General Purpose Unit
Regulator Engine Registers (FIT, TB, DEC)
Control
Integer
Special Purpose Exception
Execution Interrupt Controller
Registers Handler
Unit
FMPLL Variable Length
Multiply Instruction
Encoded
Unit Unit
Instruction
Unified
JTAG Branch
8-Kb
Prediction Unit
Cache
Nexus Memory
Nexus Load/Store
Interface Management
Unit
Unit

Calibration
Bus

Fast External External

eDMA
Ethernet Master FlexRay Master Bus
32 Channels
Controller Interface Interface

Master Master Master Master

Crossbar Switch (XBAR)

Slave Slave Slave

Boot
Flash System/Bus Slave Slave SRAM
Assist
2-Mb Integration 64-Kb
Module

Peripheral Bridge A (PBRIDGE_A) Peripheral Bridge B (PBRIDGE_B)

2.5-Kb eQADC
FlexCAN

FlexCAN

FlexCAN

FlexCAN

FlexCAN
Data RAM ADCi
DSPI

DSPI

DSPI

eSCI

eSCI

eTPU eMIOS
(32 Ch) 12-Kb (24 Ch) ADC ADC
Code RAM AMUX

LEGEND
MPC5500 Device Module Acronyms e200z6 Core Component Acronyms
CAN – Controller area network (FlexCAN) DEC – Decrementer
DSPI – Deserial/serial peripheral interface FIT – Fixed interval timer
eDMA – Enhanced direct memory access TB – Time base
eMIOS – Enhanced modular I/O system WDT – Watchdog timer
eQADC – Enhanced queued analog/digital converter
eSCI – Enhanced serial communications interface
eTPU – Enhanced time processing units
FMPLL – Frequency modulated phase-locked loop
SRAM – Static RAM

Figure 9. MPC5567 Block Diagram

MPC5500 Family Overview, Rev. 1

10 Freescale Semiconductor
 MPC5500 Family Comparison

2 MPC5500 Family Comparison

Table 1. MPC5500 Family Members

MPC5500 Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567
Power Core e200z3 e200z3 e200z6 e200z6 e200z6 e200z6 e200z6 e200z6
Variable Length Instruction Support Yes Yes No No Yes Yes Yes Yes
Cache None None 8 Kbyte 32 Kbyte 32 Kbyte 8 Kbyte 32 Kbyte 8 Kbyte
Unified1 Unified2 Unified3 Unified1 Unified3 Unified1
Memory Management Unit (MMU) 16 entry 16 entry 32 entry 32 entry 32 entry 32 entry 32 entry 32 entry
4
Crossbar 4x5 4x5 4x5 3x5 4x6 3 x5 4x5 5x5
Core Nexus Class 3+ Class 3+ Class 3+ Class 3+ Class 3+ Class 3+ Class 3+ Class 3+
(NZ3C3) (NZ3C3) (NZ6C3) (NZ6C3) (NZ6C3) (NZ6C3) (NZ6C3) (NZ6C3)
SRAM 48 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 192 Kbyte 64 Kbyte 128 Kbyte 80 Kbyte
Flash Main Array 768 1 Mbyte5 1.5 2 Mbyte6 1 Mbyte6 2 Mbyte6 3 Mbyte6 2 Mbyte6
Kbyte5 Mbyte6
Shadow Block 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte
7 bit7 bit7 bit7 32-bit7 32-bit7 32-bit7 32-bit7
External Bus Data Bus 16-bit 16 32 32
(EBI)
Address Bus 24 24 24 24 268 268 268 268

Calibration Bus Yes Yes Partial No Yes Yes Yes Yes

Direct Memory Access (DMA) 32 32 32 64 32 32 64 32
channel channel channel channel channel channel channel channel
DMA Nexus None None Class 3 Class 3 Class 3 Class 3 Class 3 Class 3
Serial 1 2 2 2 4 2 2 2
eSCI_A Yes Yes Yes Yes Yes Yes Yes Yes
eSCI_B No Yes Yes Yes Yes Yes Yes Yes
eSCI_C No No No No Yes No No No
eSCI_D No No No No Yes No No No
9
Controller Area Network (CAN) 2 2 2 3 3 39 49 59
CAN_A 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf
CAN_B No No No 64 buf No 64 buf 64 buf 64 buf
CAN_C 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf 64 buf
CAN_D No No No No No No 64 buf 64 buf
CAN_E No No No No No No No 64 buf
SPI 2 3 3 4 3 3 4 3
DSPI_A No No No Yes No No Yes No
DSPI_B No Yes Yes Yes Yes Yes Yes Yes
DSPI_C Yes Yes Yes Yes Yes Yes Yes Yes
DSPI_D Yes Yes Yes Yes No Yes Yes Yes
eMIOS 0 24 24 24 24 24 24 24
channel channel channel channel channel channel channel channel

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 11
 MPC5500 Family Memory Map

Table 1. MPC5500 Family Members (continued)

MPC5500 Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567
eTPU 32 32 32 64 0 32 64 32
channel channel channel channel channel channel channel channel
eTPU_A Yes Yes Yes Yes No Yes Yes Yes
eTPU_B No No No Yes No No Yes No
Code Memory 12 Kbyte 12 Kbyte 12 Kbyte 16 Kbyte 0 Kbyte 12 Kbyte 20 Kbyte 12 Kbyte
Parameter RAM 2.5 Kbyte 2.5 Kbyte 2.5 Kbyte 3 Kbyte 0 Kbyte 2.5 Kbyte 4 Kbyte 2.5 Kbyte
Nexus Class 3 Class 3 Class 3 Class 3 No Class 3 Class 3 Class 3
Interrupt Controller 178 210 210 300 231 231 329 281
channel channel channel channel channel channel channel channel
Analog to Digital Converter (eQADC) 40 40 40 40 40 40 40 40
channel channel channel channel channel channel channel channel
ADC_0 Yes Yes Yes Yes Yes Yes Yes Yes
ADC_1 No Yes Yes Yes Yes Yes Yes Yes
10
Fast Ethernet Controller (FEC) No No Yes No No No Yes10 Yes11
FlexRay No No No No Yes No No Yes
FlexRay Nexus No No No No Class 3 No No Class 3
Phase Lock Loop (PLL) FM FM FM FM FM FM FM FM
12
Maximum System Frequency 80 MHz 80 MHz 132 MHz 132 MHz 132 MHz 132 MHz 132 MHz 132 MHz
Crystal Range 8–20 MHz 8–20 MHz 8–20 MHz 8–20 MHz 8–40 MHz 8–20 MHz 8–20 MHz 8–40 MHz
Voltage Regulator Controller (VRC) Yes Yes Yes Yes Yes Yes Yes Yes
NOTES:
1 2-way associative
2 8-way associative
3 4-way or 8-way associative
4 The actual crossbar is implemented as a 5x5 crossbar with two unused ports
5 16-byte flash page size for programming
6 32-byte flash page size for programming
7 May not be externally available in some package configurations
8 Either ADDR[8:31] or ADDR[6:29] can be selected.
9
Updated FlexCAN module with optional individual receive filters
10
The FEC signals are shared with data bus pins DATA[16:31]
11
The FEC signals are shared with the calibration bus
12
Initial automotive temperature range qualification

3 MPC5500 Family Memory Map

This section describes the memory map for the MPC5500 devices discussed in this document. All
addresses in the device, including those that are reserved, are identified in the tables. The addresses
represent the physical addresses assigned to each IP module. Logical addresses are translated by the
memory management unit (MMU) into physical addresses.
Under software control of the MMU, the logical addresses allocated to IP blocks may be changed on a
minimum of a 4-Kbyte boundary. Peripheral blocks may be redundantly mapped. The customer must use
the MMU to prevent corruption.

MPC5500 Family Overview, Rev. 1

12 Freescale Semiconductor
 MPC5500 Family Memory Map

Table 2 shows a detailed memory map.

Table 2. Detailed MPC5500 Family Memory Map

MPC5532
MPC5533
MPC5534
MPC5553
MPC5554
MPC5561
MPC5565
MPC5566
MPC5567
Allocated Used
Address Range1 Use
Size Size

0x0000_0000–0x000B_FFFF 768 Kbyte 768 Kbyte Flash Array √ √ √ √ √ √ √ √ √

0x000C_0000–0x000F_FFFF 256 Kbyte 256 Kbyte Flash Array √ √ √ √ √ √ √ √
0x0010_0000–0x0017_FFFF 512 Kbyte 512 Kbyte Flash Array √ √ √ √ √
0x0018_0000–0x001F_FFFF 512 Kbyte 512 Kbyte Flash Array √ √ √ √
0x0020_0000–0x002F_FFFF 1 Mbyte 1 Mbyte Flash Array √
0x0030_0000–0x00FF_FBFF ~13 Mbyte N/A Reserved
0x00FF_FC00–0x00FF_FFFF 1024 bytes 1024 Flash Shadow Block √ √ √ √ √ √ √ √ √
bytes
0x0100_0000–0x1FFF_FFFF 496 Mbyte 2 Mbyte Emulation Mapping of Flash Array √ √ √ √ √ √ √ √ √
0x2000_0000–0x3FFF_FFFF 512 Mbyte N/A External Memory √ √ √ √ √ √ √ √ √
0x4000_0000–0x4000_7FFF 32 Kbyte 32 Kbyte SRAM Array, Standby Powered √ √ √ √ √ √ √ √ √
0x4000_8000–0x4000_BFFF 16 Kbyte 16 Kbyte SRAM Array √ √ √ √ √ √ √ √ √
0x4000_C000–0x4000_FFFF 16 Kbyte 16 Kbyte SRAM Array √ √ √ √ √ √ √
0x4001_0000–0x4001_3FFF 16 Kbyte 16 Kbyte SRAM Array √ √ √
0x4001_4000–0x4001_FFFF 48 Kbyte 48 Kbyte SRAM Array √ √
0x4002_0000–0x4002_FFFF 64 Kbyte 64 Kbyte SRAM Array √
0x4003_0000–0x9FFF_FFFF (<15 Gb) N/A Reserved
0xA000_0000–0xBFFF_FFFF 512 Mbyte 256 Parallel Digital Interface √
Mbyte
Bridge A Peripherals
0xC000_0000–0xC3EF_FFFF 63 Mbyte N/A Reserved
0xC3F0_0000–0xC3F0_3FFF 16 kbyte 16 kbyte Bridge A Registers √ √ √ √ √ √ √ √ √
0xC3F0_4000–0xC3F7_FFFF 496 Kbyte N/A Reserved
0xC3F8_0000–0xC3F8_3FFF 16 Kbyte 20 kbyte FMPLL √ √ √ √ √ √ √ √ √
0xC3F8_4000–0xC3F8_7FFF 16 Kbyte 48 Kbyte External Bus Interface (EBI) √ √ √ √ √ √ √ √ √
Configuration
0xC3F8_8000–0xC3F8_BFFF 16 Kbyte 28 Kbyte Flash Configuration √ √ √ √ √ √ √ √ √
0xC3F8_C000–0xC3F8_FFFF 16 Kbyte N/A Reserved
0xC3F9_0000–0xC3F9_3FFF 16 Kbyte 2.5 Kb System Integration Unit (SIU) √ √ √ √ √ √ √ √ √
0xC3F9_4000–0xC3F9_FFFF 48 Kbyte N/A Reserved
0xC3FA_0000–0xC3FA_3FFF 16 Kbyte 1056 Modular Timer System (eMIOS) √ √ √ √ √ √ √ √
3
0xC3FA_4000–0xC3FA_7FFF 16 Kbyte 1056 Modular Timer System (eMIOS_B)
0xC3FA_8000–0xC3FB_FFFF 96 Kbyte N/A Reserved
0xC3FC_0000–0xC3FC_3FFF 16 Kbyte 3 Kbyte Enhanced Time Processing Unit √ √ √ √ √ √ √ √
(eTPU) Registers
0xC3FC_4000–0xC3FC_7FFF 16 Kbyte N/A Reserved

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 13
MPC5500 Family Memory Map

Table 2. Detailed MPC5500 Family Memory Map (continued)

MPC5532
MPC5533
MPC5534
MPC5553
MPC5554
MPC5561
MPC5565
MPC5566
MPC5567
Allocated Used
Address Range1 Use
Size Size

0xC3FC_8000–0xC3FC_09FF 16 Kbyte 2.5 Kbyte eTPU Shared Data Memory √ √ √ √ √ √ √ √

0xC3FC_8A00–0xC3FC_8BFF 0.5 Kbyte (Parameter RAM) √ √
0xC3FC_8C00–0xC3FC_8FFF 1 Kbyte √
0xC3FC_9000–0xC3FC_BFFF eTPU Parameter RAM Reserved
0xC3FC_C000–0xC3FC_FFFF 16 Kbyte 3 Kbyte eTPU Shared Data Memory √ √ √ √ √ √ √ √
(Parameter RAM) mirror
0xC3FD_0000–0xC3FD_2FFF 20 Kbyte 12 Kbyte eTPU Shared Code RAM √ √ √ √ √ √ √ √
0xC3FD_3000–0xC3FD_3FFF 4 Kbyte (12K,16K, or 20K) √ √
0xC3FD_4000–0xC3FD_4FFF 4 Kbyte √
0xC3FD_5000–0xC3FF_7FFF 156 Kbyte N/A Reserved
0xC3FF_8000–0xC3FF_BFFF 16 Kbyte N/A Reserved
0xC3FF_C000–0xC3FF_FFFF 16 Kbyte N/A Reserved
0xC400_0000–0xDFFF_FFFF (448 Mbyte) N/A Reserved
Bridge B Peripherals
0xE000_0000–0xFBFF_FFFF (448 Mbyte) N/A Reserved
0xFC00_0000–0xFFEF_FFFF 63 Mbyte N/A Reserved
0xFFF0_0000–0xFFF0_3FFF 16 Kbyte N/A Bridge B Registers √ √ √ √ √ √ √ √ √
0xFFF0_4000–0xFFF0_7FFF 16 Kbyte N/A Crossbar (XBAR) √ √ √ √ √ √ √ √ √
0xFFF0_8000–0xFFF0_FFFF 32 Kbyte N/A Reserved
0xFFF1_0000–0xFFF3_FFFF 192 Kbyte N/A Reserved
0xFFF4_0000–0xFFF4_3FFF 16 Kbyte N/A ECSM √ √ √ √ √ √ √ √ √
0xFFF4_4000–0xFFF4_7FFF 16 Kbyte N/A DMA Controller 2 (eDMA) √ √ √ √ √ √ √ √ √
0xFFF4_8000–0xFFF4_BFFF 16 Kbyte N/A Interrupt Controller (INTC) √ √ √ √ √ √ √ √ √
0xFFF4_C000–0xFFF4_C3FF 1 Kbyte N/A Fast Ethernet Controller (FEC) 2
√ √ √
0xFFF4_C400–0xFFF4_FFFF 15 Kbyte N/A Reserved
0xFFF5_0000–0xFFF7_FFFF 192 Kbyte N/A Reserved
0xFFF8_0000–0xFFF8_3FFF 16 Kbyte 164 Enhanced Queued Analog-to-Digital √ √ √ √ √ √ √ √ √
Converter (eQADC)
0xFFF8_4000–0xFFF8_7FFF 16 Kbyte 164 Enhanced Queued Analog-to-Digital
Converter (eQADC_B)3
0xFFF8_8000–0xFFF8_FFFF 32 Kbyte N/A Reserved
0xFFF9_0000–0xFFF9_3FFF 16 Kbyte 200 Deserial Serial Peripheral Interface √ √
(DSPI_A)
0xFFF9_4000–0xFFF9_7FFF 16 Kbyte 200 Deserial Serial Peripheral Interface √ √ √ √ √ √ √
(DSPI_B)
0xFFF9_8000–0xFFF9_BFFF 16 Kbyte 200 Deserial Serial Peripheral Interface √ √ √ √ √ √ √ √ √
(DSPI_C)
0xFFF9_C000–0xFFF9_FFFF 16 Kbyte 200 Deserial Serial Peripheral Interface √ √ √ √ √ √ √ √ √
(DSPI_D)

MPC5500 Family Overview, Rev. 1

14 Freescale Semiconductor
 MPC5500 Family Memory Map

Table 2. Detailed MPC5500 Family Memory Map (continued)

MPC5532
MPC5533
MPC5534
MPC5553
MPC5554
MPC5561
MPC5565
MPC5566
MPC5567
Allocated Used
Address Range1 Use
Size Size

0xFFFA_0000–0xFFFA_3FFF 16 Kbyte 200 Deserial Serial Peripheral Interface

(DSPI_E)3
0xFFFA_4000–0xFFFA_7FFF 16 Kbyte 200 Deserial Serial Peripheral Interface
(DSPI_F)3
0xFFFA_8000–0xFFFA_FFFF 32 Kbyte N/A Reserved
0xFFFB_0000–0xFFFB_3FFF 16 Kbyte 44 Serial Communications Interface √ √ √ √ √ √ √ √ √
(SCI_A)
0xFFFB_4000–0xFFFB_7FFF 16 Kbyte 44 Serial Communications Interface √ √ √ √ √ √ √ √
(SCI_B)
0xFFFB_8000–0xFFFB_BFFF 16 Kbyte 44 Serial Communications Interface √
(SCI_C)
0xFFFB_C000–0xFFFC_FFFF 16 Kbyte 44 Serial Communications Interface √
(SCI_D)
0xFFFC_0000–0xFFFC_3FFF 16 Kbyte 1152 Controller Area Network √ √ √ √ √ √ √ √ √
(FlexCAN_A)
0xFFFC_4000–0xFFFC_7FFF 16 Kbyte 1152 Controller Area Network √ √ √ √
(FlexCAN_B)
0xFFFC_8000–0xFFFC_BFFF 16 Kbyte 1152 Controller Area Network √ √ √ √ √ √ √ √
(FlexCAN_C)
0xFFFC_C000–0xFFFC_FFFF 16 Kbyte 1152 Controller Area Network √ √
(FlexCAN_D)
0xFFFD_0000–0xFFFD_3FFF 16 Kbyte 1152 Controller Area Network √
(FlexCAN_E)
0xFFFD_4000–0xFFFD_FFFF 48 Kbyte N/A Reserved
0xFFFE_0000–0xFFFE_3FFF 16 Kbyte 2 kbyte FlexRay √ √
0xFFFE4000–0xFFFE_7FFF 16 Kbyte Reserved
0xFFFE_8000–0xFFFE_BFFF 16 Kbyte Parallel Digital Interface √
0xFFFF_C000–0xFFFF_FFFF4 16 Kbyte 16 Kbyte Boot Assist Module (BAM) √ √ √ √ √ √ √ √ √
NOTES:
1
If allocated size is greater than used size, the base address for the module is the lowest address of the listed address range,
unless noted otherwise.
2 The fast Ethernet controller (FEC) uses different pins on the MPC5553/MPC5566 and the MPC5567.
3 Reserved for future compatibility. No device is currently defined that uses these regions.
4
BAM address range is configured so that 4 kbytes BAM occupies 0xFFFF_F000-0xFFFF_FFFF.

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 15
Package Options

4 Package Options
The members of the MPC5500 family are all pin-compatible, but the different devices are available in a
range of packages. Not all features are available in the smaller packages or on all devices.
Table 3. Device Package Options

Calibration
Device 208 MAPBGA1 324 PBGA 416 PBGA 496 CSP2
Bus

MPC5533 Yes3,4 No7 No Yes Yes

3,4 3
MPC5534 Yes Yes No Yes Yes
MPC5553 Yes4 Yes3 Yes5 Yes Partial6
MPC5554 No No Yes3 Yes No
MPC5561 No Yes No No No
MPC5565 No7 Yes3,4 No4,7 Yes Yes
MPC5566 No No Yes3 Yes Yes
MPC5567 No7 Yes4 Yes3,5 Yes Yes
Nexus port availability 4-bit MDO Only 4 or 12-bit MDO 4 or 12-bit MDO 4 or 12-bit MDO
Bus availability None 16-bit data / 32-bit data / 32-bit data /
(OE and CS0 20-bit address 24/26-bit address 24/26-bit address
available for 4 chip selects8 4 chip selects 4 chip selects
GPIO)
Calibration bus None None None 16-bit data /
availability 21/19-bit address
1/3 chip selects
Analog channels 34 40 40 40
9
Ethernet available No No Yes —
NOTES:
1 The 208 MAPBGA package is not available through distribution. If demand warrants, consult factory on

availability.
2
The VertiCal CSP package is a 496 ball device mounted on a sub-assembly to fit into the 208, 324, or 416 ball
footprint. It is not available as a standalone packaged device.
3 Predominate package. Though all packages may be available, the predominate package is the package in which

most of the volume deliveries are expected.

4 Not available to distribution customers.
5 Predominate package for Ethernet use.
6 The MPC5553 lose use of 16 data bus signals in the 416 ball sub-assembly for the calibration data bus. The

address bus is shared between the calibration bus and the normal system bus. Note: the fast Ethernet controller
(FEC) requires these same 16 data bus signals on this devices. On the MPC5567, the FEC is shared with the
calibration bus.
7 Depending on demand, consult factory for availability,
8
Up to 24 bits of address with zero chip selects can optionally be selected.
9 On devices that include Ethernet only.

MPC5500 Family Overview, Rev. 1

16 Freescale Semiconductor
 Package Options

4.1 416 PBGA Ball Maps

4.1.1 MPC5554/MPC5566
Figure 10 is a pinout for the MPC5554/MPC5566 416 PBGA package, Revision A.
NOTE:
On the MPC5554, Ball J23 is VDDEH6. On the MPC5566, ball J23 is
VDDEH10.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB GPIO MDO11 MDO8 VDD VDD33 VSS
A VSS VSTBY AN37 AN11 VDDA1 AN16 1 18 20 24 27 205 A

AN0 AN4 REF AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 MDO4 MDO0 VSS VDDE7 B
B VDD VSS AN36 AN39 AN19 AN20 BYPC 0 21 25 28 31

AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD
C VDD33 VDD VSS AN8 AN17 VSSA1 19 22 26 30 C

ETPUA ETPUA AN10 AN18 AN2 AN6 AN24 AN29 AN34 VDDEH AN12 ETPUB ETPUB ETPUB ETPUB MDO5 MDO2 VDDEH VSS VDDE7 TCK TDI
D 30 31 VDD VSS AN38 AN9 9 16 17 23 29 8 D

ETPUA ETPUA VDDEH VDDE7 TMS TDO TEST

E 28 29 1 VDD E

ETPUA ETPUA ETPUA VDDEH MSEO0 JCOMP EVTI EVTO F

F 24 27 26 1
ETPUA ETPUA ETPUA ETPUA MSEO1 MCKO GPIO ETPUB
G 23 22 25 21 204 15 G

H
ETPUA ETPUA ETPUA ETPUA Version 1.3p – 29 May 2004 RDY GPIO ETPUB ETPUB
H
20 19 18 17 203 14 13
ETPUA ETPUA ETPUA ETPUA VDDEH ETPUB ETPUB ETPUB
J 16 15 14 13 6/10* 12 11 9 J

ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 ETPUB ETPUB ETPUB ETPUB
K 12 11 10 9 10 8 7 5 K

ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VSS VSS VDDE7 ETPUB ETPUB ETPUB ETPUB
L 8 7 6 5 6 4 3 2 L

ETPUA ETPUA ETPUA ETPUA VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 TCRCLK ETPUB ETPUB SINB
M 4 3 2 1 B 1 0 M

ETPUA TCRCLK VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N
N BDIP TEA 0 A

P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P

R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA SINA SCKA R

T VDDE2 TSIZ0 RD_WR VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VPP T

ADDR VSS VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U
U 16 TSIZ1 TA VDD33

ADDR ADDR ADDR CNTXC RXDA RSTOUT RST

V 18 17 TS 8 CFG V

ADDR ADDR ADDR ADDR RXDB CNRXC TXDB RESET W

W 20 19 9 10
ADDR ADDR ADDR WKP BOOT VRC VSS
Y 22 21 11 VDDE2 Note: NC No connect. AC22 & AD23 reserved CFG CFG1 VSS SYN Y

ADDR ADDR ADDR ADDR VDDEH PLL BOOT EXTAL

AA 24 23 13 12 6 CFG1 CFG0 AA

ADDR ADDR ADDR VDD VRC PLL XTAL

AB VDDE2 25 15 14 CTL CFG0 AB

ADDR ADDR ADDR DATA DATA VDDE2 DATA DATA DATA DATA VDDE2 DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC VSS VDD VRC33 VDD
AC 26 27 31 VSS VDD 26 28 30 31 8 10 12 14 2 8 12 21 4 SYN AC

ADDR ADDR DATA DATA DATA DATA VDD33 GPIO DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC VSS VDD VDD33 AD
AD 28 30 VSS VDD 24 25 27 29 207 9 11 13 15 3 6 10 15 17 22
ADDR DATA DATA DATA DATA DATA DATA DATA DATA OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS VDD
AE 29 VSS VDD 17 19 21 23 0 2 4 6 1 5 9 13 16 19 23 AE

DATA DATA DATA DATA GPIO DATA DATA VDDE2 DATA DATA BB EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 ENG VSS
AF VSS VDD 16 18 VDDE2 20 22 206 1 3 5 7 0 4 7 11 14 18 20 CLK AF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 10. MPC5554/MPC5566 416 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 17
Package Options

4.1.2 MPC5553
Figure 11 is a pinout for the MPC5553 416 PBGA package. The MPC5553 and the
MPC5554/MPC5565/MPC5566 are pin-compatible; however, the MPC5553 ball map is shown here to
highlight the balls not connected to any signal on the MCP5553 (the eTPUB[0:31] and TSIZ[0:1]). The
alternate Ethernet signals that are multiplexed with the data bus are not shown for the MPC5553.
NOTE
Some pins have names that include functions unavailable on all family
members. For example, ball R25 of the 416 BGA package is named ‘SINA’,
but the MPC5553 does not have a DSPI_A module. In this case, the SINA
pin can only be used for its alternate functions of GPIO94 or PCSC2. See
the specific device reference manual for functions available on each device
in the family.
If the MPC5534 were available in the 416 PBGA package, then it would
also be missing the following signals: WE2, WE3, ADDR[8:11], and TEA.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG NC_1 NC_2 NC_3 NC_4 GPIO MDO11 MDO8 VDD VDD33 VSS
A VSS VSTBY AN37 AN11 VDDA1 AN16 1 205 A

AN0 AN4 REF AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG NC_5 NC_6 NC_7 NC_8 MDO10 MDO7 MDO4 MDO0 VSS VDDE7 B
B VDD VSS AN36 AN39 AN19 AN20 BYPC 0

C VDD33 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 NC_9 NC_10 NC_11 NC_12 MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD C

ETPUA ETPUA AN10 AN18 AN2 AN6 AN24 AN29 AN34 VDDEH AN12 NC_13 NC_14 NC_15 NC_16 MDO5 MDO2 VDDEH VSS VDDE7 TCK TDI
D 30 31 VDD VSS AN38 AN9 9 8 D

ETPUA ETPUA VDDEH VDDE7 TMS TDO TEST

E 28 29 1 VDD E

ETPUA ETPUA ETPUA VDDEH MSEO0 JCOMP EVTI EVTO F

F 24 27 26 1
ETPUA ETPUA ETPUA ETPUA MSEO1 MCKO GPIO NC_17 G
G 23 22 25 21 204

H
ETPUA ETPUA ETPUA ETPUA Version 2.1 – 13 July 2004 RDY GPIO NC_18 NC_19 H
20 19 18 17 203
ETPUA ETPUA ETPUA ETPUA VDDEH NC_20 NC_21 NC_22
J 16 15 14 13 10 J

ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 NC_23 NC_24 NC_25 NC_26 K
K 12 11 10 9
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VSS VSS VDDE7 NC_27 NC_28 NC_29 NC_30 L
L 8 7 6 5
ETPUA ETPUA ETPUA ETPUA VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 NC_31 NC_32 NC_33 SINB
M 4 3 2 1 M

ETPUA TCRCLK VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N
N BDIP TEA 0 A

P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P

R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA SINA SCKA R

T VDDE2 NC_34 RD_WR VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VPP T

ADDR VSS VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U
U 16 NC_35 TA VDD33

ADDR ADDR ADDR CNTXC RXDA RSTOUT RST

V 18 17 TS 8 CFG V

ADDR ADDR ADDR ADDR RXDB CNRXC TXDB RESET W

W 20 19 9 10
Note: NC_X No connects (x = 1 to 38)
ADDR ADDR ADDR WKP BOOT VRC VSS
Y 22 21 11 VDDE2 CFG CFG1 VSS SYN Y

ADDR ADDR ADDR ADDR

NC_36 NC_37 No connect. AC22 & AD23 reserved VDDEH PLL BOOT EXTAL
AA 24 23 13 12 6 CFG1 CFG0 AA

ADDR ADDR ADDR VDD VRC PLL XTAL

AB VDDE2 25 15 14 CTL CFG0 AB

ADDR ADDR ADDR DATA DATA VDDE2 DATA DATA DATA DATA VDDE2 DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36 VSS VDD VRC33 VDD
AC 26 27 31 VSS VDD 26 28 30 31 8 10 12 14 2 8 12 21 4 SYN AC

ADDR ADDR DATA DATA DATA DATA VDD33 GPIO DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37 VSS VDD VDD33 AD
AD 28 30 VSS VDD 24 25 27 29 207 9 11 13 15 3 6 10 15 17 22
ADDR DATA DATA DATA DATA DATA DATA DATA DATA OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS VDD
AE 29 VSS VDD 17 19 21 23 0 2 4 6 1 5 9 13 16 19 23 AE

DATA DATA DATA DATA GPIO DATA DATA VDDE2 DATA DATA NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 ENG VSS
AF VSS VDD 16 18 VDDE2 20 22 206 1 3 5 7 0 4 7 11 14 18 20 CLK AF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 11. MPC5553 416 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1

18 Freescale Semiconductor
 Package Options

4.1.3 MPC5567
Figure 11 is a pinout for the MPC5567 416 PBGA package. The MPC5567 and the MPC5553/MPC5554
are pin-compatible; however, the MPC5567 ball map is shown here to highlight the balls not connected to
any signals and the balls used for Ethernet.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG NC VDDE FEC_ FEC_ GPIO MDO11 MDO8 VDD VDD33 VSS
A VSS VSTBY AN37 AN11 VDDA1 AN16 1 13 TX_CLK TX_ER 205 A

AN0 AN4 REF AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG NC FEC_ FEC_ FEC_ MDO10 MDO7 MDO4 MDO0 VSS VDDE7 B
B VDD VSS AN36 AN39 AN19 AN20 BYPC 0 TXD2 TXD1 TXD0

AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 NC NC FEC_ FEC_ MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD
C VDD33 VDD VSS AN8 AN17 VSSA1 TX_EN TXD3 C

ETPUA ETPUA AN10 AN18 AN2 AN6 AN24 AN29 AN34 VDDEH AN12 NC FEC_ FEC_ VDDE MDO5 MDO2 VDDEH VSS VDDE7 TCK TDI
D 30 31 VDD VSS AN38 AN9 9 COL CRS 13 8 D

ETPUA ETPUA VDDEH VDDE7 TMS TDO TEST

E 28 29 1 VDD E

ETPUA ETPUA ETPUA VDDEH MSEO0 JCOMP EVTI EVTO F

F 24 27 26 1
ETPUA ETPUA ETPUA ETPUA MSEO1 MCKO GPIO FEC_
G 23 22 25 21 204 RX_ER G

H
ETPUA ETPUA ETPUA ETPUA Version 1.2 – 11 July 2005 RDY GPIO FEC_ VDDE
H
20 19 18 17 203 RX_DV 12
ETPUA ETPUA ETPUA ETPUA VDDEH FEC_ FEC_ FEC_
J 16 15 14 13 10 MDC RXD3 RX_CLK J
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 VDDE FEC_ FEC_ FEC_
K 12 11 10 9 12 RXD2 RXD1 RXD0 K

ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VSS VSS VDDE7 FEC_ NC NC NC
L 8 7 6 5 MDIO L

ETPUA ETPUA ETPUA ETPUA VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 NC NC NC SINB
M 4 3 2 1 M

ETPUA TCRCLK VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N
N BDIP TEA 0 A

P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P

R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA SINA SCKA R

T VDDE2 NC RD_WR VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VPP T

ADDR VSS VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U
U 16 NC TA VDD33

ADDR ADDR ADDR CNTXC RXDA RSTOUT RST

V 18 17 TS 8 CFG V

ADDR ADDR ADDR ADDR RXDB CNRXC TXDB RESET W

W 20 19 9 10
Note: NC No connect
ADDR ADDR ADDR WKP BOOT PLL VSS
Y 22 21 11 VDDE2 CFG CFG1 CFG2 SYN Y

ADDR ADDR ADDR ADDR

NC_1 NC_2 No connect. AC22 & AD23 reserved VDDEH PLL BOOT EXTAL
AA 24 23 13 12 6 CFG1 CFG0 AA

ADDR ADDR ADDR VDD VRC PLL XTAL

AB VDDE2 25 15 14 CTL CFG0 AB

ADDR ADDR ADDR DATA DATA VDDE2 DATA DATA DATA DATA VDDE2 DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_1 VSS VDD VRC33 VDD
AC 26 27 31 VSS VDD 26 28 30 31 8 10 12 14 2 8 12 21 4 SYN AC

ADDR ADDR DATA DATA DATA DATA VDD33 GPIO DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_2 VSS VDD VDD33 AD
AD 28 30 VSS VDD 24 25 27 29 207 9 11 13 15 3 6 10 15 17 22
ADDR DATA DATA DATA DATA DATA DATA DATA DATA OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS VDD
AE 29 VSS VDD 17 19 21 23 0 2 4 6 1 5 9 13 16 19 23 AE

DATA DATA DATA DATA GPIO DATA DATA VDDE2 DATA DATA NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 ENG VSS
AF VSS VDD 16 18 VDDE2 20 22 206 1 3 5 7 0 4 7 11 14 18 20 CLK AF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 12. MPC5567 416 PBGA Ball Map Diagram

NOTE
Ball Y25 changes from VRCVSS on all other MPC5500 devices (currently defined) to PLLCFG2 on the
MPC5567. PLLCFG2 is required to support a 40-MHz clock option for the FlexRay.

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 19
Package Options

4.2 324 PBGA Ball Maps

4.2.1 MPC5533/MPC5534/MPC5553/MPC5561/MPC5565
Figure 13 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5561/MPC5565 324 PBGA package.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

A VSS VDD VSTBY AN37 AN11 VDDA1 VSSA1 AN1 AN5 VRH VRL AN27 AN28 AN35 VSSA0 AN12 MDO11 MDO10 MDO8 VDD VDD33 VSS A

AN16 AN0 AN4 REF AN23 AN26 AN31 AN32 VSSA0 AN13 MDO9 MDO7 MDO4 MDO0 VSS VDDE7 B
B VDD33 VSS VDD AN36 AN39 AN19 BYPC
ETPUA ETPUA AN20 AN21 AN3 AN7 AN22 AN25 AN30 AN33 VDDA0 AN14 MDO5 MDO2 MDO1 VSS VDDE7 VDD
C 30 31 VSS VDD AN8 AN17 C

ETPUA ETPUA ETPUA AN9 AN10 AN18 AN2 AN6 AN24 AN29 AN34 VDDEH AN15 MDO6 MDO3 VSS VDDE7 TCK TDI
D 28 29 26 VSS VDD AN38 9 D

ETPUA ETPUA ETPUA ETPUA VDDE7 TMS TDO TEST

E 24 27 25 21 E

ETPUA ETPUA ETPUA ETPUA VDDE7 JCOMP EVTI EVTO F

F 23 22 17 18
ETPUA ETPUA ETPUA ETPUA RDY MCKO MSEO0 MSEO1 G
G 20 19 14 13 Version 2.2p – 13 July 2004
ETPUA ETPUA ETPUA VDDEH VDDEH GPIO GPIO SINB
H 16 15 10 1 10 203 204 H

ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 J
J 12 11 6 9
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 K
K 8 7 2 5
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS VSS VSS PCSB5 SOUTA SINA SCKA L
L 4 3 0 1
TCRCLK VDDE2 VDDE2 VSS VSS VSS VSS PCSA1 PCSA0 PCSA2 VPP
M BDIP A CS1 CS0 M

N CS3 CS2 WE1 WE0 VSS VSS VDDE2 VSS VSS VSS PCSA4 TXDA PCSA5 VFLASH N

ADDR ADDR VSS VSS VDDE2 VSS VSS VSS CNTXC RXDA RSTOUT RST
P 16 17 RD_WR VDD33 CFG P

ADDR ADDR VDDE2 TA WKP CNRXC TXDB RESET R

R 18 19 CFG
ADDR ADDR ADDR RXDB BOOT VRC VSS
T 20 21 12 TS CFG1 VSS SYN T
Note: NC No connect. Reserved (W18 & Y19 are shorted to each other)
ADDR ADDR ADDR ADDR VDDEH PLL BOOT EXTAL
U 22 23 13 14 6 CFG1 CFG0 U

ADDR ADDR ADDR ADDR VDD VRC PLL XTAL

V 24 25 15 31 CTL CFG0 V

ADDR ADDR VDDE2 VDD33 VDDE2 DATA DATA DATA EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 NC VSS VDD VRC33 VDD
W 26 VDDE2 30 VSS VDD 11 12 14 2 8 4 12 21 SYN W

ADDR ADDR VDDE2 DATA DATA DATA GPIO DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC VSS VDD VDD33 Y
Y 28 27 VSS VDD 8 9 10 207 13 15 6 10 15 17 22
ADDR VDDE2 DATA VDDE2 GPIO DATA DATA VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS VDD
AA 29 VSS VDD 1 206 5 7 3 5 9 13 16 19 23 AA

DATA DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 ENG VSS
AB VSS VDD VDDE2 0 2 3 4 6 OE 0 1 4 7 11 14 18 20 CLK AB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Figure 13. MPC5533/MPC5534/MPC5553/MPC5565 324 PBGA Ball Map Diagram

On the MPC5561 and MPC5567 ball T21 is PLLCFG2 instead of VRCVSS. PLLCFG2 is required to
support a 40 MHz clock option for the FlexRay.

MPC5500 Family Overview, Rev. 1

20 Freescale Semiconductor
 Package Options

4.3 208 MAP BGA Ball Map

4.3.1 MPC5533/MPC5534/MPC5553/MPC5565/MPC5566/MPC5567
Figure 14 is a pinout for the MPC5533/MPC5534/MPC5553/MPC5565/MPC5567 208 MAP PBGA
package.
NOTE
VDDEH10 and VDDEH6 are connected internally on the 208-ball package
and are listed as VDDEH6.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A VSS AN9 AN11 VDDA1 VSSA1 AN1 AN5 VRH VRL AN27 VSSA0 AN12 MDO2 MDO0 VDD33 VSS A

REF AN22 AN25 AN28 VDDA0 AN13 MDO3 MDO1 VSS VDD
B VDD VSS AN38 AN21 AN0 AN4 BYPC B

C VSTBY VDD VSS AN17 AN34 AN16 AN3 AN7 AN23 AN32 AN33 AN14 AN15 VSS MSEO0 TCK C

D VDD33 AN39 VDD VSS AN18 AN2 AN6 AN24 AN30 AN31 AN35 VDDEH VSS TMS EVTO TEST D
9
ETPUA ETPUA AN37 VDD VDDE7 TDI EVTI MSEO1 E
E 30 31
ETPUA ETPUA ETPUA AN36 VDDEH TDO MCKO JCOMP F
F 28 29 26 8 June 2005p 6
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS SOUTB PCSB3 SINB PCSB0 G
G 24 27 25 21
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS PCSA3 PCSB4 PCSB2 PCSB1 H
H 23 22 17 18
ETPUA ETPUA ETPUA ETPUA VSS VSS VSS VSS PCSB5 TXDA PCSA2 SCKB J
J 20 19 14 13
ETPUA ETPUA ETPUA VDDEH VSS VSS VSS VSS CNTXC RXDA RSTOUT VPP
K 16 15 7 1 K

ETPUA ETPUA ETPUA TCRCLK TXDB CNRXC WKP RESET L

L 12 11 6 A CFG
Note: CS0 No connect. R1 reserved for CS0
ETPUA ETPUA ETPUA ETPUA RXDB PLL BOOT VSS
M 10 9 1 5 CFG0 CFG1 SYN M

ETPUA ETPUA ETPUA VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33 VSS VRC PLL EXTAL N
N 8 4 0 VSS VDD 2 10 4 12 21 CTL CFG1
ETPUA ETPUA GPIO EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDD VSS VRC33 XTAL
P 3 2 VSS VDD 207 VDDE2 6 8 16 17 22 P

GPIO EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB VDD VSS VDD
R CS0 VSS VDD 206 4 3 9 11 14 19 23 SYN R

EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5 ENG VDD VSS
T VSS VDD OE 0 1 5 7 13 15 18 20 CLK T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 14. MPC5534/MPC5553/MPC5565/MPC5567 208 PBGA Ball Map Diagram

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 21
Package Options

Appendix A: Revision History

Table 4 is a revision history for this document.
Table 4. Revision History

Revision
Substantive Changes
Number

0 Initial release.
A.1 • Added Section 11, “MPC5554 Evaluation Board Availability.” (now removed)
• Changed TCRCLKB(IRQ6) to TCRCLKA(IRQ) in Table 16.(now removed)
• Changed NC to eTPUB24 and NC to TCRCLKB in Table 17.(now removed)
A.4 • First Confidential release for customers.

A.5 • Added MPC5566. Corrected memory map for MPC5565 and MPC5567 showing
flash size and eTPU shared RAM size.
• Corrected MPC5565 and MPC5567 block diagrams - only 1 eTPU each.
• Re-ordered the block diagrams and tables to put into devices into numeric order,
instead of introduction order.
• Added place holder for MPC557x future devices in the device roadmap.
• Added MPC5533 block diagram.
• L2 SRAM renamed just SRAM.
• Corrected SINA ball number in Section 4.1.2.
• Modified ordering of device introduction schedules in Figure 1 MPC5500 roadmap
figure.
• Added cache associativity to Table 1
• Renamed all pinout diagrams to ball map diagrams for consistency.
• Removed eMIOS on MPC5533. Corrected eDMA channels on MPC5533,
MPC5534, MPC5565, MPC5567. Corrected number of interrupt channels in
Table 1.
• Corrected FlexCAN memory map for MPC5533, MPC5534, and MPC5553 in
Table 2.
• MPC5567 ball map updated for VDDE13.
• Cache associativity added to feature table.
• Review comment - MPC5566 has 64 eTPU channels.
• Updated introduction paragraph to reference all parts covered in this document.
• Changed MPC5567 SRAM size to 80K from 64K for revision A of the MPC5567.

MPC5500 Family Overview, Rev. 1

22 Freescale Semiconductor
 Package Options

Table 4. Revision History (continued)

Revision
Substantive Changes
Number

A.6 • Changed MPC5565 416 BPGA package to consult factory—tooling based on

forecasted demand. Notes added to 208 MAPBGA and some other configurations
that they will not be available through the distribution channel.
A.6.1 • Reviewed by BB, LW, and VG. Editorial and formatting edits by AE. Figures redrawn.

0 • First Public Release

1 • Removed second ADC from MPC5533 block diagram (Figure 2).
• Updated package availability for family. On package options that were previously as
Yes (available) with the footnotes 4 (Not available to distribution customers) or 7
(Depending on demand, consult factory) changed to “No - consult factory for
availability”.
• Corrected Ball J23 (VDDEH10) on 416 MPC5553, MPC5566, and MPC5567 Ball
Map.
• Corrected VDDEH10 on 324 (H19) ball maps.
• Corrected eTPUA6 (ball L3) in the 208 MAPBGA (Figure 14).
• Added MPC5561 to family comparison (Table 1) and memory map (Table 2). Added
MPC5561 block diagram.
• Added note on MPC5565 crossbar size in comparison table (Table 1) to indicate that
there are 5 ports with 2 unused.
• Updated references from PowerPC to Power.
• Added reference for PLLCFG2 for the 324 Ball Map for the MPC5567 and
MPC5561.
• Updated roadmap timing, including the MPC5561 part number, added MPC5510
Family.
• Deleted 324 package options for MPC5533. Small editorial and formatting edits by
SF.

MPC5500 Family Overview, Rev. 1

Freescale Semiconductor 23
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected] Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
USA/Europe or Locations Not Listed:
Freescale Semiconductor implied copyright licenses granted hereunder to design or fabricate any integrated
Technical Information Center, CH370 circuits or integrated circuits based on the information in this document.
1300 N. Alma School Road
Chandler, Arizona 85224 Freescale Semiconductor reserves the right to make changes without further notice to
+1-800-521-6274 or +1-480-768-2130
[email protected] any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Europe, Middle East, and Africa: Freescale Semiconductor assume any liability arising out of the application or use of any
Freescale Halbleiter Deutschland GmbH product or circuit, and specifically disclaims any and all liability, including without
Technical Information Center limitation consequential or incidental damages. “Typical” parameters that may be
Schatzbogen 7 provided in Freescale Semiconductor data sheets and/or specifications can and do vary
81829 Muenchen, Germany in different applications and actual performance may vary over time. All operating
+44 1296 380 456 (English) parameters, including “Typicals”, must be validated for each customer application by
+46 8 52200080 (English)
+49 89 92103 559 (German) customer’s technical experts. Freescale Semiconductor does not convey any license
+33 1 69 35 48 48 (French) under its patent rights nor the rights of others. Freescale Semiconductor products are
[email protected] not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
Japan: or for any other application in which the failure of the Freescale Semiconductor product
Freescale Semiconductor Japan Ltd. could create a situation where personal injury or death may occur. Should Buyer
Headquarters purchase or use Freescale Semiconductor products for any such unintended or
ARCO Tower 15F unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064 its officers, employees, subsidiaries, affiliates, and distributors harmless against all
Japan claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
0120 191014 or +81 3 5437 9125 directly or indirectly, any claim of personal injury or death associated with such
[email protected] unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
2 Dai King Street The Power Architecture and Power.org word marks and the Power and Power.org logos
Tai Po Industrial Estate and related marks are trademarks and service markes licensed by Power.org.
Tai Po, N.T., Hong Kong The described product is a PowerPC microprocessor core. The PowerPC name is a
+800 2666 8080 trademark of IBM Corp. and is used under license. All other product or service names
[email protected] are the property of their respective owners.
For Literature Requests Only: © Freescale Semiconductor, Inc. 2006. All rights reserved.
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]

EB659
Rev. 1, 11/2006